1 // SPDX-License-Identifier: GPL-2.0 2 /* Marvell OcteonTx2 RVU Admin Function driver 3 * 4 * Copyright (C) 2018 Marvell International Ltd. 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 */ 10 11 #include <linux/module.h> 12 #include <linux/interrupt.h> 13 #include <linux/delay.h> 14 #include <linux/irq.h> 15 #include <linux/pci.h> 16 #include <linux/sysfs.h> 17 18 #include "cgx.h" 19 #include "rvu.h" 20 #include "rvu_reg.h" 21 22 #define DRV_NAME "octeontx2-af" 23 #define DRV_STRING "Marvell OcteonTX2 RVU Admin Function Driver" 24 #define DRV_VERSION "1.0" 25 26 static int rvu_get_hwvf(struct rvu *rvu, int pcifunc); 27 28 static void rvu_set_msix_offset(struct rvu *rvu, struct rvu_pfvf *pfvf, 29 struct rvu_block *block, int lf); 30 static void rvu_clear_msix_offset(struct rvu *rvu, struct rvu_pfvf *pfvf, 31 struct rvu_block *block, int lf); 32 static void __rvu_flr_handler(struct rvu *rvu, u16 pcifunc); 33 34 static int rvu_mbox_init(struct rvu *rvu, struct mbox_wq_info *mw, 35 int type, int num, 36 void (mbox_handler)(struct work_struct *), 37 void (mbox_up_handler)(struct work_struct *)); 38 enum { 39 TYPE_AFVF, 40 TYPE_AFPF, 41 }; 42 43 /* Supported devices */ 44 static const struct pci_device_id rvu_id_table[] = { 45 { PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_OCTEONTX2_RVU_AF) }, 46 { 0, } /* end of table */ 47 }; 48 49 MODULE_AUTHOR("Marvell International Ltd."); 50 MODULE_DESCRIPTION(DRV_STRING); 51 MODULE_LICENSE("GPL v2"); 52 MODULE_VERSION(DRV_VERSION); 53 MODULE_DEVICE_TABLE(pci, rvu_id_table); 54 55 static char *mkex_profile; /* MKEX profile name */ 56 module_param(mkex_profile, charp, 0000); 57 MODULE_PARM_DESC(mkex_profile, "MKEX profile name string"); 58 59 static void rvu_setup_hw_capabilities(struct rvu *rvu) 60 { 61 struct rvu_hwinfo *hw = rvu->hw; 62 63 hw->cap.nix_tx_aggr_lvl = NIX_TXSCH_LVL_TL1; 64 hw->cap.nix_fixed_txschq_mapping = false; 65 hw->cap.nix_shaping = true; 66 hw->cap.nix_tx_link_bp = true; 67 hw->cap.nix_rx_multicast = true; 68 69 if (is_rvu_96xx_B0(rvu)) { 70 hw->cap.nix_fixed_txschq_mapping = true; 71 hw->cap.nix_txsch_per_cgx_lmac = 4; 72 hw->cap.nix_txsch_per_lbk_lmac = 132; 73 hw->cap.nix_txsch_per_sdp_lmac = 76; 74 hw->cap.nix_shaping = false; 75 hw->cap.nix_tx_link_bp = false; 76 if (is_rvu_96xx_A0(rvu)) 77 hw->cap.nix_rx_multicast = false; 78 } 79 } 80 81 /* Poll a RVU block's register 'offset', for a 'zero' 82 * or 'nonzero' at bits specified by 'mask' 83 */ 84 int rvu_poll_reg(struct rvu *rvu, u64 block, u64 offset, u64 mask, bool zero) 85 { 86 unsigned long timeout = jiffies + usecs_to_jiffies(10000); 87 void __iomem *reg; 88 u64 reg_val; 89 90 reg = rvu->afreg_base + ((block << 28) | offset); 91 again: 92 reg_val = readq(reg); 93 if (zero && !(reg_val & mask)) 94 return 0; 95 if (!zero && (reg_val & mask)) 96 return 0; 97 if (time_before(jiffies, timeout)) { 98 usleep_range(1, 5); 99 goto again; 100 } 101 return -EBUSY; 102 } 103 104 int rvu_alloc_rsrc(struct rsrc_bmap *rsrc) 105 { 106 int id; 107 108 if (!rsrc->bmap) 109 return -EINVAL; 110 111 id = find_first_zero_bit(rsrc->bmap, rsrc->max); 112 if (id >= rsrc->max) 113 return -ENOSPC; 114 115 __set_bit(id, rsrc->bmap); 116 117 return id; 118 } 119 120 int rvu_alloc_rsrc_contig(struct rsrc_bmap *rsrc, int nrsrc) 121 { 122 int start; 123 124 if (!rsrc->bmap) 125 return -EINVAL; 126 127 start = bitmap_find_next_zero_area(rsrc->bmap, rsrc->max, 0, nrsrc, 0); 128 if (start >= rsrc->max) 129 return -ENOSPC; 130 131 bitmap_set(rsrc->bmap, start, nrsrc); 132 return start; 133 } 134 135 static void rvu_free_rsrc_contig(struct rsrc_bmap *rsrc, int nrsrc, int start) 136 { 137 if (!rsrc->bmap) 138 return; 139 if (start >= rsrc->max) 140 return; 141 142 bitmap_clear(rsrc->bmap, start, nrsrc); 143 } 144 145 bool rvu_rsrc_check_contig(struct rsrc_bmap *rsrc, int nrsrc) 146 { 147 int start; 148 149 if (!rsrc->bmap) 150 return false; 151 152 start = bitmap_find_next_zero_area(rsrc->bmap, rsrc->max, 0, nrsrc, 0); 153 if (start >= rsrc->max) 154 return false; 155 156 return true; 157 } 158 159 void rvu_free_rsrc(struct rsrc_bmap *rsrc, int id) 160 { 161 if (!rsrc->bmap) 162 return; 163 164 __clear_bit(id, rsrc->bmap); 165 } 166 167 int rvu_rsrc_free_count(struct rsrc_bmap *rsrc) 168 { 169 int used; 170 171 if (!rsrc->bmap) 172 return 0; 173 174 used = bitmap_weight(rsrc->bmap, rsrc->max); 175 return (rsrc->max - used); 176 } 177 178 int rvu_alloc_bitmap(struct rsrc_bmap *rsrc) 179 { 180 rsrc->bmap = kcalloc(BITS_TO_LONGS(rsrc->max), 181 sizeof(long), GFP_KERNEL); 182 if (!rsrc->bmap) 183 return -ENOMEM; 184 return 0; 185 } 186 187 /* Get block LF's HW index from a PF_FUNC's block slot number */ 188 int rvu_get_lf(struct rvu *rvu, struct rvu_block *block, u16 pcifunc, u16 slot) 189 { 190 u16 match = 0; 191 int lf; 192 193 mutex_lock(&rvu->rsrc_lock); 194 for (lf = 0; lf < block->lf.max; lf++) { 195 if (block->fn_map[lf] == pcifunc) { 196 if (slot == match) { 197 mutex_unlock(&rvu->rsrc_lock); 198 return lf; 199 } 200 match++; 201 } 202 } 203 mutex_unlock(&rvu->rsrc_lock); 204 return -ENODEV; 205 } 206 207 /* Convert BLOCK_TYPE_E to a BLOCK_ADDR_E. 208 * Some silicon variants of OcteonTX2 supports 209 * multiple blocks of same type. 210 * 211 * @pcifunc has to be zero when no LF is yet attached. 212 */ 213 int rvu_get_blkaddr(struct rvu *rvu, int blktype, u16 pcifunc) 214 { 215 int devnum, blkaddr = -ENODEV; 216 u64 cfg, reg; 217 bool is_pf; 218 219 switch (blktype) { 220 case BLKTYPE_NPC: 221 blkaddr = BLKADDR_NPC; 222 goto exit; 223 case BLKTYPE_NPA: 224 blkaddr = BLKADDR_NPA; 225 goto exit; 226 case BLKTYPE_NIX: 227 /* For now assume NIX0 */ 228 if (!pcifunc) { 229 blkaddr = BLKADDR_NIX0; 230 goto exit; 231 } 232 break; 233 case BLKTYPE_SSO: 234 blkaddr = BLKADDR_SSO; 235 goto exit; 236 case BLKTYPE_SSOW: 237 blkaddr = BLKADDR_SSOW; 238 goto exit; 239 case BLKTYPE_TIM: 240 blkaddr = BLKADDR_TIM; 241 goto exit; 242 case BLKTYPE_CPT: 243 /* For now assume CPT0 */ 244 if (!pcifunc) { 245 blkaddr = BLKADDR_CPT0; 246 goto exit; 247 } 248 break; 249 } 250 251 /* Check if this is a RVU PF or VF */ 252 if (pcifunc & RVU_PFVF_FUNC_MASK) { 253 is_pf = false; 254 devnum = rvu_get_hwvf(rvu, pcifunc); 255 } else { 256 is_pf = true; 257 devnum = rvu_get_pf(pcifunc); 258 } 259 260 /* Check if the 'pcifunc' has a NIX LF from 'BLKADDR_NIX0' */ 261 if (blktype == BLKTYPE_NIX) { 262 reg = is_pf ? RVU_PRIV_PFX_NIX0_CFG : RVU_PRIV_HWVFX_NIX0_CFG; 263 cfg = rvu_read64(rvu, BLKADDR_RVUM, reg | (devnum << 16)); 264 if (cfg) 265 blkaddr = BLKADDR_NIX0; 266 } 267 268 /* Check if the 'pcifunc' has a CPT LF from 'BLKADDR_CPT0' */ 269 if (blktype == BLKTYPE_CPT) { 270 reg = is_pf ? RVU_PRIV_PFX_CPT0_CFG : RVU_PRIV_HWVFX_CPT0_CFG; 271 cfg = rvu_read64(rvu, BLKADDR_RVUM, reg | (devnum << 16)); 272 if (cfg) 273 blkaddr = BLKADDR_CPT0; 274 } 275 276 exit: 277 if (is_block_implemented(rvu->hw, blkaddr)) 278 return blkaddr; 279 return -ENODEV; 280 } 281 282 static void rvu_update_rsrc_map(struct rvu *rvu, struct rvu_pfvf *pfvf, 283 struct rvu_block *block, u16 pcifunc, 284 u16 lf, bool attach) 285 { 286 int devnum, num_lfs = 0; 287 bool is_pf; 288 u64 reg; 289 290 if (lf >= block->lf.max) { 291 dev_err(&rvu->pdev->dev, 292 "%s: FATAL: LF %d is >= %s's max lfs i.e %d\n", 293 __func__, lf, block->name, block->lf.max); 294 return; 295 } 296 297 /* Check if this is for a RVU PF or VF */ 298 if (pcifunc & RVU_PFVF_FUNC_MASK) { 299 is_pf = false; 300 devnum = rvu_get_hwvf(rvu, pcifunc); 301 } else { 302 is_pf = true; 303 devnum = rvu_get_pf(pcifunc); 304 } 305 306 block->fn_map[lf] = attach ? pcifunc : 0; 307 308 switch (block->type) { 309 case BLKTYPE_NPA: 310 pfvf->npalf = attach ? true : false; 311 num_lfs = pfvf->npalf; 312 break; 313 case BLKTYPE_NIX: 314 pfvf->nixlf = attach ? true : false; 315 num_lfs = pfvf->nixlf; 316 break; 317 case BLKTYPE_SSO: 318 attach ? pfvf->sso++ : pfvf->sso--; 319 num_lfs = pfvf->sso; 320 break; 321 case BLKTYPE_SSOW: 322 attach ? pfvf->ssow++ : pfvf->ssow--; 323 num_lfs = pfvf->ssow; 324 break; 325 case BLKTYPE_TIM: 326 attach ? pfvf->timlfs++ : pfvf->timlfs--; 327 num_lfs = pfvf->timlfs; 328 break; 329 case BLKTYPE_CPT: 330 attach ? pfvf->cptlfs++ : pfvf->cptlfs--; 331 num_lfs = pfvf->cptlfs; 332 break; 333 } 334 335 reg = is_pf ? block->pf_lfcnt_reg : block->vf_lfcnt_reg; 336 rvu_write64(rvu, BLKADDR_RVUM, reg | (devnum << 16), num_lfs); 337 } 338 339 inline int rvu_get_pf(u16 pcifunc) 340 { 341 return (pcifunc >> RVU_PFVF_PF_SHIFT) & RVU_PFVF_PF_MASK; 342 } 343 344 void rvu_get_pf_numvfs(struct rvu *rvu, int pf, int *numvfs, int *hwvf) 345 { 346 u64 cfg; 347 348 /* Get numVFs attached to this PF and first HWVF */ 349 cfg = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_PFX_CFG(pf)); 350 *numvfs = (cfg >> 12) & 0xFF; 351 *hwvf = cfg & 0xFFF; 352 } 353 354 static int rvu_get_hwvf(struct rvu *rvu, int pcifunc) 355 { 356 int pf, func; 357 u64 cfg; 358 359 pf = rvu_get_pf(pcifunc); 360 func = pcifunc & RVU_PFVF_FUNC_MASK; 361 362 /* Get first HWVF attached to this PF */ 363 cfg = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_PFX_CFG(pf)); 364 365 return ((cfg & 0xFFF) + func - 1); 366 } 367 368 struct rvu_pfvf *rvu_get_pfvf(struct rvu *rvu, int pcifunc) 369 { 370 /* Check if it is a PF or VF */ 371 if (pcifunc & RVU_PFVF_FUNC_MASK) 372 return &rvu->hwvf[rvu_get_hwvf(rvu, pcifunc)]; 373 else 374 return &rvu->pf[rvu_get_pf(pcifunc)]; 375 } 376 377 static bool is_pf_func_valid(struct rvu *rvu, u16 pcifunc) 378 { 379 int pf, vf, nvfs; 380 u64 cfg; 381 382 pf = rvu_get_pf(pcifunc); 383 if (pf >= rvu->hw->total_pfs) 384 return false; 385 386 if (!(pcifunc & RVU_PFVF_FUNC_MASK)) 387 return true; 388 389 /* Check if VF is within number of VFs attached to this PF */ 390 vf = (pcifunc & RVU_PFVF_FUNC_MASK) - 1; 391 cfg = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_PFX_CFG(pf)); 392 nvfs = (cfg >> 12) & 0xFF; 393 if (vf >= nvfs) 394 return false; 395 396 return true; 397 } 398 399 bool is_block_implemented(struct rvu_hwinfo *hw, int blkaddr) 400 { 401 struct rvu_block *block; 402 403 if (blkaddr < BLKADDR_RVUM || blkaddr >= BLK_COUNT) 404 return false; 405 406 block = &hw->block[blkaddr]; 407 return block->implemented; 408 } 409 410 static void rvu_check_block_implemented(struct rvu *rvu) 411 { 412 struct rvu_hwinfo *hw = rvu->hw; 413 struct rvu_block *block; 414 int blkid; 415 u64 cfg; 416 417 /* For each block check if 'implemented' bit is set */ 418 for (blkid = 0; blkid < BLK_COUNT; blkid++) { 419 block = &hw->block[blkid]; 420 cfg = rvupf_read64(rvu, RVU_PF_BLOCK_ADDRX_DISC(blkid)); 421 if (cfg & BIT_ULL(11)) 422 block->implemented = true; 423 } 424 } 425 426 static void rvu_setup_rvum_blk_revid(struct rvu *rvu) 427 { 428 rvu_write64(rvu, BLKADDR_RVUM, 429 RVU_PRIV_BLOCK_TYPEX_REV(BLKTYPE_RVUM), 430 RVU_BLK_RVUM_REVID); 431 } 432 433 static void rvu_clear_rvum_blk_revid(struct rvu *rvu) 434 { 435 rvu_write64(rvu, BLKADDR_RVUM, 436 RVU_PRIV_BLOCK_TYPEX_REV(BLKTYPE_RVUM), 0x00); 437 } 438 439 int rvu_lf_reset(struct rvu *rvu, struct rvu_block *block, int lf) 440 { 441 int err; 442 443 if (!block->implemented) 444 return 0; 445 446 rvu_write64(rvu, block->addr, block->lfreset_reg, lf | BIT_ULL(12)); 447 err = rvu_poll_reg(rvu, block->addr, block->lfreset_reg, BIT_ULL(12), 448 true); 449 return err; 450 } 451 452 static void rvu_block_reset(struct rvu *rvu, int blkaddr, u64 rst_reg) 453 { 454 struct rvu_block *block = &rvu->hw->block[blkaddr]; 455 456 if (!block->implemented) 457 return; 458 459 rvu_write64(rvu, blkaddr, rst_reg, BIT_ULL(0)); 460 rvu_poll_reg(rvu, blkaddr, rst_reg, BIT_ULL(63), true); 461 } 462 463 static void rvu_reset_all_blocks(struct rvu *rvu) 464 { 465 /* Do a HW reset of all RVU blocks */ 466 rvu_block_reset(rvu, BLKADDR_NPA, NPA_AF_BLK_RST); 467 rvu_block_reset(rvu, BLKADDR_NIX0, NIX_AF_BLK_RST); 468 rvu_block_reset(rvu, BLKADDR_NPC, NPC_AF_BLK_RST); 469 rvu_block_reset(rvu, BLKADDR_SSO, SSO_AF_BLK_RST); 470 rvu_block_reset(rvu, BLKADDR_TIM, TIM_AF_BLK_RST); 471 rvu_block_reset(rvu, BLKADDR_CPT0, CPT_AF_BLK_RST); 472 rvu_block_reset(rvu, BLKADDR_NDC_NIX0_RX, NDC_AF_BLK_RST); 473 rvu_block_reset(rvu, BLKADDR_NDC_NIX0_TX, NDC_AF_BLK_RST); 474 rvu_block_reset(rvu, BLKADDR_NDC_NPA0, NDC_AF_BLK_RST); 475 } 476 477 static void rvu_scan_block(struct rvu *rvu, struct rvu_block *block) 478 { 479 struct rvu_pfvf *pfvf; 480 u64 cfg; 481 int lf; 482 483 for (lf = 0; lf < block->lf.max; lf++) { 484 cfg = rvu_read64(rvu, block->addr, 485 block->lfcfg_reg | (lf << block->lfshift)); 486 if (!(cfg & BIT_ULL(63))) 487 continue; 488 489 /* Set this resource as being used */ 490 __set_bit(lf, block->lf.bmap); 491 492 /* Get, to whom this LF is attached */ 493 pfvf = rvu_get_pfvf(rvu, (cfg >> 8) & 0xFFFF); 494 rvu_update_rsrc_map(rvu, pfvf, block, 495 (cfg >> 8) & 0xFFFF, lf, true); 496 497 /* Set start MSIX vector for this LF within this PF/VF */ 498 rvu_set_msix_offset(rvu, pfvf, block, lf); 499 } 500 } 501 502 static void rvu_check_min_msix_vec(struct rvu *rvu, int nvecs, int pf, int vf) 503 { 504 int min_vecs; 505 506 if (!vf) 507 goto check_pf; 508 509 if (!nvecs) { 510 dev_warn(rvu->dev, 511 "PF%d:VF%d is configured with zero msix vectors, %d\n", 512 pf, vf - 1, nvecs); 513 } 514 return; 515 516 check_pf: 517 if (pf == 0) 518 min_vecs = RVU_AF_INT_VEC_CNT + RVU_PF_INT_VEC_CNT; 519 else 520 min_vecs = RVU_PF_INT_VEC_CNT; 521 522 if (!(nvecs < min_vecs)) 523 return; 524 dev_warn(rvu->dev, 525 "PF%d is configured with too few vectors, %d, min is %d\n", 526 pf, nvecs, min_vecs); 527 } 528 529 static int rvu_setup_msix_resources(struct rvu *rvu) 530 { 531 struct rvu_hwinfo *hw = rvu->hw; 532 int pf, vf, numvfs, hwvf, err; 533 int nvecs, offset, max_msix; 534 struct rvu_pfvf *pfvf; 535 u64 cfg, phy_addr; 536 dma_addr_t iova; 537 538 for (pf = 0; pf < hw->total_pfs; pf++) { 539 cfg = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_PFX_CFG(pf)); 540 /* If PF is not enabled, nothing to do */ 541 if (!((cfg >> 20) & 0x01)) 542 continue; 543 544 rvu_get_pf_numvfs(rvu, pf, &numvfs, &hwvf); 545 546 pfvf = &rvu->pf[pf]; 547 /* Get num of MSIX vectors attached to this PF */ 548 cfg = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_PFX_MSIX_CFG(pf)); 549 pfvf->msix.max = ((cfg >> 32) & 0xFFF) + 1; 550 rvu_check_min_msix_vec(rvu, pfvf->msix.max, pf, 0); 551 552 /* Alloc msix bitmap for this PF */ 553 err = rvu_alloc_bitmap(&pfvf->msix); 554 if (err) 555 return err; 556 557 /* Allocate memory for MSIX vector to RVU block LF mapping */ 558 pfvf->msix_lfmap = devm_kcalloc(rvu->dev, pfvf->msix.max, 559 sizeof(u16), GFP_KERNEL); 560 if (!pfvf->msix_lfmap) 561 return -ENOMEM; 562 563 /* For PF0 (AF) firmware will set msix vector offsets for 564 * AF, block AF and PF0_INT vectors, so jump to VFs. 565 */ 566 if (!pf) 567 goto setup_vfmsix; 568 569 /* Set MSIX offset for PF's 'RVU_PF_INT_VEC' vectors. 570 * These are allocated on driver init and never freed, 571 * so no need to set 'msix_lfmap' for these. 572 */ 573 cfg = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_PFX_INT_CFG(pf)); 574 nvecs = (cfg >> 12) & 0xFF; 575 cfg &= ~0x7FFULL; 576 offset = rvu_alloc_rsrc_contig(&pfvf->msix, nvecs); 577 rvu_write64(rvu, BLKADDR_RVUM, 578 RVU_PRIV_PFX_INT_CFG(pf), cfg | offset); 579 setup_vfmsix: 580 /* Alloc msix bitmap for VFs */ 581 for (vf = 0; vf < numvfs; vf++) { 582 pfvf = &rvu->hwvf[hwvf + vf]; 583 /* Get num of MSIX vectors attached to this VF */ 584 cfg = rvu_read64(rvu, BLKADDR_RVUM, 585 RVU_PRIV_PFX_MSIX_CFG(pf)); 586 pfvf->msix.max = (cfg & 0xFFF) + 1; 587 rvu_check_min_msix_vec(rvu, pfvf->msix.max, pf, vf + 1); 588 589 /* Alloc msix bitmap for this VF */ 590 err = rvu_alloc_bitmap(&pfvf->msix); 591 if (err) 592 return err; 593 594 pfvf->msix_lfmap = 595 devm_kcalloc(rvu->dev, pfvf->msix.max, 596 sizeof(u16), GFP_KERNEL); 597 if (!pfvf->msix_lfmap) 598 return -ENOMEM; 599 600 /* Set MSIX offset for HWVF's 'RVU_VF_INT_VEC' vectors. 601 * These are allocated on driver init and never freed, 602 * so no need to set 'msix_lfmap' for these. 603 */ 604 cfg = rvu_read64(rvu, BLKADDR_RVUM, 605 RVU_PRIV_HWVFX_INT_CFG(hwvf + vf)); 606 nvecs = (cfg >> 12) & 0xFF; 607 cfg &= ~0x7FFULL; 608 offset = rvu_alloc_rsrc_contig(&pfvf->msix, nvecs); 609 rvu_write64(rvu, BLKADDR_RVUM, 610 RVU_PRIV_HWVFX_INT_CFG(hwvf + vf), 611 cfg | offset); 612 } 613 } 614 615 /* HW interprets RVU_AF_MSIXTR_BASE address as an IOVA, hence 616 * create a IOMMU mapping for the physcial address configured by 617 * firmware and reconfig RVU_AF_MSIXTR_BASE with IOVA. 618 */ 619 cfg = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_CONST); 620 max_msix = cfg & 0xFFFFF; 621 if (rvu->fwdata && rvu->fwdata->msixtr_base) 622 phy_addr = rvu->fwdata->msixtr_base; 623 else 624 phy_addr = rvu_read64(rvu, BLKADDR_RVUM, RVU_AF_MSIXTR_BASE); 625 626 iova = dma_map_resource(rvu->dev, phy_addr, 627 max_msix * PCI_MSIX_ENTRY_SIZE, 628 DMA_BIDIRECTIONAL, 0); 629 630 if (dma_mapping_error(rvu->dev, iova)) 631 return -ENOMEM; 632 633 rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_MSIXTR_BASE, (u64)iova); 634 rvu->msix_base_iova = iova; 635 rvu->msixtr_base_phy = phy_addr; 636 637 return 0; 638 } 639 640 static void rvu_reset_msix(struct rvu *rvu) 641 { 642 /* Restore msixtr base register */ 643 rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_MSIXTR_BASE, 644 rvu->msixtr_base_phy); 645 } 646 647 static void rvu_free_hw_resources(struct rvu *rvu) 648 { 649 struct rvu_hwinfo *hw = rvu->hw; 650 struct rvu_block *block; 651 struct rvu_pfvf *pfvf; 652 int id, max_msix; 653 u64 cfg; 654 655 rvu_npa_freemem(rvu); 656 rvu_npc_freemem(rvu); 657 rvu_nix_freemem(rvu); 658 659 /* Free block LF bitmaps */ 660 for (id = 0; id < BLK_COUNT; id++) { 661 block = &hw->block[id]; 662 kfree(block->lf.bmap); 663 } 664 665 /* Free MSIX bitmaps */ 666 for (id = 0; id < hw->total_pfs; id++) { 667 pfvf = &rvu->pf[id]; 668 kfree(pfvf->msix.bmap); 669 } 670 671 for (id = 0; id < hw->total_vfs; id++) { 672 pfvf = &rvu->hwvf[id]; 673 kfree(pfvf->msix.bmap); 674 } 675 676 /* Unmap MSIX vector base IOVA mapping */ 677 if (!rvu->msix_base_iova) 678 return; 679 cfg = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_CONST); 680 max_msix = cfg & 0xFFFFF; 681 dma_unmap_resource(rvu->dev, rvu->msix_base_iova, 682 max_msix * PCI_MSIX_ENTRY_SIZE, 683 DMA_BIDIRECTIONAL, 0); 684 685 rvu_reset_msix(rvu); 686 mutex_destroy(&rvu->rsrc_lock); 687 } 688 689 static void rvu_setup_pfvf_macaddress(struct rvu *rvu) 690 { 691 struct rvu_hwinfo *hw = rvu->hw; 692 int pf, vf, numvfs, hwvf; 693 struct rvu_pfvf *pfvf; 694 u64 *mac; 695 696 for (pf = 0; pf < hw->total_pfs; pf++) { 697 if (!is_pf_cgxmapped(rvu, pf)) 698 continue; 699 /* Assign MAC address to PF */ 700 pfvf = &rvu->pf[pf]; 701 if (rvu->fwdata && pf < PF_MACNUM_MAX) { 702 mac = &rvu->fwdata->pf_macs[pf]; 703 if (*mac) 704 u64_to_ether_addr(*mac, pfvf->mac_addr); 705 else 706 eth_random_addr(pfvf->mac_addr); 707 } else { 708 eth_random_addr(pfvf->mac_addr); 709 } 710 711 /* Assign MAC address to VFs */ 712 rvu_get_pf_numvfs(rvu, pf, &numvfs, &hwvf); 713 for (vf = 0; vf < numvfs; vf++, hwvf++) { 714 pfvf = &rvu->hwvf[hwvf]; 715 if (rvu->fwdata && hwvf < VF_MACNUM_MAX) { 716 mac = &rvu->fwdata->vf_macs[hwvf]; 717 if (*mac) 718 u64_to_ether_addr(*mac, pfvf->mac_addr); 719 else 720 eth_random_addr(pfvf->mac_addr); 721 } else { 722 eth_random_addr(pfvf->mac_addr); 723 } 724 } 725 } 726 } 727 728 static int rvu_fwdata_init(struct rvu *rvu) 729 { 730 u64 fwdbase; 731 int err; 732 733 /* Get firmware data base address */ 734 err = cgx_get_fwdata_base(&fwdbase); 735 if (err) 736 goto fail; 737 rvu->fwdata = ioremap_wc(fwdbase, sizeof(struct rvu_fwdata)); 738 if (!rvu->fwdata) 739 goto fail; 740 if (!is_rvu_fwdata_valid(rvu)) { 741 dev_err(rvu->dev, 742 "Mismatch in 'fwdata' struct btw kernel and firmware\n"); 743 iounmap(rvu->fwdata); 744 rvu->fwdata = NULL; 745 return -EINVAL; 746 } 747 return 0; 748 fail: 749 dev_info(rvu->dev, "Unable to fetch 'fwdata' from firmware\n"); 750 return -EIO; 751 } 752 753 static void rvu_fwdata_exit(struct rvu *rvu) 754 { 755 if (rvu->fwdata) 756 iounmap(rvu->fwdata); 757 } 758 759 static int rvu_setup_hw_resources(struct rvu *rvu) 760 { 761 struct rvu_hwinfo *hw = rvu->hw; 762 struct rvu_block *block; 763 int blkid, err; 764 u64 cfg; 765 766 /* Get HW supported max RVU PF & VF count */ 767 cfg = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_CONST); 768 hw->total_pfs = (cfg >> 32) & 0xFF; 769 hw->total_vfs = (cfg >> 20) & 0xFFF; 770 hw->max_vfs_per_pf = (cfg >> 40) & 0xFF; 771 772 /* Init NPA LF's bitmap */ 773 block = &hw->block[BLKADDR_NPA]; 774 if (!block->implemented) 775 goto nix; 776 cfg = rvu_read64(rvu, BLKADDR_NPA, NPA_AF_CONST); 777 block->lf.max = (cfg >> 16) & 0xFFF; 778 block->addr = BLKADDR_NPA; 779 block->type = BLKTYPE_NPA; 780 block->lfshift = 8; 781 block->lookup_reg = NPA_AF_RVU_LF_CFG_DEBUG; 782 block->pf_lfcnt_reg = RVU_PRIV_PFX_NPA_CFG; 783 block->vf_lfcnt_reg = RVU_PRIV_HWVFX_NPA_CFG; 784 block->lfcfg_reg = NPA_PRIV_LFX_CFG; 785 block->msixcfg_reg = NPA_PRIV_LFX_INT_CFG; 786 block->lfreset_reg = NPA_AF_LF_RST; 787 sprintf(block->name, "NPA"); 788 err = rvu_alloc_bitmap(&block->lf); 789 if (err) 790 return err; 791 792 nix: 793 /* Init NIX LF's bitmap */ 794 block = &hw->block[BLKADDR_NIX0]; 795 if (!block->implemented) 796 goto sso; 797 cfg = rvu_read64(rvu, BLKADDR_NIX0, NIX_AF_CONST2); 798 block->lf.max = cfg & 0xFFF; 799 block->addr = BLKADDR_NIX0; 800 block->type = BLKTYPE_NIX; 801 block->lfshift = 8; 802 block->lookup_reg = NIX_AF_RVU_LF_CFG_DEBUG; 803 block->pf_lfcnt_reg = RVU_PRIV_PFX_NIX0_CFG; 804 block->vf_lfcnt_reg = RVU_PRIV_HWVFX_NIX0_CFG; 805 block->lfcfg_reg = NIX_PRIV_LFX_CFG; 806 block->msixcfg_reg = NIX_PRIV_LFX_INT_CFG; 807 block->lfreset_reg = NIX_AF_LF_RST; 808 sprintf(block->name, "NIX"); 809 err = rvu_alloc_bitmap(&block->lf); 810 if (err) 811 return err; 812 813 sso: 814 /* Init SSO group's bitmap */ 815 block = &hw->block[BLKADDR_SSO]; 816 if (!block->implemented) 817 goto ssow; 818 cfg = rvu_read64(rvu, BLKADDR_SSO, SSO_AF_CONST); 819 block->lf.max = cfg & 0xFFFF; 820 block->addr = BLKADDR_SSO; 821 block->type = BLKTYPE_SSO; 822 block->multislot = true; 823 block->lfshift = 3; 824 block->lookup_reg = SSO_AF_RVU_LF_CFG_DEBUG; 825 block->pf_lfcnt_reg = RVU_PRIV_PFX_SSO_CFG; 826 block->vf_lfcnt_reg = RVU_PRIV_HWVFX_SSO_CFG; 827 block->lfcfg_reg = SSO_PRIV_LFX_HWGRP_CFG; 828 block->msixcfg_reg = SSO_PRIV_LFX_HWGRP_INT_CFG; 829 block->lfreset_reg = SSO_AF_LF_HWGRP_RST; 830 sprintf(block->name, "SSO GROUP"); 831 err = rvu_alloc_bitmap(&block->lf); 832 if (err) 833 return err; 834 835 ssow: 836 /* Init SSO workslot's bitmap */ 837 block = &hw->block[BLKADDR_SSOW]; 838 if (!block->implemented) 839 goto tim; 840 block->lf.max = (cfg >> 56) & 0xFF; 841 block->addr = BLKADDR_SSOW; 842 block->type = BLKTYPE_SSOW; 843 block->multislot = true; 844 block->lfshift = 3; 845 block->lookup_reg = SSOW_AF_RVU_LF_HWS_CFG_DEBUG; 846 block->pf_lfcnt_reg = RVU_PRIV_PFX_SSOW_CFG; 847 block->vf_lfcnt_reg = RVU_PRIV_HWVFX_SSOW_CFG; 848 block->lfcfg_reg = SSOW_PRIV_LFX_HWS_CFG; 849 block->msixcfg_reg = SSOW_PRIV_LFX_HWS_INT_CFG; 850 block->lfreset_reg = SSOW_AF_LF_HWS_RST; 851 sprintf(block->name, "SSOWS"); 852 err = rvu_alloc_bitmap(&block->lf); 853 if (err) 854 return err; 855 856 tim: 857 /* Init TIM LF's bitmap */ 858 block = &hw->block[BLKADDR_TIM]; 859 if (!block->implemented) 860 goto cpt; 861 cfg = rvu_read64(rvu, BLKADDR_TIM, TIM_AF_CONST); 862 block->lf.max = cfg & 0xFFFF; 863 block->addr = BLKADDR_TIM; 864 block->type = BLKTYPE_TIM; 865 block->multislot = true; 866 block->lfshift = 3; 867 block->lookup_reg = TIM_AF_RVU_LF_CFG_DEBUG; 868 block->pf_lfcnt_reg = RVU_PRIV_PFX_TIM_CFG; 869 block->vf_lfcnt_reg = RVU_PRIV_HWVFX_TIM_CFG; 870 block->lfcfg_reg = TIM_PRIV_LFX_CFG; 871 block->msixcfg_reg = TIM_PRIV_LFX_INT_CFG; 872 block->lfreset_reg = TIM_AF_LF_RST; 873 sprintf(block->name, "TIM"); 874 err = rvu_alloc_bitmap(&block->lf); 875 if (err) 876 return err; 877 878 cpt: 879 /* Init CPT LF's bitmap */ 880 block = &hw->block[BLKADDR_CPT0]; 881 if (!block->implemented) 882 goto init; 883 cfg = rvu_read64(rvu, BLKADDR_CPT0, CPT_AF_CONSTANTS0); 884 block->lf.max = cfg & 0xFF; 885 block->addr = BLKADDR_CPT0; 886 block->type = BLKTYPE_CPT; 887 block->multislot = true; 888 block->lfshift = 3; 889 block->lookup_reg = CPT_AF_RVU_LF_CFG_DEBUG; 890 block->pf_lfcnt_reg = RVU_PRIV_PFX_CPT0_CFG; 891 block->vf_lfcnt_reg = RVU_PRIV_HWVFX_CPT0_CFG; 892 block->lfcfg_reg = CPT_PRIV_LFX_CFG; 893 block->msixcfg_reg = CPT_PRIV_LFX_INT_CFG; 894 block->lfreset_reg = CPT_AF_LF_RST; 895 sprintf(block->name, "CPT"); 896 err = rvu_alloc_bitmap(&block->lf); 897 if (err) 898 return err; 899 900 init: 901 /* Allocate memory for PFVF data */ 902 rvu->pf = devm_kcalloc(rvu->dev, hw->total_pfs, 903 sizeof(struct rvu_pfvf), GFP_KERNEL); 904 if (!rvu->pf) 905 return -ENOMEM; 906 907 rvu->hwvf = devm_kcalloc(rvu->dev, hw->total_vfs, 908 sizeof(struct rvu_pfvf), GFP_KERNEL); 909 if (!rvu->hwvf) 910 return -ENOMEM; 911 912 mutex_init(&rvu->rsrc_lock); 913 914 rvu_fwdata_init(rvu); 915 916 err = rvu_setup_msix_resources(rvu); 917 if (err) 918 return err; 919 920 for (blkid = 0; blkid < BLK_COUNT; blkid++) { 921 block = &hw->block[blkid]; 922 if (!block->lf.bmap) 923 continue; 924 925 /* Allocate memory for block LF/slot to pcifunc mapping info */ 926 block->fn_map = devm_kcalloc(rvu->dev, block->lf.max, 927 sizeof(u16), GFP_KERNEL); 928 if (!block->fn_map) { 929 err = -ENOMEM; 930 goto msix_err; 931 } 932 933 /* Scan all blocks to check if low level firmware has 934 * already provisioned any of the resources to a PF/VF. 935 */ 936 rvu_scan_block(rvu, block); 937 } 938 939 err = rvu_npc_init(rvu); 940 if (err) 941 goto npc_err; 942 943 err = rvu_cgx_init(rvu); 944 if (err) 945 goto cgx_err; 946 947 /* Assign MACs for CGX mapped functions */ 948 rvu_setup_pfvf_macaddress(rvu); 949 950 err = rvu_npa_init(rvu); 951 if (err) 952 goto npa_err; 953 954 err = rvu_nix_init(rvu); 955 if (err) 956 goto nix_err; 957 958 return 0; 959 960 nix_err: 961 rvu_nix_freemem(rvu); 962 npa_err: 963 rvu_npa_freemem(rvu); 964 cgx_err: 965 rvu_cgx_exit(rvu); 966 npc_err: 967 rvu_npc_freemem(rvu); 968 rvu_fwdata_exit(rvu); 969 msix_err: 970 rvu_reset_msix(rvu); 971 return err; 972 } 973 974 /* NPA and NIX admin queue APIs */ 975 void rvu_aq_free(struct rvu *rvu, struct admin_queue *aq) 976 { 977 if (!aq) 978 return; 979 980 qmem_free(rvu->dev, aq->inst); 981 qmem_free(rvu->dev, aq->res); 982 devm_kfree(rvu->dev, aq); 983 } 984 985 int rvu_aq_alloc(struct rvu *rvu, struct admin_queue **ad_queue, 986 int qsize, int inst_size, int res_size) 987 { 988 struct admin_queue *aq; 989 int err; 990 991 *ad_queue = devm_kzalloc(rvu->dev, sizeof(*aq), GFP_KERNEL); 992 if (!*ad_queue) 993 return -ENOMEM; 994 aq = *ad_queue; 995 996 /* Alloc memory for instructions i.e AQ */ 997 err = qmem_alloc(rvu->dev, &aq->inst, qsize, inst_size); 998 if (err) { 999 devm_kfree(rvu->dev, aq); 1000 return err; 1001 } 1002 1003 /* Alloc memory for results */ 1004 err = qmem_alloc(rvu->dev, &aq->res, qsize, res_size); 1005 if (err) { 1006 rvu_aq_free(rvu, aq); 1007 return err; 1008 } 1009 1010 spin_lock_init(&aq->lock); 1011 return 0; 1012 } 1013 1014 int rvu_mbox_handler_ready(struct rvu *rvu, struct msg_req *req, 1015 struct ready_msg_rsp *rsp) 1016 { 1017 if (rvu->fwdata) { 1018 rsp->rclk_freq = rvu->fwdata->rclk; 1019 rsp->sclk_freq = rvu->fwdata->sclk; 1020 } 1021 return 0; 1022 } 1023 1024 /* Get current count of a RVU block's LF/slots 1025 * provisioned to a given RVU func. 1026 */ 1027 static u16 rvu_get_rsrc_mapcount(struct rvu_pfvf *pfvf, int blktype) 1028 { 1029 switch (blktype) { 1030 case BLKTYPE_NPA: 1031 return pfvf->npalf ? 1 : 0; 1032 case BLKTYPE_NIX: 1033 return pfvf->nixlf ? 1 : 0; 1034 case BLKTYPE_SSO: 1035 return pfvf->sso; 1036 case BLKTYPE_SSOW: 1037 return pfvf->ssow; 1038 case BLKTYPE_TIM: 1039 return pfvf->timlfs; 1040 case BLKTYPE_CPT: 1041 return pfvf->cptlfs; 1042 } 1043 return 0; 1044 } 1045 1046 bool is_pffunc_map_valid(struct rvu *rvu, u16 pcifunc, int blktype) 1047 { 1048 struct rvu_pfvf *pfvf; 1049 1050 if (!is_pf_func_valid(rvu, pcifunc)) 1051 return false; 1052 1053 pfvf = rvu_get_pfvf(rvu, pcifunc); 1054 1055 /* Check if this PFFUNC has a LF of type blktype attached */ 1056 if (!rvu_get_rsrc_mapcount(pfvf, blktype)) 1057 return false; 1058 1059 return true; 1060 } 1061 1062 static int rvu_lookup_rsrc(struct rvu *rvu, struct rvu_block *block, 1063 int pcifunc, int slot) 1064 { 1065 u64 val; 1066 1067 val = ((u64)pcifunc << 24) | (slot << 16) | (1ULL << 13); 1068 rvu_write64(rvu, block->addr, block->lookup_reg, val); 1069 /* Wait for the lookup to finish */ 1070 /* TODO: put some timeout here */ 1071 while (rvu_read64(rvu, block->addr, block->lookup_reg) & (1ULL << 13)) 1072 ; 1073 1074 val = rvu_read64(rvu, block->addr, block->lookup_reg); 1075 1076 /* Check LF valid bit */ 1077 if (!(val & (1ULL << 12))) 1078 return -1; 1079 1080 return (val & 0xFFF); 1081 } 1082 1083 static void rvu_detach_block(struct rvu *rvu, int pcifunc, int blktype) 1084 { 1085 struct rvu_pfvf *pfvf = rvu_get_pfvf(rvu, pcifunc); 1086 struct rvu_hwinfo *hw = rvu->hw; 1087 struct rvu_block *block; 1088 int slot, lf, num_lfs; 1089 int blkaddr; 1090 1091 blkaddr = rvu_get_blkaddr(rvu, blktype, pcifunc); 1092 if (blkaddr < 0) 1093 return; 1094 1095 block = &hw->block[blkaddr]; 1096 1097 num_lfs = rvu_get_rsrc_mapcount(pfvf, block->type); 1098 if (!num_lfs) 1099 return; 1100 1101 for (slot = 0; slot < num_lfs; slot++) { 1102 lf = rvu_lookup_rsrc(rvu, block, pcifunc, slot); 1103 if (lf < 0) /* This should never happen */ 1104 continue; 1105 1106 /* Disable the LF */ 1107 rvu_write64(rvu, blkaddr, block->lfcfg_reg | 1108 (lf << block->lfshift), 0x00ULL); 1109 1110 /* Update SW maintained mapping info as well */ 1111 rvu_update_rsrc_map(rvu, pfvf, block, 1112 pcifunc, lf, false); 1113 1114 /* Free the resource */ 1115 rvu_free_rsrc(&block->lf, lf); 1116 1117 /* Clear MSIX vector offset for this LF */ 1118 rvu_clear_msix_offset(rvu, pfvf, block, lf); 1119 } 1120 } 1121 1122 static int rvu_detach_rsrcs(struct rvu *rvu, struct rsrc_detach *detach, 1123 u16 pcifunc) 1124 { 1125 struct rvu_hwinfo *hw = rvu->hw; 1126 bool detach_all = true; 1127 struct rvu_block *block; 1128 int blkid; 1129 1130 mutex_lock(&rvu->rsrc_lock); 1131 1132 /* Check for partial resource detach */ 1133 if (detach && detach->partial) 1134 detach_all = false; 1135 1136 /* Check for RVU block's LFs attached to this func, 1137 * if so, detach them. 1138 */ 1139 for (blkid = 0; blkid < BLK_COUNT; blkid++) { 1140 block = &hw->block[blkid]; 1141 if (!block->lf.bmap) 1142 continue; 1143 if (!detach_all && detach) { 1144 if (blkid == BLKADDR_NPA && !detach->npalf) 1145 continue; 1146 else if ((blkid == BLKADDR_NIX0) && !detach->nixlf) 1147 continue; 1148 else if ((blkid == BLKADDR_SSO) && !detach->sso) 1149 continue; 1150 else if ((blkid == BLKADDR_SSOW) && !detach->ssow) 1151 continue; 1152 else if ((blkid == BLKADDR_TIM) && !detach->timlfs) 1153 continue; 1154 else if ((blkid == BLKADDR_CPT0) && !detach->cptlfs) 1155 continue; 1156 } 1157 rvu_detach_block(rvu, pcifunc, block->type); 1158 } 1159 1160 mutex_unlock(&rvu->rsrc_lock); 1161 return 0; 1162 } 1163 1164 int rvu_mbox_handler_detach_resources(struct rvu *rvu, 1165 struct rsrc_detach *detach, 1166 struct msg_rsp *rsp) 1167 { 1168 return rvu_detach_rsrcs(rvu, detach, detach->hdr.pcifunc); 1169 } 1170 1171 static void rvu_attach_block(struct rvu *rvu, int pcifunc, 1172 int blktype, int num_lfs) 1173 { 1174 struct rvu_pfvf *pfvf = rvu_get_pfvf(rvu, pcifunc); 1175 struct rvu_hwinfo *hw = rvu->hw; 1176 struct rvu_block *block; 1177 int slot, lf; 1178 int blkaddr; 1179 u64 cfg; 1180 1181 if (!num_lfs) 1182 return; 1183 1184 blkaddr = rvu_get_blkaddr(rvu, blktype, 0); 1185 if (blkaddr < 0) 1186 return; 1187 1188 block = &hw->block[blkaddr]; 1189 if (!block->lf.bmap) 1190 return; 1191 1192 for (slot = 0; slot < num_lfs; slot++) { 1193 /* Allocate the resource */ 1194 lf = rvu_alloc_rsrc(&block->lf); 1195 if (lf < 0) 1196 return; 1197 1198 cfg = (1ULL << 63) | (pcifunc << 8) | slot; 1199 rvu_write64(rvu, blkaddr, block->lfcfg_reg | 1200 (lf << block->lfshift), cfg); 1201 rvu_update_rsrc_map(rvu, pfvf, block, 1202 pcifunc, lf, true); 1203 1204 /* Set start MSIX vector for this LF within this PF/VF */ 1205 rvu_set_msix_offset(rvu, pfvf, block, lf); 1206 } 1207 } 1208 1209 static int rvu_check_rsrc_availability(struct rvu *rvu, 1210 struct rsrc_attach *req, u16 pcifunc) 1211 { 1212 struct rvu_pfvf *pfvf = rvu_get_pfvf(rvu, pcifunc); 1213 struct rvu_hwinfo *hw = rvu->hw; 1214 struct rvu_block *block; 1215 int free_lfs, mappedlfs; 1216 1217 /* Only one NPA LF can be attached */ 1218 if (req->npalf && !rvu_get_rsrc_mapcount(pfvf, BLKTYPE_NPA)) { 1219 block = &hw->block[BLKADDR_NPA]; 1220 free_lfs = rvu_rsrc_free_count(&block->lf); 1221 if (!free_lfs) 1222 goto fail; 1223 } else if (req->npalf) { 1224 dev_err(&rvu->pdev->dev, 1225 "Func 0x%x: Invalid req, already has NPA\n", 1226 pcifunc); 1227 return -EINVAL; 1228 } 1229 1230 /* Only one NIX LF can be attached */ 1231 if (req->nixlf && !rvu_get_rsrc_mapcount(pfvf, BLKTYPE_NIX)) { 1232 block = &hw->block[BLKADDR_NIX0]; 1233 free_lfs = rvu_rsrc_free_count(&block->lf); 1234 if (!free_lfs) 1235 goto fail; 1236 } else if (req->nixlf) { 1237 dev_err(&rvu->pdev->dev, 1238 "Func 0x%x: Invalid req, already has NIX\n", 1239 pcifunc); 1240 return -EINVAL; 1241 } 1242 1243 if (req->sso) { 1244 block = &hw->block[BLKADDR_SSO]; 1245 /* Is request within limits ? */ 1246 if (req->sso > block->lf.max) { 1247 dev_err(&rvu->pdev->dev, 1248 "Func 0x%x: Invalid SSO req, %d > max %d\n", 1249 pcifunc, req->sso, block->lf.max); 1250 return -EINVAL; 1251 } 1252 mappedlfs = rvu_get_rsrc_mapcount(pfvf, block->type); 1253 free_lfs = rvu_rsrc_free_count(&block->lf); 1254 /* Check if additional resources are available */ 1255 if (req->sso > mappedlfs && 1256 ((req->sso - mappedlfs) > free_lfs)) 1257 goto fail; 1258 } 1259 1260 if (req->ssow) { 1261 block = &hw->block[BLKADDR_SSOW]; 1262 if (req->ssow > block->lf.max) { 1263 dev_err(&rvu->pdev->dev, 1264 "Func 0x%x: Invalid SSOW req, %d > max %d\n", 1265 pcifunc, req->sso, block->lf.max); 1266 return -EINVAL; 1267 } 1268 mappedlfs = rvu_get_rsrc_mapcount(pfvf, block->type); 1269 free_lfs = rvu_rsrc_free_count(&block->lf); 1270 if (req->ssow > mappedlfs && 1271 ((req->ssow - mappedlfs) > free_lfs)) 1272 goto fail; 1273 } 1274 1275 if (req->timlfs) { 1276 block = &hw->block[BLKADDR_TIM]; 1277 if (req->timlfs > block->lf.max) { 1278 dev_err(&rvu->pdev->dev, 1279 "Func 0x%x: Invalid TIMLF req, %d > max %d\n", 1280 pcifunc, req->timlfs, block->lf.max); 1281 return -EINVAL; 1282 } 1283 mappedlfs = rvu_get_rsrc_mapcount(pfvf, block->type); 1284 free_lfs = rvu_rsrc_free_count(&block->lf); 1285 if (req->timlfs > mappedlfs && 1286 ((req->timlfs - mappedlfs) > free_lfs)) 1287 goto fail; 1288 } 1289 1290 if (req->cptlfs) { 1291 block = &hw->block[BLKADDR_CPT0]; 1292 if (req->cptlfs > block->lf.max) { 1293 dev_err(&rvu->pdev->dev, 1294 "Func 0x%x: Invalid CPTLF req, %d > max %d\n", 1295 pcifunc, req->cptlfs, block->lf.max); 1296 return -EINVAL; 1297 } 1298 mappedlfs = rvu_get_rsrc_mapcount(pfvf, block->type); 1299 free_lfs = rvu_rsrc_free_count(&block->lf); 1300 if (req->cptlfs > mappedlfs && 1301 ((req->cptlfs - mappedlfs) > free_lfs)) 1302 goto fail; 1303 } 1304 1305 return 0; 1306 1307 fail: 1308 dev_info(rvu->dev, "Request for %s failed\n", block->name); 1309 return -ENOSPC; 1310 } 1311 1312 int rvu_mbox_handler_attach_resources(struct rvu *rvu, 1313 struct rsrc_attach *attach, 1314 struct msg_rsp *rsp) 1315 { 1316 u16 pcifunc = attach->hdr.pcifunc; 1317 int err; 1318 1319 /* If first request, detach all existing attached resources */ 1320 if (!attach->modify) 1321 rvu_detach_rsrcs(rvu, NULL, pcifunc); 1322 1323 mutex_lock(&rvu->rsrc_lock); 1324 1325 /* Check if the request can be accommodated */ 1326 err = rvu_check_rsrc_availability(rvu, attach, pcifunc); 1327 if (err) 1328 goto exit; 1329 1330 /* Now attach the requested resources */ 1331 if (attach->npalf) 1332 rvu_attach_block(rvu, pcifunc, BLKTYPE_NPA, 1); 1333 1334 if (attach->nixlf) 1335 rvu_attach_block(rvu, pcifunc, BLKTYPE_NIX, 1); 1336 1337 if (attach->sso) { 1338 /* RVU func doesn't know which exact LF or slot is attached 1339 * to it, it always sees as slot 0,1,2. So for a 'modify' 1340 * request, simply detach all existing attached LFs/slots 1341 * and attach a fresh. 1342 */ 1343 if (attach->modify) 1344 rvu_detach_block(rvu, pcifunc, BLKTYPE_SSO); 1345 rvu_attach_block(rvu, pcifunc, BLKTYPE_SSO, attach->sso); 1346 } 1347 1348 if (attach->ssow) { 1349 if (attach->modify) 1350 rvu_detach_block(rvu, pcifunc, BLKTYPE_SSOW); 1351 rvu_attach_block(rvu, pcifunc, BLKTYPE_SSOW, attach->ssow); 1352 } 1353 1354 if (attach->timlfs) { 1355 if (attach->modify) 1356 rvu_detach_block(rvu, pcifunc, BLKTYPE_TIM); 1357 rvu_attach_block(rvu, pcifunc, BLKTYPE_TIM, attach->timlfs); 1358 } 1359 1360 if (attach->cptlfs) { 1361 if (attach->modify) 1362 rvu_detach_block(rvu, pcifunc, BLKTYPE_CPT); 1363 rvu_attach_block(rvu, pcifunc, BLKTYPE_CPT, attach->cptlfs); 1364 } 1365 1366 exit: 1367 mutex_unlock(&rvu->rsrc_lock); 1368 return err; 1369 } 1370 1371 static u16 rvu_get_msix_offset(struct rvu *rvu, struct rvu_pfvf *pfvf, 1372 int blkaddr, int lf) 1373 { 1374 u16 vec; 1375 1376 if (lf < 0) 1377 return MSIX_VECTOR_INVALID; 1378 1379 for (vec = 0; vec < pfvf->msix.max; vec++) { 1380 if (pfvf->msix_lfmap[vec] == MSIX_BLKLF(blkaddr, lf)) 1381 return vec; 1382 } 1383 return MSIX_VECTOR_INVALID; 1384 } 1385 1386 static void rvu_set_msix_offset(struct rvu *rvu, struct rvu_pfvf *pfvf, 1387 struct rvu_block *block, int lf) 1388 { 1389 u16 nvecs, vec, offset; 1390 u64 cfg; 1391 1392 cfg = rvu_read64(rvu, block->addr, block->msixcfg_reg | 1393 (lf << block->lfshift)); 1394 nvecs = (cfg >> 12) & 0xFF; 1395 1396 /* Check and alloc MSIX vectors, must be contiguous */ 1397 if (!rvu_rsrc_check_contig(&pfvf->msix, nvecs)) 1398 return; 1399 1400 offset = rvu_alloc_rsrc_contig(&pfvf->msix, nvecs); 1401 1402 /* Config MSIX offset in LF */ 1403 rvu_write64(rvu, block->addr, block->msixcfg_reg | 1404 (lf << block->lfshift), (cfg & ~0x7FFULL) | offset); 1405 1406 /* Update the bitmap as well */ 1407 for (vec = 0; vec < nvecs; vec++) 1408 pfvf->msix_lfmap[offset + vec] = MSIX_BLKLF(block->addr, lf); 1409 } 1410 1411 static void rvu_clear_msix_offset(struct rvu *rvu, struct rvu_pfvf *pfvf, 1412 struct rvu_block *block, int lf) 1413 { 1414 u16 nvecs, vec, offset; 1415 u64 cfg; 1416 1417 cfg = rvu_read64(rvu, block->addr, block->msixcfg_reg | 1418 (lf << block->lfshift)); 1419 nvecs = (cfg >> 12) & 0xFF; 1420 1421 /* Clear MSIX offset in LF */ 1422 rvu_write64(rvu, block->addr, block->msixcfg_reg | 1423 (lf << block->lfshift), cfg & ~0x7FFULL); 1424 1425 offset = rvu_get_msix_offset(rvu, pfvf, block->addr, lf); 1426 1427 /* Update the mapping */ 1428 for (vec = 0; vec < nvecs; vec++) 1429 pfvf->msix_lfmap[offset + vec] = 0; 1430 1431 /* Free the same in MSIX bitmap */ 1432 rvu_free_rsrc_contig(&pfvf->msix, nvecs, offset); 1433 } 1434 1435 int rvu_mbox_handler_msix_offset(struct rvu *rvu, struct msg_req *req, 1436 struct msix_offset_rsp *rsp) 1437 { 1438 struct rvu_hwinfo *hw = rvu->hw; 1439 u16 pcifunc = req->hdr.pcifunc; 1440 struct rvu_pfvf *pfvf; 1441 int lf, slot; 1442 1443 pfvf = rvu_get_pfvf(rvu, pcifunc); 1444 if (!pfvf->msix.bmap) 1445 return 0; 1446 1447 /* Set MSIX offsets for each block's LFs attached to this PF/VF */ 1448 lf = rvu_get_lf(rvu, &hw->block[BLKADDR_NPA], pcifunc, 0); 1449 rsp->npa_msixoff = rvu_get_msix_offset(rvu, pfvf, BLKADDR_NPA, lf); 1450 1451 lf = rvu_get_lf(rvu, &hw->block[BLKADDR_NIX0], pcifunc, 0); 1452 rsp->nix_msixoff = rvu_get_msix_offset(rvu, pfvf, BLKADDR_NIX0, lf); 1453 1454 rsp->sso = pfvf->sso; 1455 for (slot = 0; slot < rsp->sso; slot++) { 1456 lf = rvu_get_lf(rvu, &hw->block[BLKADDR_SSO], pcifunc, slot); 1457 rsp->sso_msixoff[slot] = 1458 rvu_get_msix_offset(rvu, pfvf, BLKADDR_SSO, lf); 1459 } 1460 1461 rsp->ssow = pfvf->ssow; 1462 for (slot = 0; slot < rsp->ssow; slot++) { 1463 lf = rvu_get_lf(rvu, &hw->block[BLKADDR_SSOW], pcifunc, slot); 1464 rsp->ssow_msixoff[slot] = 1465 rvu_get_msix_offset(rvu, pfvf, BLKADDR_SSOW, lf); 1466 } 1467 1468 rsp->timlfs = pfvf->timlfs; 1469 for (slot = 0; slot < rsp->timlfs; slot++) { 1470 lf = rvu_get_lf(rvu, &hw->block[BLKADDR_TIM], pcifunc, slot); 1471 rsp->timlf_msixoff[slot] = 1472 rvu_get_msix_offset(rvu, pfvf, BLKADDR_TIM, lf); 1473 } 1474 1475 rsp->cptlfs = pfvf->cptlfs; 1476 for (slot = 0; slot < rsp->cptlfs; slot++) { 1477 lf = rvu_get_lf(rvu, &hw->block[BLKADDR_CPT0], pcifunc, slot); 1478 rsp->cptlf_msixoff[slot] = 1479 rvu_get_msix_offset(rvu, pfvf, BLKADDR_CPT0, lf); 1480 } 1481 return 0; 1482 } 1483 1484 int rvu_mbox_handler_vf_flr(struct rvu *rvu, struct msg_req *req, 1485 struct msg_rsp *rsp) 1486 { 1487 u16 pcifunc = req->hdr.pcifunc; 1488 u16 vf, numvfs; 1489 u64 cfg; 1490 1491 vf = pcifunc & RVU_PFVF_FUNC_MASK; 1492 cfg = rvu_read64(rvu, BLKADDR_RVUM, 1493 RVU_PRIV_PFX_CFG(rvu_get_pf(pcifunc))); 1494 numvfs = (cfg >> 12) & 0xFF; 1495 1496 if (vf && vf <= numvfs) 1497 __rvu_flr_handler(rvu, pcifunc); 1498 else 1499 return RVU_INVALID_VF_ID; 1500 1501 return 0; 1502 } 1503 1504 int rvu_mbox_handler_get_hw_cap(struct rvu *rvu, struct msg_req *req, 1505 struct get_hw_cap_rsp *rsp) 1506 { 1507 struct rvu_hwinfo *hw = rvu->hw; 1508 1509 rsp->nix_fixed_txschq_mapping = hw->cap.nix_fixed_txschq_mapping; 1510 rsp->nix_shaping = hw->cap.nix_shaping; 1511 1512 return 0; 1513 } 1514 1515 static int rvu_process_mbox_msg(struct otx2_mbox *mbox, int devid, 1516 struct mbox_msghdr *req) 1517 { 1518 struct rvu *rvu = pci_get_drvdata(mbox->pdev); 1519 1520 /* Check if valid, if not reply with a invalid msg */ 1521 if (req->sig != OTX2_MBOX_REQ_SIG) 1522 goto bad_message; 1523 1524 switch (req->id) { 1525 #define M(_name, _id, _fn_name, _req_type, _rsp_type) \ 1526 case _id: { \ 1527 struct _rsp_type *rsp; \ 1528 int err; \ 1529 \ 1530 rsp = (struct _rsp_type *)otx2_mbox_alloc_msg( \ 1531 mbox, devid, \ 1532 sizeof(struct _rsp_type)); \ 1533 /* some handlers should complete even if reply */ \ 1534 /* could not be allocated */ \ 1535 if (!rsp && \ 1536 _id != MBOX_MSG_DETACH_RESOURCES && \ 1537 _id != MBOX_MSG_NIX_TXSCH_FREE && \ 1538 _id != MBOX_MSG_VF_FLR) \ 1539 return -ENOMEM; \ 1540 if (rsp) { \ 1541 rsp->hdr.id = _id; \ 1542 rsp->hdr.sig = OTX2_MBOX_RSP_SIG; \ 1543 rsp->hdr.pcifunc = req->pcifunc; \ 1544 rsp->hdr.rc = 0; \ 1545 } \ 1546 \ 1547 err = rvu_mbox_handler_ ## _fn_name(rvu, \ 1548 (struct _req_type *)req, \ 1549 rsp); \ 1550 if (rsp && err) \ 1551 rsp->hdr.rc = err; \ 1552 \ 1553 return rsp ? err : -ENOMEM; \ 1554 } 1555 MBOX_MESSAGES 1556 #undef M 1557 1558 bad_message: 1559 default: 1560 otx2_reply_invalid_msg(mbox, devid, req->pcifunc, req->id); 1561 return -ENODEV; 1562 } 1563 } 1564 1565 static void __rvu_mbox_handler(struct rvu_work *mwork, int type) 1566 { 1567 struct rvu *rvu = mwork->rvu; 1568 int offset, err, id, devid; 1569 struct otx2_mbox_dev *mdev; 1570 struct mbox_hdr *req_hdr; 1571 struct mbox_msghdr *msg; 1572 struct mbox_wq_info *mw; 1573 struct otx2_mbox *mbox; 1574 1575 switch (type) { 1576 case TYPE_AFPF: 1577 mw = &rvu->afpf_wq_info; 1578 break; 1579 case TYPE_AFVF: 1580 mw = &rvu->afvf_wq_info; 1581 break; 1582 default: 1583 return; 1584 } 1585 1586 devid = mwork - mw->mbox_wrk; 1587 mbox = &mw->mbox; 1588 mdev = &mbox->dev[devid]; 1589 1590 /* Process received mbox messages */ 1591 req_hdr = mdev->mbase + mbox->rx_start; 1592 if (mw->mbox_wrk[devid].num_msgs == 0) 1593 return; 1594 1595 offset = mbox->rx_start + ALIGN(sizeof(*req_hdr), MBOX_MSG_ALIGN); 1596 1597 for (id = 0; id < mw->mbox_wrk[devid].num_msgs; id++) { 1598 msg = mdev->mbase + offset; 1599 1600 /* Set which PF/VF sent this message based on mbox IRQ */ 1601 switch (type) { 1602 case TYPE_AFPF: 1603 msg->pcifunc &= 1604 ~(RVU_PFVF_PF_MASK << RVU_PFVF_PF_SHIFT); 1605 msg->pcifunc |= (devid << RVU_PFVF_PF_SHIFT); 1606 break; 1607 case TYPE_AFVF: 1608 msg->pcifunc &= 1609 ~(RVU_PFVF_FUNC_MASK << RVU_PFVF_FUNC_SHIFT); 1610 msg->pcifunc |= (devid << RVU_PFVF_FUNC_SHIFT) + 1; 1611 break; 1612 } 1613 1614 err = rvu_process_mbox_msg(mbox, devid, msg); 1615 if (!err) { 1616 offset = mbox->rx_start + msg->next_msgoff; 1617 continue; 1618 } 1619 1620 if (msg->pcifunc & RVU_PFVF_FUNC_MASK) 1621 dev_warn(rvu->dev, "Error %d when processing message %s (0x%x) from PF%d:VF%d\n", 1622 err, otx2_mbox_id2name(msg->id), 1623 msg->id, rvu_get_pf(msg->pcifunc), 1624 (msg->pcifunc & RVU_PFVF_FUNC_MASK) - 1); 1625 else 1626 dev_warn(rvu->dev, "Error %d when processing message %s (0x%x) from PF%d\n", 1627 err, otx2_mbox_id2name(msg->id), 1628 msg->id, devid); 1629 } 1630 mw->mbox_wrk[devid].num_msgs = 0; 1631 1632 /* Send mbox responses to VF/PF */ 1633 otx2_mbox_msg_send(mbox, devid); 1634 } 1635 1636 static inline void rvu_afpf_mbox_handler(struct work_struct *work) 1637 { 1638 struct rvu_work *mwork = container_of(work, struct rvu_work, work); 1639 1640 __rvu_mbox_handler(mwork, TYPE_AFPF); 1641 } 1642 1643 static inline void rvu_afvf_mbox_handler(struct work_struct *work) 1644 { 1645 struct rvu_work *mwork = container_of(work, struct rvu_work, work); 1646 1647 __rvu_mbox_handler(mwork, TYPE_AFVF); 1648 } 1649 1650 static void __rvu_mbox_up_handler(struct rvu_work *mwork, int type) 1651 { 1652 struct rvu *rvu = mwork->rvu; 1653 struct otx2_mbox_dev *mdev; 1654 struct mbox_hdr *rsp_hdr; 1655 struct mbox_msghdr *msg; 1656 struct mbox_wq_info *mw; 1657 struct otx2_mbox *mbox; 1658 int offset, id, devid; 1659 1660 switch (type) { 1661 case TYPE_AFPF: 1662 mw = &rvu->afpf_wq_info; 1663 break; 1664 case TYPE_AFVF: 1665 mw = &rvu->afvf_wq_info; 1666 break; 1667 default: 1668 return; 1669 } 1670 1671 devid = mwork - mw->mbox_wrk_up; 1672 mbox = &mw->mbox_up; 1673 mdev = &mbox->dev[devid]; 1674 1675 rsp_hdr = mdev->mbase + mbox->rx_start; 1676 if (mw->mbox_wrk_up[devid].up_num_msgs == 0) { 1677 dev_warn(rvu->dev, "mbox up handler: num_msgs = 0\n"); 1678 return; 1679 } 1680 1681 offset = mbox->rx_start + ALIGN(sizeof(*rsp_hdr), MBOX_MSG_ALIGN); 1682 1683 for (id = 0; id < mw->mbox_wrk_up[devid].up_num_msgs; id++) { 1684 msg = mdev->mbase + offset; 1685 1686 if (msg->id >= MBOX_MSG_MAX) { 1687 dev_err(rvu->dev, 1688 "Mbox msg with unknown ID 0x%x\n", msg->id); 1689 goto end; 1690 } 1691 1692 if (msg->sig != OTX2_MBOX_RSP_SIG) { 1693 dev_err(rvu->dev, 1694 "Mbox msg with wrong signature %x, ID 0x%x\n", 1695 msg->sig, msg->id); 1696 goto end; 1697 } 1698 1699 switch (msg->id) { 1700 case MBOX_MSG_CGX_LINK_EVENT: 1701 break; 1702 default: 1703 if (msg->rc) 1704 dev_err(rvu->dev, 1705 "Mbox msg response has err %d, ID 0x%x\n", 1706 msg->rc, msg->id); 1707 break; 1708 } 1709 end: 1710 offset = mbox->rx_start + msg->next_msgoff; 1711 mdev->msgs_acked++; 1712 } 1713 mw->mbox_wrk_up[devid].up_num_msgs = 0; 1714 1715 otx2_mbox_reset(mbox, devid); 1716 } 1717 1718 static inline void rvu_afpf_mbox_up_handler(struct work_struct *work) 1719 { 1720 struct rvu_work *mwork = container_of(work, struct rvu_work, work); 1721 1722 __rvu_mbox_up_handler(mwork, TYPE_AFPF); 1723 } 1724 1725 static inline void rvu_afvf_mbox_up_handler(struct work_struct *work) 1726 { 1727 struct rvu_work *mwork = container_of(work, struct rvu_work, work); 1728 1729 __rvu_mbox_up_handler(mwork, TYPE_AFVF); 1730 } 1731 1732 static int rvu_mbox_init(struct rvu *rvu, struct mbox_wq_info *mw, 1733 int type, int num, 1734 void (mbox_handler)(struct work_struct *), 1735 void (mbox_up_handler)(struct work_struct *)) 1736 { 1737 void __iomem *hwbase = NULL, *reg_base; 1738 int err, i, dir, dir_up; 1739 struct rvu_work *mwork; 1740 const char *name; 1741 u64 bar4_addr; 1742 1743 switch (type) { 1744 case TYPE_AFPF: 1745 name = "rvu_afpf_mailbox"; 1746 bar4_addr = rvu_read64(rvu, BLKADDR_RVUM, RVU_AF_PF_BAR4_ADDR); 1747 dir = MBOX_DIR_AFPF; 1748 dir_up = MBOX_DIR_AFPF_UP; 1749 reg_base = rvu->afreg_base; 1750 break; 1751 case TYPE_AFVF: 1752 name = "rvu_afvf_mailbox"; 1753 bar4_addr = rvupf_read64(rvu, RVU_PF_VF_BAR4_ADDR); 1754 dir = MBOX_DIR_PFVF; 1755 dir_up = MBOX_DIR_PFVF_UP; 1756 reg_base = rvu->pfreg_base; 1757 break; 1758 default: 1759 return -EINVAL; 1760 } 1761 1762 mw->mbox_wq = alloc_workqueue(name, 1763 WQ_UNBOUND | WQ_HIGHPRI | WQ_MEM_RECLAIM, 1764 num); 1765 if (!mw->mbox_wq) 1766 return -ENOMEM; 1767 1768 mw->mbox_wrk = devm_kcalloc(rvu->dev, num, 1769 sizeof(struct rvu_work), GFP_KERNEL); 1770 if (!mw->mbox_wrk) { 1771 err = -ENOMEM; 1772 goto exit; 1773 } 1774 1775 mw->mbox_wrk_up = devm_kcalloc(rvu->dev, num, 1776 sizeof(struct rvu_work), GFP_KERNEL); 1777 if (!mw->mbox_wrk_up) { 1778 err = -ENOMEM; 1779 goto exit; 1780 } 1781 1782 /* Mailbox is a reserved memory (in RAM) region shared between 1783 * RVU devices, shouldn't be mapped as device memory to allow 1784 * unaligned accesses. 1785 */ 1786 hwbase = ioremap_wc(bar4_addr, MBOX_SIZE * num); 1787 if (!hwbase) { 1788 dev_err(rvu->dev, "Unable to map mailbox region\n"); 1789 err = -ENOMEM; 1790 goto exit; 1791 } 1792 1793 err = otx2_mbox_init(&mw->mbox, hwbase, rvu->pdev, reg_base, dir, num); 1794 if (err) 1795 goto exit; 1796 1797 err = otx2_mbox_init(&mw->mbox_up, hwbase, rvu->pdev, 1798 reg_base, dir_up, num); 1799 if (err) 1800 goto exit; 1801 1802 for (i = 0; i < num; i++) { 1803 mwork = &mw->mbox_wrk[i]; 1804 mwork->rvu = rvu; 1805 INIT_WORK(&mwork->work, mbox_handler); 1806 1807 mwork = &mw->mbox_wrk_up[i]; 1808 mwork->rvu = rvu; 1809 INIT_WORK(&mwork->work, mbox_up_handler); 1810 } 1811 1812 return 0; 1813 exit: 1814 if (hwbase) 1815 iounmap((void __iomem *)hwbase); 1816 destroy_workqueue(mw->mbox_wq); 1817 return err; 1818 } 1819 1820 static void rvu_mbox_destroy(struct mbox_wq_info *mw) 1821 { 1822 if (mw->mbox_wq) { 1823 flush_workqueue(mw->mbox_wq); 1824 destroy_workqueue(mw->mbox_wq); 1825 mw->mbox_wq = NULL; 1826 } 1827 1828 if (mw->mbox.hwbase) 1829 iounmap((void __iomem *)mw->mbox.hwbase); 1830 1831 otx2_mbox_destroy(&mw->mbox); 1832 otx2_mbox_destroy(&mw->mbox_up); 1833 } 1834 1835 static void rvu_queue_work(struct mbox_wq_info *mw, int first, 1836 int mdevs, u64 intr) 1837 { 1838 struct otx2_mbox_dev *mdev; 1839 struct otx2_mbox *mbox; 1840 struct mbox_hdr *hdr; 1841 int i; 1842 1843 for (i = first; i < mdevs; i++) { 1844 /* start from 0 */ 1845 if (!(intr & BIT_ULL(i - first))) 1846 continue; 1847 1848 mbox = &mw->mbox; 1849 mdev = &mbox->dev[i]; 1850 hdr = mdev->mbase + mbox->rx_start; 1851 1852 /*The hdr->num_msgs is set to zero immediately in the interrupt 1853 * handler to ensure that it holds a correct value next time 1854 * when the interrupt handler is called. 1855 * pf->mbox.num_msgs holds the data for use in pfaf_mbox_handler 1856 * pf>mbox.up_num_msgs holds the data for use in 1857 * pfaf_mbox_up_handler. 1858 */ 1859 1860 if (hdr->num_msgs) { 1861 mw->mbox_wrk[i].num_msgs = hdr->num_msgs; 1862 hdr->num_msgs = 0; 1863 queue_work(mw->mbox_wq, &mw->mbox_wrk[i].work); 1864 } 1865 mbox = &mw->mbox_up; 1866 mdev = &mbox->dev[i]; 1867 hdr = mdev->mbase + mbox->rx_start; 1868 if (hdr->num_msgs) { 1869 mw->mbox_wrk_up[i].up_num_msgs = hdr->num_msgs; 1870 hdr->num_msgs = 0; 1871 queue_work(mw->mbox_wq, &mw->mbox_wrk_up[i].work); 1872 } 1873 } 1874 } 1875 1876 static irqreturn_t rvu_mbox_intr_handler(int irq, void *rvu_irq) 1877 { 1878 struct rvu *rvu = (struct rvu *)rvu_irq; 1879 int vfs = rvu->vfs; 1880 u64 intr; 1881 1882 intr = rvu_read64(rvu, BLKADDR_RVUM, RVU_AF_PFAF_MBOX_INT); 1883 /* Clear interrupts */ 1884 rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_PFAF_MBOX_INT, intr); 1885 1886 /* Sync with mbox memory region */ 1887 rmb(); 1888 1889 rvu_queue_work(&rvu->afpf_wq_info, 0, rvu->hw->total_pfs, intr); 1890 1891 /* Handle VF interrupts */ 1892 if (vfs > 64) { 1893 intr = rvupf_read64(rvu, RVU_PF_VFPF_MBOX_INTX(1)); 1894 rvupf_write64(rvu, RVU_PF_VFPF_MBOX_INTX(1), intr); 1895 1896 rvu_queue_work(&rvu->afvf_wq_info, 64, vfs, intr); 1897 vfs -= 64; 1898 } 1899 1900 intr = rvupf_read64(rvu, RVU_PF_VFPF_MBOX_INTX(0)); 1901 rvupf_write64(rvu, RVU_PF_VFPF_MBOX_INTX(0), intr); 1902 1903 rvu_queue_work(&rvu->afvf_wq_info, 0, vfs, intr); 1904 1905 return IRQ_HANDLED; 1906 } 1907 1908 static void rvu_enable_mbox_intr(struct rvu *rvu) 1909 { 1910 struct rvu_hwinfo *hw = rvu->hw; 1911 1912 /* Clear spurious irqs, if any */ 1913 rvu_write64(rvu, BLKADDR_RVUM, 1914 RVU_AF_PFAF_MBOX_INT, INTR_MASK(hw->total_pfs)); 1915 1916 /* Enable mailbox interrupt for all PFs except PF0 i.e AF itself */ 1917 rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_PFAF_MBOX_INT_ENA_W1S, 1918 INTR_MASK(hw->total_pfs) & ~1ULL); 1919 } 1920 1921 static void rvu_blklf_teardown(struct rvu *rvu, u16 pcifunc, u8 blkaddr) 1922 { 1923 struct rvu_block *block; 1924 int slot, lf, num_lfs; 1925 int err; 1926 1927 block = &rvu->hw->block[blkaddr]; 1928 num_lfs = rvu_get_rsrc_mapcount(rvu_get_pfvf(rvu, pcifunc), 1929 block->type); 1930 if (!num_lfs) 1931 return; 1932 for (slot = 0; slot < num_lfs; slot++) { 1933 lf = rvu_get_lf(rvu, block, pcifunc, slot); 1934 if (lf < 0) 1935 continue; 1936 1937 /* Cleanup LF and reset it */ 1938 if (block->addr == BLKADDR_NIX0) 1939 rvu_nix_lf_teardown(rvu, pcifunc, block->addr, lf); 1940 else if (block->addr == BLKADDR_NPA) 1941 rvu_npa_lf_teardown(rvu, pcifunc, lf); 1942 1943 err = rvu_lf_reset(rvu, block, lf); 1944 if (err) { 1945 dev_err(rvu->dev, "Failed to reset blkaddr %d LF%d\n", 1946 block->addr, lf); 1947 } 1948 } 1949 } 1950 1951 static void __rvu_flr_handler(struct rvu *rvu, u16 pcifunc) 1952 { 1953 mutex_lock(&rvu->flr_lock); 1954 /* Reset order should reflect inter-block dependencies: 1955 * 1. Reset any packet/work sources (NIX, CPT, TIM) 1956 * 2. Flush and reset SSO/SSOW 1957 * 3. Cleanup pools (NPA) 1958 */ 1959 rvu_blklf_teardown(rvu, pcifunc, BLKADDR_NIX0); 1960 rvu_blklf_teardown(rvu, pcifunc, BLKADDR_CPT0); 1961 rvu_blklf_teardown(rvu, pcifunc, BLKADDR_TIM); 1962 rvu_blklf_teardown(rvu, pcifunc, BLKADDR_SSOW); 1963 rvu_blklf_teardown(rvu, pcifunc, BLKADDR_SSO); 1964 rvu_blklf_teardown(rvu, pcifunc, BLKADDR_NPA); 1965 rvu_detach_rsrcs(rvu, NULL, pcifunc); 1966 mutex_unlock(&rvu->flr_lock); 1967 } 1968 1969 static void rvu_afvf_flr_handler(struct rvu *rvu, int vf) 1970 { 1971 int reg = 0; 1972 1973 /* pcifunc = 0(PF0) | (vf + 1) */ 1974 __rvu_flr_handler(rvu, vf + 1); 1975 1976 if (vf >= 64) { 1977 reg = 1; 1978 vf = vf - 64; 1979 } 1980 1981 /* Signal FLR finish and enable IRQ */ 1982 rvupf_write64(rvu, RVU_PF_VFTRPENDX(reg), BIT_ULL(vf)); 1983 rvupf_write64(rvu, RVU_PF_VFFLR_INT_ENA_W1SX(reg), BIT_ULL(vf)); 1984 } 1985 1986 static void rvu_flr_handler(struct work_struct *work) 1987 { 1988 struct rvu_work *flrwork = container_of(work, struct rvu_work, work); 1989 struct rvu *rvu = flrwork->rvu; 1990 u16 pcifunc, numvfs, vf; 1991 u64 cfg; 1992 int pf; 1993 1994 pf = flrwork - rvu->flr_wrk; 1995 if (pf >= rvu->hw->total_pfs) { 1996 rvu_afvf_flr_handler(rvu, pf - rvu->hw->total_pfs); 1997 return; 1998 } 1999 2000 cfg = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_PFX_CFG(pf)); 2001 numvfs = (cfg >> 12) & 0xFF; 2002 pcifunc = pf << RVU_PFVF_PF_SHIFT; 2003 2004 for (vf = 0; vf < numvfs; vf++) 2005 __rvu_flr_handler(rvu, (pcifunc | (vf + 1))); 2006 2007 __rvu_flr_handler(rvu, pcifunc); 2008 2009 /* Signal FLR finish */ 2010 rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_PFTRPEND, BIT_ULL(pf)); 2011 2012 /* Enable interrupt */ 2013 rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_PFFLR_INT_ENA_W1S, BIT_ULL(pf)); 2014 } 2015 2016 static void rvu_afvf_queue_flr_work(struct rvu *rvu, int start_vf, int numvfs) 2017 { 2018 int dev, vf, reg = 0; 2019 u64 intr; 2020 2021 if (start_vf >= 64) 2022 reg = 1; 2023 2024 intr = rvupf_read64(rvu, RVU_PF_VFFLR_INTX(reg)); 2025 if (!intr) 2026 return; 2027 2028 for (vf = 0; vf < numvfs; vf++) { 2029 if (!(intr & BIT_ULL(vf))) 2030 continue; 2031 dev = vf + start_vf + rvu->hw->total_pfs; 2032 queue_work(rvu->flr_wq, &rvu->flr_wrk[dev].work); 2033 /* Clear and disable the interrupt */ 2034 rvupf_write64(rvu, RVU_PF_VFFLR_INTX(reg), BIT_ULL(vf)); 2035 rvupf_write64(rvu, RVU_PF_VFFLR_INT_ENA_W1CX(reg), BIT_ULL(vf)); 2036 } 2037 } 2038 2039 static irqreturn_t rvu_flr_intr_handler(int irq, void *rvu_irq) 2040 { 2041 struct rvu *rvu = (struct rvu *)rvu_irq; 2042 u64 intr; 2043 u8 pf; 2044 2045 intr = rvu_read64(rvu, BLKADDR_RVUM, RVU_AF_PFFLR_INT); 2046 if (!intr) 2047 goto afvf_flr; 2048 2049 for (pf = 0; pf < rvu->hw->total_pfs; pf++) { 2050 if (intr & (1ULL << pf)) { 2051 /* PF is already dead do only AF related operations */ 2052 queue_work(rvu->flr_wq, &rvu->flr_wrk[pf].work); 2053 /* clear interrupt */ 2054 rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_PFFLR_INT, 2055 BIT_ULL(pf)); 2056 /* Disable the interrupt */ 2057 rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_PFFLR_INT_ENA_W1C, 2058 BIT_ULL(pf)); 2059 } 2060 } 2061 2062 afvf_flr: 2063 rvu_afvf_queue_flr_work(rvu, 0, 64); 2064 if (rvu->vfs > 64) 2065 rvu_afvf_queue_flr_work(rvu, 64, rvu->vfs - 64); 2066 2067 return IRQ_HANDLED; 2068 } 2069 2070 static void rvu_me_handle_vfset(struct rvu *rvu, int idx, u64 intr) 2071 { 2072 int vf; 2073 2074 /* Nothing to be done here other than clearing the 2075 * TRPEND bit. 2076 */ 2077 for (vf = 0; vf < 64; vf++) { 2078 if (intr & (1ULL << vf)) { 2079 /* clear the trpend due to ME(master enable) */ 2080 rvupf_write64(rvu, RVU_PF_VFTRPENDX(idx), BIT_ULL(vf)); 2081 /* clear interrupt */ 2082 rvupf_write64(rvu, RVU_PF_VFME_INTX(idx), BIT_ULL(vf)); 2083 } 2084 } 2085 } 2086 2087 /* Handles ME interrupts from VFs of AF */ 2088 static irqreturn_t rvu_me_vf_intr_handler(int irq, void *rvu_irq) 2089 { 2090 struct rvu *rvu = (struct rvu *)rvu_irq; 2091 int vfset; 2092 u64 intr; 2093 2094 intr = rvu_read64(rvu, BLKADDR_RVUM, RVU_AF_PFME_INT); 2095 2096 for (vfset = 0; vfset <= 1; vfset++) { 2097 intr = rvupf_read64(rvu, RVU_PF_VFME_INTX(vfset)); 2098 if (intr) 2099 rvu_me_handle_vfset(rvu, vfset, intr); 2100 } 2101 2102 return IRQ_HANDLED; 2103 } 2104 2105 /* Handles ME interrupts from PFs */ 2106 static irqreturn_t rvu_me_pf_intr_handler(int irq, void *rvu_irq) 2107 { 2108 struct rvu *rvu = (struct rvu *)rvu_irq; 2109 u64 intr; 2110 u8 pf; 2111 2112 intr = rvu_read64(rvu, BLKADDR_RVUM, RVU_AF_PFME_INT); 2113 2114 /* Nothing to be done here other than clearing the 2115 * TRPEND bit. 2116 */ 2117 for (pf = 0; pf < rvu->hw->total_pfs; pf++) { 2118 if (intr & (1ULL << pf)) { 2119 /* clear the trpend due to ME(master enable) */ 2120 rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_PFTRPEND, 2121 BIT_ULL(pf)); 2122 /* clear interrupt */ 2123 rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_PFME_INT, 2124 BIT_ULL(pf)); 2125 } 2126 } 2127 2128 return IRQ_HANDLED; 2129 } 2130 2131 static void rvu_unregister_interrupts(struct rvu *rvu) 2132 { 2133 int irq; 2134 2135 /* Disable the Mbox interrupt */ 2136 rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_PFAF_MBOX_INT_ENA_W1C, 2137 INTR_MASK(rvu->hw->total_pfs) & ~1ULL); 2138 2139 /* Disable the PF FLR interrupt */ 2140 rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_PFFLR_INT_ENA_W1C, 2141 INTR_MASK(rvu->hw->total_pfs) & ~1ULL); 2142 2143 /* Disable the PF ME interrupt */ 2144 rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_PFME_INT_ENA_W1C, 2145 INTR_MASK(rvu->hw->total_pfs) & ~1ULL); 2146 2147 for (irq = 0; irq < rvu->num_vec; irq++) { 2148 if (rvu->irq_allocated[irq]) 2149 free_irq(pci_irq_vector(rvu->pdev, irq), rvu); 2150 } 2151 2152 pci_free_irq_vectors(rvu->pdev); 2153 rvu->num_vec = 0; 2154 } 2155 2156 static int rvu_afvf_msix_vectors_num_ok(struct rvu *rvu) 2157 { 2158 struct rvu_pfvf *pfvf = &rvu->pf[0]; 2159 int offset; 2160 2161 pfvf = &rvu->pf[0]; 2162 offset = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_PFX_INT_CFG(0)) & 0x3ff; 2163 2164 /* Make sure there are enough MSIX vectors configured so that 2165 * VF interrupts can be handled. Offset equal to zero means 2166 * that PF vectors are not configured and overlapping AF vectors. 2167 */ 2168 return (pfvf->msix.max >= RVU_AF_INT_VEC_CNT + RVU_PF_INT_VEC_CNT) && 2169 offset; 2170 } 2171 2172 static int rvu_register_interrupts(struct rvu *rvu) 2173 { 2174 int ret, offset, pf_vec_start; 2175 2176 rvu->num_vec = pci_msix_vec_count(rvu->pdev); 2177 2178 rvu->irq_name = devm_kmalloc_array(rvu->dev, rvu->num_vec, 2179 NAME_SIZE, GFP_KERNEL); 2180 if (!rvu->irq_name) 2181 return -ENOMEM; 2182 2183 rvu->irq_allocated = devm_kcalloc(rvu->dev, rvu->num_vec, 2184 sizeof(bool), GFP_KERNEL); 2185 if (!rvu->irq_allocated) 2186 return -ENOMEM; 2187 2188 /* Enable MSI-X */ 2189 ret = pci_alloc_irq_vectors(rvu->pdev, rvu->num_vec, 2190 rvu->num_vec, PCI_IRQ_MSIX); 2191 if (ret < 0) { 2192 dev_err(rvu->dev, 2193 "RVUAF: Request for %d msix vectors failed, ret %d\n", 2194 rvu->num_vec, ret); 2195 return ret; 2196 } 2197 2198 /* Register mailbox interrupt handler */ 2199 sprintf(&rvu->irq_name[RVU_AF_INT_VEC_MBOX * NAME_SIZE], "RVUAF Mbox"); 2200 ret = request_irq(pci_irq_vector(rvu->pdev, RVU_AF_INT_VEC_MBOX), 2201 rvu_mbox_intr_handler, 0, 2202 &rvu->irq_name[RVU_AF_INT_VEC_MBOX * NAME_SIZE], rvu); 2203 if (ret) { 2204 dev_err(rvu->dev, 2205 "RVUAF: IRQ registration failed for mbox irq\n"); 2206 goto fail; 2207 } 2208 2209 rvu->irq_allocated[RVU_AF_INT_VEC_MBOX] = true; 2210 2211 /* Enable mailbox interrupts from all PFs */ 2212 rvu_enable_mbox_intr(rvu); 2213 2214 /* Register FLR interrupt handler */ 2215 sprintf(&rvu->irq_name[RVU_AF_INT_VEC_PFFLR * NAME_SIZE], 2216 "RVUAF FLR"); 2217 ret = request_irq(pci_irq_vector(rvu->pdev, RVU_AF_INT_VEC_PFFLR), 2218 rvu_flr_intr_handler, 0, 2219 &rvu->irq_name[RVU_AF_INT_VEC_PFFLR * NAME_SIZE], 2220 rvu); 2221 if (ret) { 2222 dev_err(rvu->dev, 2223 "RVUAF: IRQ registration failed for FLR\n"); 2224 goto fail; 2225 } 2226 rvu->irq_allocated[RVU_AF_INT_VEC_PFFLR] = true; 2227 2228 /* Enable FLR interrupt for all PFs*/ 2229 rvu_write64(rvu, BLKADDR_RVUM, 2230 RVU_AF_PFFLR_INT, INTR_MASK(rvu->hw->total_pfs)); 2231 2232 rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_PFFLR_INT_ENA_W1S, 2233 INTR_MASK(rvu->hw->total_pfs) & ~1ULL); 2234 2235 /* Register ME interrupt handler */ 2236 sprintf(&rvu->irq_name[RVU_AF_INT_VEC_PFME * NAME_SIZE], 2237 "RVUAF ME"); 2238 ret = request_irq(pci_irq_vector(rvu->pdev, RVU_AF_INT_VEC_PFME), 2239 rvu_me_pf_intr_handler, 0, 2240 &rvu->irq_name[RVU_AF_INT_VEC_PFME * NAME_SIZE], 2241 rvu); 2242 if (ret) { 2243 dev_err(rvu->dev, 2244 "RVUAF: IRQ registration failed for ME\n"); 2245 } 2246 rvu->irq_allocated[RVU_AF_INT_VEC_PFME] = true; 2247 2248 /* Clear TRPEND bit for all PF */ 2249 rvu_write64(rvu, BLKADDR_RVUM, 2250 RVU_AF_PFTRPEND, INTR_MASK(rvu->hw->total_pfs)); 2251 /* Enable ME interrupt for all PFs*/ 2252 rvu_write64(rvu, BLKADDR_RVUM, 2253 RVU_AF_PFME_INT, INTR_MASK(rvu->hw->total_pfs)); 2254 2255 rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_PFME_INT_ENA_W1S, 2256 INTR_MASK(rvu->hw->total_pfs) & ~1ULL); 2257 2258 if (!rvu_afvf_msix_vectors_num_ok(rvu)) 2259 return 0; 2260 2261 /* Get PF MSIX vectors offset. */ 2262 pf_vec_start = rvu_read64(rvu, BLKADDR_RVUM, 2263 RVU_PRIV_PFX_INT_CFG(0)) & 0x3ff; 2264 2265 /* Register MBOX0 interrupt. */ 2266 offset = pf_vec_start + RVU_PF_INT_VEC_VFPF_MBOX0; 2267 sprintf(&rvu->irq_name[offset * NAME_SIZE], "RVUAFVF Mbox0"); 2268 ret = request_irq(pci_irq_vector(rvu->pdev, offset), 2269 rvu_mbox_intr_handler, 0, 2270 &rvu->irq_name[offset * NAME_SIZE], 2271 rvu); 2272 if (ret) 2273 dev_err(rvu->dev, 2274 "RVUAF: IRQ registration failed for Mbox0\n"); 2275 2276 rvu->irq_allocated[offset] = true; 2277 2278 /* Register MBOX1 interrupt. MBOX1 IRQ number follows MBOX0 so 2279 * simply increment current offset by 1. 2280 */ 2281 offset = pf_vec_start + RVU_PF_INT_VEC_VFPF_MBOX1; 2282 sprintf(&rvu->irq_name[offset * NAME_SIZE], "RVUAFVF Mbox1"); 2283 ret = request_irq(pci_irq_vector(rvu->pdev, offset), 2284 rvu_mbox_intr_handler, 0, 2285 &rvu->irq_name[offset * NAME_SIZE], 2286 rvu); 2287 if (ret) 2288 dev_err(rvu->dev, 2289 "RVUAF: IRQ registration failed for Mbox1\n"); 2290 2291 rvu->irq_allocated[offset] = true; 2292 2293 /* Register FLR interrupt handler for AF's VFs */ 2294 offset = pf_vec_start + RVU_PF_INT_VEC_VFFLR0; 2295 sprintf(&rvu->irq_name[offset * NAME_SIZE], "RVUAFVF FLR0"); 2296 ret = request_irq(pci_irq_vector(rvu->pdev, offset), 2297 rvu_flr_intr_handler, 0, 2298 &rvu->irq_name[offset * NAME_SIZE], rvu); 2299 if (ret) { 2300 dev_err(rvu->dev, 2301 "RVUAF: IRQ registration failed for RVUAFVF FLR0\n"); 2302 goto fail; 2303 } 2304 rvu->irq_allocated[offset] = true; 2305 2306 offset = pf_vec_start + RVU_PF_INT_VEC_VFFLR1; 2307 sprintf(&rvu->irq_name[offset * NAME_SIZE], "RVUAFVF FLR1"); 2308 ret = request_irq(pci_irq_vector(rvu->pdev, offset), 2309 rvu_flr_intr_handler, 0, 2310 &rvu->irq_name[offset * NAME_SIZE], rvu); 2311 if (ret) { 2312 dev_err(rvu->dev, 2313 "RVUAF: IRQ registration failed for RVUAFVF FLR1\n"); 2314 goto fail; 2315 } 2316 rvu->irq_allocated[offset] = true; 2317 2318 /* Register ME interrupt handler for AF's VFs */ 2319 offset = pf_vec_start + RVU_PF_INT_VEC_VFME0; 2320 sprintf(&rvu->irq_name[offset * NAME_SIZE], "RVUAFVF ME0"); 2321 ret = request_irq(pci_irq_vector(rvu->pdev, offset), 2322 rvu_me_vf_intr_handler, 0, 2323 &rvu->irq_name[offset * NAME_SIZE], rvu); 2324 if (ret) { 2325 dev_err(rvu->dev, 2326 "RVUAF: IRQ registration failed for RVUAFVF ME0\n"); 2327 goto fail; 2328 } 2329 rvu->irq_allocated[offset] = true; 2330 2331 offset = pf_vec_start + RVU_PF_INT_VEC_VFME1; 2332 sprintf(&rvu->irq_name[offset * NAME_SIZE], "RVUAFVF ME1"); 2333 ret = request_irq(pci_irq_vector(rvu->pdev, offset), 2334 rvu_me_vf_intr_handler, 0, 2335 &rvu->irq_name[offset * NAME_SIZE], rvu); 2336 if (ret) { 2337 dev_err(rvu->dev, 2338 "RVUAF: IRQ registration failed for RVUAFVF ME1\n"); 2339 goto fail; 2340 } 2341 rvu->irq_allocated[offset] = true; 2342 return 0; 2343 2344 fail: 2345 rvu_unregister_interrupts(rvu); 2346 return ret; 2347 } 2348 2349 static void rvu_flr_wq_destroy(struct rvu *rvu) 2350 { 2351 if (rvu->flr_wq) { 2352 flush_workqueue(rvu->flr_wq); 2353 destroy_workqueue(rvu->flr_wq); 2354 rvu->flr_wq = NULL; 2355 } 2356 } 2357 2358 static int rvu_flr_init(struct rvu *rvu) 2359 { 2360 int dev, num_devs; 2361 u64 cfg; 2362 int pf; 2363 2364 /* Enable FLR for all PFs*/ 2365 for (pf = 0; pf < rvu->hw->total_pfs; pf++) { 2366 cfg = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_PFX_CFG(pf)); 2367 rvu_write64(rvu, BLKADDR_RVUM, RVU_PRIV_PFX_CFG(pf), 2368 cfg | BIT_ULL(22)); 2369 } 2370 2371 rvu->flr_wq = alloc_workqueue("rvu_afpf_flr", 2372 WQ_UNBOUND | WQ_HIGHPRI | WQ_MEM_RECLAIM, 2373 1); 2374 if (!rvu->flr_wq) 2375 return -ENOMEM; 2376 2377 num_devs = rvu->hw->total_pfs + pci_sriov_get_totalvfs(rvu->pdev); 2378 rvu->flr_wrk = devm_kcalloc(rvu->dev, num_devs, 2379 sizeof(struct rvu_work), GFP_KERNEL); 2380 if (!rvu->flr_wrk) { 2381 destroy_workqueue(rvu->flr_wq); 2382 return -ENOMEM; 2383 } 2384 2385 for (dev = 0; dev < num_devs; dev++) { 2386 rvu->flr_wrk[dev].rvu = rvu; 2387 INIT_WORK(&rvu->flr_wrk[dev].work, rvu_flr_handler); 2388 } 2389 2390 mutex_init(&rvu->flr_lock); 2391 2392 return 0; 2393 } 2394 2395 static void rvu_disable_afvf_intr(struct rvu *rvu) 2396 { 2397 int vfs = rvu->vfs; 2398 2399 rvupf_write64(rvu, RVU_PF_VFPF_MBOX_INT_ENA_W1CX(0), INTR_MASK(vfs)); 2400 rvupf_write64(rvu, RVU_PF_VFFLR_INT_ENA_W1CX(0), INTR_MASK(vfs)); 2401 rvupf_write64(rvu, RVU_PF_VFME_INT_ENA_W1CX(0), INTR_MASK(vfs)); 2402 if (vfs <= 64) 2403 return; 2404 2405 rvupf_write64(rvu, RVU_PF_VFPF_MBOX_INT_ENA_W1CX(1), 2406 INTR_MASK(vfs - 64)); 2407 rvupf_write64(rvu, RVU_PF_VFFLR_INT_ENA_W1CX(1), INTR_MASK(vfs - 64)); 2408 rvupf_write64(rvu, RVU_PF_VFME_INT_ENA_W1CX(1), INTR_MASK(vfs - 64)); 2409 } 2410 2411 static void rvu_enable_afvf_intr(struct rvu *rvu) 2412 { 2413 int vfs = rvu->vfs; 2414 2415 /* Clear any pending interrupts and enable AF VF interrupts for 2416 * the first 64 VFs. 2417 */ 2418 /* Mbox */ 2419 rvupf_write64(rvu, RVU_PF_VFPF_MBOX_INTX(0), INTR_MASK(vfs)); 2420 rvupf_write64(rvu, RVU_PF_VFPF_MBOX_INT_ENA_W1SX(0), INTR_MASK(vfs)); 2421 2422 /* FLR */ 2423 rvupf_write64(rvu, RVU_PF_VFFLR_INTX(0), INTR_MASK(vfs)); 2424 rvupf_write64(rvu, RVU_PF_VFFLR_INT_ENA_W1SX(0), INTR_MASK(vfs)); 2425 rvupf_write64(rvu, RVU_PF_VFME_INT_ENA_W1SX(0), INTR_MASK(vfs)); 2426 2427 /* Same for remaining VFs, if any. */ 2428 if (vfs <= 64) 2429 return; 2430 2431 rvupf_write64(rvu, RVU_PF_VFPF_MBOX_INTX(1), INTR_MASK(vfs - 64)); 2432 rvupf_write64(rvu, RVU_PF_VFPF_MBOX_INT_ENA_W1SX(1), 2433 INTR_MASK(vfs - 64)); 2434 2435 rvupf_write64(rvu, RVU_PF_VFFLR_INTX(1), INTR_MASK(vfs - 64)); 2436 rvupf_write64(rvu, RVU_PF_VFFLR_INT_ENA_W1SX(1), INTR_MASK(vfs - 64)); 2437 rvupf_write64(rvu, RVU_PF_VFME_INT_ENA_W1SX(1), INTR_MASK(vfs - 64)); 2438 } 2439 2440 #define PCI_DEVID_OCTEONTX2_LBK 0xA061 2441 2442 static int lbk_get_num_chans(void) 2443 { 2444 struct pci_dev *pdev; 2445 void __iomem *base; 2446 int ret = -EIO; 2447 2448 pdev = pci_get_device(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_OCTEONTX2_LBK, 2449 NULL); 2450 if (!pdev) 2451 goto err; 2452 2453 base = pci_ioremap_bar(pdev, 0); 2454 if (!base) 2455 goto err_put; 2456 2457 /* Read number of available LBK channels from LBK(0)_CONST register. */ 2458 ret = (readq(base + 0x10) >> 32) & 0xffff; 2459 iounmap(base); 2460 err_put: 2461 pci_dev_put(pdev); 2462 err: 2463 return ret; 2464 } 2465 2466 static int rvu_enable_sriov(struct rvu *rvu) 2467 { 2468 struct pci_dev *pdev = rvu->pdev; 2469 int err, chans, vfs; 2470 2471 if (!rvu_afvf_msix_vectors_num_ok(rvu)) { 2472 dev_warn(&pdev->dev, 2473 "Skipping SRIOV enablement since not enough IRQs are available\n"); 2474 return 0; 2475 } 2476 2477 chans = lbk_get_num_chans(); 2478 if (chans < 0) 2479 return chans; 2480 2481 vfs = pci_sriov_get_totalvfs(pdev); 2482 2483 /* Limit VFs in case we have more VFs than LBK channels available. */ 2484 if (vfs > chans) 2485 vfs = chans; 2486 2487 if (!vfs) 2488 return 0; 2489 2490 /* Save VFs number for reference in VF interrupts handlers. 2491 * Since interrupts might start arriving during SRIOV enablement 2492 * ordinary API cannot be used to get number of enabled VFs. 2493 */ 2494 rvu->vfs = vfs; 2495 2496 err = rvu_mbox_init(rvu, &rvu->afvf_wq_info, TYPE_AFVF, vfs, 2497 rvu_afvf_mbox_handler, rvu_afvf_mbox_up_handler); 2498 if (err) 2499 return err; 2500 2501 rvu_enable_afvf_intr(rvu); 2502 /* Make sure IRQs are enabled before SRIOV. */ 2503 mb(); 2504 2505 err = pci_enable_sriov(pdev, vfs); 2506 if (err) { 2507 rvu_disable_afvf_intr(rvu); 2508 rvu_mbox_destroy(&rvu->afvf_wq_info); 2509 return err; 2510 } 2511 2512 return 0; 2513 } 2514 2515 static void rvu_disable_sriov(struct rvu *rvu) 2516 { 2517 rvu_disable_afvf_intr(rvu); 2518 rvu_mbox_destroy(&rvu->afvf_wq_info); 2519 pci_disable_sriov(rvu->pdev); 2520 } 2521 2522 static void rvu_update_module_params(struct rvu *rvu) 2523 { 2524 const char *default_pfl_name = "default"; 2525 2526 strscpy(rvu->mkex_pfl_name, 2527 mkex_profile ? mkex_profile : default_pfl_name, MKEX_NAME_LEN); 2528 } 2529 2530 static int rvu_probe(struct pci_dev *pdev, const struct pci_device_id *id) 2531 { 2532 struct device *dev = &pdev->dev; 2533 struct rvu *rvu; 2534 int err; 2535 2536 rvu = devm_kzalloc(dev, sizeof(*rvu), GFP_KERNEL); 2537 if (!rvu) 2538 return -ENOMEM; 2539 2540 rvu->hw = devm_kzalloc(dev, sizeof(struct rvu_hwinfo), GFP_KERNEL); 2541 if (!rvu->hw) { 2542 devm_kfree(dev, rvu); 2543 return -ENOMEM; 2544 } 2545 2546 pci_set_drvdata(pdev, rvu); 2547 rvu->pdev = pdev; 2548 rvu->dev = &pdev->dev; 2549 2550 err = pci_enable_device(pdev); 2551 if (err) { 2552 dev_err(dev, "Failed to enable PCI device\n"); 2553 goto err_freemem; 2554 } 2555 2556 err = pci_request_regions(pdev, DRV_NAME); 2557 if (err) { 2558 dev_err(dev, "PCI request regions failed 0x%x\n", err); 2559 goto err_disable_device; 2560 } 2561 2562 err = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(48)); 2563 if (err) { 2564 dev_err(dev, "DMA mask config failed, abort\n"); 2565 goto err_release_regions; 2566 } 2567 2568 pci_set_master(pdev); 2569 2570 /* Map Admin function CSRs */ 2571 rvu->afreg_base = pcim_iomap(pdev, PCI_AF_REG_BAR_NUM, 0); 2572 rvu->pfreg_base = pcim_iomap(pdev, PCI_PF_REG_BAR_NUM, 0); 2573 if (!rvu->afreg_base || !rvu->pfreg_base) { 2574 dev_err(dev, "Unable to map admin function CSRs, aborting\n"); 2575 err = -ENOMEM; 2576 goto err_release_regions; 2577 } 2578 2579 /* Store module params in rvu structure */ 2580 rvu_update_module_params(rvu); 2581 2582 /* Check which blocks the HW supports */ 2583 rvu_check_block_implemented(rvu); 2584 2585 rvu_reset_all_blocks(rvu); 2586 2587 rvu_setup_hw_capabilities(rvu); 2588 2589 err = rvu_setup_hw_resources(rvu); 2590 if (err) 2591 goto err_release_regions; 2592 2593 /* Init mailbox btw AF and PFs */ 2594 err = rvu_mbox_init(rvu, &rvu->afpf_wq_info, TYPE_AFPF, 2595 rvu->hw->total_pfs, rvu_afpf_mbox_handler, 2596 rvu_afpf_mbox_up_handler); 2597 if (err) 2598 goto err_hwsetup; 2599 2600 err = rvu_flr_init(rvu); 2601 if (err) 2602 goto err_mbox; 2603 2604 err = rvu_register_interrupts(rvu); 2605 if (err) 2606 goto err_flr; 2607 2608 rvu_setup_rvum_blk_revid(rvu); 2609 2610 /* Enable AF's VFs (if any) */ 2611 err = rvu_enable_sriov(rvu); 2612 if (err) 2613 goto err_irq; 2614 2615 /* Initialize debugfs */ 2616 rvu_dbg_init(rvu); 2617 2618 return 0; 2619 err_irq: 2620 rvu_unregister_interrupts(rvu); 2621 err_flr: 2622 rvu_flr_wq_destroy(rvu); 2623 err_mbox: 2624 rvu_mbox_destroy(&rvu->afpf_wq_info); 2625 err_hwsetup: 2626 rvu_cgx_exit(rvu); 2627 rvu_fwdata_exit(rvu); 2628 rvu_reset_all_blocks(rvu); 2629 rvu_free_hw_resources(rvu); 2630 rvu_clear_rvum_blk_revid(rvu); 2631 err_release_regions: 2632 pci_release_regions(pdev); 2633 err_disable_device: 2634 pci_disable_device(pdev); 2635 err_freemem: 2636 pci_set_drvdata(pdev, NULL); 2637 devm_kfree(&pdev->dev, rvu->hw); 2638 devm_kfree(dev, rvu); 2639 return err; 2640 } 2641 2642 static void rvu_remove(struct pci_dev *pdev) 2643 { 2644 struct rvu *rvu = pci_get_drvdata(pdev); 2645 2646 rvu_dbg_exit(rvu); 2647 rvu_unregister_interrupts(rvu); 2648 rvu_flr_wq_destroy(rvu); 2649 rvu_cgx_exit(rvu); 2650 rvu_fwdata_exit(rvu); 2651 rvu_mbox_destroy(&rvu->afpf_wq_info); 2652 rvu_disable_sriov(rvu); 2653 rvu_reset_all_blocks(rvu); 2654 rvu_free_hw_resources(rvu); 2655 rvu_clear_rvum_blk_revid(rvu); 2656 pci_release_regions(pdev); 2657 pci_disable_device(pdev); 2658 pci_set_drvdata(pdev, NULL); 2659 2660 devm_kfree(&pdev->dev, rvu->hw); 2661 devm_kfree(&pdev->dev, rvu); 2662 } 2663 2664 static struct pci_driver rvu_driver = { 2665 .name = DRV_NAME, 2666 .id_table = rvu_id_table, 2667 .probe = rvu_probe, 2668 .remove = rvu_remove, 2669 }; 2670 2671 static int __init rvu_init_module(void) 2672 { 2673 int err; 2674 2675 pr_info("%s: %s\n", DRV_NAME, DRV_STRING); 2676 2677 err = pci_register_driver(&cgx_driver); 2678 if (err < 0) 2679 return err; 2680 2681 err = pci_register_driver(&rvu_driver); 2682 if (err < 0) 2683 pci_unregister_driver(&cgx_driver); 2684 2685 return err; 2686 } 2687 2688 static void __exit rvu_cleanup_module(void) 2689 { 2690 pci_unregister_driver(&rvu_driver); 2691 pci_unregister_driver(&cgx_driver); 2692 } 2693 2694 module_init(rvu_init_module); 2695 module_exit(rvu_cleanup_module); 2696