1 // SPDX-License-Identifier: GPL-2.0 2 /* Marvell OcteonTx2 RVU Admin Function driver 3 * 4 * Copyright (C) 2018 Marvell International Ltd. 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 */ 10 11 #include <linux/module.h> 12 #include <linux/interrupt.h> 13 #include <linux/delay.h> 14 #include <linux/irq.h> 15 #include <linux/pci.h> 16 #include <linux/sysfs.h> 17 18 #include "cgx.h" 19 #include "rvu.h" 20 #include "rvu_reg.h" 21 22 #define DRV_NAME "octeontx2-af" 23 #define DRV_STRING "Marvell OcteonTX2 RVU Admin Function Driver" 24 #define DRV_VERSION "1.0" 25 26 static int rvu_get_hwvf(struct rvu *rvu, int pcifunc); 27 28 static void rvu_set_msix_offset(struct rvu *rvu, struct rvu_pfvf *pfvf, 29 struct rvu_block *block, int lf); 30 static void rvu_clear_msix_offset(struct rvu *rvu, struct rvu_pfvf *pfvf, 31 struct rvu_block *block, int lf); 32 static void __rvu_flr_handler(struct rvu *rvu, u16 pcifunc); 33 34 static int rvu_mbox_init(struct rvu *rvu, struct mbox_wq_info *mw, 35 int type, int num, 36 void (mbox_handler)(struct work_struct *), 37 void (mbox_up_handler)(struct work_struct *)); 38 enum { 39 TYPE_AFVF, 40 TYPE_AFPF, 41 }; 42 43 /* Supported devices */ 44 static const struct pci_device_id rvu_id_table[] = { 45 { PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_OCTEONTX2_RVU_AF) }, 46 { 0, } /* end of table */ 47 }; 48 49 MODULE_AUTHOR("Marvell International Ltd."); 50 MODULE_DESCRIPTION(DRV_STRING); 51 MODULE_LICENSE("GPL v2"); 52 MODULE_VERSION(DRV_VERSION); 53 MODULE_DEVICE_TABLE(pci, rvu_id_table); 54 55 /* Poll a RVU block's register 'offset', for a 'zero' 56 * or 'nonzero' at bits specified by 'mask' 57 */ 58 int rvu_poll_reg(struct rvu *rvu, u64 block, u64 offset, u64 mask, bool zero) 59 { 60 unsigned long timeout = jiffies + usecs_to_jiffies(100); 61 void __iomem *reg; 62 u64 reg_val; 63 64 reg = rvu->afreg_base + ((block << 28) | offset); 65 while (time_before(jiffies, timeout)) { 66 reg_val = readq(reg); 67 if (zero && !(reg_val & mask)) 68 return 0; 69 if (!zero && (reg_val & mask)) 70 return 0; 71 usleep_range(1, 5); 72 timeout--; 73 } 74 return -EBUSY; 75 } 76 77 int rvu_alloc_rsrc(struct rsrc_bmap *rsrc) 78 { 79 int id; 80 81 if (!rsrc->bmap) 82 return -EINVAL; 83 84 id = find_first_zero_bit(rsrc->bmap, rsrc->max); 85 if (id >= rsrc->max) 86 return -ENOSPC; 87 88 __set_bit(id, rsrc->bmap); 89 90 return id; 91 } 92 93 int rvu_alloc_rsrc_contig(struct rsrc_bmap *rsrc, int nrsrc) 94 { 95 int start; 96 97 if (!rsrc->bmap) 98 return -EINVAL; 99 100 start = bitmap_find_next_zero_area(rsrc->bmap, rsrc->max, 0, nrsrc, 0); 101 if (start >= rsrc->max) 102 return -ENOSPC; 103 104 bitmap_set(rsrc->bmap, start, nrsrc); 105 return start; 106 } 107 108 static void rvu_free_rsrc_contig(struct rsrc_bmap *rsrc, int nrsrc, int start) 109 { 110 if (!rsrc->bmap) 111 return; 112 if (start >= rsrc->max) 113 return; 114 115 bitmap_clear(rsrc->bmap, start, nrsrc); 116 } 117 118 bool rvu_rsrc_check_contig(struct rsrc_bmap *rsrc, int nrsrc) 119 { 120 int start; 121 122 if (!rsrc->bmap) 123 return false; 124 125 start = bitmap_find_next_zero_area(rsrc->bmap, rsrc->max, 0, nrsrc, 0); 126 if (start >= rsrc->max) 127 return false; 128 129 return true; 130 } 131 132 void rvu_free_rsrc(struct rsrc_bmap *rsrc, int id) 133 { 134 if (!rsrc->bmap) 135 return; 136 137 __clear_bit(id, rsrc->bmap); 138 } 139 140 int rvu_rsrc_free_count(struct rsrc_bmap *rsrc) 141 { 142 int used; 143 144 if (!rsrc->bmap) 145 return 0; 146 147 used = bitmap_weight(rsrc->bmap, rsrc->max); 148 return (rsrc->max - used); 149 } 150 151 int rvu_alloc_bitmap(struct rsrc_bmap *rsrc) 152 { 153 rsrc->bmap = kcalloc(BITS_TO_LONGS(rsrc->max), 154 sizeof(long), GFP_KERNEL); 155 if (!rsrc->bmap) 156 return -ENOMEM; 157 return 0; 158 } 159 160 /* Get block LF's HW index from a PF_FUNC's block slot number */ 161 int rvu_get_lf(struct rvu *rvu, struct rvu_block *block, u16 pcifunc, u16 slot) 162 { 163 u16 match = 0; 164 int lf; 165 166 mutex_lock(&rvu->rsrc_lock); 167 for (lf = 0; lf < block->lf.max; lf++) { 168 if (block->fn_map[lf] == pcifunc) { 169 if (slot == match) { 170 mutex_unlock(&rvu->rsrc_lock); 171 return lf; 172 } 173 match++; 174 } 175 } 176 mutex_unlock(&rvu->rsrc_lock); 177 return -ENODEV; 178 } 179 180 /* Convert BLOCK_TYPE_E to a BLOCK_ADDR_E. 181 * Some silicon variants of OcteonTX2 supports 182 * multiple blocks of same type. 183 * 184 * @pcifunc has to be zero when no LF is yet attached. 185 */ 186 int rvu_get_blkaddr(struct rvu *rvu, int blktype, u16 pcifunc) 187 { 188 int devnum, blkaddr = -ENODEV; 189 u64 cfg, reg; 190 bool is_pf; 191 192 switch (blktype) { 193 case BLKTYPE_NPC: 194 blkaddr = BLKADDR_NPC; 195 goto exit; 196 case BLKTYPE_NPA: 197 blkaddr = BLKADDR_NPA; 198 goto exit; 199 case BLKTYPE_NIX: 200 /* For now assume NIX0 */ 201 if (!pcifunc) { 202 blkaddr = BLKADDR_NIX0; 203 goto exit; 204 } 205 break; 206 case BLKTYPE_SSO: 207 blkaddr = BLKADDR_SSO; 208 goto exit; 209 case BLKTYPE_SSOW: 210 blkaddr = BLKADDR_SSOW; 211 goto exit; 212 case BLKTYPE_TIM: 213 blkaddr = BLKADDR_TIM; 214 goto exit; 215 case BLKTYPE_CPT: 216 /* For now assume CPT0 */ 217 if (!pcifunc) { 218 blkaddr = BLKADDR_CPT0; 219 goto exit; 220 } 221 break; 222 } 223 224 /* Check if this is a RVU PF or VF */ 225 if (pcifunc & RVU_PFVF_FUNC_MASK) { 226 is_pf = false; 227 devnum = rvu_get_hwvf(rvu, pcifunc); 228 } else { 229 is_pf = true; 230 devnum = rvu_get_pf(pcifunc); 231 } 232 233 /* Check if the 'pcifunc' has a NIX LF from 'BLKADDR_NIX0' */ 234 if (blktype == BLKTYPE_NIX) { 235 reg = is_pf ? RVU_PRIV_PFX_NIX0_CFG : RVU_PRIV_HWVFX_NIX0_CFG; 236 cfg = rvu_read64(rvu, BLKADDR_RVUM, reg | (devnum << 16)); 237 if (cfg) 238 blkaddr = BLKADDR_NIX0; 239 } 240 241 /* Check if the 'pcifunc' has a CPT LF from 'BLKADDR_CPT0' */ 242 if (blktype == BLKTYPE_CPT) { 243 reg = is_pf ? RVU_PRIV_PFX_CPT0_CFG : RVU_PRIV_HWVFX_CPT0_CFG; 244 cfg = rvu_read64(rvu, BLKADDR_RVUM, reg | (devnum << 16)); 245 if (cfg) 246 blkaddr = BLKADDR_CPT0; 247 } 248 249 exit: 250 if (is_block_implemented(rvu->hw, blkaddr)) 251 return blkaddr; 252 return -ENODEV; 253 } 254 255 static void rvu_update_rsrc_map(struct rvu *rvu, struct rvu_pfvf *pfvf, 256 struct rvu_block *block, u16 pcifunc, 257 u16 lf, bool attach) 258 { 259 int devnum, num_lfs = 0; 260 bool is_pf; 261 u64 reg; 262 263 if (lf >= block->lf.max) { 264 dev_err(&rvu->pdev->dev, 265 "%s: FATAL: LF %d is >= %s's max lfs i.e %d\n", 266 __func__, lf, block->name, block->lf.max); 267 return; 268 } 269 270 /* Check if this is for a RVU PF or VF */ 271 if (pcifunc & RVU_PFVF_FUNC_MASK) { 272 is_pf = false; 273 devnum = rvu_get_hwvf(rvu, pcifunc); 274 } else { 275 is_pf = true; 276 devnum = rvu_get_pf(pcifunc); 277 } 278 279 block->fn_map[lf] = attach ? pcifunc : 0; 280 281 switch (block->type) { 282 case BLKTYPE_NPA: 283 pfvf->npalf = attach ? true : false; 284 num_lfs = pfvf->npalf; 285 break; 286 case BLKTYPE_NIX: 287 pfvf->nixlf = attach ? true : false; 288 num_lfs = pfvf->nixlf; 289 break; 290 case BLKTYPE_SSO: 291 attach ? pfvf->sso++ : pfvf->sso--; 292 num_lfs = pfvf->sso; 293 break; 294 case BLKTYPE_SSOW: 295 attach ? pfvf->ssow++ : pfvf->ssow--; 296 num_lfs = pfvf->ssow; 297 break; 298 case BLKTYPE_TIM: 299 attach ? pfvf->timlfs++ : pfvf->timlfs--; 300 num_lfs = pfvf->timlfs; 301 break; 302 case BLKTYPE_CPT: 303 attach ? pfvf->cptlfs++ : pfvf->cptlfs--; 304 num_lfs = pfvf->cptlfs; 305 break; 306 } 307 308 reg = is_pf ? block->pf_lfcnt_reg : block->vf_lfcnt_reg; 309 rvu_write64(rvu, BLKADDR_RVUM, reg | (devnum << 16), num_lfs); 310 } 311 312 inline int rvu_get_pf(u16 pcifunc) 313 { 314 return (pcifunc >> RVU_PFVF_PF_SHIFT) & RVU_PFVF_PF_MASK; 315 } 316 317 void rvu_get_pf_numvfs(struct rvu *rvu, int pf, int *numvfs, int *hwvf) 318 { 319 u64 cfg; 320 321 /* Get numVFs attached to this PF and first HWVF */ 322 cfg = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_PFX_CFG(pf)); 323 *numvfs = (cfg >> 12) & 0xFF; 324 *hwvf = cfg & 0xFFF; 325 } 326 327 static int rvu_get_hwvf(struct rvu *rvu, int pcifunc) 328 { 329 int pf, func; 330 u64 cfg; 331 332 pf = rvu_get_pf(pcifunc); 333 func = pcifunc & RVU_PFVF_FUNC_MASK; 334 335 /* Get first HWVF attached to this PF */ 336 cfg = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_PFX_CFG(pf)); 337 338 return ((cfg & 0xFFF) + func - 1); 339 } 340 341 struct rvu_pfvf *rvu_get_pfvf(struct rvu *rvu, int pcifunc) 342 { 343 /* Check if it is a PF or VF */ 344 if (pcifunc & RVU_PFVF_FUNC_MASK) 345 return &rvu->hwvf[rvu_get_hwvf(rvu, pcifunc)]; 346 else 347 return &rvu->pf[rvu_get_pf(pcifunc)]; 348 } 349 350 static bool is_pf_func_valid(struct rvu *rvu, u16 pcifunc) 351 { 352 int pf, vf, nvfs; 353 u64 cfg; 354 355 pf = rvu_get_pf(pcifunc); 356 if (pf >= rvu->hw->total_pfs) 357 return false; 358 359 if (!(pcifunc & RVU_PFVF_FUNC_MASK)) 360 return true; 361 362 /* Check if VF is within number of VFs attached to this PF */ 363 vf = (pcifunc & RVU_PFVF_FUNC_MASK) - 1; 364 cfg = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_PFX_CFG(pf)); 365 nvfs = (cfg >> 12) & 0xFF; 366 if (vf >= nvfs) 367 return false; 368 369 return true; 370 } 371 372 bool is_block_implemented(struct rvu_hwinfo *hw, int blkaddr) 373 { 374 struct rvu_block *block; 375 376 if (blkaddr < BLKADDR_RVUM || blkaddr >= BLK_COUNT) 377 return false; 378 379 block = &hw->block[blkaddr]; 380 return block->implemented; 381 } 382 383 static void rvu_check_block_implemented(struct rvu *rvu) 384 { 385 struct rvu_hwinfo *hw = rvu->hw; 386 struct rvu_block *block; 387 int blkid; 388 u64 cfg; 389 390 /* For each block check if 'implemented' bit is set */ 391 for (blkid = 0; blkid < BLK_COUNT; blkid++) { 392 block = &hw->block[blkid]; 393 cfg = rvupf_read64(rvu, RVU_PF_BLOCK_ADDRX_DISC(blkid)); 394 if (cfg & BIT_ULL(11)) 395 block->implemented = true; 396 } 397 } 398 399 int rvu_lf_reset(struct rvu *rvu, struct rvu_block *block, int lf) 400 { 401 int err; 402 403 if (!block->implemented) 404 return 0; 405 406 rvu_write64(rvu, block->addr, block->lfreset_reg, lf | BIT_ULL(12)); 407 err = rvu_poll_reg(rvu, block->addr, block->lfreset_reg, BIT_ULL(12), 408 true); 409 return err; 410 } 411 412 static void rvu_block_reset(struct rvu *rvu, int blkaddr, u64 rst_reg) 413 { 414 struct rvu_block *block = &rvu->hw->block[blkaddr]; 415 416 if (!block->implemented) 417 return; 418 419 rvu_write64(rvu, blkaddr, rst_reg, BIT_ULL(0)); 420 rvu_poll_reg(rvu, blkaddr, rst_reg, BIT_ULL(63), true); 421 } 422 423 static void rvu_reset_all_blocks(struct rvu *rvu) 424 { 425 /* Do a HW reset of all RVU blocks */ 426 rvu_block_reset(rvu, BLKADDR_NPA, NPA_AF_BLK_RST); 427 rvu_block_reset(rvu, BLKADDR_NIX0, NIX_AF_BLK_RST); 428 rvu_block_reset(rvu, BLKADDR_NPC, NPC_AF_BLK_RST); 429 rvu_block_reset(rvu, BLKADDR_SSO, SSO_AF_BLK_RST); 430 rvu_block_reset(rvu, BLKADDR_TIM, TIM_AF_BLK_RST); 431 rvu_block_reset(rvu, BLKADDR_CPT0, CPT_AF_BLK_RST); 432 rvu_block_reset(rvu, BLKADDR_NDC0, NDC_AF_BLK_RST); 433 rvu_block_reset(rvu, BLKADDR_NDC1, NDC_AF_BLK_RST); 434 rvu_block_reset(rvu, BLKADDR_NDC2, NDC_AF_BLK_RST); 435 } 436 437 static void rvu_scan_block(struct rvu *rvu, struct rvu_block *block) 438 { 439 struct rvu_pfvf *pfvf; 440 u64 cfg; 441 int lf; 442 443 for (lf = 0; lf < block->lf.max; lf++) { 444 cfg = rvu_read64(rvu, block->addr, 445 block->lfcfg_reg | (lf << block->lfshift)); 446 if (!(cfg & BIT_ULL(63))) 447 continue; 448 449 /* Set this resource as being used */ 450 __set_bit(lf, block->lf.bmap); 451 452 /* Get, to whom this LF is attached */ 453 pfvf = rvu_get_pfvf(rvu, (cfg >> 8) & 0xFFFF); 454 rvu_update_rsrc_map(rvu, pfvf, block, 455 (cfg >> 8) & 0xFFFF, lf, true); 456 457 /* Set start MSIX vector for this LF within this PF/VF */ 458 rvu_set_msix_offset(rvu, pfvf, block, lf); 459 } 460 } 461 462 static void rvu_check_min_msix_vec(struct rvu *rvu, int nvecs, int pf, int vf) 463 { 464 int min_vecs; 465 466 if (!vf) 467 goto check_pf; 468 469 if (!nvecs) { 470 dev_warn(rvu->dev, 471 "PF%d:VF%d is configured with zero msix vectors, %d\n", 472 pf, vf - 1, nvecs); 473 } 474 return; 475 476 check_pf: 477 if (pf == 0) 478 min_vecs = RVU_AF_INT_VEC_CNT + RVU_PF_INT_VEC_CNT; 479 else 480 min_vecs = RVU_PF_INT_VEC_CNT; 481 482 if (!(nvecs < min_vecs)) 483 return; 484 dev_warn(rvu->dev, 485 "PF%d is configured with too few vectors, %d, min is %d\n", 486 pf, nvecs, min_vecs); 487 } 488 489 static int rvu_setup_msix_resources(struct rvu *rvu) 490 { 491 struct rvu_hwinfo *hw = rvu->hw; 492 int pf, vf, numvfs, hwvf, err; 493 int nvecs, offset, max_msix; 494 struct rvu_pfvf *pfvf; 495 u64 cfg, phy_addr; 496 dma_addr_t iova; 497 498 for (pf = 0; pf < hw->total_pfs; pf++) { 499 cfg = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_PFX_CFG(pf)); 500 /* If PF is not enabled, nothing to do */ 501 if (!((cfg >> 20) & 0x01)) 502 continue; 503 504 rvu_get_pf_numvfs(rvu, pf, &numvfs, &hwvf); 505 506 pfvf = &rvu->pf[pf]; 507 /* Get num of MSIX vectors attached to this PF */ 508 cfg = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_PFX_MSIX_CFG(pf)); 509 pfvf->msix.max = ((cfg >> 32) & 0xFFF) + 1; 510 rvu_check_min_msix_vec(rvu, pfvf->msix.max, pf, 0); 511 512 /* Alloc msix bitmap for this PF */ 513 err = rvu_alloc_bitmap(&pfvf->msix); 514 if (err) 515 return err; 516 517 /* Allocate memory for MSIX vector to RVU block LF mapping */ 518 pfvf->msix_lfmap = devm_kcalloc(rvu->dev, pfvf->msix.max, 519 sizeof(u16), GFP_KERNEL); 520 if (!pfvf->msix_lfmap) 521 return -ENOMEM; 522 523 /* For PF0 (AF) firmware will set msix vector offsets for 524 * AF, block AF and PF0_INT vectors, so jump to VFs. 525 */ 526 if (!pf) 527 goto setup_vfmsix; 528 529 /* Set MSIX offset for PF's 'RVU_PF_INT_VEC' vectors. 530 * These are allocated on driver init and never freed, 531 * so no need to set 'msix_lfmap' for these. 532 */ 533 cfg = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_PFX_INT_CFG(pf)); 534 nvecs = (cfg >> 12) & 0xFF; 535 cfg &= ~0x7FFULL; 536 offset = rvu_alloc_rsrc_contig(&pfvf->msix, nvecs); 537 rvu_write64(rvu, BLKADDR_RVUM, 538 RVU_PRIV_PFX_INT_CFG(pf), cfg | offset); 539 setup_vfmsix: 540 /* Alloc msix bitmap for VFs */ 541 for (vf = 0; vf < numvfs; vf++) { 542 pfvf = &rvu->hwvf[hwvf + vf]; 543 /* Get num of MSIX vectors attached to this VF */ 544 cfg = rvu_read64(rvu, BLKADDR_RVUM, 545 RVU_PRIV_PFX_MSIX_CFG(pf)); 546 pfvf->msix.max = (cfg & 0xFFF) + 1; 547 rvu_check_min_msix_vec(rvu, pfvf->msix.max, pf, vf + 1); 548 549 /* Alloc msix bitmap for this VF */ 550 err = rvu_alloc_bitmap(&pfvf->msix); 551 if (err) 552 return err; 553 554 pfvf->msix_lfmap = 555 devm_kcalloc(rvu->dev, pfvf->msix.max, 556 sizeof(u16), GFP_KERNEL); 557 if (!pfvf->msix_lfmap) 558 return -ENOMEM; 559 560 /* Set MSIX offset for HWVF's 'RVU_VF_INT_VEC' vectors. 561 * These are allocated on driver init and never freed, 562 * so no need to set 'msix_lfmap' for these. 563 */ 564 cfg = rvu_read64(rvu, BLKADDR_RVUM, 565 RVU_PRIV_HWVFX_INT_CFG(hwvf + vf)); 566 nvecs = (cfg >> 12) & 0xFF; 567 cfg &= ~0x7FFULL; 568 offset = rvu_alloc_rsrc_contig(&pfvf->msix, nvecs); 569 rvu_write64(rvu, BLKADDR_RVUM, 570 RVU_PRIV_HWVFX_INT_CFG(hwvf + vf), 571 cfg | offset); 572 } 573 } 574 575 /* HW interprets RVU_AF_MSIXTR_BASE address as an IOVA, hence 576 * create a IOMMU mapping for the physcial address configured by 577 * firmware and reconfig RVU_AF_MSIXTR_BASE with IOVA. 578 */ 579 cfg = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_CONST); 580 max_msix = cfg & 0xFFFFF; 581 phy_addr = rvu_read64(rvu, BLKADDR_RVUM, RVU_AF_MSIXTR_BASE); 582 iova = dma_map_resource(rvu->dev, phy_addr, 583 max_msix * PCI_MSIX_ENTRY_SIZE, 584 DMA_BIDIRECTIONAL, 0); 585 586 if (dma_mapping_error(rvu->dev, iova)) 587 return -ENOMEM; 588 589 rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_MSIXTR_BASE, (u64)iova); 590 rvu->msix_base_iova = iova; 591 592 return 0; 593 } 594 595 static void rvu_free_hw_resources(struct rvu *rvu) 596 { 597 struct rvu_hwinfo *hw = rvu->hw; 598 struct rvu_block *block; 599 struct rvu_pfvf *pfvf; 600 int id, max_msix; 601 u64 cfg; 602 603 rvu_npa_freemem(rvu); 604 rvu_npc_freemem(rvu); 605 rvu_nix_freemem(rvu); 606 607 /* Free block LF bitmaps */ 608 for (id = 0; id < BLK_COUNT; id++) { 609 block = &hw->block[id]; 610 kfree(block->lf.bmap); 611 } 612 613 /* Free MSIX bitmaps */ 614 for (id = 0; id < hw->total_pfs; id++) { 615 pfvf = &rvu->pf[id]; 616 kfree(pfvf->msix.bmap); 617 } 618 619 for (id = 0; id < hw->total_vfs; id++) { 620 pfvf = &rvu->hwvf[id]; 621 kfree(pfvf->msix.bmap); 622 } 623 624 /* Unmap MSIX vector base IOVA mapping */ 625 if (!rvu->msix_base_iova) 626 return; 627 cfg = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_CONST); 628 max_msix = cfg & 0xFFFFF; 629 dma_unmap_resource(rvu->dev, rvu->msix_base_iova, 630 max_msix * PCI_MSIX_ENTRY_SIZE, 631 DMA_BIDIRECTIONAL, 0); 632 633 mutex_destroy(&rvu->rsrc_lock); 634 } 635 636 static int rvu_setup_hw_resources(struct rvu *rvu) 637 { 638 struct rvu_hwinfo *hw = rvu->hw; 639 struct rvu_block *block; 640 int blkid, err; 641 u64 cfg; 642 643 /* Get HW supported max RVU PF & VF count */ 644 cfg = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_CONST); 645 hw->total_pfs = (cfg >> 32) & 0xFF; 646 hw->total_vfs = (cfg >> 20) & 0xFFF; 647 hw->max_vfs_per_pf = (cfg >> 40) & 0xFF; 648 649 /* Init NPA LF's bitmap */ 650 block = &hw->block[BLKADDR_NPA]; 651 if (!block->implemented) 652 goto nix; 653 cfg = rvu_read64(rvu, BLKADDR_NPA, NPA_AF_CONST); 654 block->lf.max = (cfg >> 16) & 0xFFF; 655 block->addr = BLKADDR_NPA; 656 block->type = BLKTYPE_NPA; 657 block->lfshift = 8; 658 block->lookup_reg = NPA_AF_RVU_LF_CFG_DEBUG; 659 block->pf_lfcnt_reg = RVU_PRIV_PFX_NPA_CFG; 660 block->vf_lfcnt_reg = RVU_PRIV_HWVFX_NPA_CFG; 661 block->lfcfg_reg = NPA_PRIV_LFX_CFG; 662 block->msixcfg_reg = NPA_PRIV_LFX_INT_CFG; 663 block->lfreset_reg = NPA_AF_LF_RST; 664 sprintf(block->name, "NPA"); 665 err = rvu_alloc_bitmap(&block->lf); 666 if (err) 667 return err; 668 669 nix: 670 /* Init NIX LF's bitmap */ 671 block = &hw->block[BLKADDR_NIX0]; 672 if (!block->implemented) 673 goto sso; 674 cfg = rvu_read64(rvu, BLKADDR_NIX0, NIX_AF_CONST2); 675 block->lf.max = cfg & 0xFFF; 676 block->addr = BLKADDR_NIX0; 677 block->type = BLKTYPE_NIX; 678 block->lfshift = 8; 679 block->lookup_reg = NIX_AF_RVU_LF_CFG_DEBUG; 680 block->pf_lfcnt_reg = RVU_PRIV_PFX_NIX0_CFG; 681 block->vf_lfcnt_reg = RVU_PRIV_HWVFX_NIX0_CFG; 682 block->lfcfg_reg = NIX_PRIV_LFX_CFG; 683 block->msixcfg_reg = NIX_PRIV_LFX_INT_CFG; 684 block->lfreset_reg = NIX_AF_LF_RST; 685 sprintf(block->name, "NIX"); 686 err = rvu_alloc_bitmap(&block->lf); 687 if (err) 688 return err; 689 690 sso: 691 /* Init SSO group's bitmap */ 692 block = &hw->block[BLKADDR_SSO]; 693 if (!block->implemented) 694 goto ssow; 695 cfg = rvu_read64(rvu, BLKADDR_SSO, SSO_AF_CONST); 696 block->lf.max = cfg & 0xFFFF; 697 block->addr = BLKADDR_SSO; 698 block->type = BLKTYPE_SSO; 699 block->multislot = true; 700 block->lfshift = 3; 701 block->lookup_reg = SSO_AF_RVU_LF_CFG_DEBUG; 702 block->pf_lfcnt_reg = RVU_PRIV_PFX_SSO_CFG; 703 block->vf_lfcnt_reg = RVU_PRIV_HWVFX_SSO_CFG; 704 block->lfcfg_reg = SSO_PRIV_LFX_HWGRP_CFG; 705 block->msixcfg_reg = SSO_PRIV_LFX_HWGRP_INT_CFG; 706 block->lfreset_reg = SSO_AF_LF_HWGRP_RST; 707 sprintf(block->name, "SSO GROUP"); 708 err = rvu_alloc_bitmap(&block->lf); 709 if (err) 710 return err; 711 712 ssow: 713 /* Init SSO workslot's bitmap */ 714 block = &hw->block[BLKADDR_SSOW]; 715 if (!block->implemented) 716 goto tim; 717 block->lf.max = (cfg >> 56) & 0xFF; 718 block->addr = BLKADDR_SSOW; 719 block->type = BLKTYPE_SSOW; 720 block->multislot = true; 721 block->lfshift = 3; 722 block->lookup_reg = SSOW_AF_RVU_LF_HWS_CFG_DEBUG; 723 block->pf_lfcnt_reg = RVU_PRIV_PFX_SSOW_CFG; 724 block->vf_lfcnt_reg = RVU_PRIV_HWVFX_SSOW_CFG; 725 block->lfcfg_reg = SSOW_PRIV_LFX_HWS_CFG; 726 block->msixcfg_reg = SSOW_PRIV_LFX_HWS_INT_CFG; 727 block->lfreset_reg = SSOW_AF_LF_HWS_RST; 728 sprintf(block->name, "SSOWS"); 729 err = rvu_alloc_bitmap(&block->lf); 730 if (err) 731 return err; 732 733 tim: 734 /* Init TIM LF's bitmap */ 735 block = &hw->block[BLKADDR_TIM]; 736 if (!block->implemented) 737 goto cpt; 738 cfg = rvu_read64(rvu, BLKADDR_TIM, TIM_AF_CONST); 739 block->lf.max = cfg & 0xFFFF; 740 block->addr = BLKADDR_TIM; 741 block->type = BLKTYPE_TIM; 742 block->multislot = true; 743 block->lfshift = 3; 744 block->lookup_reg = TIM_AF_RVU_LF_CFG_DEBUG; 745 block->pf_lfcnt_reg = RVU_PRIV_PFX_TIM_CFG; 746 block->vf_lfcnt_reg = RVU_PRIV_HWVFX_TIM_CFG; 747 block->lfcfg_reg = TIM_PRIV_LFX_CFG; 748 block->msixcfg_reg = TIM_PRIV_LFX_INT_CFG; 749 block->lfreset_reg = TIM_AF_LF_RST; 750 sprintf(block->name, "TIM"); 751 err = rvu_alloc_bitmap(&block->lf); 752 if (err) 753 return err; 754 755 cpt: 756 /* Init CPT LF's bitmap */ 757 block = &hw->block[BLKADDR_CPT0]; 758 if (!block->implemented) 759 goto init; 760 cfg = rvu_read64(rvu, BLKADDR_CPT0, CPT_AF_CONSTANTS0); 761 block->lf.max = cfg & 0xFF; 762 block->addr = BLKADDR_CPT0; 763 block->type = BLKTYPE_CPT; 764 block->multislot = true; 765 block->lfshift = 3; 766 block->lookup_reg = CPT_AF_RVU_LF_CFG_DEBUG; 767 block->pf_lfcnt_reg = RVU_PRIV_PFX_CPT0_CFG; 768 block->vf_lfcnt_reg = RVU_PRIV_HWVFX_CPT0_CFG; 769 block->lfcfg_reg = CPT_PRIV_LFX_CFG; 770 block->msixcfg_reg = CPT_PRIV_LFX_INT_CFG; 771 block->lfreset_reg = CPT_AF_LF_RST; 772 sprintf(block->name, "CPT"); 773 err = rvu_alloc_bitmap(&block->lf); 774 if (err) 775 return err; 776 777 init: 778 /* Allocate memory for PFVF data */ 779 rvu->pf = devm_kcalloc(rvu->dev, hw->total_pfs, 780 sizeof(struct rvu_pfvf), GFP_KERNEL); 781 if (!rvu->pf) 782 return -ENOMEM; 783 784 rvu->hwvf = devm_kcalloc(rvu->dev, hw->total_vfs, 785 sizeof(struct rvu_pfvf), GFP_KERNEL); 786 if (!rvu->hwvf) 787 return -ENOMEM; 788 789 mutex_init(&rvu->rsrc_lock); 790 791 err = rvu_setup_msix_resources(rvu); 792 if (err) 793 return err; 794 795 for (blkid = 0; blkid < BLK_COUNT; blkid++) { 796 block = &hw->block[blkid]; 797 if (!block->lf.bmap) 798 continue; 799 800 /* Allocate memory for block LF/slot to pcifunc mapping info */ 801 block->fn_map = devm_kcalloc(rvu->dev, block->lf.max, 802 sizeof(u16), GFP_KERNEL); 803 if (!block->fn_map) 804 return -ENOMEM; 805 806 /* Scan all blocks to check if low level firmware has 807 * already provisioned any of the resources to a PF/VF. 808 */ 809 rvu_scan_block(rvu, block); 810 } 811 812 err = rvu_npc_init(rvu); 813 if (err) 814 goto exit; 815 816 err = rvu_cgx_init(rvu); 817 if (err) 818 goto exit; 819 820 err = rvu_npa_init(rvu); 821 if (err) 822 goto cgx_err; 823 824 err = rvu_nix_init(rvu); 825 if (err) 826 goto cgx_err; 827 828 return 0; 829 830 cgx_err: 831 rvu_cgx_exit(rvu); 832 exit: 833 return err; 834 } 835 836 /* NPA and NIX admin queue APIs */ 837 void rvu_aq_free(struct rvu *rvu, struct admin_queue *aq) 838 { 839 if (!aq) 840 return; 841 842 qmem_free(rvu->dev, aq->inst); 843 qmem_free(rvu->dev, aq->res); 844 devm_kfree(rvu->dev, aq); 845 } 846 847 int rvu_aq_alloc(struct rvu *rvu, struct admin_queue **ad_queue, 848 int qsize, int inst_size, int res_size) 849 { 850 struct admin_queue *aq; 851 int err; 852 853 *ad_queue = devm_kzalloc(rvu->dev, sizeof(*aq), GFP_KERNEL); 854 if (!*ad_queue) 855 return -ENOMEM; 856 aq = *ad_queue; 857 858 /* Alloc memory for instructions i.e AQ */ 859 err = qmem_alloc(rvu->dev, &aq->inst, qsize, inst_size); 860 if (err) { 861 devm_kfree(rvu->dev, aq); 862 return err; 863 } 864 865 /* Alloc memory for results */ 866 err = qmem_alloc(rvu->dev, &aq->res, qsize, res_size); 867 if (err) { 868 rvu_aq_free(rvu, aq); 869 return err; 870 } 871 872 spin_lock_init(&aq->lock); 873 return 0; 874 } 875 876 static int rvu_mbox_handler_ready(struct rvu *rvu, struct msg_req *req, 877 struct ready_msg_rsp *rsp) 878 { 879 return 0; 880 } 881 882 /* Get current count of a RVU block's LF/slots 883 * provisioned to a given RVU func. 884 */ 885 static u16 rvu_get_rsrc_mapcount(struct rvu_pfvf *pfvf, int blktype) 886 { 887 switch (blktype) { 888 case BLKTYPE_NPA: 889 return pfvf->npalf ? 1 : 0; 890 case BLKTYPE_NIX: 891 return pfvf->nixlf ? 1 : 0; 892 case BLKTYPE_SSO: 893 return pfvf->sso; 894 case BLKTYPE_SSOW: 895 return pfvf->ssow; 896 case BLKTYPE_TIM: 897 return pfvf->timlfs; 898 case BLKTYPE_CPT: 899 return pfvf->cptlfs; 900 } 901 return 0; 902 } 903 904 bool is_pffunc_map_valid(struct rvu *rvu, u16 pcifunc, int blktype) 905 { 906 struct rvu_pfvf *pfvf; 907 908 if (!is_pf_func_valid(rvu, pcifunc)) 909 return false; 910 911 pfvf = rvu_get_pfvf(rvu, pcifunc); 912 913 /* Check if this PFFUNC has a LF of type blktype attached */ 914 if (!rvu_get_rsrc_mapcount(pfvf, blktype)) 915 return false; 916 917 return true; 918 } 919 920 static int rvu_lookup_rsrc(struct rvu *rvu, struct rvu_block *block, 921 int pcifunc, int slot) 922 { 923 u64 val; 924 925 val = ((u64)pcifunc << 24) | (slot << 16) | (1ULL << 13); 926 rvu_write64(rvu, block->addr, block->lookup_reg, val); 927 /* Wait for the lookup to finish */ 928 /* TODO: put some timeout here */ 929 while (rvu_read64(rvu, block->addr, block->lookup_reg) & (1ULL << 13)) 930 ; 931 932 val = rvu_read64(rvu, block->addr, block->lookup_reg); 933 934 /* Check LF valid bit */ 935 if (!(val & (1ULL << 12))) 936 return -1; 937 938 return (val & 0xFFF); 939 } 940 941 static void rvu_detach_block(struct rvu *rvu, int pcifunc, int blktype) 942 { 943 struct rvu_pfvf *pfvf = rvu_get_pfvf(rvu, pcifunc); 944 struct rvu_hwinfo *hw = rvu->hw; 945 struct rvu_block *block; 946 int slot, lf, num_lfs; 947 int blkaddr; 948 949 blkaddr = rvu_get_blkaddr(rvu, blktype, pcifunc); 950 if (blkaddr < 0) 951 return; 952 953 block = &hw->block[blkaddr]; 954 955 num_lfs = rvu_get_rsrc_mapcount(pfvf, block->type); 956 if (!num_lfs) 957 return; 958 959 for (slot = 0; slot < num_lfs; slot++) { 960 lf = rvu_lookup_rsrc(rvu, block, pcifunc, slot); 961 if (lf < 0) /* This should never happen */ 962 continue; 963 964 /* Disable the LF */ 965 rvu_write64(rvu, blkaddr, block->lfcfg_reg | 966 (lf << block->lfshift), 0x00ULL); 967 968 /* Update SW maintained mapping info as well */ 969 rvu_update_rsrc_map(rvu, pfvf, block, 970 pcifunc, lf, false); 971 972 /* Free the resource */ 973 rvu_free_rsrc(&block->lf, lf); 974 975 /* Clear MSIX vector offset for this LF */ 976 rvu_clear_msix_offset(rvu, pfvf, block, lf); 977 } 978 } 979 980 static int rvu_detach_rsrcs(struct rvu *rvu, struct rsrc_detach *detach, 981 u16 pcifunc) 982 { 983 struct rvu_hwinfo *hw = rvu->hw; 984 bool detach_all = true; 985 struct rvu_block *block; 986 int blkid; 987 988 mutex_lock(&rvu->rsrc_lock); 989 990 /* Check for partial resource detach */ 991 if (detach && detach->partial) 992 detach_all = false; 993 994 /* Check for RVU block's LFs attached to this func, 995 * if so, detach them. 996 */ 997 for (blkid = 0; blkid < BLK_COUNT; blkid++) { 998 block = &hw->block[blkid]; 999 if (!block->lf.bmap) 1000 continue; 1001 if (!detach_all && detach) { 1002 if (blkid == BLKADDR_NPA && !detach->npalf) 1003 continue; 1004 else if ((blkid == BLKADDR_NIX0) && !detach->nixlf) 1005 continue; 1006 else if ((blkid == BLKADDR_SSO) && !detach->sso) 1007 continue; 1008 else if ((blkid == BLKADDR_SSOW) && !detach->ssow) 1009 continue; 1010 else if ((blkid == BLKADDR_TIM) && !detach->timlfs) 1011 continue; 1012 else if ((blkid == BLKADDR_CPT0) && !detach->cptlfs) 1013 continue; 1014 } 1015 rvu_detach_block(rvu, pcifunc, block->type); 1016 } 1017 1018 mutex_unlock(&rvu->rsrc_lock); 1019 return 0; 1020 } 1021 1022 static int rvu_mbox_handler_detach_resources(struct rvu *rvu, 1023 struct rsrc_detach *detach, 1024 struct msg_rsp *rsp) 1025 { 1026 return rvu_detach_rsrcs(rvu, detach, detach->hdr.pcifunc); 1027 } 1028 1029 static void rvu_attach_block(struct rvu *rvu, int pcifunc, 1030 int blktype, int num_lfs) 1031 { 1032 struct rvu_pfvf *pfvf = rvu_get_pfvf(rvu, pcifunc); 1033 struct rvu_hwinfo *hw = rvu->hw; 1034 struct rvu_block *block; 1035 int slot, lf; 1036 int blkaddr; 1037 u64 cfg; 1038 1039 if (!num_lfs) 1040 return; 1041 1042 blkaddr = rvu_get_blkaddr(rvu, blktype, 0); 1043 if (blkaddr < 0) 1044 return; 1045 1046 block = &hw->block[blkaddr]; 1047 if (!block->lf.bmap) 1048 return; 1049 1050 for (slot = 0; slot < num_lfs; slot++) { 1051 /* Allocate the resource */ 1052 lf = rvu_alloc_rsrc(&block->lf); 1053 if (lf < 0) 1054 return; 1055 1056 cfg = (1ULL << 63) | (pcifunc << 8) | slot; 1057 rvu_write64(rvu, blkaddr, block->lfcfg_reg | 1058 (lf << block->lfshift), cfg); 1059 rvu_update_rsrc_map(rvu, pfvf, block, 1060 pcifunc, lf, true); 1061 1062 /* Set start MSIX vector for this LF within this PF/VF */ 1063 rvu_set_msix_offset(rvu, pfvf, block, lf); 1064 } 1065 } 1066 1067 static int rvu_check_rsrc_availability(struct rvu *rvu, 1068 struct rsrc_attach *req, u16 pcifunc) 1069 { 1070 struct rvu_pfvf *pfvf = rvu_get_pfvf(rvu, pcifunc); 1071 struct rvu_hwinfo *hw = rvu->hw; 1072 struct rvu_block *block; 1073 int free_lfs, mappedlfs; 1074 1075 /* Only one NPA LF can be attached */ 1076 if (req->npalf && !rvu_get_rsrc_mapcount(pfvf, BLKTYPE_NPA)) { 1077 block = &hw->block[BLKADDR_NPA]; 1078 free_lfs = rvu_rsrc_free_count(&block->lf); 1079 if (!free_lfs) 1080 goto fail; 1081 } else if (req->npalf) { 1082 dev_err(&rvu->pdev->dev, 1083 "Func 0x%x: Invalid req, already has NPA\n", 1084 pcifunc); 1085 return -EINVAL; 1086 } 1087 1088 /* Only one NIX LF can be attached */ 1089 if (req->nixlf && !rvu_get_rsrc_mapcount(pfvf, BLKTYPE_NIX)) { 1090 block = &hw->block[BLKADDR_NIX0]; 1091 free_lfs = rvu_rsrc_free_count(&block->lf); 1092 if (!free_lfs) 1093 goto fail; 1094 } else if (req->nixlf) { 1095 dev_err(&rvu->pdev->dev, 1096 "Func 0x%x: Invalid req, already has NIX\n", 1097 pcifunc); 1098 return -EINVAL; 1099 } 1100 1101 if (req->sso) { 1102 block = &hw->block[BLKADDR_SSO]; 1103 /* Is request within limits ? */ 1104 if (req->sso > block->lf.max) { 1105 dev_err(&rvu->pdev->dev, 1106 "Func 0x%x: Invalid SSO req, %d > max %d\n", 1107 pcifunc, req->sso, block->lf.max); 1108 return -EINVAL; 1109 } 1110 mappedlfs = rvu_get_rsrc_mapcount(pfvf, block->type); 1111 free_lfs = rvu_rsrc_free_count(&block->lf); 1112 /* Check if additional resources are available */ 1113 if (req->sso > mappedlfs && 1114 ((req->sso - mappedlfs) > free_lfs)) 1115 goto fail; 1116 } 1117 1118 if (req->ssow) { 1119 block = &hw->block[BLKADDR_SSOW]; 1120 if (req->ssow > block->lf.max) { 1121 dev_err(&rvu->pdev->dev, 1122 "Func 0x%x: Invalid SSOW req, %d > max %d\n", 1123 pcifunc, req->sso, block->lf.max); 1124 return -EINVAL; 1125 } 1126 mappedlfs = rvu_get_rsrc_mapcount(pfvf, block->type); 1127 free_lfs = rvu_rsrc_free_count(&block->lf); 1128 if (req->ssow > mappedlfs && 1129 ((req->ssow - mappedlfs) > free_lfs)) 1130 goto fail; 1131 } 1132 1133 if (req->timlfs) { 1134 block = &hw->block[BLKADDR_TIM]; 1135 if (req->timlfs > block->lf.max) { 1136 dev_err(&rvu->pdev->dev, 1137 "Func 0x%x: Invalid TIMLF req, %d > max %d\n", 1138 pcifunc, req->timlfs, block->lf.max); 1139 return -EINVAL; 1140 } 1141 mappedlfs = rvu_get_rsrc_mapcount(pfvf, block->type); 1142 free_lfs = rvu_rsrc_free_count(&block->lf); 1143 if (req->timlfs > mappedlfs && 1144 ((req->timlfs - mappedlfs) > free_lfs)) 1145 goto fail; 1146 } 1147 1148 if (req->cptlfs) { 1149 block = &hw->block[BLKADDR_CPT0]; 1150 if (req->cptlfs > block->lf.max) { 1151 dev_err(&rvu->pdev->dev, 1152 "Func 0x%x: Invalid CPTLF req, %d > max %d\n", 1153 pcifunc, req->cptlfs, block->lf.max); 1154 return -EINVAL; 1155 } 1156 mappedlfs = rvu_get_rsrc_mapcount(pfvf, block->type); 1157 free_lfs = rvu_rsrc_free_count(&block->lf); 1158 if (req->cptlfs > mappedlfs && 1159 ((req->cptlfs - mappedlfs) > free_lfs)) 1160 goto fail; 1161 } 1162 1163 return 0; 1164 1165 fail: 1166 dev_info(rvu->dev, "Request for %s failed\n", block->name); 1167 return -ENOSPC; 1168 } 1169 1170 static int rvu_mbox_handler_attach_resources(struct rvu *rvu, 1171 struct rsrc_attach *attach, 1172 struct msg_rsp *rsp) 1173 { 1174 u16 pcifunc = attach->hdr.pcifunc; 1175 int err; 1176 1177 /* If first request, detach all existing attached resources */ 1178 if (!attach->modify) 1179 rvu_detach_rsrcs(rvu, NULL, pcifunc); 1180 1181 mutex_lock(&rvu->rsrc_lock); 1182 1183 /* Check if the request can be accommodated */ 1184 err = rvu_check_rsrc_availability(rvu, attach, pcifunc); 1185 if (err) 1186 goto exit; 1187 1188 /* Now attach the requested resources */ 1189 if (attach->npalf) 1190 rvu_attach_block(rvu, pcifunc, BLKTYPE_NPA, 1); 1191 1192 if (attach->nixlf) 1193 rvu_attach_block(rvu, pcifunc, BLKTYPE_NIX, 1); 1194 1195 if (attach->sso) { 1196 /* RVU func doesn't know which exact LF or slot is attached 1197 * to it, it always sees as slot 0,1,2. So for a 'modify' 1198 * request, simply detach all existing attached LFs/slots 1199 * and attach a fresh. 1200 */ 1201 if (attach->modify) 1202 rvu_detach_block(rvu, pcifunc, BLKTYPE_SSO); 1203 rvu_attach_block(rvu, pcifunc, BLKTYPE_SSO, attach->sso); 1204 } 1205 1206 if (attach->ssow) { 1207 if (attach->modify) 1208 rvu_detach_block(rvu, pcifunc, BLKTYPE_SSOW); 1209 rvu_attach_block(rvu, pcifunc, BLKTYPE_SSOW, attach->ssow); 1210 } 1211 1212 if (attach->timlfs) { 1213 if (attach->modify) 1214 rvu_detach_block(rvu, pcifunc, BLKTYPE_TIM); 1215 rvu_attach_block(rvu, pcifunc, BLKTYPE_TIM, attach->timlfs); 1216 } 1217 1218 if (attach->cptlfs) { 1219 if (attach->modify) 1220 rvu_detach_block(rvu, pcifunc, BLKTYPE_CPT); 1221 rvu_attach_block(rvu, pcifunc, BLKTYPE_CPT, attach->cptlfs); 1222 } 1223 1224 exit: 1225 mutex_unlock(&rvu->rsrc_lock); 1226 return err; 1227 } 1228 1229 static u16 rvu_get_msix_offset(struct rvu *rvu, struct rvu_pfvf *pfvf, 1230 int blkaddr, int lf) 1231 { 1232 u16 vec; 1233 1234 if (lf < 0) 1235 return MSIX_VECTOR_INVALID; 1236 1237 for (vec = 0; vec < pfvf->msix.max; vec++) { 1238 if (pfvf->msix_lfmap[vec] == MSIX_BLKLF(blkaddr, lf)) 1239 return vec; 1240 } 1241 return MSIX_VECTOR_INVALID; 1242 } 1243 1244 static void rvu_set_msix_offset(struct rvu *rvu, struct rvu_pfvf *pfvf, 1245 struct rvu_block *block, int lf) 1246 { 1247 u16 nvecs, vec, offset; 1248 u64 cfg; 1249 1250 cfg = rvu_read64(rvu, block->addr, block->msixcfg_reg | 1251 (lf << block->lfshift)); 1252 nvecs = (cfg >> 12) & 0xFF; 1253 1254 /* Check and alloc MSIX vectors, must be contiguous */ 1255 if (!rvu_rsrc_check_contig(&pfvf->msix, nvecs)) 1256 return; 1257 1258 offset = rvu_alloc_rsrc_contig(&pfvf->msix, nvecs); 1259 1260 /* Config MSIX offset in LF */ 1261 rvu_write64(rvu, block->addr, block->msixcfg_reg | 1262 (lf << block->lfshift), (cfg & ~0x7FFULL) | offset); 1263 1264 /* Update the bitmap as well */ 1265 for (vec = 0; vec < nvecs; vec++) 1266 pfvf->msix_lfmap[offset + vec] = MSIX_BLKLF(block->addr, lf); 1267 } 1268 1269 static void rvu_clear_msix_offset(struct rvu *rvu, struct rvu_pfvf *pfvf, 1270 struct rvu_block *block, int lf) 1271 { 1272 u16 nvecs, vec, offset; 1273 u64 cfg; 1274 1275 cfg = rvu_read64(rvu, block->addr, block->msixcfg_reg | 1276 (lf << block->lfshift)); 1277 nvecs = (cfg >> 12) & 0xFF; 1278 1279 /* Clear MSIX offset in LF */ 1280 rvu_write64(rvu, block->addr, block->msixcfg_reg | 1281 (lf << block->lfshift), cfg & ~0x7FFULL); 1282 1283 offset = rvu_get_msix_offset(rvu, pfvf, block->addr, lf); 1284 1285 /* Update the mapping */ 1286 for (vec = 0; vec < nvecs; vec++) 1287 pfvf->msix_lfmap[offset + vec] = 0; 1288 1289 /* Free the same in MSIX bitmap */ 1290 rvu_free_rsrc_contig(&pfvf->msix, nvecs, offset); 1291 } 1292 1293 static int rvu_mbox_handler_msix_offset(struct rvu *rvu, struct msg_req *req, 1294 struct msix_offset_rsp *rsp) 1295 { 1296 struct rvu_hwinfo *hw = rvu->hw; 1297 u16 pcifunc = req->hdr.pcifunc; 1298 struct rvu_pfvf *pfvf; 1299 int lf, slot; 1300 1301 pfvf = rvu_get_pfvf(rvu, pcifunc); 1302 if (!pfvf->msix.bmap) 1303 return 0; 1304 1305 /* Set MSIX offsets for each block's LFs attached to this PF/VF */ 1306 lf = rvu_get_lf(rvu, &hw->block[BLKADDR_NPA], pcifunc, 0); 1307 rsp->npa_msixoff = rvu_get_msix_offset(rvu, pfvf, BLKADDR_NPA, lf); 1308 1309 lf = rvu_get_lf(rvu, &hw->block[BLKADDR_NIX0], pcifunc, 0); 1310 rsp->nix_msixoff = rvu_get_msix_offset(rvu, pfvf, BLKADDR_NIX0, lf); 1311 1312 rsp->sso = pfvf->sso; 1313 for (slot = 0; slot < rsp->sso; slot++) { 1314 lf = rvu_get_lf(rvu, &hw->block[BLKADDR_SSO], pcifunc, slot); 1315 rsp->sso_msixoff[slot] = 1316 rvu_get_msix_offset(rvu, pfvf, BLKADDR_SSO, lf); 1317 } 1318 1319 rsp->ssow = pfvf->ssow; 1320 for (slot = 0; slot < rsp->ssow; slot++) { 1321 lf = rvu_get_lf(rvu, &hw->block[BLKADDR_SSOW], pcifunc, slot); 1322 rsp->ssow_msixoff[slot] = 1323 rvu_get_msix_offset(rvu, pfvf, BLKADDR_SSOW, lf); 1324 } 1325 1326 rsp->timlfs = pfvf->timlfs; 1327 for (slot = 0; slot < rsp->timlfs; slot++) { 1328 lf = rvu_get_lf(rvu, &hw->block[BLKADDR_TIM], pcifunc, slot); 1329 rsp->timlf_msixoff[slot] = 1330 rvu_get_msix_offset(rvu, pfvf, BLKADDR_TIM, lf); 1331 } 1332 1333 rsp->cptlfs = pfvf->cptlfs; 1334 for (slot = 0; slot < rsp->cptlfs; slot++) { 1335 lf = rvu_get_lf(rvu, &hw->block[BLKADDR_CPT0], pcifunc, slot); 1336 rsp->cptlf_msixoff[slot] = 1337 rvu_get_msix_offset(rvu, pfvf, BLKADDR_CPT0, lf); 1338 } 1339 return 0; 1340 } 1341 1342 static int rvu_mbox_handler_vf_flr(struct rvu *rvu, struct msg_req *req, 1343 struct msg_rsp *rsp) 1344 { 1345 u16 pcifunc = req->hdr.pcifunc; 1346 u16 vf, numvfs; 1347 u64 cfg; 1348 1349 vf = pcifunc & RVU_PFVF_FUNC_MASK; 1350 cfg = rvu_read64(rvu, BLKADDR_RVUM, 1351 RVU_PRIV_PFX_CFG(rvu_get_pf(pcifunc))); 1352 numvfs = (cfg >> 12) & 0xFF; 1353 1354 if (vf && vf <= numvfs) 1355 __rvu_flr_handler(rvu, pcifunc); 1356 else 1357 return RVU_INVALID_VF_ID; 1358 1359 return 0; 1360 } 1361 1362 static int rvu_process_mbox_msg(struct otx2_mbox *mbox, int devid, 1363 struct mbox_msghdr *req) 1364 { 1365 struct rvu *rvu = pci_get_drvdata(mbox->pdev); 1366 1367 /* Check if valid, if not reply with a invalid msg */ 1368 if (req->sig != OTX2_MBOX_REQ_SIG) 1369 goto bad_message; 1370 1371 switch (req->id) { 1372 #define M(_name, _id, _fn_name, _req_type, _rsp_type) \ 1373 case _id: { \ 1374 struct _rsp_type *rsp; \ 1375 int err; \ 1376 \ 1377 rsp = (struct _rsp_type *)otx2_mbox_alloc_msg( \ 1378 mbox, devid, \ 1379 sizeof(struct _rsp_type)); \ 1380 /* some handlers should complete even if reply */ \ 1381 /* could not be allocated */ \ 1382 if (!rsp && \ 1383 _id != MBOX_MSG_DETACH_RESOURCES && \ 1384 _id != MBOX_MSG_NIX_TXSCH_FREE && \ 1385 _id != MBOX_MSG_VF_FLR) \ 1386 return -ENOMEM; \ 1387 if (rsp) { \ 1388 rsp->hdr.id = _id; \ 1389 rsp->hdr.sig = OTX2_MBOX_RSP_SIG; \ 1390 rsp->hdr.pcifunc = req->pcifunc; \ 1391 rsp->hdr.rc = 0; \ 1392 } \ 1393 \ 1394 err = rvu_mbox_handler_ ## _fn_name(rvu, \ 1395 (struct _req_type *)req, \ 1396 rsp); \ 1397 if (rsp && err) \ 1398 rsp->hdr.rc = err; \ 1399 \ 1400 return rsp ? err : -ENOMEM; \ 1401 } 1402 MBOX_MESSAGES 1403 #undef M 1404 1405 bad_message: 1406 default: 1407 otx2_reply_invalid_msg(mbox, devid, req->pcifunc, req->id); 1408 return -ENODEV; 1409 } 1410 } 1411 1412 static void __rvu_mbox_handler(struct rvu_work *mwork, int type) 1413 { 1414 struct rvu *rvu = mwork->rvu; 1415 int offset, err, id, devid; 1416 struct otx2_mbox_dev *mdev; 1417 struct mbox_hdr *req_hdr; 1418 struct mbox_msghdr *msg; 1419 struct mbox_wq_info *mw; 1420 struct otx2_mbox *mbox; 1421 1422 switch (type) { 1423 case TYPE_AFPF: 1424 mw = &rvu->afpf_wq_info; 1425 break; 1426 case TYPE_AFVF: 1427 mw = &rvu->afvf_wq_info; 1428 break; 1429 default: 1430 return; 1431 } 1432 1433 devid = mwork - mw->mbox_wrk; 1434 mbox = &mw->mbox; 1435 mdev = &mbox->dev[devid]; 1436 1437 /* Process received mbox messages */ 1438 req_hdr = mdev->mbase + mbox->rx_start; 1439 if (req_hdr->num_msgs == 0) 1440 return; 1441 1442 offset = mbox->rx_start + ALIGN(sizeof(*req_hdr), MBOX_MSG_ALIGN); 1443 1444 for (id = 0; id < req_hdr->num_msgs; id++) { 1445 msg = mdev->mbase + offset; 1446 1447 /* Set which PF/VF sent this message based on mbox IRQ */ 1448 switch (type) { 1449 case TYPE_AFPF: 1450 msg->pcifunc &= 1451 ~(RVU_PFVF_PF_MASK << RVU_PFVF_PF_SHIFT); 1452 msg->pcifunc |= (devid << RVU_PFVF_PF_SHIFT); 1453 break; 1454 case TYPE_AFVF: 1455 msg->pcifunc &= 1456 ~(RVU_PFVF_FUNC_MASK << RVU_PFVF_FUNC_SHIFT); 1457 msg->pcifunc |= (devid << RVU_PFVF_FUNC_SHIFT) + 1; 1458 break; 1459 } 1460 1461 err = rvu_process_mbox_msg(mbox, devid, msg); 1462 if (!err) { 1463 offset = mbox->rx_start + msg->next_msgoff; 1464 continue; 1465 } 1466 1467 if (msg->pcifunc & RVU_PFVF_FUNC_MASK) 1468 dev_warn(rvu->dev, "Error %d when processing message %s (0x%x) from PF%d:VF%d\n", 1469 err, otx2_mbox_id2name(msg->id), 1470 msg->id, devid, 1471 (msg->pcifunc & RVU_PFVF_FUNC_MASK) - 1); 1472 else 1473 dev_warn(rvu->dev, "Error %d when processing message %s (0x%x) from PF%d\n", 1474 err, otx2_mbox_id2name(msg->id), 1475 msg->id, devid); 1476 } 1477 1478 /* Send mbox responses to VF/PF */ 1479 otx2_mbox_msg_send(mbox, devid); 1480 } 1481 1482 static inline void rvu_afpf_mbox_handler(struct work_struct *work) 1483 { 1484 struct rvu_work *mwork = container_of(work, struct rvu_work, work); 1485 1486 __rvu_mbox_handler(mwork, TYPE_AFPF); 1487 } 1488 1489 static inline void rvu_afvf_mbox_handler(struct work_struct *work) 1490 { 1491 struct rvu_work *mwork = container_of(work, struct rvu_work, work); 1492 1493 __rvu_mbox_handler(mwork, TYPE_AFVF); 1494 } 1495 1496 static void __rvu_mbox_up_handler(struct rvu_work *mwork, int type) 1497 { 1498 struct rvu *rvu = mwork->rvu; 1499 struct otx2_mbox_dev *mdev; 1500 struct mbox_hdr *rsp_hdr; 1501 struct mbox_msghdr *msg; 1502 struct mbox_wq_info *mw; 1503 struct otx2_mbox *mbox; 1504 int offset, id, devid; 1505 1506 switch (type) { 1507 case TYPE_AFPF: 1508 mw = &rvu->afpf_wq_info; 1509 break; 1510 case TYPE_AFVF: 1511 mw = &rvu->afvf_wq_info; 1512 break; 1513 default: 1514 return; 1515 } 1516 1517 devid = mwork - mw->mbox_wrk_up; 1518 mbox = &mw->mbox_up; 1519 mdev = &mbox->dev[devid]; 1520 1521 rsp_hdr = mdev->mbase + mbox->rx_start; 1522 if (rsp_hdr->num_msgs == 0) { 1523 dev_warn(rvu->dev, "mbox up handler: num_msgs = 0\n"); 1524 return; 1525 } 1526 1527 offset = mbox->rx_start + ALIGN(sizeof(*rsp_hdr), MBOX_MSG_ALIGN); 1528 1529 for (id = 0; id < rsp_hdr->num_msgs; id++) { 1530 msg = mdev->mbase + offset; 1531 1532 if (msg->id >= MBOX_MSG_MAX) { 1533 dev_err(rvu->dev, 1534 "Mbox msg with unknown ID 0x%x\n", msg->id); 1535 goto end; 1536 } 1537 1538 if (msg->sig != OTX2_MBOX_RSP_SIG) { 1539 dev_err(rvu->dev, 1540 "Mbox msg with wrong signature %x, ID 0x%x\n", 1541 msg->sig, msg->id); 1542 goto end; 1543 } 1544 1545 switch (msg->id) { 1546 case MBOX_MSG_CGX_LINK_EVENT: 1547 break; 1548 default: 1549 if (msg->rc) 1550 dev_err(rvu->dev, 1551 "Mbox msg response has err %d, ID 0x%x\n", 1552 msg->rc, msg->id); 1553 break; 1554 } 1555 end: 1556 offset = mbox->rx_start + msg->next_msgoff; 1557 mdev->msgs_acked++; 1558 } 1559 1560 otx2_mbox_reset(mbox, devid); 1561 } 1562 1563 static inline void rvu_afpf_mbox_up_handler(struct work_struct *work) 1564 { 1565 struct rvu_work *mwork = container_of(work, struct rvu_work, work); 1566 1567 __rvu_mbox_up_handler(mwork, TYPE_AFPF); 1568 } 1569 1570 static inline void rvu_afvf_mbox_up_handler(struct work_struct *work) 1571 { 1572 struct rvu_work *mwork = container_of(work, struct rvu_work, work); 1573 1574 __rvu_mbox_up_handler(mwork, TYPE_AFVF); 1575 } 1576 1577 static int rvu_mbox_init(struct rvu *rvu, struct mbox_wq_info *mw, 1578 int type, int num, 1579 void (mbox_handler)(struct work_struct *), 1580 void (mbox_up_handler)(struct work_struct *)) 1581 { 1582 void __iomem *hwbase = NULL, *reg_base; 1583 int err, i, dir, dir_up; 1584 struct rvu_work *mwork; 1585 const char *name; 1586 u64 bar4_addr; 1587 1588 switch (type) { 1589 case TYPE_AFPF: 1590 name = "rvu_afpf_mailbox"; 1591 bar4_addr = rvu_read64(rvu, BLKADDR_RVUM, RVU_AF_PF_BAR4_ADDR); 1592 dir = MBOX_DIR_AFPF; 1593 dir_up = MBOX_DIR_AFPF_UP; 1594 reg_base = rvu->afreg_base; 1595 break; 1596 case TYPE_AFVF: 1597 name = "rvu_afvf_mailbox"; 1598 bar4_addr = rvupf_read64(rvu, RVU_PF_VF_BAR4_ADDR); 1599 dir = MBOX_DIR_PFVF; 1600 dir_up = MBOX_DIR_PFVF_UP; 1601 reg_base = rvu->pfreg_base; 1602 break; 1603 default: 1604 return -EINVAL; 1605 } 1606 1607 mw->mbox_wq = alloc_workqueue(name, 1608 WQ_UNBOUND | WQ_HIGHPRI | WQ_MEM_RECLAIM, 1609 num); 1610 if (!mw->mbox_wq) 1611 return -ENOMEM; 1612 1613 mw->mbox_wrk = devm_kcalloc(rvu->dev, num, 1614 sizeof(struct rvu_work), GFP_KERNEL); 1615 if (!mw->mbox_wrk) { 1616 err = -ENOMEM; 1617 goto exit; 1618 } 1619 1620 mw->mbox_wrk_up = devm_kcalloc(rvu->dev, num, 1621 sizeof(struct rvu_work), GFP_KERNEL); 1622 if (!mw->mbox_wrk_up) { 1623 err = -ENOMEM; 1624 goto exit; 1625 } 1626 1627 /* Mailbox is a reserved memory (in RAM) region shared between 1628 * RVU devices, shouldn't be mapped as device memory to allow 1629 * unaligned accesses. 1630 */ 1631 hwbase = ioremap_wc(bar4_addr, MBOX_SIZE * num); 1632 if (!hwbase) { 1633 dev_err(rvu->dev, "Unable to map mailbox region\n"); 1634 err = -ENOMEM; 1635 goto exit; 1636 } 1637 1638 err = otx2_mbox_init(&mw->mbox, hwbase, rvu->pdev, reg_base, dir, num); 1639 if (err) 1640 goto exit; 1641 1642 err = otx2_mbox_init(&mw->mbox_up, hwbase, rvu->pdev, 1643 reg_base, dir_up, num); 1644 if (err) 1645 goto exit; 1646 1647 for (i = 0; i < num; i++) { 1648 mwork = &mw->mbox_wrk[i]; 1649 mwork->rvu = rvu; 1650 INIT_WORK(&mwork->work, mbox_handler); 1651 1652 mwork = &mw->mbox_wrk_up[i]; 1653 mwork->rvu = rvu; 1654 INIT_WORK(&mwork->work, mbox_up_handler); 1655 } 1656 1657 return 0; 1658 exit: 1659 if (hwbase) 1660 iounmap((void __iomem *)hwbase); 1661 destroy_workqueue(mw->mbox_wq); 1662 return err; 1663 } 1664 1665 static void rvu_mbox_destroy(struct mbox_wq_info *mw) 1666 { 1667 if (mw->mbox_wq) { 1668 flush_workqueue(mw->mbox_wq); 1669 destroy_workqueue(mw->mbox_wq); 1670 mw->mbox_wq = NULL; 1671 } 1672 1673 if (mw->mbox.hwbase) 1674 iounmap((void __iomem *)mw->mbox.hwbase); 1675 1676 otx2_mbox_destroy(&mw->mbox); 1677 otx2_mbox_destroy(&mw->mbox_up); 1678 } 1679 1680 static void rvu_queue_work(struct mbox_wq_info *mw, int first, 1681 int mdevs, u64 intr) 1682 { 1683 struct otx2_mbox_dev *mdev; 1684 struct otx2_mbox *mbox; 1685 struct mbox_hdr *hdr; 1686 int i; 1687 1688 for (i = first; i < mdevs; i++) { 1689 /* start from 0 */ 1690 if (!(intr & BIT_ULL(i - first))) 1691 continue; 1692 1693 mbox = &mw->mbox; 1694 mdev = &mbox->dev[i]; 1695 hdr = mdev->mbase + mbox->rx_start; 1696 if (hdr->num_msgs) 1697 queue_work(mw->mbox_wq, &mw->mbox_wrk[i].work); 1698 1699 mbox = &mw->mbox_up; 1700 mdev = &mbox->dev[i]; 1701 hdr = mdev->mbase + mbox->rx_start; 1702 if (hdr->num_msgs) 1703 queue_work(mw->mbox_wq, &mw->mbox_wrk_up[i].work); 1704 } 1705 } 1706 1707 static irqreturn_t rvu_mbox_intr_handler(int irq, void *rvu_irq) 1708 { 1709 struct rvu *rvu = (struct rvu *)rvu_irq; 1710 int vfs = rvu->vfs; 1711 u64 intr; 1712 1713 intr = rvu_read64(rvu, BLKADDR_RVUM, RVU_AF_PFAF_MBOX_INT); 1714 /* Clear interrupts */ 1715 rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_PFAF_MBOX_INT, intr); 1716 1717 /* Sync with mbox memory region */ 1718 rmb(); 1719 1720 rvu_queue_work(&rvu->afpf_wq_info, 0, rvu->hw->total_pfs, intr); 1721 1722 /* Handle VF interrupts */ 1723 if (vfs > 64) { 1724 intr = rvupf_read64(rvu, RVU_PF_VFPF_MBOX_INTX(1)); 1725 rvupf_write64(rvu, RVU_PF_VFPF_MBOX_INTX(1), intr); 1726 1727 rvu_queue_work(&rvu->afvf_wq_info, 64, vfs, intr); 1728 vfs -= 64; 1729 } 1730 1731 intr = rvupf_read64(rvu, RVU_PF_VFPF_MBOX_INTX(0)); 1732 rvupf_write64(rvu, RVU_PF_VFPF_MBOX_INTX(0), intr); 1733 1734 rvu_queue_work(&rvu->afvf_wq_info, 0, vfs, intr); 1735 1736 return IRQ_HANDLED; 1737 } 1738 1739 static void rvu_enable_mbox_intr(struct rvu *rvu) 1740 { 1741 struct rvu_hwinfo *hw = rvu->hw; 1742 1743 /* Clear spurious irqs, if any */ 1744 rvu_write64(rvu, BLKADDR_RVUM, 1745 RVU_AF_PFAF_MBOX_INT, INTR_MASK(hw->total_pfs)); 1746 1747 /* Enable mailbox interrupt for all PFs except PF0 i.e AF itself */ 1748 rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_PFAF_MBOX_INT_ENA_W1S, 1749 INTR_MASK(hw->total_pfs) & ~1ULL); 1750 } 1751 1752 static void rvu_blklf_teardown(struct rvu *rvu, u16 pcifunc, u8 blkaddr) 1753 { 1754 struct rvu_block *block; 1755 int slot, lf, num_lfs; 1756 int err; 1757 1758 block = &rvu->hw->block[blkaddr]; 1759 num_lfs = rvu_get_rsrc_mapcount(rvu_get_pfvf(rvu, pcifunc), 1760 block->type); 1761 if (!num_lfs) 1762 return; 1763 for (slot = 0; slot < num_lfs; slot++) { 1764 lf = rvu_get_lf(rvu, block, pcifunc, slot); 1765 if (lf < 0) 1766 continue; 1767 1768 /* Cleanup LF and reset it */ 1769 if (block->addr == BLKADDR_NIX0) 1770 rvu_nix_lf_teardown(rvu, pcifunc, block->addr, lf); 1771 else if (block->addr == BLKADDR_NPA) 1772 rvu_npa_lf_teardown(rvu, pcifunc, lf); 1773 1774 err = rvu_lf_reset(rvu, block, lf); 1775 if (err) { 1776 dev_err(rvu->dev, "Failed to reset blkaddr %d LF%d\n", 1777 block->addr, lf); 1778 } 1779 } 1780 } 1781 1782 static void __rvu_flr_handler(struct rvu *rvu, u16 pcifunc) 1783 { 1784 mutex_lock(&rvu->flr_lock); 1785 /* Reset order should reflect inter-block dependencies: 1786 * 1. Reset any packet/work sources (NIX, CPT, TIM) 1787 * 2. Flush and reset SSO/SSOW 1788 * 3. Cleanup pools (NPA) 1789 */ 1790 rvu_blklf_teardown(rvu, pcifunc, BLKADDR_NIX0); 1791 rvu_blklf_teardown(rvu, pcifunc, BLKADDR_CPT0); 1792 rvu_blklf_teardown(rvu, pcifunc, BLKADDR_TIM); 1793 rvu_blklf_teardown(rvu, pcifunc, BLKADDR_SSOW); 1794 rvu_blklf_teardown(rvu, pcifunc, BLKADDR_SSO); 1795 rvu_blklf_teardown(rvu, pcifunc, BLKADDR_NPA); 1796 rvu_detach_rsrcs(rvu, NULL, pcifunc); 1797 mutex_unlock(&rvu->flr_lock); 1798 } 1799 1800 static void rvu_afvf_flr_handler(struct rvu *rvu, int vf) 1801 { 1802 int reg = 0; 1803 1804 /* pcifunc = 0(PF0) | (vf + 1) */ 1805 __rvu_flr_handler(rvu, vf + 1); 1806 1807 if (vf >= 64) { 1808 reg = 1; 1809 vf = vf - 64; 1810 } 1811 1812 /* Signal FLR finish and enable IRQ */ 1813 rvupf_write64(rvu, RVU_PF_VFTRPENDX(reg), BIT_ULL(vf)); 1814 rvupf_write64(rvu, RVU_PF_VFFLR_INT_ENA_W1SX(reg), BIT_ULL(vf)); 1815 } 1816 1817 static void rvu_flr_handler(struct work_struct *work) 1818 { 1819 struct rvu_work *flrwork = container_of(work, struct rvu_work, work); 1820 struct rvu *rvu = flrwork->rvu; 1821 u16 pcifunc, numvfs, vf; 1822 u64 cfg; 1823 int pf; 1824 1825 pf = flrwork - rvu->flr_wrk; 1826 if (pf >= rvu->hw->total_pfs) { 1827 rvu_afvf_flr_handler(rvu, pf - rvu->hw->total_pfs); 1828 return; 1829 } 1830 1831 cfg = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_PFX_CFG(pf)); 1832 numvfs = (cfg >> 12) & 0xFF; 1833 pcifunc = pf << RVU_PFVF_PF_SHIFT; 1834 1835 for (vf = 0; vf < numvfs; vf++) 1836 __rvu_flr_handler(rvu, (pcifunc | (vf + 1))); 1837 1838 __rvu_flr_handler(rvu, pcifunc); 1839 1840 /* Signal FLR finish */ 1841 rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_PFTRPEND, BIT_ULL(pf)); 1842 1843 /* Enable interrupt */ 1844 rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_PFFLR_INT_ENA_W1S, BIT_ULL(pf)); 1845 } 1846 1847 static void rvu_afvf_queue_flr_work(struct rvu *rvu, int start_vf, int numvfs) 1848 { 1849 int dev, vf, reg = 0; 1850 u64 intr; 1851 1852 if (start_vf >= 64) 1853 reg = 1; 1854 1855 intr = rvupf_read64(rvu, RVU_PF_VFFLR_INTX(reg)); 1856 if (!intr) 1857 return; 1858 1859 for (vf = 0; vf < numvfs; vf++) { 1860 if (!(intr & BIT_ULL(vf))) 1861 continue; 1862 dev = vf + start_vf + rvu->hw->total_pfs; 1863 queue_work(rvu->flr_wq, &rvu->flr_wrk[dev].work); 1864 /* Clear and disable the interrupt */ 1865 rvupf_write64(rvu, RVU_PF_VFFLR_INTX(reg), BIT_ULL(vf)); 1866 rvupf_write64(rvu, RVU_PF_VFFLR_INT_ENA_W1CX(reg), BIT_ULL(vf)); 1867 } 1868 } 1869 1870 static irqreturn_t rvu_flr_intr_handler(int irq, void *rvu_irq) 1871 { 1872 struct rvu *rvu = (struct rvu *)rvu_irq; 1873 u64 intr; 1874 u8 pf; 1875 1876 intr = rvu_read64(rvu, BLKADDR_RVUM, RVU_AF_PFFLR_INT); 1877 if (!intr) 1878 goto afvf_flr; 1879 1880 for (pf = 0; pf < rvu->hw->total_pfs; pf++) { 1881 if (intr & (1ULL << pf)) { 1882 /* PF is already dead do only AF related operations */ 1883 queue_work(rvu->flr_wq, &rvu->flr_wrk[pf].work); 1884 /* clear interrupt */ 1885 rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_PFFLR_INT, 1886 BIT_ULL(pf)); 1887 /* Disable the interrupt */ 1888 rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_PFFLR_INT_ENA_W1C, 1889 BIT_ULL(pf)); 1890 } 1891 } 1892 1893 afvf_flr: 1894 rvu_afvf_queue_flr_work(rvu, 0, 64); 1895 if (rvu->vfs > 64) 1896 rvu_afvf_queue_flr_work(rvu, 64, rvu->vfs - 64); 1897 1898 return IRQ_HANDLED; 1899 } 1900 1901 static void rvu_me_handle_vfset(struct rvu *rvu, int idx, u64 intr) 1902 { 1903 int vf; 1904 1905 /* Nothing to be done here other than clearing the 1906 * TRPEND bit. 1907 */ 1908 for (vf = 0; vf < 64; vf++) { 1909 if (intr & (1ULL << vf)) { 1910 /* clear the trpend due to ME(master enable) */ 1911 rvupf_write64(rvu, RVU_PF_VFTRPENDX(idx), BIT_ULL(vf)); 1912 /* clear interrupt */ 1913 rvupf_write64(rvu, RVU_PF_VFME_INTX(idx), BIT_ULL(vf)); 1914 } 1915 } 1916 } 1917 1918 /* Handles ME interrupts from VFs of AF */ 1919 static irqreturn_t rvu_me_vf_intr_handler(int irq, void *rvu_irq) 1920 { 1921 struct rvu *rvu = (struct rvu *)rvu_irq; 1922 int vfset; 1923 u64 intr; 1924 1925 intr = rvu_read64(rvu, BLKADDR_RVUM, RVU_AF_PFME_INT); 1926 1927 for (vfset = 0; vfset <= 1; vfset++) { 1928 intr = rvupf_read64(rvu, RVU_PF_VFME_INTX(vfset)); 1929 if (intr) 1930 rvu_me_handle_vfset(rvu, vfset, intr); 1931 } 1932 1933 return IRQ_HANDLED; 1934 } 1935 1936 /* Handles ME interrupts from PFs */ 1937 static irqreturn_t rvu_me_pf_intr_handler(int irq, void *rvu_irq) 1938 { 1939 struct rvu *rvu = (struct rvu *)rvu_irq; 1940 u64 intr; 1941 u8 pf; 1942 1943 intr = rvu_read64(rvu, BLKADDR_RVUM, RVU_AF_PFME_INT); 1944 1945 /* Nothing to be done here other than clearing the 1946 * TRPEND bit. 1947 */ 1948 for (pf = 0; pf < rvu->hw->total_pfs; pf++) { 1949 if (intr & (1ULL << pf)) { 1950 /* clear the trpend due to ME(master enable) */ 1951 rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_PFTRPEND, 1952 BIT_ULL(pf)); 1953 /* clear interrupt */ 1954 rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_PFME_INT, 1955 BIT_ULL(pf)); 1956 } 1957 } 1958 1959 return IRQ_HANDLED; 1960 } 1961 1962 static void rvu_unregister_interrupts(struct rvu *rvu) 1963 { 1964 int irq; 1965 1966 /* Disable the Mbox interrupt */ 1967 rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_PFAF_MBOX_INT_ENA_W1C, 1968 INTR_MASK(rvu->hw->total_pfs) & ~1ULL); 1969 1970 /* Disable the PF FLR interrupt */ 1971 rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_PFFLR_INT_ENA_W1C, 1972 INTR_MASK(rvu->hw->total_pfs) & ~1ULL); 1973 1974 /* Disable the PF ME interrupt */ 1975 rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_PFME_INT_ENA_W1C, 1976 INTR_MASK(rvu->hw->total_pfs) & ~1ULL); 1977 1978 for (irq = 0; irq < rvu->num_vec; irq++) { 1979 if (rvu->irq_allocated[irq]) 1980 free_irq(pci_irq_vector(rvu->pdev, irq), rvu); 1981 } 1982 1983 pci_free_irq_vectors(rvu->pdev); 1984 rvu->num_vec = 0; 1985 } 1986 1987 static int rvu_afvf_msix_vectors_num_ok(struct rvu *rvu) 1988 { 1989 struct rvu_pfvf *pfvf = &rvu->pf[0]; 1990 int offset; 1991 1992 pfvf = &rvu->pf[0]; 1993 offset = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_PFX_INT_CFG(0)) & 0x3ff; 1994 1995 /* Make sure there are enough MSIX vectors configured so that 1996 * VF interrupts can be handled. Offset equal to zero means 1997 * that PF vectors are not configured and overlapping AF vectors. 1998 */ 1999 return (pfvf->msix.max >= RVU_AF_INT_VEC_CNT + RVU_PF_INT_VEC_CNT) && 2000 offset; 2001 } 2002 2003 static int rvu_register_interrupts(struct rvu *rvu) 2004 { 2005 int ret, offset, pf_vec_start; 2006 2007 rvu->num_vec = pci_msix_vec_count(rvu->pdev); 2008 2009 rvu->irq_name = devm_kmalloc_array(rvu->dev, rvu->num_vec, 2010 NAME_SIZE, GFP_KERNEL); 2011 if (!rvu->irq_name) 2012 return -ENOMEM; 2013 2014 rvu->irq_allocated = devm_kcalloc(rvu->dev, rvu->num_vec, 2015 sizeof(bool), GFP_KERNEL); 2016 if (!rvu->irq_allocated) 2017 return -ENOMEM; 2018 2019 /* Enable MSI-X */ 2020 ret = pci_alloc_irq_vectors(rvu->pdev, rvu->num_vec, 2021 rvu->num_vec, PCI_IRQ_MSIX); 2022 if (ret < 0) { 2023 dev_err(rvu->dev, 2024 "RVUAF: Request for %d msix vectors failed, ret %d\n", 2025 rvu->num_vec, ret); 2026 return ret; 2027 } 2028 2029 /* Register mailbox interrupt handler */ 2030 sprintf(&rvu->irq_name[RVU_AF_INT_VEC_MBOX * NAME_SIZE], "RVUAF Mbox"); 2031 ret = request_irq(pci_irq_vector(rvu->pdev, RVU_AF_INT_VEC_MBOX), 2032 rvu_mbox_intr_handler, 0, 2033 &rvu->irq_name[RVU_AF_INT_VEC_MBOX * NAME_SIZE], rvu); 2034 if (ret) { 2035 dev_err(rvu->dev, 2036 "RVUAF: IRQ registration failed for mbox irq\n"); 2037 goto fail; 2038 } 2039 2040 rvu->irq_allocated[RVU_AF_INT_VEC_MBOX] = true; 2041 2042 /* Enable mailbox interrupts from all PFs */ 2043 rvu_enable_mbox_intr(rvu); 2044 2045 /* Register FLR interrupt handler */ 2046 sprintf(&rvu->irq_name[RVU_AF_INT_VEC_PFFLR * NAME_SIZE], 2047 "RVUAF FLR"); 2048 ret = request_irq(pci_irq_vector(rvu->pdev, RVU_AF_INT_VEC_PFFLR), 2049 rvu_flr_intr_handler, 0, 2050 &rvu->irq_name[RVU_AF_INT_VEC_PFFLR * NAME_SIZE], 2051 rvu); 2052 if (ret) { 2053 dev_err(rvu->dev, 2054 "RVUAF: IRQ registration failed for FLR\n"); 2055 goto fail; 2056 } 2057 rvu->irq_allocated[RVU_AF_INT_VEC_PFFLR] = true; 2058 2059 /* Enable FLR interrupt for all PFs*/ 2060 rvu_write64(rvu, BLKADDR_RVUM, 2061 RVU_AF_PFFLR_INT, INTR_MASK(rvu->hw->total_pfs)); 2062 2063 rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_PFFLR_INT_ENA_W1S, 2064 INTR_MASK(rvu->hw->total_pfs) & ~1ULL); 2065 2066 /* Register ME interrupt handler */ 2067 sprintf(&rvu->irq_name[RVU_AF_INT_VEC_PFME * NAME_SIZE], 2068 "RVUAF ME"); 2069 ret = request_irq(pci_irq_vector(rvu->pdev, RVU_AF_INT_VEC_PFME), 2070 rvu_me_pf_intr_handler, 0, 2071 &rvu->irq_name[RVU_AF_INT_VEC_PFME * NAME_SIZE], 2072 rvu); 2073 if (ret) { 2074 dev_err(rvu->dev, 2075 "RVUAF: IRQ registration failed for ME\n"); 2076 } 2077 rvu->irq_allocated[RVU_AF_INT_VEC_PFME] = true; 2078 2079 /* Enable ME interrupt for all PFs*/ 2080 rvu_write64(rvu, BLKADDR_RVUM, 2081 RVU_AF_PFME_INT, INTR_MASK(rvu->hw->total_pfs)); 2082 2083 rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_PFME_INT_ENA_W1S, 2084 INTR_MASK(rvu->hw->total_pfs) & ~1ULL); 2085 2086 if (!rvu_afvf_msix_vectors_num_ok(rvu)) 2087 return 0; 2088 2089 /* Get PF MSIX vectors offset. */ 2090 pf_vec_start = rvu_read64(rvu, BLKADDR_RVUM, 2091 RVU_PRIV_PFX_INT_CFG(0)) & 0x3ff; 2092 2093 /* Register MBOX0 interrupt. */ 2094 offset = pf_vec_start + RVU_PF_INT_VEC_VFPF_MBOX0; 2095 sprintf(&rvu->irq_name[offset * NAME_SIZE], "RVUAFVF Mbox0"); 2096 ret = request_irq(pci_irq_vector(rvu->pdev, offset), 2097 rvu_mbox_intr_handler, 0, 2098 &rvu->irq_name[offset * NAME_SIZE], 2099 rvu); 2100 if (ret) 2101 dev_err(rvu->dev, 2102 "RVUAF: IRQ registration failed for Mbox0\n"); 2103 2104 rvu->irq_allocated[offset] = true; 2105 2106 /* Register MBOX1 interrupt. MBOX1 IRQ number follows MBOX0 so 2107 * simply increment current offset by 1. 2108 */ 2109 offset = pf_vec_start + RVU_PF_INT_VEC_VFPF_MBOX1; 2110 sprintf(&rvu->irq_name[offset * NAME_SIZE], "RVUAFVF Mbox1"); 2111 ret = request_irq(pci_irq_vector(rvu->pdev, offset), 2112 rvu_mbox_intr_handler, 0, 2113 &rvu->irq_name[offset * NAME_SIZE], 2114 rvu); 2115 if (ret) 2116 dev_err(rvu->dev, 2117 "RVUAF: IRQ registration failed for Mbox1\n"); 2118 2119 rvu->irq_allocated[offset] = true; 2120 2121 /* Register FLR interrupt handler for AF's VFs */ 2122 offset = pf_vec_start + RVU_PF_INT_VEC_VFFLR0; 2123 sprintf(&rvu->irq_name[offset * NAME_SIZE], "RVUAFVF FLR0"); 2124 ret = request_irq(pci_irq_vector(rvu->pdev, offset), 2125 rvu_flr_intr_handler, 0, 2126 &rvu->irq_name[offset * NAME_SIZE], rvu); 2127 if (ret) { 2128 dev_err(rvu->dev, 2129 "RVUAF: IRQ registration failed for RVUAFVF FLR0\n"); 2130 goto fail; 2131 } 2132 rvu->irq_allocated[offset] = true; 2133 2134 offset = pf_vec_start + RVU_PF_INT_VEC_VFFLR1; 2135 sprintf(&rvu->irq_name[offset * NAME_SIZE], "RVUAFVF FLR1"); 2136 ret = request_irq(pci_irq_vector(rvu->pdev, offset), 2137 rvu_flr_intr_handler, 0, 2138 &rvu->irq_name[offset * NAME_SIZE], rvu); 2139 if (ret) { 2140 dev_err(rvu->dev, 2141 "RVUAF: IRQ registration failed for RVUAFVF FLR1\n"); 2142 goto fail; 2143 } 2144 rvu->irq_allocated[offset] = true; 2145 2146 /* Register ME interrupt handler for AF's VFs */ 2147 offset = pf_vec_start + RVU_PF_INT_VEC_VFME0; 2148 sprintf(&rvu->irq_name[offset * NAME_SIZE], "RVUAFVF ME0"); 2149 ret = request_irq(pci_irq_vector(rvu->pdev, offset), 2150 rvu_me_vf_intr_handler, 0, 2151 &rvu->irq_name[offset * NAME_SIZE], rvu); 2152 if (ret) { 2153 dev_err(rvu->dev, 2154 "RVUAF: IRQ registration failed for RVUAFVF ME0\n"); 2155 goto fail; 2156 } 2157 rvu->irq_allocated[offset] = true; 2158 2159 offset = pf_vec_start + RVU_PF_INT_VEC_VFME1; 2160 sprintf(&rvu->irq_name[offset * NAME_SIZE], "RVUAFVF ME1"); 2161 ret = request_irq(pci_irq_vector(rvu->pdev, offset), 2162 rvu_me_vf_intr_handler, 0, 2163 &rvu->irq_name[offset * NAME_SIZE], rvu); 2164 if (ret) { 2165 dev_err(rvu->dev, 2166 "RVUAF: IRQ registration failed for RVUAFVF ME1\n"); 2167 goto fail; 2168 } 2169 rvu->irq_allocated[offset] = true; 2170 return 0; 2171 2172 fail: 2173 rvu_unregister_interrupts(rvu); 2174 return ret; 2175 } 2176 2177 static void rvu_flr_wq_destroy(struct rvu *rvu) 2178 { 2179 if (rvu->flr_wq) { 2180 flush_workqueue(rvu->flr_wq); 2181 destroy_workqueue(rvu->flr_wq); 2182 rvu->flr_wq = NULL; 2183 } 2184 } 2185 2186 static int rvu_flr_init(struct rvu *rvu) 2187 { 2188 int dev, num_devs; 2189 u64 cfg; 2190 int pf; 2191 2192 /* Enable FLR for all PFs*/ 2193 for (pf = 0; pf < rvu->hw->total_pfs; pf++) { 2194 cfg = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_PFX_CFG(pf)); 2195 rvu_write64(rvu, BLKADDR_RVUM, RVU_PRIV_PFX_CFG(pf), 2196 cfg | BIT_ULL(22)); 2197 } 2198 2199 rvu->flr_wq = alloc_workqueue("rvu_afpf_flr", 2200 WQ_UNBOUND | WQ_HIGHPRI | WQ_MEM_RECLAIM, 2201 1); 2202 if (!rvu->flr_wq) 2203 return -ENOMEM; 2204 2205 num_devs = rvu->hw->total_pfs + pci_sriov_get_totalvfs(rvu->pdev); 2206 rvu->flr_wrk = devm_kcalloc(rvu->dev, num_devs, 2207 sizeof(struct rvu_work), GFP_KERNEL); 2208 if (!rvu->flr_wrk) { 2209 destroy_workqueue(rvu->flr_wq); 2210 return -ENOMEM; 2211 } 2212 2213 for (dev = 0; dev < num_devs; dev++) { 2214 rvu->flr_wrk[dev].rvu = rvu; 2215 INIT_WORK(&rvu->flr_wrk[dev].work, rvu_flr_handler); 2216 } 2217 2218 mutex_init(&rvu->flr_lock); 2219 2220 return 0; 2221 } 2222 2223 static void rvu_disable_afvf_intr(struct rvu *rvu) 2224 { 2225 int vfs = rvu->vfs; 2226 2227 rvupf_write64(rvu, RVU_PF_VFPF_MBOX_INT_ENA_W1CX(0), INTR_MASK(vfs)); 2228 rvupf_write64(rvu, RVU_PF_VFFLR_INT_ENA_W1CX(0), INTR_MASK(vfs)); 2229 rvupf_write64(rvu, RVU_PF_VFME_INT_ENA_W1CX(0), INTR_MASK(vfs)); 2230 if (vfs <= 64) 2231 return; 2232 2233 rvupf_write64(rvu, RVU_PF_VFPF_MBOX_INT_ENA_W1CX(1), 2234 INTR_MASK(vfs - 64)); 2235 rvupf_write64(rvu, RVU_PF_VFFLR_INT_ENA_W1CX(1), INTR_MASK(vfs - 64)); 2236 rvupf_write64(rvu, RVU_PF_VFME_INT_ENA_W1CX(1), INTR_MASK(vfs - 64)); 2237 } 2238 2239 static void rvu_enable_afvf_intr(struct rvu *rvu) 2240 { 2241 int vfs = rvu->vfs; 2242 2243 /* Clear any pending interrupts and enable AF VF interrupts for 2244 * the first 64 VFs. 2245 */ 2246 /* Mbox */ 2247 rvupf_write64(rvu, RVU_PF_VFPF_MBOX_INTX(0), INTR_MASK(vfs)); 2248 rvupf_write64(rvu, RVU_PF_VFPF_MBOX_INT_ENA_W1SX(0), INTR_MASK(vfs)); 2249 2250 /* FLR */ 2251 rvupf_write64(rvu, RVU_PF_VFFLR_INTX(0), INTR_MASK(vfs)); 2252 rvupf_write64(rvu, RVU_PF_VFFLR_INT_ENA_W1SX(0), INTR_MASK(vfs)); 2253 rvupf_write64(rvu, RVU_PF_VFME_INT_ENA_W1SX(0), INTR_MASK(vfs)); 2254 2255 /* Same for remaining VFs, if any. */ 2256 if (vfs <= 64) 2257 return; 2258 2259 rvupf_write64(rvu, RVU_PF_VFPF_MBOX_INTX(1), INTR_MASK(vfs - 64)); 2260 rvupf_write64(rvu, RVU_PF_VFPF_MBOX_INT_ENA_W1SX(1), 2261 INTR_MASK(vfs - 64)); 2262 2263 rvupf_write64(rvu, RVU_PF_VFFLR_INTX(1), INTR_MASK(vfs - 64)); 2264 rvupf_write64(rvu, RVU_PF_VFFLR_INT_ENA_W1SX(1), INTR_MASK(vfs - 64)); 2265 rvupf_write64(rvu, RVU_PF_VFME_INT_ENA_W1SX(1), INTR_MASK(vfs - 64)); 2266 } 2267 2268 #define PCI_DEVID_OCTEONTX2_LBK 0xA061 2269 2270 static int lbk_get_num_chans(void) 2271 { 2272 struct pci_dev *pdev; 2273 void __iomem *base; 2274 int ret = -EIO; 2275 2276 pdev = pci_get_device(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_OCTEONTX2_LBK, 2277 NULL); 2278 if (!pdev) 2279 goto err; 2280 2281 base = pci_ioremap_bar(pdev, 0); 2282 if (!base) 2283 goto err_put; 2284 2285 /* Read number of available LBK channels from LBK(0)_CONST register. */ 2286 ret = (readq(base + 0x10) >> 32) & 0xffff; 2287 iounmap(base); 2288 err_put: 2289 pci_dev_put(pdev); 2290 err: 2291 return ret; 2292 } 2293 2294 static int rvu_enable_sriov(struct rvu *rvu) 2295 { 2296 struct pci_dev *pdev = rvu->pdev; 2297 int err, chans, vfs; 2298 2299 if (!rvu_afvf_msix_vectors_num_ok(rvu)) { 2300 dev_warn(&pdev->dev, 2301 "Skipping SRIOV enablement since not enough IRQs are available\n"); 2302 return 0; 2303 } 2304 2305 chans = lbk_get_num_chans(); 2306 if (chans < 0) 2307 return chans; 2308 2309 vfs = pci_sriov_get_totalvfs(pdev); 2310 2311 /* Limit VFs in case we have more VFs than LBK channels available. */ 2312 if (vfs > chans) 2313 vfs = chans; 2314 2315 /* AF's VFs work in pairs and talk over consecutive loopback channels. 2316 * Thus we want to enable maximum even number of VFs. In case 2317 * odd number of VFs are available then the last VF on the list 2318 * remains disabled. 2319 */ 2320 if (vfs & 0x1) { 2321 dev_warn(&pdev->dev, 2322 "Number of VFs should be even. Enabling %d out of %d.\n", 2323 vfs - 1, vfs); 2324 vfs--; 2325 } 2326 2327 if (!vfs) 2328 return 0; 2329 2330 /* Save VFs number for reference in VF interrupts handlers. 2331 * Since interrupts might start arriving during SRIOV enablement 2332 * ordinary API cannot be used to get number of enabled VFs. 2333 */ 2334 rvu->vfs = vfs; 2335 2336 err = rvu_mbox_init(rvu, &rvu->afvf_wq_info, TYPE_AFVF, vfs, 2337 rvu_afvf_mbox_handler, rvu_afvf_mbox_up_handler); 2338 if (err) 2339 return err; 2340 2341 rvu_enable_afvf_intr(rvu); 2342 /* Make sure IRQs are enabled before SRIOV. */ 2343 mb(); 2344 2345 err = pci_enable_sriov(pdev, vfs); 2346 if (err) { 2347 rvu_disable_afvf_intr(rvu); 2348 rvu_mbox_destroy(&rvu->afvf_wq_info); 2349 return err; 2350 } 2351 2352 return 0; 2353 } 2354 2355 static void rvu_disable_sriov(struct rvu *rvu) 2356 { 2357 rvu_disable_afvf_intr(rvu); 2358 rvu_mbox_destroy(&rvu->afvf_wq_info); 2359 pci_disable_sriov(rvu->pdev); 2360 } 2361 2362 static int rvu_probe(struct pci_dev *pdev, const struct pci_device_id *id) 2363 { 2364 struct device *dev = &pdev->dev; 2365 struct rvu *rvu; 2366 int err; 2367 2368 rvu = devm_kzalloc(dev, sizeof(*rvu), GFP_KERNEL); 2369 if (!rvu) 2370 return -ENOMEM; 2371 2372 rvu->hw = devm_kzalloc(dev, sizeof(struct rvu_hwinfo), GFP_KERNEL); 2373 if (!rvu->hw) { 2374 devm_kfree(dev, rvu); 2375 return -ENOMEM; 2376 } 2377 2378 pci_set_drvdata(pdev, rvu); 2379 rvu->pdev = pdev; 2380 rvu->dev = &pdev->dev; 2381 2382 err = pci_enable_device(pdev); 2383 if (err) { 2384 dev_err(dev, "Failed to enable PCI device\n"); 2385 goto err_freemem; 2386 } 2387 2388 err = pci_request_regions(pdev, DRV_NAME); 2389 if (err) { 2390 dev_err(dev, "PCI request regions failed 0x%x\n", err); 2391 goto err_disable_device; 2392 } 2393 2394 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(48)); 2395 if (err) { 2396 dev_err(dev, "Unable to set DMA mask\n"); 2397 goto err_release_regions; 2398 } 2399 2400 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(48)); 2401 if (err) { 2402 dev_err(dev, "Unable to set consistent DMA mask\n"); 2403 goto err_release_regions; 2404 } 2405 2406 /* Map Admin function CSRs */ 2407 rvu->afreg_base = pcim_iomap(pdev, PCI_AF_REG_BAR_NUM, 0); 2408 rvu->pfreg_base = pcim_iomap(pdev, PCI_PF_REG_BAR_NUM, 0); 2409 if (!rvu->afreg_base || !rvu->pfreg_base) { 2410 dev_err(dev, "Unable to map admin function CSRs, aborting\n"); 2411 err = -ENOMEM; 2412 goto err_release_regions; 2413 } 2414 2415 /* Check which blocks the HW supports */ 2416 rvu_check_block_implemented(rvu); 2417 2418 rvu_reset_all_blocks(rvu); 2419 2420 err = rvu_setup_hw_resources(rvu); 2421 if (err) 2422 goto err_release_regions; 2423 2424 /* Init mailbox btw AF and PFs */ 2425 err = rvu_mbox_init(rvu, &rvu->afpf_wq_info, TYPE_AFPF, 2426 rvu->hw->total_pfs, rvu_afpf_mbox_handler, 2427 rvu_afpf_mbox_up_handler); 2428 if (err) 2429 goto err_hwsetup; 2430 2431 err = rvu_flr_init(rvu); 2432 if (err) 2433 goto err_mbox; 2434 2435 err = rvu_register_interrupts(rvu); 2436 if (err) 2437 goto err_flr; 2438 2439 /* Enable AF's VFs (if any) */ 2440 err = rvu_enable_sriov(rvu); 2441 if (err) 2442 goto err_irq; 2443 2444 return 0; 2445 err_irq: 2446 rvu_unregister_interrupts(rvu); 2447 err_flr: 2448 rvu_flr_wq_destroy(rvu); 2449 err_mbox: 2450 rvu_mbox_destroy(&rvu->afpf_wq_info); 2451 err_hwsetup: 2452 rvu_cgx_exit(rvu); 2453 rvu_reset_all_blocks(rvu); 2454 rvu_free_hw_resources(rvu); 2455 err_release_regions: 2456 pci_release_regions(pdev); 2457 err_disable_device: 2458 pci_disable_device(pdev); 2459 err_freemem: 2460 pci_set_drvdata(pdev, NULL); 2461 devm_kfree(&pdev->dev, rvu->hw); 2462 devm_kfree(dev, rvu); 2463 return err; 2464 } 2465 2466 static void rvu_remove(struct pci_dev *pdev) 2467 { 2468 struct rvu *rvu = pci_get_drvdata(pdev); 2469 2470 rvu_unregister_interrupts(rvu); 2471 rvu_flr_wq_destroy(rvu); 2472 rvu_cgx_exit(rvu); 2473 rvu_mbox_destroy(&rvu->afpf_wq_info); 2474 rvu_disable_sriov(rvu); 2475 rvu_reset_all_blocks(rvu); 2476 rvu_free_hw_resources(rvu); 2477 2478 pci_release_regions(pdev); 2479 pci_disable_device(pdev); 2480 pci_set_drvdata(pdev, NULL); 2481 2482 devm_kfree(&pdev->dev, rvu->hw); 2483 devm_kfree(&pdev->dev, rvu); 2484 } 2485 2486 static struct pci_driver rvu_driver = { 2487 .name = DRV_NAME, 2488 .id_table = rvu_id_table, 2489 .probe = rvu_probe, 2490 .remove = rvu_remove, 2491 }; 2492 2493 static int __init rvu_init_module(void) 2494 { 2495 int err; 2496 2497 pr_info("%s: %s\n", DRV_NAME, DRV_STRING); 2498 2499 err = pci_register_driver(&cgx_driver); 2500 if (err < 0) 2501 return err; 2502 2503 err = pci_register_driver(&rvu_driver); 2504 if (err < 0) 2505 pci_unregister_driver(&cgx_driver); 2506 2507 return err; 2508 } 2509 2510 static void __exit rvu_cleanup_module(void) 2511 { 2512 pci_unregister_driver(&rvu_driver); 2513 pci_unregister_driver(&cgx_driver); 2514 } 2515 2516 module_init(rvu_init_module); 2517 module_exit(rvu_cleanup_module); 2518