1 // SPDX-License-Identifier: GPL-2.0 2 /* Marvell RVU Admin Function driver 3 * 4 * Copyright (C) 2018 Marvell. 5 * 6 */ 7 8 #include <linux/module.h> 9 #include <linux/interrupt.h> 10 #include <linux/delay.h> 11 #include <linux/irq.h> 12 #include <linux/pci.h> 13 #include <linux/sysfs.h> 14 15 #include "cgx.h" 16 #include "rvu.h" 17 #include "rvu_reg.h" 18 #include "ptp.h" 19 20 #include "rvu_trace.h" 21 #include "rvu_npc_hash.h" 22 23 #define DRV_NAME "rvu_af" 24 #define DRV_STRING "Marvell OcteonTX2 RVU Admin Function Driver" 25 26 static int rvu_get_hwvf(struct rvu *rvu, int pcifunc); 27 28 static void rvu_set_msix_offset(struct rvu *rvu, struct rvu_pfvf *pfvf, 29 struct rvu_block *block, int lf); 30 static void rvu_clear_msix_offset(struct rvu *rvu, struct rvu_pfvf *pfvf, 31 struct rvu_block *block, int lf); 32 static void __rvu_flr_handler(struct rvu *rvu, u16 pcifunc); 33 34 static int rvu_mbox_init(struct rvu *rvu, struct mbox_wq_info *mw, 35 int type, int num, 36 void (mbox_handler)(struct work_struct *), 37 void (mbox_up_handler)(struct work_struct *)); 38 enum { 39 TYPE_AFVF, 40 TYPE_AFPF, 41 }; 42 43 /* Supported devices */ 44 static const struct pci_device_id rvu_id_table[] = { 45 { PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_OCTEONTX2_RVU_AF) }, 46 { 0, } /* end of table */ 47 }; 48 49 MODULE_AUTHOR("Sunil Goutham <sgoutham@marvell.com>"); 50 MODULE_DESCRIPTION(DRV_STRING); 51 MODULE_LICENSE("GPL v2"); 52 MODULE_DEVICE_TABLE(pci, rvu_id_table); 53 54 static char *mkex_profile; /* MKEX profile name */ 55 module_param(mkex_profile, charp, 0000); 56 MODULE_PARM_DESC(mkex_profile, "MKEX profile name string"); 57 58 static char *kpu_profile; /* KPU profile name */ 59 module_param(kpu_profile, charp, 0000); 60 MODULE_PARM_DESC(kpu_profile, "KPU profile name string"); 61 62 static void rvu_setup_hw_capabilities(struct rvu *rvu) 63 { 64 struct rvu_hwinfo *hw = rvu->hw; 65 66 hw->cap.nix_tx_aggr_lvl = NIX_TXSCH_LVL_TL1; 67 hw->cap.nix_fixed_txschq_mapping = false; 68 hw->cap.nix_shaping = true; 69 hw->cap.nix_tx_link_bp = true; 70 hw->cap.nix_rx_multicast = true; 71 hw->cap.nix_shaper_toggle_wait = false; 72 hw->cap.npc_hash_extract = false; 73 hw->cap.npc_exact_match_enabled = false; 74 hw->rvu = rvu; 75 76 if (is_rvu_pre_96xx_C0(rvu)) { 77 hw->cap.nix_fixed_txschq_mapping = true; 78 hw->cap.nix_txsch_per_cgx_lmac = 4; 79 hw->cap.nix_txsch_per_lbk_lmac = 132; 80 hw->cap.nix_txsch_per_sdp_lmac = 76; 81 hw->cap.nix_shaping = false; 82 hw->cap.nix_tx_link_bp = false; 83 if (is_rvu_96xx_A0(rvu) || is_rvu_95xx_A0(rvu)) 84 hw->cap.nix_rx_multicast = false; 85 } 86 if (!is_rvu_pre_96xx_C0(rvu)) 87 hw->cap.nix_shaper_toggle_wait = true; 88 89 if (!is_rvu_otx2(rvu)) 90 hw->cap.per_pf_mbox_regs = true; 91 92 if (is_rvu_npc_hash_extract_en(rvu)) 93 hw->cap.npc_hash_extract = true; 94 } 95 96 /* Poll a RVU block's register 'offset', for a 'zero' 97 * or 'nonzero' at bits specified by 'mask' 98 */ 99 int rvu_poll_reg(struct rvu *rvu, u64 block, u64 offset, u64 mask, bool zero) 100 { 101 unsigned long timeout = jiffies + usecs_to_jiffies(20000); 102 bool twice = false; 103 void __iomem *reg; 104 u64 reg_val; 105 106 reg = rvu->afreg_base + ((block << 28) | offset); 107 again: 108 reg_val = readq(reg); 109 if (zero && !(reg_val & mask)) 110 return 0; 111 if (!zero && (reg_val & mask)) 112 return 0; 113 if (time_before(jiffies, timeout)) { 114 usleep_range(1, 5); 115 goto again; 116 } 117 /* In scenarios where CPU is scheduled out before checking 118 * 'time_before' (above) and gets scheduled in such that 119 * jiffies are beyond timeout value, then check again if HW is 120 * done with the operation in the meantime. 121 */ 122 if (!twice) { 123 twice = true; 124 goto again; 125 } 126 return -EBUSY; 127 } 128 129 int rvu_alloc_rsrc(struct rsrc_bmap *rsrc) 130 { 131 int id; 132 133 if (!rsrc->bmap) 134 return -EINVAL; 135 136 id = find_first_zero_bit(rsrc->bmap, rsrc->max); 137 if (id >= rsrc->max) 138 return -ENOSPC; 139 140 __set_bit(id, rsrc->bmap); 141 142 return id; 143 } 144 145 int rvu_alloc_rsrc_contig(struct rsrc_bmap *rsrc, int nrsrc) 146 { 147 int start; 148 149 if (!rsrc->bmap) 150 return -EINVAL; 151 152 start = bitmap_find_next_zero_area(rsrc->bmap, rsrc->max, 0, nrsrc, 0); 153 if (start >= rsrc->max) 154 return -ENOSPC; 155 156 bitmap_set(rsrc->bmap, start, nrsrc); 157 return start; 158 } 159 160 static void rvu_free_rsrc_contig(struct rsrc_bmap *rsrc, int nrsrc, int start) 161 { 162 if (!rsrc->bmap) 163 return; 164 if (start >= rsrc->max) 165 return; 166 167 bitmap_clear(rsrc->bmap, start, nrsrc); 168 } 169 170 bool rvu_rsrc_check_contig(struct rsrc_bmap *rsrc, int nrsrc) 171 { 172 int start; 173 174 if (!rsrc->bmap) 175 return false; 176 177 start = bitmap_find_next_zero_area(rsrc->bmap, rsrc->max, 0, nrsrc, 0); 178 if (start >= rsrc->max) 179 return false; 180 181 return true; 182 } 183 184 void rvu_free_rsrc(struct rsrc_bmap *rsrc, int id) 185 { 186 if (!rsrc->bmap) 187 return; 188 189 __clear_bit(id, rsrc->bmap); 190 } 191 192 int rvu_rsrc_free_count(struct rsrc_bmap *rsrc) 193 { 194 int used; 195 196 if (!rsrc->bmap) 197 return 0; 198 199 used = bitmap_weight(rsrc->bmap, rsrc->max); 200 return (rsrc->max - used); 201 } 202 203 bool is_rsrc_free(struct rsrc_bmap *rsrc, int id) 204 { 205 if (!rsrc->bmap) 206 return false; 207 208 return !test_bit(id, rsrc->bmap); 209 } 210 211 int rvu_alloc_bitmap(struct rsrc_bmap *rsrc) 212 { 213 rsrc->bmap = kcalloc(BITS_TO_LONGS(rsrc->max), 214 sizeof(long), GFP_KERNEL); 215 if (!rsrc->bmap) 216 return -ENOMEM; 217 return 0; 218 } 219 220 void rvu_free_bitmap(struct rsrc_bmap *rsrc) 221 { 222 kfree(rsrc->bmap); 223 } 224 225 /* Get block LF's HW index from a PF_FUNC's block slot number */ 226 int rvu_get_lf(struct rvu *rvu, struct rvu_block *block, u16 pcifunc, u16 slot) 227 { 228 u16 match = 0; 229 int lf; 230 231 mutex_lock(&rvu->rsrc_lock); 232 for (lf = 0; lf < block->lf.max; lf++) { 233 if (block->fn_map[lf] == pcifunc) { 234 if (slot == match) { 235 mutex_unlock(&rvu->rsrc_lock); 236 return lf; 237 } 238 match++; 239 } 240 } 241 mutex_unlock(&rvu->rsrc_lock); 242 return -ENODEV; 243 } 244 245 /* Convert BLOCK_TYPE_E to a BLOCK_ADDR_E. 246 * Some silicon variants of OcteonTX2 supports 247 * multiple blocks of same type. 248 * 249 * @pcifunc has to be zero when no LF is yet attached. 250 * 251 * For a pcifunc if LFs are attached from multiple blocks of same type, then 252 * return blkaddr of first encountered block. 253 */ 254 int rvu_get_blkaddr(struct rvu *rvu, int blktype, u16 pcifunc) 255 { 256 int devnum, blkaddr = -ENODEV; 257 u64 cfg, reg; 258 bool is_pf; 259 260 switch (blktype) { 261 case BLKTYPE_NPC: 262 blkaddr = BLKADDR_NPC; 263 goto exit; 264 case BLKTYPE_NPA: 265 blkaddr = BLKADDR_NPA; 266 goto exit; 267 case BLKTYPE_NIX: 268 /* For now assume NIX0 */ 269 if (!pcifunc) { 270 blkaddr = BLKADDR_NIX0; 271 goto exit; 272 } 273 break; 274 case BLKTYPE_SSO: 275 blkaddr = BLKADDR_SSO; 276 goto exit; 277 case BLKTYPE_SSOW: 278 blkaddr = BLKADDR_SSOW; 279 goto exit; 280 case BLKTYPE_TIM: 281 blkaddr = BLKADDR_TIM; 282 goto exit; 283 case BLKTYPE_CPT: 284 /* For now assume CPT0 */ 285 if (!pcifunc) { 286 blkaddr = BLKADDR_CPT0; 287 goto exit; 288 } 289 break; 290 } 291 292 /* Check if this is a RVU PF or VF */ 293 if (pcifunc & RVU_PFVF_FUNC_MASK) { 294 is_pf = false; 295 devnum = rvu_get_hwvf(rvu, pcifunc); 296 } else { 297 is_pf = true; 298 devnum = rvu_get_pf(pcifunc); 299 } 300 301 /* Check if the 'pcifunc' has a NIX LF from 'BLKADDR_NIX0' or 302 * 'BLKADDR_NIX1'. 303 */ 304 if (blktype == BLKTYPE_NIX) { 305 reg = is_pf ? RVU_PRIV_PFX_NIXX_CFG(0) : 306 RVU_PRIV_HWVFX_NIXX_CFG(0); 307 cfg = rvu_read64(rvu, BLKADDR_RVUM, reg | (devnum << 16)); 308 if (cfg) { 309 blkaddr = BLKADDR_NIX0; 310 goto exit; 311 } 312 313 reg = is_pf ? RVU_PRIV_PFX_NIXX_CFG(1) : 314 RVU_PRIV_HWVFX_NIXX_CFG(1); 315 cfg = rvu_read64(rvu, BLKADDR_RVUM, reg | (devnum << 16)); 316 if (cfg) 317 blkaddr = BLKADDR_NIX1; 318 } 319 320 if (blktype == BLKTYPE_CPT) { 321 reg = is_pf ? RVU_PRIV_PFX_CPTX_CFG(0) : 322 RVU_PRIV_HWVFX_CPTX_CFG(0); 323 cfg = rvu_read64(rvu, BLKADDR_RVUM, reg | (devnum << 16)); 324 if (cfg) { 325 blkaddr = BLKADDR_CPT0; 326 goto exit; 327 } 328 329 reg = is_pf ? RVU_PRIV_PFX_CPTX_CFG(1) : 330 RVU_PRIV_HWVFX_CPTX_CFG(1); 331 cfg = rvu_read64(rvu, BLKADDR_RVUM, reg | (devnum << 16)); 332 if (cfg) 333 blkaddr = BLKADDR_CPT1; 334 } 335 336 exit: 337 if (is_block_implemented(rvu->hw, blkaddr)) 338 return blkaddr; 339 return -ENODEV; 340 } 341 342 static void rvu_update_rsrc_map(struct rvu *rvu, struct rvu_pfvf *pfvf, 343 struct rvu_block *block, u16 pcifunc, 344 u16 lf, bool attach) 345 { 346 int devnum, num_lfs = 0; 347 bool is_pf; 348 u64 reg; 349 350 if (lf >= block->lf.max) { 351 dev_err(&rvu->pdev->dev, 352 "%s: FATAL: LF %d is >= %s's max lfs i.e %d\n", 353 __func__, lf, block->name, block->lf.max); 354 return; 355 } 356 357 /* Check if this is for a RVU PF or VF */ 358 if (pcifunc & RVU_PFVF_FUNC_MASK) { 359 is_pf = false; 360 devnum = rvu_get_hwvf(rvu, pcifunc); 361 } else { 362 is_pf = true; 363 devnum = rvu_get_pf(pcifunc); 364 } 365 366 block->fn_map[lf] = attach ? pcifunc : 0; 367 368 switch (block->addr) { 369 case BLKADDR_NPA: 370 pfvf->npalf = attach ? true : false; 371 num_lfs = pfvf->npalf; 372 break; 373 case BLKADDR_NIX0: 374 case BLKADDR_NIX1: 375 pfvf->nixlf = attach ? true : false; 376 num_lfs = pfvf->nixlf; 377 break; 378 case BLKADDR_SSO: 379 attach ? pfvf->sso++ : pfvf->sso--; 380 num_lfs = pfvf->sso; 381 break; 382 case BLKADDR_SSOW: 383 attach ? pfvf->ssow++ : pfvf->ssow--; 384 num_lfs = pfvf->ssow; 385 break; 386 case BLKADDR_TIM: 387 attach ? pfvf->timlfs++ : pfvf->timlfs--; 388 num_lfs = pfvf->timlfs; 389 break; 390 case BLKADDR_CPT0: 391 attach ? pfvf->cptlfs++ : pfvf->cptlfs--; 392 num_lfs = pfvf->cptlfs; 393 break; 394 case BLKADDR_CPT1: 395 attach ? pfvf->cpt1_lfs++ : pfvf->cpt1_lfs--; 396 num_lfs = pfvf->cpt1_lfs; 397 break; 398 } 399 400 reg = is_pf ? block->pf_lfcnt_reg : block->vf_lfcnt_reg; 401 rvu_write64(rvu, BLKADDR_RVUM, reg | (devnum << 16), num_lfs); 402 } 403 404 inline int rvu_get_pf(u16 pcifunc) 405 { 406 return (pcifunc >> RVU_PFVF_PF_SHIFT) & RVU_PFVF_PF_MASK; 407 } 408 409 void rvu_get_pf_numvfs(struct rvu *rvu, int pf, int *numvfs, int *hwvf) 410 { 411 u64 cfg; 412 413 /* Get numVFs attached to this PF and first HWVF */ 414 cfg = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_PFX_CFG(pf)); 415 if (numvfs) 416 *numvfs = (cfg >> 12) & 0xFF; 417 if (hwvf) 418 *hwvf = cfg & 0xFFF; 419 } 420 421 static int rvu_get_hwvf(struct rvu *rvu, int pcifunc) 422 { 423 int pf, func; 424 u64 cfg; 425 426 pf = rvu_get_pf(pcifunc); 427 func = pcifunc & RVU_PFVF_FUNC_MASK; 428 429 /* Get first HWVF attached to this PF */ 430 cfg = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_PFX_CFG(pf)); 431 432 return ((cfg & 0xFFF) + func - 1); 433 } 434 435 struct rvu_pfvf *rvu_get_pfvf(struct rvu *rvu, int pcifunc) 436 { 437 /* Check if it is a PF or VF */ 438 if (pcifunc & RVU_PFVF_FUNC_MASK) 439 return &rvu->hwvf[rvu_get_hwvf(rvu, pcifunc)]; 440 else 441 return &rvu->pf[rvu_get_pf(pcifunc)]; 442 } 443 444 static bool is_pf_func_valid(struct rvu *rvu, u16 pcifunc) 445 { 446 int pf, vf, nvfs; 447 u64 cfg; 448 449 pf = rvu_get_pf(pcifunc); 450 if (pf >= rvu->hw->total_pfs) 451 return false; 452 453 if (!(pcifunc & RVU_PFVF_FUNC_MASK)) 454 return true; 455 456 /* Check if VF is within number of VFs attached to this PF */ 457 vf = (pcifunc & RVU_PFVF_FUNC_MASK) - 1; 458 cfg = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_PFX_CFG(pf)); 459 nvfs = (cfg >> 12) & 0xFF; 460 if (vf >= nvfs) 461 return false; 462 463 return true; 464 } 465 466 bool is_block_implemented(struct rvu_hwinfo *hw, int blkaddr) 467 { 468 struct rvu_block *block; 469 470 if (blkaddr < BLKADDR_RVUM || blkaddr >= BLK_COUNT) 471 return false; 472 473 block = &hw->block[blkaddr]; 474 return block->implemented; 475 } 476 477 static void rvu_check_block_implemented(struct rvu *rvu) 478 { 479 struct rvu_hwinfo *hw = rvu->hw; 480 struct rvu_block *block; 481 int blkid; 482 u64 cfg; 483 484 /* For each block check if 'implemented' bit is set */ 485 for (blkid = 0; blkid < BLK_COUNT; blkid++) { 486 block = &hw->block[blkid]; 487 cfg = rvupf_read64(rvu, RVU_PF_BLOCK_ADDRX_DISC(blkid)); 488 if (cfg & BIT_ULL(11)) 489 block->implemented = true; 490 } 491 } 492 493 static void rvu_setup_rvum_blk_revid(struct rvu *rvu) 494 { 495 rvu_write64(rvu, BLKADDR_RVUM, 496 RVU_PRIV_BLOCK_TYPEX_REV(BLKTYPE_RVUM), 497 RVU_BLK_RVUM_REVID); 498 } 499 500 static void rvu_clear_rvum_blk_revid(struct rvu *rvu) 501 { 502 rvu_write64(rvu, BLKADDR_RVUM, 503 RVU_PRIV_BLOCK_TYPEX_REV(BLKTYPE_RVUM), 0x00); 504 } 505 506 int rvu_lf_reset(struct rvu *rvu, struct rvu_block *block, int lf) 507 { 508 int err; 509 510 if (!block->implemented) 511 return 0; 512 513 rvu_write64(rvu, block->addr, block->lfreset_reg, lf | BIT_ULL(12)); 514 err = rvu_poll_reg(rvu, block->addr, block->lfreset_reg, BIT_ULL(12), 515 true); 516 return err; 517 } 518 519 static void rvu_block_reset(struct rvu *rvu, int blkaddr, u64 rst_reg) 520 { 521 struct rvu_block *block = &rvu->hw->block[blkaddr]; 522 int err; 523 524 if (!block->implemented) 525 return; 526 527 rvu_write64(rvu, blkaddr, rst_reg, BIT_ULL(0)); 528 err = rvu_poll_reg(rvu, blkaddr, rst_reg, BIT_ULL(63), true); 529 if (err) { 530 dev_err(rvu->dev, "HW block:%d reset timeout retrying again\n", blkaddr); 531 while (rvu_poll_reg(rvu, blkaddr, rst_reg, BIT_ULL(63), true) == -EBUSY) 532 ; 533 } 534 } 535 536 static void rvu_reset_all_blocks(struct rvu *rvu) 537 { 538 /* Do a HW reset of all RVU blocks */ 539 rvu_block_reset(rvu, BLKADDR_NPA, NPA_AF_BLK_RST); 540 rvu_block_reset(rvu, BLKADDR_NIX0, NIX_AF_BLK_RST); 541 rvu_block_reset(rvu, BLKADDR_NIX1, NIX_AF_BLK_RST); 542 rvu_block_reset(rvu, BLKADDR_NPC, NPC_AF_BLK_RST); 543 rvu_block_reset(rvu, BLKADDR_SSO, SSO_AF_BLK_RST); 544 rvu_block_reset(rvu, BLKADDR_TIM, TIM_AF_BLK_RST); 545 rvu_block_reset(rvu, BLKADDR_CPT0, CPT_AF_BLK_RST); 546 rvu_block_reset(rvu, BLKADDR_CPT1, CPT_AF_BLK_RST); 547 rvu_block_reset(rvu, BLKADDR_NDC_NIX0_RX, NDC_AF_BLK_RST); 548 rvu_block_reset(rvu, BLKADDR_NDC_NIX0_TX, NDC_AF_BLK_RST); 549 rvu_block_reset(rvu, BLKADDR_NDC_NIX1_RX, NDC_AF_BLK_RST); 550 rvu_block_reset(rvu, BLKADDR_NDC_NIX1_TX, NDC_AF_BLK_RST); 551 rvu_block_reset(rvu, BLKADDR_NDC_NPA0, NDC_AF_BLK_RST); 552 } 553 554 static void rvu_scan_block(struct rvu *rvu, struct rvu_block *block) 555 { 556 struct rvu_pfvf *pfvf; 557 u64 cfg; 558 int lf; 559 560 for (lf = 0; lf < block->lf.max; lf++) { 561 cfg = rvu_read64(rvu, block->addr, 562 block->lfcfg_reg | (lf << block->lfshift)); 563 if (!(cfg & BIT_ULL(63))) 564 continue; 565 566 /* Set this resource as being used */ 567 __set_bit(lf, block->lf.bmap); 568 569 /* Get, to whom this LF is attached */ 570 pfvf = rvu_get_pfvf(rvu, (cfg >> 8) & 0xFFFF); 571 rvu_update_rsrc_map(rvu, pfvf, block, 572 (cfg >> 8) & 0xFFFF, lf, true); 573 574 /* Set start MSIX vector for this LF within this PF/VF */ 575 rvu_set_msix_offset(rvu, pfvf, block, lf); 576 } 577 } 578 579 static void rvu_check_min_msix_vec(struct rvu *rvu, int nvecs, int pf, int vf) 580 { 581 int min_vecs; 582 583 if (!vf) 584 goto check_pf; 585 586 if (!nvecs) { 587 dev_warn(rvu->dev, 588 "PF%d:VF%d is configured with zero msix vectors, %d\n", 589 pf, vf - 1, nvecs); 590 } 591 return; 592 593 check_pf: 594 if (pf == 0) 595 min_vecs = RVU_AF_INT_VEC_CNT + RVU_PF_INT_VEC_CNT; 596 else 597 min_vecs = RVU_PF_INT_VEC_CNT; 598 599 if (!(nvecs < min_vecs)) 600 return; 601 dev_warn(rvu->dev, 602 "PF%d is configured with too few vectors, %d, min is %d\n", 603 pf, nvecs, min_vecs); 604 } 605 606 static int rvu_setup_msix_resources(struct rvu *rvu) 607 { 608 struct rvu_hwinfo *hw = rvu->hw; 609 int pf, vf, numvfs, hwvf, err; 610 int nvecs, offset, max_msix; 611 struct rvu_pfvf *pfvf; 612 u64 cfg, phy_addr; 613 dma_addr_t iova; 614 615 for (pf = 0; pf < hw->total_pfs; pf++) { 616 cfg = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_PFX_CFG(pf)); 617 /* If PF is not enabled, nothing to do */ 618 if (!((cfg >> 20) & 0x01)) 619 continue; 620 621 rvu_get_pf_numvfs(rvu, pf, &numvfs, &hwvf); 622 623 pfvf = &rvu->pf[pf]; 624 /* Get num of MSIX vectors attached to this PF */ 625 cfg = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_PFX_MSIX_CFG(pf)); 626 pfvf->msix.max = ((cfg >> 32) & 0xFFF) + 1; 627 rvu_check_min_msix_vec(rvu, pfvf->msix.max, pf, 0); 628 629 /* Alloc msix bitmap for this PF */ 630 err = rvu_alloc_bitmap(&pfvf->msix); 631 if (err) 632 return err; 633 634 /* Allocate memory for MSIX vector to RVU block LF mapping */ 635 pfvf->msix_lfmap = devm_kcalloc(rvu->dev, pfvf->msix.max, 636 sizeof(u16), GFP_KERNEL); 637 if (!pfvf->msix_lfmap) 638 return -ENOMEM; 639 640 /* For PF0 (AF) firmware will set msix vector offsets for 641 * AF, block AF and PF0_INT vectors, so jump to VFs. 642 */ 643 if (!pf) 644 goto setup_vfmsix; 645 646 /* Set MSIX offset for PF's 'RVU_PF_INT_VEC' vectors. 647 * These are allocated on driver init and never freed, 648 * so no need to set 'msix_lfmap' for these. 649 */ 650 cfg = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_PFX_INT_CFG(pf)); 651 nvecs = (cfg >> 12) & 0xFF; 652 cfg &= ~0x7FFULL; 653 offset = rvu_alloc_rsrc_contig(&pfvf->msix, nvecs); 654 rvu_write64(rvu, BLKADDR_RVUM, 655 RVU_PRIV_PFX_INT_CFG(pf), cfg | offset); 656 setup_vfmsix: 657 /* Alloc msix bitmap for VFs */ 658 for (vf = 0; vf < numvfs; vf++) { 659 pfvf = &rvu->hwvf[hwvf + vf]; 660 /* Get num of MSIX vectors attached to this VF */ 661 cfg = rvu_read64(rvu, BLKADDR_RVUM, 662 RVU_PRIV_PFX_MSIX_CFG(pf)); 663 pfvf->msix.max = (cfg & 0xFFF) + 1; 664 rvu_check_min_msix_vec(rvu, pfvf->msix.max, pf, vf + 1); 665 666 /* Alloc msix bitmap for this VF */ 667 err = rvu_alloc_bitmap(&pfvf->msix); 668 if (err) 669 return err; 670 671 pfvf->msix_lfmap = 672 devm_kcalloc(rvu->dev, pfvf->msix.max, 673 sizeof(u16), GFP_KERNEL); 674 if (!pfvf->msix_lfmap) 675 return -ENOMEM; 676 677 /* Set MSIX offset for HWVF's 'RVU_VF_INT_VEC' vectors. 678 * These are allocated on driver init and never freed, 679 * so no need to set 'msix_lfmap' for these. 680 */ 681 cfg = rvu_read64(rvu, BLKADDR_RVUM, 682 RVU_PRIV_HWVFX_INT_CFG(hwvf + vf)); 683 nvecs = (cfg >> 12) & 0xFF; 684 cfg &= ~0x7FFULL; 685 offset = rvu_alloc_rsrc_contig(&pfvf->msix, nvecs); 686 rvu_write64(rvu, BLKADDR_RVUM, 687 RVU_PRIV_HWVFX_INT_CFG(hwvf + vf), 688 cfg | offset); 689 } 690 } 691 692 /* HW interprets RVU_AF_MSIXTR_BASE address as an IOVA, hence 693 * create an IOMMU mapping for the physical address configured by 694 * firmware and reconfig RVU_AF_MSIXTR_BASE with IOVA. 695 */ 696 cfg = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_CONST); 697 max_msix = cfg & 0xFFFFF; 698 if (rvu->fwdata && rvu->fwdata->msixtr_base) 699 phy_addr = rvu->fwdata->msixtr_base; 700 else 701 phy_addr = rvu_read64(rvu, BLKADDR_RVUM, RVU_AF_MSIXTR_BASE); 702 703 iova = dma_map_resource(rvu->dev, phy_addr, 704 max_msix * PCI_MSIX_ENTRY_SIZE, 705 DMA_BIDIRECTIONAL, 0); 706 707 if (dma_mapping_error(rvu->dev, iova)) 708 return -ENOMEM; 709 710 rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_MSIXTR_BASE, (u64)iova); 711 rvu->msix_base_iova = iova; 712 rvu->msixtr_base_phy = phy_addr; 713 714 return 0; 715 } 716 717 static void rvu_reset_msix(struct rvu *rvu) 718 { 719 /* Restore msixtr base register */ 720 rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_MSIXTR_BASE, 721 rvu->msixtr_base_phy); 722 } 723 724 static void rvu_free_hw_resources(struct rvu *rvu) 725 { 726 struct rvu_hwinfo *hw = rvu->hw; 727 struct rvu_block *block; 728 struct rvu_pfvf *pfvf; 729 int id, max_msix; 730 u64 cfg; 731 732 rvu_npa_freemem(rvu); 733 rvu_npc_freemem(rvu); 734 rvu_nix_freemem(rvu); 735 736 /* Free block LF bitmaps */ 737 for (id = 0; id < BLK_COUNT; id++) { 738 block = &hw->block[id]; 739 kfree(block->lf.bmap); 740 } 741 742 /* Free MSIX bitmaps */ 743 for (id = 0; id < hw->total_pfs; id++) { 744 pfvf = &rvu->pf[id]; 745 kfree(pfvf->msix.bmap); 746 } 747 748 for (id = 0; id < hw->total_vfs; id++) { 749 pfvf = &rvu->hwvf[id]; 750 kfree(pfvf->msix.bmap); 751 } 752 753 /* Unmap MSIX vector base IOVA mapping */ 754 if (!rvu->msix_base_iova) 755 return; 756 cfg = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_CONST); 757 max_msix = cfg & 0xFFFFF; 758 dma_unmap_resource(rvu->dev, rvu->msix_base_iova, 759 max_msix * PCI_MSIX_ENTRY_SIZE, 760 DMA_BIDIRECTIONAL, 0); 761 762 rvu_reset_msix(rvu); 763 mutex_destroy(&rvu->rsrc_lock); 764 } 765 766 static void rvu_setup_pfvf_macaddress(struct rvu *rvu) 767 { 768 struct rvu_hwinfo *hw = rvu->hw; 769 int pf, vf, numvfs, hwvf; 770 struct rvu_pfvf *pfvf; 771 u64 *mac; 772 773 for (pf = 0; pf < hw->total_pfs; pf++) { 774 /* For PF0(AF), Assign MAC address to only VFs (LBKVFs) */ 775 if (!pf) 776 goto lbkvf; 777 778 if (!is_pf_cgxmapped(rvu, pf)) 779 continue; 780 /* Assign MAC address to PF */ 781 pfvf = &rvu->pf[pf]; 782 if (rvu->fwdata && pf < PF_MACNUM_MAX) { 783 mac = &rvu->fwdata->pf_macs[pf]; 784 if (*mac) 785 u64_to_ether_addr(*mac, pfvf->mac_addr); 786 else 787 eth_random_addr(pfvf->mac_addr); 788 } else { 789 eth_random_addr(pfvf->mac_addr); 790 } 791 ether_addr_copy(pfvf->default_mac, pfvf->mac_addr); 792 793 lbkvf: 794 /* Assign MAC address to VFs*/ 795 rvu_get_pf_numvfs(rvu, pf, &numvfs, &hwvf); 796 for (vf = 0; vf < numvfs; vf++, hwvf++) { 797 pfvf = &rvu->hwvf[hwvf]; 798 if (rvu->fwdata && hwvf < VF_MACNUM_MAX) { 799 mac = &rvu->fwdata->vf_macs[hwvf]; 800 if (*mac) 801 u64_to_ether_addr(*mac, pfvf->mac_addr); 802 else 803 eth_random_addr(pfvf->mac_addr); 804 } else { 805 eth_random_addr(pfvf->mac_addr); 806 } 807 ether_addr_copy(pfvf->default_mac, pfvf->mac_addr); 808 } 809 } 810 } 811 812 static int rvu_fwdata_init(struct rvu *rvu) 813 { 814 u64 fwdbase; 815 int err; 816 817 /* Get firmware data base address */ 818 err = cgx_get_fwdata_base(&fwdbase); 819 if (err) 820 goto fail; 821 rvu->fwdata = ioremap_wc(fwdbase, sizeof(struct rvu_fwdata)); 822 if (!rvu->fwdata) 823 goto fail; 824 if (!is_rvu_fwdata_valid(rvu)) { 825 dev_err(rvu->dev, 826 "Mismatch in 'fwdata' struct btw kernel and firmware\n"); 827 iounmap(rvu->fwdata); 828 rvu->fwdata = NULL; 829 return -EINVAL; 830 } 831 return 0; 832 fail: 833 dev_info(rvu->dev, "Unable to fetch 'fwdata' from firmware\n"); 834 return -EIO; 835 } 836 837 static void rvu_fwdata_exit(struct rvu *rvu) 838 { 839 if (rvu->fwdata) 840 iounmap(rvu->fwdata); 841 } 842 843 static int rvu_setup_nix_hw_resource(struct rvu *rvu, int blkaddr) 844 { 845 struct rvu_hwinfo *hw = rvu->hw; 846 struct rvu_block *block; 847 int blkid; 848 u64 cfg; 849 850 /* Init NIX LF's bitmap */ 851 block = &hw->block[blkaddr]; 852 if (!block->implemented) 853 return 0; 854 blkid = (blkaddr == BLKADDR_NIX0) ? 0 : 1; 855 cfg = rvu_read64(rvu, blkaddr, NIX_AF_CONST2); 856 block->lf.max = cfg & 0xFFF; 857 block->addr = blkaddr; 858 block->type = BLKTYPE_NIX; 859 block->lfshift = 8; 860 block->lookup_reg = NIX_AF_RVU_LF_CFG_DEBUG; 861 block->pf_lfcnt_reg = RVU_PRIV_PFX_NIXX_CFG(blkid); 862 block->vf_lfcnt_reg = RVU_PRIV_HWVFX_NIXX_CFG(blkid); 863 block->lfcfg_reg = NIX_PRIV_LFX_CFG; 864 block->msixcfg_reg = NIX_PRIV_LFX_INT_CFG; 865 block->lfreset_reg = NIX_AF_LF_RST; 866 block->rvu = rvu; 867 sprintf(block->name, "NIX%d", blkid); 868 rvu->nix_blkaddr[blkid] = blkaddr; 869 return rvu_alloc_bitmap(&block->lf); 870 } 871 872 static int rvu_setup_cpt_hw_resource(struct rvu *rvu, int blkaddr) 873 { 874 struct rvu_hwinfo *hw = rvu->hw; 875 struct rvu_block *block; 876 int blkid; 877 u64 cfg; 878 879 /* Init CPT LF's bitmap */ 880 block = &hw->block[blkaddr]; 881 if (!block->implemented) 882 return 0; 883 blkid = (blkaddr == BLKADDR_CPT0) ? 0 : 1; 884 cfg = rvu_read64(rvu, blkaddr, CPT_AF_CONSTANTS0); 885 block->lf.max = cfg & 0xFF; 886 block->addr = blkaddr; 887 block->type = BLKTYPE_CPT; 888 block->multislot = true; 889 block->lfshift = 3; 890 block->lookup_reg = CPT_AF_RVU_LF_CFG_DEBUG; 891 block->pf_lfcnt_reg = RVU_PRIV_PFX_CPTX_CFG(blkid); 892 block->vf_lfcnt_reg = RVU_PRIV_HWVFX_CPTX_CFG(blkid); 893 block->lfcfg_reg = CPT_PRIV_LFX_CFG; 894 block->msixcfg_reg = CPT_PRIV_LFX_INT_CFG; 895 block->lfreset_reg = CPT_AF_LF_RST; 896 block->rvu = rvu; 897 sprintf(block->name, "CPT%d", blkid); 898 return rvu_alloc_bitmap(&block->lf); 899 } 900 901 static void rvu_get_lbk_bufsize(struct rvu *rvu) 902 { 903 struct pci_dev *pdev = NULL; 904 void __iomem *base; 905 u64 lbk_const; 906 907 pdev = pci_get_device(PCI_VENDOR_ID_CAVIUM, 908 PCI_DEVID_OCTEONTX2_LBK, pdev); 909 if (!pdev) 910 return; 911 912 base = pci_ioremap_bar(pdev, 0); 913 if (!base) 914 goto err_put; 915 916 lbk_const = readq(base + LBK_CONST); 917 918 /* cache fifo size */ 919 rvu->hw->lbk_bufsize = FIELD_GET(LBK_CONST_BUF_SIZE, lbk_const); 920 921 iounmap(base); 922 err_put: 923 pci_dev_put(pdev); 924 } 925 926 static int rvu_setup_hw_resources(struct rvu *rvu) 927 { 928 struct rvu_hwinfo *hw = rvu->hw; 929 struct rvu_block *block; 930 int blkid, err; 931 u64 cfg; 932 933 /* Get HW supported max RVU PF & VF count */ 934 cfg = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_CONST); 935 hw->total_pfs = (cfg >> 32) & 0xFF; 936 hw->total_vfs = (cfg >> 20) & 0xFFF; 937 hw->max_vfs_per_pf = (cfg >> 40) & 0xFF; 938 939 /* Init NPA LF's bitmap */ 940 block = &hw->block[BLKADDR_NPA]; 941 if (!block->implemented) 942 goto nix; 943 cfg = rvu_read64(rvu, BLKADDR_NPA, NPA_AF_CONST); 944 block->lf.max = (cfg >> 16) & 0xFFF; 945 block->addr = BLKADDR_NPA; 946 block->type = BLKTYPE_NPA; 947 block->lfshift = 8; 948 block->lookup_reg = NPA_AF_RVU_LF_CFG_DEBUG; 949 block->pf_lfcnt_reg = RVU_PRIV_PFX_NPA_CFG; 950 block->vf_lfcnt_reg = RVU_PRIV_HWVFX_NPA_CFG; 951 block->lfcfg_reg = NPA_PRIV_LFX_CFG; 952 block->msixcfg_reg = NPA_PRIV_LFX_INT_CFG; 953 block->lfreset_reg = NPA_AF_LF_RST; 954 block->rvu = rvu; 955 sprintf(block->name, "NPA"); 956 err = rvu_alloc_bitmap(&block->lf); 957 if (err) { 958 dev_err(rvu->dev, 959 "%s: Failed to allocate NPA LF bitmap\n", __func__); 960 return err; 961 } 962 963 nix: 964 err = rvu_setup_nix_hw_resource(rvu, BLKADDR_NIX0); 965 if (err) { 966 dev_err(rvu->dev, 967 "%s: Failed to allocate NIX0 LFs bitmap\n", __func__); 968 return err; 969 } 970 971 err = rvu_setup_nix_hw_resource(rvu, BLKADDR_NIX1); 972 if (err) { 973 dev_err(rvu->dev, 974 "%s: Failed to allocate NIX1 LFs bitmap\n", __func__); 975 return err; 976 } 977 978 /* Init SSO group's bitmap */ 979 block = &hw->block[BLKADDR_SSO]; 980 if (!block->implemented) 981 goto ssow; 982 cfg = rvu_read64(rvu, BLKADDR_SSO, SSO_AF_CONST); 983 block->lf.max = cfg & 0xFFFF; 984 block->addr = BLKADDR_SSO; 985 block->type = BLKTYPE_SSO; 986 block->multislot = true; 987 block->lfshift = 3; 988 block->lookup_reg = SSO_AF_RVU_LF_CFG_DEBUG; 989 block->pf_lfcnt_reg = RVU_PRIV_PFX_SSO_CFG; 990 block->vf_lfcnt_reg = RVU_PRIV_HWVFX_SSO_CFG; 991 block->lfcfg_reg = SSO_PRIV_LFX_HWGRP_CFG; 992 block->msixcfg_reg = SSO_PRIV_LFX_HWGRP_INT_CFG; 993 block->lfreset_reg = SSO_AF_LF_HWGRP_RST; 994 block->rvu = rvu; 995 sprintf(block->name, "SSO GROUP"); 996 err = rvu_alloc_bitmap(&block->lf); 997 if (err) { 998 dev_err(rvu->dev, 999 "%s: Failed to allocate SSO LF bitmap\n", __func__); 1000 return err; 1001 } 1002 1003 ssow: 1004 /* Init SSO workslot's bitmap */ 1005 block = &hw->block[BLKADDR_SSOW]; 1006 if (!block->implemented) 1007 goto tim; 1008 block->lf.max = (cfg >> 56) & 0xFF; 1009 block->addr = BLKADDR_SSOW; 1010 block->type = BLKTYPE_SSOW; 1011 block->multislot = true; 1012 block->lfshift = 3; 1013 block->lookup_reg = SSOW_AF_RVU_LF_HWS_CFG_DEBUG; 1014 block->pf_lfcnt_reg = RVU_PRIV_PFX_SSOW_CFG; 1015 block->vf_lfcnt_reg = RVU_PRIV_HWVFX_SSOW_CFG; 1016 block->lfcfg_reg = SSOW_PRIV_LFX_HWS_CFG; 1017 block->msixcfg_reg = SSOW_PRIV_LFX_HWS_INT_CFG; 1018 block->lfreset_reg = SSOW_AF_LF_HWS_RST; 1019 block->rvu = rvu; 1020 sprintf(block->name, "SSOWS"); 1021 err = rvu_alloc_bitmap(&block->lf); 1022 if (err) { 1023 dev_err(rvu->dev, 1024 "%s: Failed to allocate SSOW LF bitmap\n", __func__); 1025 return err; 1026 } 1027 1028 tim: 1029 /* Init TIM LF's bitmap */ 1030 block = &hw->block[BLKADDR_TIM]; 1031 if (!block->implemented) 1032 goto cpt; 1033 cfg = rvu_read64(rvu, BLKADDR_TIM, TIM_AF_CONST); 1034 block->lf.max = cfg & 0xFFFF; 1035 block->addr = BLKADDR_TIM; 1036 block->type = BLKTYPE_TIM; 1037 block->multislot = true; 1038 block->lfshift = 3; 1039 block->lookup_reg = TIM_AF_RVU_LF_CFG_DEBUG; 1040 block->pf_lfcnt_reg = RVU_PRIV_PFX_TIM_CFG; 1041 block->vf_lfcnt_reg = RVU_PRIV_HWVFX_TIM_CFG; 1042 block->lfcfg_reg = TIM_PRIV_LFX_CFG; 1043 block->msixcfg_reg = TIM_PRIV_LFX_INT_CFG; 1044 block->lfreset_reg = TIM_AF_LF_RST; 1045 block->rvu = rvu; 1046 sprintf(block->name, "TIM"); 1047 err = rvu_alloc_bitmap(&block->lf); 1048 if (err) { 1049 dev_err(rvu->dev, 1050 "%s: Failed to allocate TIM LF bitmap\n", __func__); 1051 return err; 1052 } 1053 1054 cpt: 1055 err = rvu_setup_cpt_hw_resource(rvu, BLKADDR_CPT0); 1056 if (err) { 1057 dev_err(rvu->dev, 1058 "%s: Failed to allocate CPT0 LF bitmap\n", __func__); 1059 return err; 1060 } 1061 err = rvu_setup_cpt_hw_resource(rvu, BLKADDR_CPT1); 1062 if (err) { 1063 dev_err(rvu->dev, 1064 "%s: Failed to allocate CPT1 LF bitmap\n", __func__); 1065 return err; 1066 } 1067 1068 /* Allocate memory for PFVF data */ 1069 rvu->pf = devm_kcalloc(rvu->dev, hw->total_pfs, 1070 sizeof(struct rvu_pfvf), GFP_KERNEL); 1071 if (!rvu->pf) { 1072 dev_err(rvu->dev, 1073 "%s: Failed to allocate memory for PF's rvu_pfvf struct\n", __func__); 1074 return -ENOMEM; 1075 } 1076 1077 rvu->hwvf = devm_kcalloc(rvu->dev, hw->total_vfs, 1078 sizeof(struct rvu_pfvf), GFP_KERNEL); 1079 if (!rvu->hwvf) { 1080 dev_err(rvu->dev, 1081 "%s: Failed to allocate memory for VF's rvu_pfvf struct\n", __func__); 1082 return -ENOMEM; 1083 } 1084 1085 mutex_init(&rvu->rsrc_lock); 1086 1087 rvu_fwdata_init(rvu); 1088 1089 err = rvu_setup_msix_resources(rvu); 1090 if (err) { 1091 dev_err(rvu->dev, 1092 "%s: Failed to setup MSIX resources\n", __func__); 1093 return err; 1094 } 1095 1096 for (blkid = 0; blkid < BLK_COUNT; blkid++) { 1097 block = &hw->block[blkid]; 1098 if (!block->lf.bmap) 1099 continue; 1100 1101 /* Allocate memory for block LF/slot to pcifunc mapping info */ 1102 block->fn_map = devm_kcalloc(rvu->dev, block->lf.max, 1103 sizeof(u16), GFP_KERNEL); 1104 if (!block->fn_map) { 1105 err = -ENOMEM; 1106 goto msix_err; 1107 } 1108 1109 /* Scan all blocks to check if low level firmware has 1110 * already provisioned any of the resources to a PF/VF. 1111 */ 1112 rvu_scan_block(rvu, block); 1113 } 1114 1115 err = rvu_set_channels_base(rvu); 1116 if (err) 1117 goto msix_err; 1118 1119 err = rvu_npc_init(rvu); 1120 if (err) { 1121 dev_err(rvu->dev, "%s: Failed to initialize npc\n", __func__); 1122 goto npc_err; 1123 } 1124 1125 err = rvu_cgx_init(rvu); 1126 if (err) { 1127 dev_err(rvu->dev, "%s: Failed to initialize cgx\n", __func__); 1128 goto cgx_err; 1129 } 1130 1131 err = rvu_npc_exact_init(rvu); 1132 if (err) { 1133 dev_err(rvu->dev, "failed to initialize exact match table\n"); 1134 return err; 1135 } 1136 1137 /* Assign MACs for CGX mapped functions */ 1138 rvu_setup_pfvf_macaddress(rvu); 1139 1140 err = rvu_npa_init(rvu); 1141 if (err) { 1142 dev_err(rvu->dev, "%s: Failed to initialize npa\n", __func__); 1143 goto npa_err; 1144 } 1145 1146 rvu_get_lbk_bufsize(rvu); 1147 1148 err = rvu_nix_init(rvu); 1149 if (err) { 1150 dev_err(rvu->dev, "%s: Failed to initialize nix\n", __func__); 1151 goto nix_err; 1152 } 1153 1154 err = rvu_sdp_init(rvu); 1155 if (err) { 1156 dev_err(rvu->dev, "%s: Failed to initialize sdp\n", __func__); 1157 goto nix_err; 1158 } 1159 1160 rvu_program_channels(rvu); 1161 1162 return 0; 1163 1164 nix_err: 1165 rvu_nix_freemem(rvu); 1166 npa_err: 1167 rvu_npa_freemem(rvu); 1168 cgx_err: 1169 rvu_cgx_exit(rvu); 1170 npc_err: 1171 rvu_npc_freemem(rvu); 1172 rvu_fwdata_exit(rvu); 1173 msix_err: 1174 rvu_reset_msix(rvu); 1175 return err; 1176 } 1177 1178 /* NPA and NIX admin queue APIs */ 1179 void rvu_aq_free(struct rvu *rvu, struct admin_queue *aq) 1180 { 1181 if (!aq) 1182 return; 1183 1184 qmem_free(rvu->dev, aq->inst); 1185 qmem_free(rvu->dev, aq->res); 1186 devm_kfree(rvu->dev, aq); 1187 } 1188 1189 int rvu_aq_alloc(struct rvu *rvu, struct admin_queue **ad_queue, 1190 int qsize, int inst_size, int res_size) 1191 { 1192 struct admin_queue *aq; 1193 int err; 1194 1195 *ad_queue = devm_kzalloc(rvu->dev, sizeof(*aq), GFP_KERNEL); 1196 if (!*ad_queue) 1197 return -ENOMEM; 1198 aq = *ad_queue; 1199 1200 /* Alloc memory for instructions i.e AQ */ 1201 err = qmem_alloc(rvu->dev, &aq->inst, qsize, inst_size); 1202 if (err) { 1203 devm_kfree(rvu->dev, aq); 1204 return err; 1205 } 1206 1207 /* Alloc memory for results */ 1208 err = qmem_alloc(rvu->dev, &aq->res, qsize, res_size); 1209 if (err) { 1210 rvu_aq_free(rvu, aq); 1211 return err; 1212 } 1213 1214 spin_lock_init(&aq->lock); 1215 return 0; 1216 } 1217 1218 int rvu_mbox_handler_ready(struct rvu *rvu, struct msg_req *req, 1219 struct ready_msg_rsp *rsp) 1220 { 1221 if (rvu->fwdata) { 1222 rsp->rclk_freq = rvu->fwdata->rclk; 1223 rsp->sclk_freq = rvu->fwdata->sclk; 1224 } 1225 return 0; 1226 } 1227 1228 /* Get current count of a RVU block's LF/slots 1229 * provisioned to a given RVU func. 1230 */ 1231 u16 rvu_get_rsrc_mapcount(struct rvu_pfvf *pfvf, int blkaddr) 1232 { 1233 switch (blkaddr) { 1234 case BLKADDR_NPA: 1235 return pfvf->npalf ? 1 : 0; 1236 case BLKADDR_NIX0: 1237 case BLKADDR_NIX1: 1238 return pfvf->nixlf ? 1 : 0; 1239 case BLKADDR_SSO: 1240 return pfvf->sso; 1241 case BLKADDR_SSOW: 1242 return pfvf->ssow; 1243 case BLKADDR_TIM: 1244 return pfvf->timlfs; 1245 case BLKADDR_CPT0: 1246 return pfvf->cptlfs; 1247 case BLKADDR_CPT1: 1248 return pfvf->cpt1_lfs; 1249 } 1250 return 0; 1251 } 1252 1253 /* Return true if LFs of block type are attached to pcifunc */ 1254 static bool is_blktype_attached(struct rvu_pfvf *pfvf, int blktype) 1255 { 1256 switch (blktype) { 1257 case BLKTYPE_NPA: 1258 return pfvf->npalf ? 1 : 0; 1259 case BLKTYPE_NIX: 1260 return pfvf->nixlf ? 1 : 0; 1261 case BLKTYPE_SSO: 1262 return !!pfvf->sso; 1263 case BLKTYPE_SSOW: 1264 return !!pfvf->ssow; 1265 case BLKTYPE_TIM: 1266 return !!pfvf->timlfs; 1267 case BLKTYPE_CPT: 1268 return pfvf->cptlfs || pfvf->cpt1_lfs; 1269 } 1270 1271 return false; 1272 } 1273 1274 bool is_pffunc_map_valid(struct rvu *rvu, u16 pcifunc, int blktype) 1275 { 1276 struct rvu_pfvf *pfvf; 1277 1278 if (!is_pf_func_valid(rvu, pcifunc)) 1279 return false; 1280 1281 pfvf = rvu_get_pfvf(rvu, pcifunc); 1282 1283 /* Check if this PFFUNC has a LF of type blktype attached */ 1284 if (!is_blktype_attached(pfvf, blktype)) 1285 return false; 1286 1287 return true; 1288 } 1289 1290 static int rvu_lookup_rsrc(struct rvu *rvu, struct rvu_block *block, 1291 int pcifunc, int slot) 1292 { 1293 u64 val; 1294 1295 val = ((u64)pcifunc << 24) | (slot << 16) | (1ULL << 13); 1296 rvu_write64(rvu, block->addr, block->lookup_reg, val); 1297 /* Wait for the lookup to finish */ 1298 /* TODO: put some timeout here */ 1299 while (rvu_read64(rvu, block->addr, block->lookup_reg) & (1ULL << 13)) 1300 ; 1301 1302 val = rvu_read64(rvu, block->addr, block->lookup_reg); 1303 1304 /* Check LF valid bit */ 1305 if (!(val & (1ULL << 12))) 1306 return -1; 1307 1308 return (val & 0xFFF); 1309 } 1310 1311 int rvu_get_blkaddr_from_slot(struct rvu *rvu, int blktype, u16 pcifunc, 1312 u16 global_slot, u16 *slot_in_block) 1313 { 1314 struct rvu_pfvf *pfvf = rvu_get_pfvf(rvu, pcifunc); 1315 int numlfs, total_lfs = 0, nr_blocks = 0; 1316 int i, num_blkaddr[BLK_COUNT] = { 0 }; 1317 struct rvu_block *block; 1318 int blkaddr; 1319 u16 start_slot; 1320 1321 if (!is_blktype_attached(pfvf, blktype)) 1322 return -ENODEV; 1323 1324 /* Get all the block addresses from which LFs are attached to 1325 * the given pcifunc in num_blkaddr[]. 1326 */ 1327 for (blkaddr = BLKADDR_RVUM; blkaddr < BLK_COUNT; blkaddr++) { 1328 block = &rvu->hw->block[blkaddr]; 1329 if (block->type != blktype) 1330 continue; 1331 if (!is_block_implemented(rvu->hw, blkaddr)) 1332 continue; 1333 1334 numlfs = rvu_get_rsrc_mapcount(pfvf, blkaddr); 1335 if (numlfs) { 1336 total_lfs += numlfs; 1337 num_blkaddr[nr_blocks] = blkaddr; 1338 nr_blocks++; 1339 } 1340 } 1341 1342 if (global_slot >= total_lfs) 1343 return -ENODEV; 1344 1345 /* Based on the given global slot number retrieve the 1346 * correct block address out of all attached block 1347 * addresses and slot number in that block. 1348 */ 1349 total_lfs = 0; 1350 blkaddr = -ENODEV; 1351 for (i = 0; i < nr_blocks; i++) { 1352 numlfs = rvu_get_rsrc_mapcount(pfvf, num_blkaddr[i]); 1353 total_lfs += numlfs; 1354 if (global_slot < total_lfs) { 1355 blkaddr = num_blkaddr[i]; 1356 start_slot = total_lfs - numlfs; 1357 *slot_in_block = global_slot - start_slot; 1358 break; 1359 } 1360 } 1361 1362 return blkaddr; 1363 } 1364 1365 static void rvu_detach_block(struct rvu *rvu, int pcifunc, int blktype) 1366 { 1367 struct rvu_pfvf *pfvf = rvu_get_pfvf(rvu, pcifunc); 1368 struct rvu_hwinfo *hw = rvu->hw; 1369 struct rvu_block *block; 1370 int slot, lf, num_lfs; 1371 int blkaddr; 1372 1373 blkaddr = rvu_get_blkaddr(rvu, blktype, pcifunc); 1374 if (blkaddr < 0) 1375 return; 1376 1377 if (blktype == BLKTYPE_NIX) 1378 rvu_nix_reset_mac(pfvf, pcifunc); 1379 1380 block = &hw->block[blkaddr]; 1381 1382 num_lfs = rvu_get_rsrc_mapcount(pfvf, block->addr); 1383 if (!num_lfs) 1384 return; 1385 1386 for (slot = 0; slot < num_lfs; slot++) { 1387 lf = rvu_lookup_rsrc(rvu, block, pcifunc, slot); 1388 if (lf < 0) /* This should never happen */ 1389 continue; 1390 1391 /* Disable the LF */ 1392 rvu_write64(rvu, blkaddr, block->lfcfg_reg | 1393 (lf << block->lfshift), 0x00ULL); 1394 1395 /* Update SW maintained mapping info as well */ 1396 rvu_update_rsrc_map(rvu, pfvf, block, 1397 pcifunc, lf, false); 1398 1399 /* Free the resource */ 1400 rvu_free_rsrc(&block->lf, lf); 1401 1402 /* Clear MSIX vector offset for this LF */ 1403 rvu_clear_msix_offset(rvu, pfvf, block, lf); 1404 } 1405 } 1406 1407 static int rvu_detach_rsrcs(struct rvu *rvu, struct rsrc_detach *detach, 1408 u16 pcifunc) 1409 { 1410 struct rvu_hwinfo *hw = rvu->hw; 1411 bool detach_all = true; 1412 struct rvu_block *block; 1413 int blkid; 1414 1415 mutex_lock(&rvu->rsrc_lock); 1416 1417 /* Check for partial resource detach */ 1418 if (detach && detach->partial) 1419 detach_all = false; 1420 1421 /* Check for RVU block's LFs attached to this func, 1422 * if so, detach them. 1423 */ 1424 for (blkid = 0; blkid < BLK_COUNT; blkid++) { 1425 block = &hw->block[blkid]; 1426 if (!block->lf.bmap) 1427 continue; 1428 if (!detach_all && detach) { 1429 if (blkid == BLKADDR_NPA && !detach->npalf) 1430 continue; 1431 else if ((blkid == BLKADDR_NIX0) && !detach->nixlf) 1432 continue; 1433 else if ((blkid == BLKADDR_NIX1) && !detach->nixlf) 1434 continue; 1435 else if ((blkid == BLKADDR_SSO) && !detach->sso) 1436 continue; 1437 else if ((blkid == BLKADDR_SSOW) && !detach->ssow) 1438 continue; 1439 else if ((blkid == BLKADDR_TIM) && !detach->timlfs) 1440 continue; 1441 else if ((blkid == BLKADDR_CPT0) && !detach->cptlfs) 1442 continue; 1443 else if ((blkid == BLKADDR_CPT1) && !detach->cptlfs) 1444 continue; 1445 } 1446 rvu_detach_block(rvu, pcifunc, block->type); 1447 } 1448 1449 mutex_unlock(&rvu->rsrc_lock); 1450 return 0; 1451 } 1452 1453 int rvu_mbox_handler_detach_resources(struct rvu *rvu, 1454 struct rsrc_detach *detach, 1455 struct msg_rsp *rsp) 1456 { 1457 return rvu_detach_rsrcs(rvu, detach, detach->hdr.pcifunc); 1458 } 1459 1460 int rvu_get_nix_blkaddr(struct rvu *rvu, u16 pcifunc) 1461 { 1462 struct rvu_pfvf *pfvf = rvu_get_pfvf(rvu, pcifunc); 1463 int blkaddr = BLKADDR_NIX0, vf; 1464 struct rvu_pfvf *pf; 1465 1466 pf = rvu_get_pfvf(rvu, pcifunc & ~RVU_PFVF_FUNC_MASK); 1467 1468 /* All CGX mapped PFs are set with assigned NIX block during init */ 1469 if (is_pf_cgxmapped(rvu, rvu_get_pf(pcifunc))) { 1470 blkaddr = pf->nix_blkaddr; 1471 } else if (is_afvf(pcifunc)) { 1472 vf = pcifunc - 1; 1473 /* Assign NIX based on VF number. All even numbered VFs get 1474 * NIX0 and odd numbered gets NIX1 1475 */ 1476 blkaddr = (vf & 1) ? BLKADDR_NIX1 : BLKADDR_NIX0; 1477 /* NIX1 is not present on all silicons */ 1478 if (!is_block_implemented(rvu->hw, BLKADDR_NIX1)) 1479 blkaddr = BLKADDR_NIX0; 1480 } 1481 1482 /* if SDP1 then the blkaddr is NIX1 */ 1483 if (is_sdp_pfvf(pcifunc) && pf->sdp_info->node_id == 1) 1484 blkaddr = BLKADDR_NIX1; 1485 1486 switch (blkaddr) { 1487 case BLKADDR_NIX1: 1488 pfvf->nix_blkaddr = BLKADDR_NIX1; 1489 pfvf->nix_rx_intf = NIX_INTFX_RX(1); 1490 pfvf->nix_tx_intf = NIX_INTFX_TX(1); 1491 break; 1492 case BLKADDR_NIX0: 1493 default: 1494 pfvf->nix_blkaddr = BLKADDR_NIX0; 1495 pfvf->nix_rx_intf = NIX_INTFX_RX(0); 1496 pfvf->nix_tx_intf = NIX_INTFX_TX(0); 1497 break; 1498 } 1499 1500 return pfvf->nix_blkaddr; 1501 } 1502 1503 static int rvu_get_attach_blkaddr(struct rvu *rvu, int blktype, 1504 u16 pcifunc, struct rsrc_attach *attach) 1505 { 1506 int blkaddr; 1507 1508 switch (blktype) { 1509 case BLKTYPE_NIX: 1510 blkaddr = rvu_get_nix_blkaddr(rvu, pcifunc); 1511 break; 1512 case BLKTYPE_CPT: 1513 if (attach->hdr.ver < RVU_MULTI_BLK_VER) 1514 return rvu_get_blkaddr(rvu, blktype, 0); 1515 blkaddr = attach->cpt_blkaddr ? attach->cpt_blkaddr : 1516 BLKADDR_CPT0; 1517 if (blkaddr != BLKADDR_CPT0 && blkaddr != BLKADDR_CPT1) 1518 return -ENODEV; 1519 break; 1520 default: 1521 return rvu_get_blkaddr(rvu, blktype, 0); 1522 } 1523 1524 if (is_block_implemented(rvu->hw, blkaddr)) 1525 return blkaddr; 1526 1527 return -ENODEV; 1528 } 1529 1530 static void rvu_attach_block(struct rvu *rvu, int pcifunc, int blktype, 1531 int num_lfs, struct rsrc_attach *attach) 1532 { 1533 struct rvu_pfvf *pfvf = rvu_get_pfvf(rvu, pcifunc); 1534 struct rvu_hwinfo *hw = rvu->hw; 1535 struct rvu_block *block; 1536 int slot, lf; 1537 int blkaddr; 1538 u64 cfg; 1539 1540 if (!num_lfs) 1541 return; 1542 1543 blkaddr = rvu_get_attach_blkaddr(rvu, blktype, pcifunc, attach); 1544 if (blkaddr < 0) 1545 return; 1546 1547 block = &hw->block[blkaddr]; 1548 if (!block->lf.bmap) 1549 return; 1550 1551 for (slot = 0; slot < num_lfs; slot++) { 1552 /* Allocate the resource */ 1553 lf = rvu_alloc_rsrc(&block->lf); 1554 if (lf < 0) 1555 return; 1556 1557 cfg = (1ULL << 63) | (pcifunc << 8) | slot; 1558 rvu_write64(rvu, blkaddr, block->lfcfg_reg | 1559 (lf << block->lfshift), cfg); 1560 rvu_update_rsrc_map(rvu, pfvf, block, 1561 pcifunc, lf, true); 1562 1563 /* Set start MSIX vector for this LF within this PF/VF */ 1564 rvu_set_msix_offset(rvu, pfvf, block, lf); 1565 } 1566 } 1567 1568 static int rvu_check_rsrc_availability(struct rvu *rvu, 1569 struct rsrc_attach *req, u16 pcifunc) 1570 { 1571 struct rvu_pfvf *pfvf = rvu_get_pfvf(rvu, pcifunc); 1572 int free_lfs, mappedlfs, blkaddr; 1573 struct rvu_hwinfo *hw = rvu->hw; 1574 struct rvu_block *block; 1575 1576 /* Only one NPA LF can be attached */ 1577 if (req->npalf && !is_blktype_attached(pfvf, BLKTYPE_NPA)) { 1578 block = &hw->block[BLKADDR_NPA]; 1579 free_lfs = rvu_rsrc_free_count(&block->lf); 1580 if (!free_lfs) 1581 goto fail; 1582 } else if (req->npalf) { 1583 dev_err(&rvu->pdev->dev, 1584 "Func 0x%x: Invalid req, already has NPA\n", 1585 pcifunc); 1586 return -EINVAL; 1587 } 1588 1589 /* Only one NIX LF can be attached */ 1590 if (req->nixlf && !is_blktype_attached(pfvf, BLKTYPE_NIX)) { 1591 blkaddr = rvu_get_attach_blkaddr(rvu, BLKTYPE_NIX, 1592 pcifunc, req); 1593 if (blkaddr < 0) 1594 return blkaddr; 1595 block = &hw->block[blkaddr]; 1596 free_lfs = rvu_rsrc_free_count(&block->lf); 1597 if (!free_lfs) 1598 goto fail; 1599 } else if (req->nixlf) { 1600 dev_err(&rvu->pdev->dev, 1601 "Func 0x%x: Invalid req, already has NIX\n", 1602 pcifunc); 1603 return -EINVAL; 1604 } 1605 1606 if (req->sso) { 1607 block = &hw->block[BLKADDR_SSO]; 1608 /* Is request within limits ? */ 1609 if (req->sso > block->lf.max) { 1610 dev_err(&rvu->pdev->dev, 1611 "Func 0x%x: Invalid SSO req, %d > max %d\n", 1612 pcifunc, req->sso, block->lf.max); 1613 return -EINVAL; 1614 } 1615 mappedlfs = rvu_get_rsrc_mapcount(pfvf, block->addr); 1616 free_lfs = rvu_rsrc_free_count(&block->lf); 1617 /* Check if additional resources are available */ 1618 if (req->sso > mappedlfs && 1619 ((req->sso - mappedlfs) > free_lfs)) 1620 goto fail; 1621 } 1622 1623 if (req->ssow) { 1624 block = &hw->block[BLKADDR_SSOW]; 1625 if (req->ssow > block->lf.max) { 1626 dev_err(&rvu->pdev->dev, 1627 "Func 0x%x: Invalid SSOW req, %d > max %d\n", 1628 pcifunc, req->sso, block->lf.max); 1629 return -EINVAL; 1630 } 1631 mappedlfs = rvu_get_rsrc_mapcount(pfvf, block->addr); 1632 free_lfs = rvu_rsrc_free_count(&block->lf); 1633 if (req->ssow > mappedlfs && 1634 ((req->ssow - mappedlfs) > free_lfs)) 1635 goto fail; 1636 } 1637 1638 if (req->timlfs) { 1639 block = &hw->block[BLKADDR_TIM]; 1640 if (req->timlfs > block->lf.max) { 1641 dev_err(&rvu->pdev->dev, 1642 "Func 0x%x: Invalid TIMLF req, %d > max %d\n", 1643 pcifunc, req->timlfs, block->lf.max); 1644 return -EINVAL; 1645 } 1646 mappedlfs = rvu_get_rsrc_mapcount(pfvf, block->addr); 1647 free_lfs = rvu_rsrc_free_count(&block->lf); 1648 if (req->timlfs > mappedlfs && 1649 ((req->timlfs - mappedlfs) > free_lfs)) 1650 goto fail; 1651 } 1652 1653 if (req->cptlfs) { 1654 blkaddr = rvu_get_attach_blkaddr(rvu, BLKTYPE_CPT, 1655 pcifunc, req); 1656 if (blkaddr < 0) 1657 return blkaddr; 1658 block = &hw->block[blkaddr]; 1659 if (req->cptlfs > block->lf.max) { 1660 dev_err(&rvu->pdev->dev, 1661 "Func 0x%x: Invalid CPTLF req, %d > max %d\n", 1662 pcifunc, req->cptlfs, block->lf.max); 1663 return -EINVAL; 1664 } 1665 mappedlfs = rvu_get_rsrc_mapcount(pfvf, block->addr); 1666 free_lfs = rvu_rsrc_free_count(&block->lf); 1667 if (req->cptlfs > mappedlfs && 1668 ((req->cptlfs - mappedlfs) > free_lfs)) 1669 goto fail; 1670 } 1671 1672 return 0; 1673 1674 fail: 1675 dev_info(rvu->dev, "Request for %s failed\n", block->name); 1676 return -ENOSPC; 1677 } 1678 1679 static bool rvu_attach_from_same_block(struct rvu *rvu, int blktype, 1680 struct rsrc_attach *attach) 1681 { 1682 int blkaddr, num_lfs; 1683 1684 blkaddr = rvu_get_attach_blkaddr(rvu, blktype, 1685 attach->hdr.pcifunc, attach); 1686 if (blkaddr < 0) 1687 return false; 1688 1689 num_lfs = rvu_get_rsrc_mapcount(rvu_get_pfvf(rvu, attach->hdr.pcifunc), 1690 blkaddr); 1691 /* Requester already has LFs from given block ? */ 1692 return !!num_lfs; 1693 } 1694 1695 int rvu_mbox_handler_attach_resources(struct rvu *rvu, 1696 struct rsrc_attach *attach, 1697 struct msg_rsp *rsp) 1698 { 1699 u16 pcifunc = attach->hdr.pcifunc; 1700 int err; 1701 1702 /* If first request, detach all existing attached resources */ 1703 if (!attach->modify) 1704 rvu_detach_rsrcs(rvu, NULL, pcifunc); 1705 1706 mutex_lock(&rvu->rsrc_lock); 1707 1708 /* Check if the request can be accommodated */ 1709 err = rvu_check_rsrc_availability(rvu, attach, pcifunc); 1710 if (err) 1711 goto exit; 1712 1713 /* Now attach the requested resources */ 1714 if (attach->npalf) 1715 rvu_attach_block(rvu, pcifunc, BLKTYPE_NPA, 1, attach); 1716 1717 if (attach->nixlf) 1718 rvu_attach_block(rvu, pcifunc, BLKTYPE_NIX, 1, attach); 1719 1720 if (attach->sso) { 1721 /* RVU func doesn't know which exact LF or slot is attached 1722 * to it, it always sees as slot 0,1,2. So for a 'modify' 1723 * request, simply detach all existing attached LFs/slots 1724 * and attach a fresh. 1725 */ 1726 if (attach->modify) 1727 rvu_detach_block(rvu, pcifunc, BLKTYPE_SSO); 1728 rvu_attach_block(rvu, pcifunc, BLKTYPE_SSO, 1729 attach->sso, attach); 1730 } 1731 1732 if (attach->ssow) { 1733 if (attach->modify) 1734 rvu_detach_block(rvu, pcifunc, BLKTYPE_SSOW); 1735 rvu_attach_block(rvu, pcifunc, BLKTYPE_SSOW, 1736 attach->ssow, attach); 1737 } 1738 1739 if (attach->timlfs) { 1740 if (attach->modify) 1741 rvu_detach_block(rvu, pcifunc, BLKTYPE_TIM); 1742 rvu_attach_block(rvu, pcifunc, BLKTYPE_TIM, 1743 attach->timlfs, attach); 1744 } 1745 1746 if (attach->cptlfs) { 1747 if (attach->modify && 1748 rvu_attach_from_same_block(rvu, BLKTYPE_CPT, attach)) 1749 rvu_detach_block(rvu, pcifunc, BLKTYPE_CPT); 1750 rvu_attach_block(rvu, pcifunc, BLKTYPE_CPT, 1751 attach->cptlfs, attach); 1752 } 1753 1754 exit: 1755 mutex_unlock(&rvu->rsrc_lock); 1756 return err; 1757 } 1758 1759 static u16 rvu_get_msix_offset(struct rvu *rvu, struct rvu_pfvf *pfvf, 1760 int blkaddr, int lf) 1761 { 1762 u16 vec; 1763 1764 if (lf < 0) 1765 return MSIX_VECTOR_INVALID; 1766 1767 for (vec = 0; vec < pfvf->msix.max; vec++) { 1768 if (pfvf->msix_lfmap[vec] == MSIX_BLKLF(blkaddr, lf)) 1769 return vec; 1770 } 1771 return MSIX_VECTOR_INVALID; 1772 } 1773 1774 static void rvu_set_msix_offset(struct rvu *rvu, struct rvu_pfvf *pfvf, 1775 struct rvu_block *block, int lf) 1776 { 1777 u16 nvecs, vec, offset; 1778 u64 cfg; 1779 1780 cfg = rvu_read64(rvu, block->addr, block->msixcfg_reg | 1781 (lf << block->lfshift)); 1782 nvecs = (cfg >> 12) & 0xFF; 1783 1784 /* Check and alloc MSIX vectors, must be contiguous */ 1785 if (!rvu_rsrc_check_contig(&pfvf->msix, nvecs)) 1786 return; 1787 1788 offset = rvu_alloc_rsrc_contig(&pfvf->msix, nvecs); 1789 1790 /* Config MSIX offset in LF */ 1791 rvu_write64(rvu, block->addr, block->msixcfg_reg | 1792 (lf << block->lfshift), (cfg & ~0x7FFULL) | offset); 1793 1794 /* Update the bitmap as well */ 1795 for (vec = 0; vec < nvecs; vec++) 1796 pfvf->msix_lfmap[offset + vec] = MSIX_BLKLF(block->addr, lf); 1797 } 1798 1799 static void rvu_clear_msix_offset(struct rvu *rvu, struct rvu_pfvf *pfvf, 1800 struct rvu_block *block, int lf) 1801 { 1802 u16 nvecs, vec, offset; 1803 u64 cfg; 1804 1805 cfg = rvu_read64(rvu, block->addr, block->msixcfg_reg | 1806 (lf << block->lfshift)); 1807 nvecs = (cfg >> 12) & 0xFF; 1808 1809 /* Clear MSIX offset in LF */ 1810 rvu_write64(rvu, block->addr, block->msixcfg_reg | 1811 (lf << block->lfshift), cfg & ~0x7FFULL); 1812 1813 offset = rvu_get_msix_offset(rvu, pfvf, block->addr, lf); 1814 1815 /* Update the mapping */ 1816 for (vec = 0; vec < nvecs; vec++) 1817 pfvf->msix_lfmap[offset + vec] = 0; 1818 1819 /* Free the same in MSIX bitmap */ 1820 rvu_free_rsrc_contig(&pfvf->msix, nvecs, offset); 1821 } 1822 1823 int rvu_mbox_handler_msix_offset(struct rvu *rvu, struct msg_req *req, 1824 struct msix_offset_rsp *rsp) 1825 { 1826 struct rvu_hwinfo *hw = rvu->hw; 1827 u16 pcifunc = req->hdr.pcifunc; 1828 struct rvu_pfvf *pfvf; 1829 int lf, slot, blkaddr; 1830 1831 pfvf = rvu_get_pfvf(rvu, pcifunc); 1832 if (!pfvf->msix.bmap) 1833 return 0; 1834 1835 /* Set MSIX offsets for each block's LFs attached to this PF/VF */ 1836 lf = rvu_get_lf(rvu, &hw->block[BLKADDR_NPA], pcifunc, 0); 1837 rsp->npa_msixoff = rvu_get_msix_offset(rvu, pfvf, BLKADDR_NPA, lf); 1838 1839 /* Get BLKADDR from which LFs are attached to pcifunc */ 1840 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NIX, pcifunc); 1841 if (blkaddr < 0) { 1842 rsp->nix_msixoff = MSIX_VECTOR_INVALID; 1843 } else { 1844 lf = rvu_get_lf(rvu, &hw->block[blkaddr], pcifunc, 0); 1845 rsp->nix_msixoff = rvu_get_msix_offset(rvu, pfvf, blkaddr, lf); 1846 } 1847 1848 rsp->sso = pfvf->sso; 1849 for (slot = 0; slot < rsp->sso; slot++) { 1850 lf = rvu_get_lf(rvu, &hw->block[BLKADDR_SSO], pcifunc, slot); 1851 rsp->sso_msixoff[slot] = 1852 rvu_get_msix_offset(rvu, pfvf, BLKADDR_SSO, lf); 1853 } 1854 1855 rsp->ssow = pfvf->ssow; 1856 for (slot = 0; slot < rsp->ssow; slot++) { 1857 lf = rvu_get_lf(rvu, &hw->block[BLKADDR_SSOW], pcifunc, slot); 1858 rsp->ssow_msixoff[slot] = 1859 rvu_get_msix_offset(rvu, pfvf, BLKADDR_SSOW, lf); 1860 } 1861 1862 rsp->timlfs = pfvf->timlfs; 1863 for (slot = 0; slot < rsp->timlfs; slot++) { 1864 lf = rvu_get_lf(rvu, &hw->block[BLKADDR_TIM], pcifunc, slot); 1865 rsp->timlf_msixoff[slot] = 1866 rvu_get_msix_offset(rvu, pfvf, BLKADDR_TIM, lf); 1867 } 1868 1869 rsp->cptlfs = pfvf->cptlfs; 1870 for (slot = 0; slot < rsp->cptlfs; slot++) { 1871 lf = rvu_get_lf(rvu, &hw->block[BLKADDR_CPT0], pcifunc, slot); 1872 rsp->cptlf_msixoff[slot] = 1873 rvu_get_msix_offset(rvu, pfvf, BLKADDR_CPT0, lf); 1874 } 1875 1876 rsp->cpt1_lfs = pfvf->cpt1_lfs; 1877 for (slot = 0; slot < rsp->cpt1_lfs; slot++) { 1878 lf = rvu_get_lf(rvu, &hw->block[BLKADDR_CPT1], pcifunc, slot); 1879 rsp->cpt1_lf_msixoff[slot] = 1880 rvu_get_msix_offset(rvu, pfvf, BLKADDR_CPT1, lf); 1881 } 1882 1883 return 0; 1884 } 1885 1886 int rvu_mbox_handler_free_rsrc_cnt(struct rvu *rvu, struct msg_req *req, 1887 struct free_rsrcs_rsp *rsp) 1888 { 1889 struct rvu_hwinfo *hw = rvu->hw; 1890 struct rvu_block *block; 1891 struct nix_txsch *txsch; 1892 struct nix_hw *nix_hw; 1893 1894 mutex_lock(&rvu->rsrc_lock); 1895 1896 block = &hw->block[BLKADDR_NPA]; 1897 rsp->npa = rvu_rsrc_free_count(&block->lf); 1898 1899 block = &hw->block[BLKADDR_NIX0]; 1900 rsp->nix = rvu_rsrc_free_count(&block->lf); 1901 1902 block = &hw->block[BLKADDR_NIX1]; 1903 rsp->nix1 = rvu_rsrc_free_count(&block->lf); 1904 1905 block = &hw->block[BLKADDR_SSO]; 1906 rsp->sso = rvu_rsrc_free_count(&block->lf); 1907 1908 block = &hw->block[BLKADDR_SSOW]; 1909 rsp->ssow = rvu_rsrc_free_count(&block->lf); 1910 1911 block = &hw->block[BLKADDR_TIM]; 1912 rsp->tim = rvu_rsrc_free_count(&block->lf); 1913 1914 block = &hw->block[BLKADDR_CPT0]; 1915 rsp->cpt = rvu_rsrc_free_count(&block->lf); 1916 1917 block = &hw->block[BLKADDR_CPT1]; 1918 rsp->cpt1 = rvu_rsrc_free_count(&block->lf); 1919 1920 if (rvu->hw->cap.nix_fixed_txschq_mapping) { 1921 rsp->schq[NIX_TXSCH_LVL_SMQ] = 1; 1922 rsp->schq[NIX_TXSCH_LVL_TL4] = 1; 1923 rsp->schq[NIX_TXSCH_LVL_TL3] = 1; 1924 rsp->schq[NIX_TXSCH_LVL_TL2] = 1; 1925 /* NIX1 */ 1926 if (!is_block_implemented(rvu->hw, BLKADDR_NIX1)) 1927 goto out; 1928 rsp->schq_nix1[NIX_TXSCH_LVL_SMQ] = 1; 1929 rsp->schq_nix1[NIX_TXSCH_LVL_TL4] = 1; 1930 rsp->schq_nix1[NIX_TXSCH_LVL_TL3] = 1; 1931 rsp->schq_nix1[NIX_TXSCH_LVL_TL2] = 1; 1932 } else { 1933 nix_hw = get_nix_hw(hw, BLKADDR_NIX0); 1934 txsch = &nix_hw->txsch[NIX_TXSCH_LVL_SMQ]; 1935 rsp->schq[NIX_TXSCH_LVL_SMQ] = 1936 rvu_rsrc_free_count(&txsch->schq); 1937 1938 txsch = &nix_hw->txsch[NIX_TXSCH_LVL_TL4]; 1939 rsp->schq[NIX_TXSCH_LVL_TL4] = 1940 rvu_rsrc_free_count(&txsch->schq); 1941 1942 txsch = &nix_hw->txsch[NIX_TXSCH_LVL_TL3]; 1943 rsp->schq[NIX_TXSCH_LVL_TL3] = 1944 rvu_rsrc_free_count(&txsch->schq); 1945 1946 txsch = &nix_hw->txsch[NIX_TXSCH_LVL_TL2]; 1947 rsp->schq[NIX_TXSCH_LVL_TL2] = 1948 rvu_rsrc_free_count(&txsch->schq); 1949 1950 if (!is_block_implemented(rvu->hw, BLKADDR_NIX1)) 1951 goto out; 1952 1953 nix_hw = get_nix_hw(hw, BLKADDR_NIX1); 1954 txsch = &nix_hw->txsch[NIX_TXSCH_LVL_SMQ]; 1955 rsp->schq_nix1[NIX_TXSCH_LVL_SMQ] = 1956 rvu_rsrc_free_count(&txsch->schq); 1957 1958 txsch = &nix_hw->txsch[NIX_TXSCH_LVL_TL4]; 1959 rsp->schq_nix1[NIX_TXSCH_LVL_TL4] = 1960 rvu_rsrc_free_count(&txsch->schq); 1961 1962 txsch = &nix_hw->txsch[NIX_TXSCH_LVL_TL3]; 1963 rsp->schq_nix1[NIX_TXSCH_LVL_TL3] = 1964 rvu_rsrc_free_count(&txsch->schq); 1965 1966 txsch = &nix_hw->txsch[NIX_TXSCH_LVL_TL2]; 1967 rsp->schq_nix1[NIX_TXSCH_LVL_TL2] = 1968 rvu_rsrc_free_count(&txsch->schq); 1969 } 1970 1971 rsp->schq_nix1[NIX_TXSCH_LVL_TL1] = 1; 1972 out: 1973 rsp->schq[NIX_TXSCH_LVL_TL1] = 1; 1974 mutex_unlock(&rvu->rsrc_lock); 1975 1976 return 0; 1977 } 1978 1979 int rvu_mbox_handler_vf_flr(struct rvu *rvu, struct msg_req *req, 1980 struct msg_rsp *rsp) 1981 { 1982 u16 pcifunc = req->hdr.pcifunc; 1983 u16 vf, numvfs; 1984 u64 cfg; 1985 1986 vf = pcifunc & RVU_PFVF_FUNC_MASK; 1987 cfg = rvu_read64(rvu, BLKADDR_RVUM, 1988 RVU_PRIV_PFX_CFG(rvu_get_pf(pcifunc))); 1989 numvfs = (cfg >> 12) & 0xFF; 1990 1991 if (vf && vf <= numvfs) 1992 __rvu_flr_handler(rvu, pcifunc); 1993 else 1994 return RVU_INVALID_VF_ID; 1995 1996 return 0; 1997 } 1998 1999 int rvu_mbox_handler_get_hw_cap(struct rvu *rvu, struct msg_req *req, 2000 struct get_hw_cap_rsp *rsp) 2001 { 2002 struct rvu_hwinfo *hw = rvu->hw; 2003 2004 rsp->nix_fixed_txschq_mapping = hw->cap.nix_fixed_txschq_mapping; 2005 rsp->nix_shaping = hw->cap.nix_shaping; 2006 rsp->npc_hash_extract = hw->cap.npc_hash_extract; 2007 2008 return 0; 2009 } 2010 2011 int rvu_mbox_handler_set_vf_perm(struct rvu *rvu, struct set_vf_perm *req, 2012 struct msg_rsp *rsp) 2013 { 2014 struct rvu_hwinfo *hw = rvu->hw; 2015 u16 pcifunc = req->hdr.pcifunc; 2016 struct rvu_pfvf *pfvf; 2017 int blkaddr, nixlf; 2018 u16 target; 2019 2020 /* Only PF can add VF permissions */ 2021 if ((pcifunc & RVU_PFVF_FUNC_MASK) || is_afvf(pcifunc)) 2022 return -EOPNOTSUPP; 2023 2024 target = (pcifunc & ~RVU_PFVF_FUNC_MASK) | (req->vf + 1); 2025 pfvf = rvu_get_pfvf(rvu, target); 2026 2027 if (req->flags & RESET_VF_PERM) { 2028 pfvf->flags &= RVU_CLEAR_VF_PERM; 2029 } else if (test_bit(PF_SET_VF_TRUSTED, &pfvf->flags) ^ 2030 (req->flags & VF_TRUSTED)) { 2031 change_bit(PF_SET_VF_TRUSTED, &pfvf->flags); 2032 /* disable multicast and promisc entries */ 2033 if (!test_bit(PF_SET_VF_TRUSTED, &pfvf->flags)) { 2034 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NIX, target); 2035 if (blkaddr < 0) 2036 return 0; 2037 nixlf = rvu_get_lf(rvu, &hw->block[blkaddr], 2038 target, 0); 2039 if (nixlf < 0) 2040 return 0; 2041 npc_enadis_default_mce_entry(rvu, target, nixlf, 2042 NIXLF_ALLMULTI_ENTRY, 2043 false); 2044 npc_enadis_default_mce_entry(rvu, target, nixlf, 2045 NIXLF_PROMISC_ENTRY, 2046 false); 2047 } 2048 } 2049 2050 return 0; 2051 } 2052 2053 static int rvu_process_mbox_msg(struct otx2_mbox *mbox, int devid, 2054 struct mbox_msghdr *req) 2055 { 2056 struct rvu *rvu = pci_get_drvdata(mbox->pdev); 2057 2058 /* Check if valid, if not reply with a invalid msg */ 2059 if (req->sig != OTX2_MBOX_REQ_SIG) 2060 goto bad_message; 2061 2062 switch (req->id) { 2063 #define M(_name, _id, _fn_name, _req_type, _rsp_type) \ 2064 case _id: { \ 2065 struct _rsp_type *rsp; \ 2066 int err; \ 2067 \ 2068 rsp = (struct _rsp_type *)otx2_mbox_alloc_msg( \ 2069 mbox, devid, \ 2070 sizeof(struct _rsp_type)); \ 2071 /* some handlers should complete even if reply */ \ 2072 /* could not be allocated */ \ 2073 if (!rsp && \ 2074 _id != MBOX_MSG_DETACH_RESOURCES && \ 2075 _id != MBOX_MSG_NIX_TXSCH_FREE && \ 2076 _id != MBOX_MSG_VF_FLR) \ 2077 return -ENOMEM; \ 2078 if (rsp) { \ 2079 rsp->hdr.id = _id; \ 2080 rsp->hdr.sig = OTX2_MBOX_RSP_SIG; \ 2081 rsp->hdr.pcifunc = req->pcifunc; \ 2082 rsp->hdr.rc = 0; \ 2083 } \ 2084 \ 2085 err = rvu_mbox_handler_ ## _fn_name(rvu, \ 2086 (struct _req_type *)req, \ 2087 rsp); \ 2088 if (rsp && err) \ 2089 rsp->hdr.rc = err; \ 2090 \ 2091 trace_otx2_msg_process(mbox->pdev, _id, err); \ 2092 return rsp ? err : -ENOMEM; \ 2093 } 2094 MBOX_MESSAGES 2095 #undef M 2096 2097 bad_message: 2098 default: 2099 otx2_reply_invalid_msg(mbox, devid, req->pcifunc, req->id); 2100 return -ENODEV; 2101 } 2102 } 2103 2104 static void __rvu_mbox_handler(struct rvu_work *mwork, int type) 2105 { 2106 struct rvu *rvu = mwork->rvu; 2107 int offset, err, id, devid; 2108 struct otx2_mbox_dev *mdev; 2109 struct mbox_hdr *req_hdr; 2110 struct mbox_msghdr *msg; 2111 struct mbox_wq_info *mw; 2112 struct otx2_mbox *mbox; 2113 2114 switch (type) { 2115 case TYPE_AFPF: 2116 mw = &rvu->afpf_wq_info; 2117 break; 2118 case TYPE_AFVF: 2119 mw = &rvu->afvf_wq_info; 2120 break; 2121 default: 2122 return; 2123 } 2124 2125 devid = mwork - mw->mbox_wrk; 2126 mbox = &mw->mbox; 2127 mdev = &mbox->dev[devid]; 2128 2129 /* Process received mbox messages */ 2130 req_hdr = mdev->mbase + mbox->rx_start; 2131 if (mw->mbox_wrk[devid].num_msgs == 0) 2132 return; 2133 2134 offset = mbox->rx_start + ALIGN(sizeof(*req_hdr), MBOX_MSG_ALIGN); 2135 2136 for (id = 0; id < mw->mbox_wrk[devid].num_msgs; id++) { 2137 msg = mdev->mbase + offset; 2138 2139 /* Set which PF/VF sent this message based on mbox IRQ */ 2140 switch (type) { 2141 case TYPE_AFPF: 2142 msg->pcifunc &= 2143 ~(RVU_PFVF_PF_MASK << RVU_PFVF_PF_SHIFT); 2144 msg->pcifunc |= (devid << RVU_PFVF_PF_SHIFT); 2145 break; 2146 case TYPE_AFVF: 2147 msg->pcifunc &= 2148 ~(RVU_PFVF_FUNC_MASK << RVU_PFVF_FUNC_SHIFT); 2149 msg->pcifunc |= (devid << RVU_PFVF_FUNC_SHIFT) + 1; 2150 break; 2151 } 2152 2153 err = rvu_process_mbox_msg(mbox, devid, msg); 2154 if (!err) { 2155 offset = mbox->rx_start + msg->next_msgoff; 2156 continue; 2157 } 2158 2159 if (msg->pcifunc & RVU_PFVF_FUNC_MASK) 2160 dev_warn(rvu->dev, "Error %d when processing message %s (0x%x) from PF%d:VF%d\n", 2161 err, otx2_mbox_id2name(msg->id), 2162 msg->id, rvu_get_pf(msg->pcifunc), 2163 (msg->pcifunc & RVU_PFVF_FUNC_MASK) - 1); 2164 else 2165 dev_warn(rvu->dev, "Error %d when processing message %s (0x%x) from PF%d\n", 2166 err, otx2_mbox_id2name(msg->id), 2167 msg->id, devid); 2168 } 2169 mw->mbox_wrk[devid].num_msgs = 0; 2170 2171 /* Send mbox responses to VF/PF */ 2172 otx2_mbox_msg_send(mbox, devid); 2173 } 2174 2175 static inline void rvu_afpf_mbox_handler(struct work_struct *work) 2176 { 2177 struct rvu_work *mwork = container_of(work, struct rvu_work, work); 2178 2179 __rvu_mbox_handler(mwork, TYPE_AFPF); 2180 } 2181 2182 static inline void rvu_afvf_mbox_handler(struct work_struct *work) 2183 { 2184 struct rvu_work *mwork = container_of(work, struct rvu_work, work); 2185 2186 __rvu_mbox_handler(mwork, TYPE_AFVF); 2187 } 2188 2189 static void __rvu_mbox_up_handler(struct rvu_work *mwork, int type) 2190 { 2191 struct rvu *rvu = mwork->rvu; 2192 struct otx2_mbox_dev *mdev; 2193 struct mbox_hdr *rsp_hdr; 2194 struct mbox_msghdr *msg; 2195 struct mbox_wq_info *mw; 2196 struct otx2_mbox *mbox; 2197 int offset, id, devid; 2198 2199 switch (type) { 2200 case TYPE_AFPF: 2201 mw = &rvu->afpf_wq_info; 2202 break; 2203 case TYPE_AFVF: 2204 mw = &rvu->afvf_wq_info; 2205 break; 2206 default: 2207 return; 2208 } 2209 2210 devid = mwork - mw->mbox_wrk_up; 2211 mbox = &mw->mbox_up; 2212 mdev = &mbox->dev[devid]; 2213 2214 rsp_hdr = mdev->mbase + mbox->rx_start; 2215 if (mw->mbox_wrk_up[devid].up_num_msgs == 0) { 2216 dev_warn(rvu->dev, "mbox up handler: num_msgs = 0\n"); 2217 return; 2218 } 2219 2220 offset = mbox->rx_start + ALIGN(sizeof(*rsp_hdr), MBOX_MSG_ALIGN); 2221 2222 for (id = 0; id < mw->mbox_wrk_up[devid].up_num_msgs; id++) { 2223 msg = mdev->mbase + offset; 2224 2225 if (msg->id >= MBOX_MSG_MAX) { 2226 dev_err(rvu->dev, 2227 "Mbox msg with unknown ID 0x%x\n", msg->id); 2228 goto end; 2229 } 2230 2231 if (msg->sig != OTX2_MBOX_RSP_SIG) { 2232 dev_err(rvu->dev, 2233 "Mbox msg with wrong signature %x, ID 0x%x\n", 2234 msg->sig, msg->id); 2235 goto end; 2236 } 2237 2238 switch (msg->id) { 2239 case MBOX_MSG_CGX_LINK_EVENT: 2240 break; 2241 default: 2242 if (msg->rc) 2243 dev_err(rvu->dev, 2244 "Mbox msg response has err %d, ID 0x%x\n", 2245 msg->rc, msg->id); 2246 break; 2247 } 2248 end: 2249 offset = mbox->rx_start + msg->next_msgoff; 2250 mdev->msgs_acked++; 2251 } 2252 mw->mbox_wrk_up[devid].up_num_msgs = 0; 2253 2254 otx2_mbox_reset(mbox, devid); 2255 } 2256 2257 static inline void rvu_afpf_mbox_up_handler(struct work_struct *work) 2258 { 2259 struct rvu_work *mwork = container_of(work, struct rvu_work, work); 2260 2261 __rvu_mbox_up_handler(mwork, TYPE_AFPF); 2262 } 2263 2264 static inline void rvu_afvf_mbox_up_handler(struct work_struct *work) 2265 { 2266 struct rvu_work *mwork = container_of(work, struct rvu_work, work); 2267 2268 __rvu_mbox_up_handler(mwork, TYPE_AFVF); 2269 } 2270 2271 static int rvu_get_mbox_regions(struct rvu *rvu, void **mbox_addr, 2272 int num, int type) 2273 { 2274 struct rvu_hwinfo *hw = rvu->hw; 2275 int region; 2276 u64 bar4; 2277 2278 /* For cn10k platform VF mailbox regions of a PF follows after the 2279 * PF <-> AF mailbox region. Whereas for Octeontx2 it is read from 2280 * RVU_PF_VF_BAR4_ADDR register. 2281 */ 2282 if (type == TYPE_AFVF) { 2283 for (region = 0; region < num; region++) { 2284 if (hw->cap.per_pf_mbox_regs) { 2285 bar4 = rvu_read64(rvu, BLKADDR_RVUM, 2286 RVU_AF_PFX_BAR4_ADDR(0)) + 2287 MBOX_SIZE; 2288 bar4 += region * MBOX_SIZE; 2289 } else { 2290 bar4 = rvupf_read64(rvu, RVU_PF_VF_BAR4_ADDR); 2291 bar4 += region * MBOX_SIZE; 2292 } 2293 mbox_addr[region] = (void *)ioremap_wc(bar4, MBOX_SIZE); 2294 if (!mbox_addr[region]) 2295 goto error; 2296 } 2297 return 0; 2298 } 2299 2300 /* For cn10k platform AF <-> PF mailbox region of a PF is read from per 2301 * PF registers. Whereas for Octeontx2 it is read from 2302 * RVU_AF_PF_BAR4_ADDR register. 2303 */ 2304 for (region = 0; region < num; region++) { 2305 if (hw->cap.per_pf_mbox_regs) { 2306 bar4 = rvu_read64(rvu, BLKADDR_RVUM, 2307 RVU_AF_PFX_BAR4_ADDR(region)); 2308 } else { 2309 bar4 = rvu_read64(rvu, BLKADDR_RVUM, 2310 RVU_AF_PF_BAR4_ADDR); 2311 bar4 += region * MBOX_SIZE; 2312 } 2313 mbox_addr[region] = (void *)ioremap_wc(bar4, MBOX_SIZE); 2314 if (!mbox_addr[region]) 2315 goto error; 2316 } 2317 return 0; 2318 2319 error: 2320 while (region--) 2321 iounmap((void __iomem *)mbox_addr[region]); 2322 return -ENOMEM; 2323 } 2324 2325 static int rvu_mbox_init(struct rvu *rvu, struct mbox_wq_info *mw, 2326 int type, int num, 2327 void (mbox_handler)(struct work_struct *), 2328 void (mbox_up_handler)(struct work_struct *)) 2329 { 2330 int err = -EINVAL, i, dir, dir_up; 2331 void __iomem *reg_base; 2332 struct rvu_work *mwork; 2333 void **mbox_regions; 2334 const char *name; 2335 2336 mbox_regions = kcalloc(num, sizeof(void *), GFP_KERNEL); 2337 if (!mbox_regions) 2338 return -ENOMEM; 2339 2340 switch (type) { 2341 case TYPE_AFPF: 2342 name = "rvu_afpf_mailbox"; 2343 dir = MBOX_DIR_AFPF; 2344 dir_up = MBOX_DIR_AFPF_UP; 2345 reg_base = rvu->afreg_base; 2346 err = rvu_get_mbox_regions(rvu, mbox_regions, num, TYPE_AFPF); 2347 if (err) 2348 goto free_regions; 2349 break; 2350 case TYPE_AFVF: 2351 name = "rvu_afvf_mailbox"; 2352 dir = MBOX_DIR_PFVF; 2353 dir_up = MBOX_DIR_PFVF_UP; 2354 reg_base = rvu->pfreg_base; 2355 err = rvu_get_mbox_regions(rvu, mbox_regions, num, TYPE_AFVF); 2356 if (err) 2357 goto free_regions; 2358 break; 2359 default: 2360 goto free_regions; 2361 } 2362 2363 mw->mbox_wq = alloc_workqueue(name, 2364 WQ_UNBOUND | WQ_HIGHPRI | WQ_MEM_RECLAIM, 2365 num); 2366 if (!mw->mbox_wq) { 2367 err = -ENOMEM; 2368 goto unmap_regions; 2369 } 2370 2371 mw->mbox_wrk = devm_kcalloc(rvu->dev, num, 2372 sizeof(struct rvu_work), GFP_KERNEL); 2373 if (!mw->mbox_wrk) { 2374 err = -ENOMEM; 2375 goto exit; 2376 } 2377 2378 mw->mbox_wrk_up = devm_kcalloc(rvu->dev, num, 2379 sizeof(struct rvu_work), GFP_KERNEL); 2380 if (!mw->mbox_wrk_up) { 2381 err = -ENOMEM; 2382 goto exit; 2383 } 2384 2385 err = otx2_mbox_regions_init(&mw->mbox, mbox_regions, rvu->pdev, 2386 reg_base, dir, num); 2387 if (err) 2388 goto exit; 2389 2390 err = otx2_mbox_regions_init(&mw->mbox_up, mbox_regions, rvu->pdev, 2391 reg_base, dir_up, num); 2392 if (err) 2393 goto exit; 2394 2395 for (i = 0; i < num; i++) { 2396 mwork = &mw->mbox_wrk[i]; 2397 mwork->rvu = rvu; 2398 INIT_WORK(&mwork->work, mbox_handler); 2399 2400 mwork = &mw->mbox_wrk_up[i]; 2401 mwork->rvu = rvu; 2402 INIT_WORK(&mwork->work, mbox_up_handler); 2403 } 2404 kfree(mbox_regions); 2405 return 0; 2406 2407 exit: 2408 destroy_workqueue(mw->mbox_wq); 2409 unmap_regions: 2410 while (num--) 2411 iounmap((void __iomem *)mbox_regions[num]); 2412 free_regions: 2413 kfree(mbox_regions); 2414 return err; 2415 } 2416 2417 static void rvu_mbox_destroy(struct mbox_wq_info *mw) 2418 { 2419 struct otx2_mbox *mbox = &mw->mbox; 2420 struct otx2_mbox_dev *mdev; 2421 int devid; 2422 2423 if (mw->mbox_wq) { 2424 destroy_workqueue(mw->mbox_wq); 2425 mw->mbox_wq = NULL; 2426 } 2427 2428 for (devid = 0; devid < mbox->ndevs; devid++) { 2429 mdev = &mbox->dev[devid]; 2430 if (mdev->hwbase) 2431 iounmap((void __iomem *)mdev->hwbase); 2432 } 2433 2434 otx2_mbox_destroy(&mw->mbox); 2435 otx2_mbox_destroy(&mw->mbox_up); 2436 } 2437 2438 static void rvu_queue_work(struct mbox_wq_info *mw, int first, 2439 int mdevs, u64 intr) 2440 { 2441 struct otx2_mbox_dev *mdev; 2442 struct otx2_mbox *mbox; 2443 struct mbox_hdr *hdr; 2444 int i; 2445 2446 for (i = first; i < mdevs; i++) { 2447 /* start from 0 */ 2448 if (!(intr & BIT_ULL(i - first))) 2449 continue; 2450 2451 mbox = &mw->mbox; 2452 mdev = &mbox->dev[i]; 2453 hdr = mdev->mbase + mbox->rx_start; 2454 2455 /*The hdr->num_msgs is set to zero immediately in the interrupt 2456 * handler to ensure that it holds a correct value next time 2457 * when the interrupt handler is called. 2458 * pf->mbox.num_msgs holds the data for use in pfaf_mbox_handler 2459 * pf>mbox.up_num_msgs holds the data for use in 2460 * pfaf_mbox_up_handler. 2461 */ 2462 2463 if (hdr->num_msgs) { 2464 mw->mbox_wrk[i].num_msgs = hdr->num_msgs; 2465 hdr->num_msgs = 0; 2466 queue_work(mw->mbox_wq, &mw->mbox_wrk[i].work); 2467 } 2468 mbox = &mw->mbox_up; 2469 mdev = &mbox->dev[i]; 2470 hdr = mdev->mbase + mbox->rx_start; 2471 if (hdr->num_msgs) { 2472 mw->mbox_wrk_up[i].up_num_msgs = hdr->num_msgs; 2473 hdr->num_msgs = 0; 2474 queue_work(mw->mbox_wq, &mw->mbox_wrk_up[i].work); 2475 } 2476 } 2477 } 2478 2479 static irqreturn_t rvu_mbox_intr_handler(int irq, void *rvu_irq) 2480 { 2481 struct rvu *rvu = (struct rvu *)rvu_irq; 2482 int vfs = rvu->vfs; 2483 u64 intr; 2484 2485 intr = rvu_read64(rvu, BLKADDR_RVUM, RVU_AF_PFAF_MBOX_INT); 2486 /* Clear interrupts */ 2487 rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_PFAF_MBOX_INT, intr); 2488 if (intr) 2489 trace_otx2_msg_interrupt(rvu->pdev, "PF(s) to AF", intr); 2490 2491 /* Sync with mbox memory region */ 2492 rmb(); 2493 2494 rvu_queue_work(&rvu->afpf_wq_info, 0, rvu->hw->total_pfs, intr); 2495 2496 /* Handle VF interrupts */ 2497 if (vfs > 64) { 2498 intr = rvupf_read64(rvu, RVU_PF_VFPF_MBOX_INTX(1)); 2499 rvupf_write64(rvu, RVU_PF_VFPF_MBOX_INTX(1), intr); 2500 2501 rvu_queue_work(&rvu->afvf_wq_info, 64, vfs, intr); 2502 vfs -= 64; 2503 } 2504 2505 intr = rvupf_read64(rvu, RVU_PF_VFPF_MBOX_INTX(0)); 2506 rvupf_write64(rvu, RVU_PF_VFPF_MBOX_INTX(0), intr); 2507 if (intr) 2508 trace_otx2_msg_interrupt(rvu->pdev, "VF(s) to AF", intr); 2509 2510 rvu_queue_work(&rvu->afvf_wq_info, 0, vfs, intr); 2511 2512 return IRQ_HANDLED; 2513 } 2514 2515 static void rvu_enable_mbox_intr(struct rvu *rvu) 2516 { 2517 struct rvu_hwinfo *hw = rvu->hw; 2518 2519 /* Clear spurious irqs, if any */ 2520 rvu_write64(rvu, BLKADDR_RVUM, 2521 RVU_AF_PFAF_MBOX_INT, INTR_MASK(hw->total_pfs)); 2522 2523 /* Enable mailbox interrupt for all PFs except PF0 i.e AF itself */ 2524 rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_PFAF_MBOX_INT_ENA_W1S, 2525 INTR_MASK(hw->total_pfs) & ~1ULL); 2526 } 2527 2528 static void rvu_blklf_teardown(struct rvu *rvu, u16 pcifunc, u8 blkaddr) 2529 { 2530 struct rvu_block *block; 2531 int slot, lf, num_lfs; 2532 int err; 2533 2534 block = &rvu->hw->block[blkaddr]; 2535 num_lfs = rvu_get_rsrc_mapcount(rvu_get_pfvf(rvu, pcifunc), 2536 block->addr); 2537 if (!num_lfs) 2538 return; 2539 for (slot = 0; slot < num_lfs; slot++) { 2540 lf = rvu_get_lf(rvu, block, pcifunc, slot); 2541 if (lf < 0) 2542 continue; 2543 2544 /* Cleanup LF and reset it */ 2545 if (block->addr == BLKADDR_NIX0 || block->addr == BLKADDR_NIX1) 2546 rvu_nix_lf_teardown(rvu, pcifunc, block->addr, lf); 2547 else if (block->addr == BLKADDR_NPA) 2548 rvu_npa_lf_teardown(rvu, pcifunc, lf); 2549 else if ((block->addr == BLKADDR_CPT0) || 2550 (block->addr == BLKADDR_CPT1)) 2551 rvu_cpt_lf_teardown(rvu, pcifunc, block->addr, lf, 2552 slot); 2553 2554 err = rvu_lf_reset(rvu, block, lf); 2555 if (err) { 2556 dev_err(rvu->dev, "Failed to reset blkaddr %d LF%d\n", 2557 block->addr, lf); 2558 } 2559 } 2560 } 2561 2562 static void __rvu_flr_handler(struct rvu *rvu, u16 pcifunc) 2563 { 2564 if (rvu_npc_exact_has_match_table(rvu)) 2565 rvu_npc_exact_reset(rvu, pcifunc); 2566 2567 mutex_lock(&rvu->flr_lock); 2568 /* Reset order should reflect inter-block dependencies: 2569 * 1. Reset any packet/work sources (NIX, CPT, TIM) 2570 * 2. Flush and reset SSO/SSOW 2571 * 3. Cleanup pools (NPA) 2572 */ 2573 rvu_blklf_teardown(rvu, pcifunc, BLKADDR_NIX0); 2574 rvu_blklf_teardown(rvu, pcifunc, BLKADDR_NIX1); 2575 rvu_blklf_teardown(rvu, pcifunc, BLKADDR_CPT0); 2576 rvu_blklf_teardown(rvu, pcifunc, BLKADDR_CPT1); 2577 rvu_blklf_teardown(rvu, pcifunc, BLKADDR_TIM); 2578 rvu_blklf_teardown(rvu, pcifunc, BLKADDR_SSOW); 2579 rvu_blklf_teardown(rvu, pcifunc, BLKADDR_SSO); 2580 rvu_blklf_teardown(rvu, pcifunc, BLKADDR_NPA); 2581 rvu_reset_lmt_map_tbl(rvu, pcifunc); 2582 rvu_detach_rsrcs(rvu, NULL, pcifunc); 2583 /* In scenarios where PF/VF drivers detach NIXLF without freeing MCAM 2584 * entries, check and free the MCAM entries explicitly to avoid leak. 2585 * Since LF is detached use LF number as -1. 2586 */ 2587 rvu_npc_free_mcam_entries(rvu, pcifunc, -1); 2588 2589 mutex_unlock(&rvu->flr_lock); 2590 } 2591 2592 static void rvu_afvf_flr_handler(struct rvu *rvu, int vf) 2593 { 2594 int reg = 0; 2595 2596 /* pcifunc = 0(PF0) | (vf + 1) */ 2597 __rvu_flr_handler(rvu, vf + 1); 2598 2599 if (vf >= 64) { 2600 reg = 1; 2601 vf = vf - 64; 2602 } 2603 2604 /* Signal FLR finish and enable IRQ */ 2605 rvupf_write64(rvu, RVU_PF_VFTRPENDX(reg), BIT_ULL(vf)); 2606 rvupf_write64(rvu, RVU_PF_VFFLR_INT_ENA_W1SX(reg), BIT_ULL(vf)); 2607 } 2608 2609 static void rvu_flr_handler(struct work_struct *work) 2610 { 2611 struct rvu_work *flrwork = container_of(work, struct rvu_work, work); 2612 struct rvu *rvu = flrwork->rvu; 2613 u16 pcifunc, numvfs, vf; 2614 u64 cfg; 2615 int pf; 2616 2617 pf = flrwork - rvu->flr_wrk; 2618 if (pf >= rvu->hw->total_pfs) { 2619 rvu_afvf_flr_handler(rvu, pf - rvu->hw->total_pfs); 2620 return; 2621 } 2622 2623 cfg = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_PFX_CFG(pf)); 2624 numvfs = (cfg >> 12) & 0xFF; 2625 pcifunc = pf << RVU_PFVF_PF_SHIFT; 2626 2627 for (vf = 0; vf < numvfs; vf++) 2628 __rvu_flr_handler(rvu, (pcifunc | (vf + 1))); 2629 2630 __rvu_flr_handler(rvu, pcifunc); 2631 2632 /* Signal FLR finish */ 2633 rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_PFTRPEND, BIT_ULL(pf)); 2634 2635 /* Enable interrupt */ 2636 rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_PFFLR_INT_ENA_W1S, BIT_ULL(pf)); 2637 } 2638 2639 static void rvu_afvf_queue_flr_work(struct rvu *rvu, int start_vf, int numvfs) 2640 { 2641 int dev, vf, reg = 0; 2642 u64 intr; 2643 2644 if (start_vf >= 64) 2645 reg = 1; 2646 2647 intr = rvupf_read64(rvu, RVU_PF_VFFLR_INTX(reg)); 2648 if (!intr) 2649 return; 2650 2651 for (vf = 0; vf < numvfs; vf++) { 2652 if (!(intr & BIT_ULL(vf))) 2653 continue; 2654 /* Clear and disable the interrupt */ 2655 rvupf_write64(rvu, RVU_PF_VFFLR_INTX(reg), BIT_ULL(vf)); 2656 rvupf_write64(rvu, RVU_PF_VFFLR_INT_ENA_W1CX(reg), BIT_ULL(vf)); 2657 2658 dev = vf + start_vf + rvu->hw->total_pfs; 2659 queue_work(rvu->flr_wq, &rvu->flr_wrk[dev].work); 2660 } 2661 } 2662 2663 static irqreturn_t rvu_flr_intr_handler(int irq, void *rvu_irq) 2664 { 2665 struct rvu *rvu = (struct rvu *)rvu_irq; 2666 u64 intr; 2667 u8 pf; 2668 2669 intr = rvu_read64(rvu, BLKADDR_RVUM, RVU_AF_PFFLR_INT); 2670 if (!intr) 2671 goto afvf_flr; 2672 2673 for (pf = 0; pf < rvu->hw->total_pfs; pf++) { 2674 if (intr & (1ULL << pf)) { 2675 /* clear interrupt */ 2676 rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_PFFLR_INT, 2677 BIT_ULL(pf)); 2678 /* Disable the interrupt */ 2679 rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_PFFLR_INT_ENA_W1C, 2680 BIT_ULL(pf)); 2681 /* PF is already dead do only AF related operations */ 2682 queue_work(rvu->flr_wq, &rvu->flr_wrk[pf].work); 2683 } 2684 } 2685 2686 afvf_flr: 2687 rvu_afvf_queue_flr_work(rvu, 0, 64); 2688 if (rvu->vfs > 64) 2689 rvu_afvf_queue_flr_work(rvu, 64, rvu->vfs - 64); 2690 2691 return IRQ_HANDLED; 2692 } 2693 2694 static void rvu_me_handle_vfset(struct rvu *rvu, int idx, u64 intr) 2695 { 2696 int vf; 2697 2698 /* Nothing to be done here other than clearing the 2699 * TRPEND bit. 2700 */ 2701 for (vf = 0; vf < 64; vf++) { 2702 if (intr & (1ULL << vf)) { 2703 /* clear the trpend due to ME(master enable) */ 2704 rvupf_write64(rvu, RVU_PF_VFTRPENDX(idx), BIT_ULL(vf)); 2705 /* clear interrupt */ 2706 rvupf_write64(rvu, RVU_PF_VFME_INTX(idx), BIT_ULL(vf)); 2707 } 2708 } 2709 } 2710 2711 /* Handles ME interrupts from VFs of AF */ 2712 static irqreturn_t rvu_me_vf_intr_handler(int irq, void *rvu_irq) 2713 { 2714 struct rvu *rvu = (struct rvu *)rvu_irq; 2715 int vfset; 2716 u64 intr; 2717 2718 intr = rvu_read64(rvu, BLKADDR_RVUM, RVU_AF_PFME_INT); 2719 2720 for (vfset = 0; vfset <= 1; vfset++) { 2721 intr = rvupf_read64(rvu, RVU_PF_VFME_INTX(vfset)); 2722 if (intr) 2723 rvu_me_handle_vfset(rvu, vfset, intr); 2724 } 2725 2726 return IRQ_HANDLED; 2727 } 2728 2729 /* Handles ME interrupts from PFs */ 2730 static irqreturn_t rvu_me_pf_intr_handler(int irq, void *rvu_irq) 2731 { 2732 struct rvu *rvu = (struct rvu *)rvu_irq; 2733 u64 intr; 2734 u8 pf; 2735 2736 intr = rvu_read64(rvu, BLKADDR_RVUM, RVU_AF_PFME_INT); 2737 2738 /* Nothing to be done here other than clearing the 2739 * TRPEND bit. 2740 */ 2741 for (pf = 0; pf < rvu->hw->total_pfs; pf++) { 2742 if (intr & (1ULL << pf)) { 2743 /* clear the trpend due to ME(master enable) */ 2744 rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_PFTRPEND, 2745 BIT_ULL(pf)); 2746 /* clear interrupt */ 2747 rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_PFME_INT, 2748 BIT_ULL(pf)); 2749 } 2750 } 2751 2752 return IRQ_HANDLED; 2753 } 2754 2755 static void rvu_unregister_interrupts(struct rvu *rvu) 2756 { 2757 int irq; 2758 2759 rvu_cpt_unregister_interrupts(rvu); 2760 2761 /* Disable the Mbox interrupt */ 2762 rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_PFAF_MBOX_INT_ENA_W1C, 2763 INTR_MASK(rvu->hw->total_pfs) & ~1ULL); 2764 2765 /* Disable the PF FLR interrupt */ 2766 rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_PFFLR_INT_ENA_W1C, 2767 INTR_MASK(rvu->hw->total_pfs) & ~1ULL); 2768 2769 /* Disable the PF ME interrupt */ 2770 rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_PFME_INT_ENA_W1C, 2771 INTR_MASK(rvu->hw->total_pfs) & ~1ULL); 2772 2773 for (irq = 0; irq < rvu->num_vec; irq++) { 2774 if (rvu->irq_allocated[irq]) { 2775 free_irq(pci_irq_vector(rvu->pdev, irq), rvu); 2776 rvu->irq_allocated[irq] = false; 2777 } 2778 } 2779 2780 pci_free_irq_vectors(rvu->pdev); 2781 rvu->num_vec = 0; 2782 } 2783 2784 static int rvu_afvf_msix_vectors_num_ok(struct rvu *rvu) 2785 { 2786 struct rvu_pfvf *pfvf = &rvu->pf[0]; 2787 int offset; 2788 2789 pfvf = &rvu->pf[0]; 2790 offset = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_PFX_INT_CFG(0)) & 0x3ff; 2791 2792 /* Make sure there are enough MSIX vectors configured so that 2793 * VF interrupts can be handled. Offset equal to zero means 2794 * that PF vectors are not configured and overlapping AF vectors. 2795 */ 2796 return (pfvf->msix.max >= RVU_AF_INT_VEC_CNT + RVU_PF_INT_VEC_CNT) && 2797 offset; 2798 } 2799 2800 static int rvu_register_interrupts(struct rvu *rvu) 2801 { 2802 int ret, offset, pf_vec_start; 2803 2804 rvu->num_vec = pci_msix_vec_count(rvu->pdev); 2805 2806 rvu->irq_name = devm_kmalloc_array(rvu->dev, rvu->num_vec, 2807 NAME_SIZE, GFP_KERNEL); 2808 if (!rvu->irq_name) 2809 return -ENOMEM; 2810 2811 rvu->irq_allocated = devm_kcalloc(rvu->dev, rvu->num_vec, 2812 sizeof(bool), GFP_KERNEL); 2813 if (!rvu->irq_allocated) 2814 return -ENOMEM; 2815 2816 /* Enable MSI-X */ 2817 ret = pci_alloc_irq_vectors(rvu->pdev, rvu->num_vec, 2818 rvu->num_vec, PCI_IRQ_MSIX); 2819 if (ret < 0) { 2820 dev_err(rvu->dev, 2821 "RVUAF: Request for %d msix vectors failed, ret %d\n", 2822 rvu->num_vec, ret); 2823 return ret; 2824 } 2825 2826 /* Register mailbox interrupt handler */ 2827 sprintf(&rvu->irq_name[RVU_AF_INT_VEC_MBOX * NAME_SIZE], "RVUAF Mbox"); 2828 ret = request_irq(pci_irq_vector(rvu->pdev, RVU_AF_INT_VEC_MBOX), 2829 rvu_mbox_intr_handler, 0, 2830 &rvu->irq_name[RVU_AF_INT_VEC_MBOX * NAME_SIZE], rvu); 2831 if (ret) { 2832 dev_err(rvu->dev, 2833 "RVUAF: IRQ registration failed for mbox irq\n"); 2834 goto fail; 2835 } 2836 2837 rvu->irq_allocated[RVU_AF_INT_VEC_MBOX] = true; 2838 2839 /* Enable mailbox interrupts from all PFs */ 2840 rvu_enable_mbox_intr(rvu); 2841 2842 /* Register FLR interrupt handler */ 2843 sprintf(&rvu->irq_name[RVU_AF_INT_VEC_PFFLR * NAME_SIZE], 2844 "RVUAF FLR"); 2845 ret = request_irq(pci_irq_vector(rvu->pdev, RVU_AF_INT_VEC_PFFLR), 2846 rvu_flr_intr_handler, 0, 2847 &rvu->irq_name[RVU_AF_INT_VEC_PFFLR * NAME_SIZE], 2848 rvu); 2849 if (ret) { 2850 dev_err(rvu->dev, 2851 "RVUAF: IRQ registration failed for FLR\n"); 2852 goto fail; 2853 } 2854 rvu->irq_allocated[RVU_AF_INT_VEC_PFFLR] = true; 2855 2856 /* Enable FLR interrupt for all PFs*/ 2857 rvu_write64(rvu, BLKADDR_RVUM, 2858 RVU_AF_PFFLR_INT, INTR_MASK(rvu->hw->total_pfs)); 2859 2860 rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_PFFLR_INT_ENA_W1S, 2861 INTR_MASK(rvu->hw->total_pfs) & ~1ULL); 2862 2863 /* Register ME interrupt handler */ 2864 sprintf(&rvu->irq_name[RVU_AF_INT_VEC_PFME * NAME_SIZE], 2865 "RVUAF ME"); 2866 ret = request_irq(pci_irq_vector(rvu->pdev, RVU_AF_INT_VEC_PFME), 2867 rvu_me_pf_intr_handler, 0, 2868 &rvu->irq_name[RVU_AF_INT_VEC_PFME * NAME_SIZE], 2869 rvu); 2870 if (ret) { 2871 dev_err(rvu->dev, 2872 "RVUAF: IRQ registration failed for ME\n"); 2873 } 2874 rvu->irq_allocated[RVU_AF_INT_VEC_PFME] = true; 2875 2876 /* Clear TRPEND bit for all PF */ 2877 rvu_write64(rvu, BLKADDR_RVUM, 2878 RVU_AF_PFTRPEND, INTR_MASK(rvu->hw->total_pfs)); 2879 /* Enable ME interrupt for all PFs*/ 2880 rvu_write64(rvu, BLKADDR_RVUM, 2881 RVU_AF_PFME_INT, INTR_MASK(rvu->hw->total_pfs)); 2882 2883 rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_PFME_INT_ENA_W1S, 2884 INTR_MASK(rvu->hw->total_pfs) & ~1ULL); 2885 2886 if (!rvu_afvf_msix_vectors_num_ok(rvu)) 2887 return 0; 2888 2889 /* Get PF MSIX vectors offset. */ 2890 pf_vec_start = rvu_read64(rvu, BLKADDR_RVUM, 2891 RVU_PRIV_PFX_INT_CFG(0)) & 0x3ff; 2892 2893 /* Register MBOX0 interrupt. */ 2894 offset = pf_vec_start + RVU_PF_INT_VEC_VFPF_MBOX0; 2895 sprintf(&rvu->irq_name[offset * NAME_SIZE], "RVUAFVF Mbox0"); 2896 ret = request_irq(pci_irq_vector(rvu->pdev, offset), 2897 rvu_mbox_intr_handler, 0, 2898 &rvu->irq_name[offset * NAME_SIZE], 2899 rvu); 2900 if (ret) 2901 dev_err(rvu->dev, 2902 "RVUAF: IRQ registration failed for Mbox0\n"); 2903 2904 rvu->irq_allocated[offset] = true; 2905 2906 /* Register MBOX1 interrupt. MBOX1 IRQ number follows MBOX0 so 2907 * simply increment current offset by 1. 2908 */ 2909 offset = pf_vec_start + RVU_PF_INT_VEC_VFPF_MBOX1; 2910 sprintf(&rvu->irq_name[offset * NAME_SIZE], "RVUAFVF Mbox1"); 2911 ret = request_irq(pci_irq_vector(rvu->pdev, offset), 2912 rvu_mbox_intr_handler, 0, 2913 &rvu->irq_name[offset * NAME_SIZE], 2914 rvu); 2915 if (ret) 2916 dev_err(rvu->dev, 2917 "RVUAF: IRQ registration failed for Mbox1\n"); 2918 2919 rvu->irq_allocated[offset] = true; 2920 2921 /* Register FLR interrupt handler for AF's VFs */ 2922 offset = pf_vec_start + RVU_PF_INT_VEC_VFFLR0; 2923 sprintf(&rvu->irq_name[offset * NAME_SIZE], "RVUAFVF FLR0"); 2924 ret = request_irq(pci_irq_vector(rvu->pdev, offset), 2925 rvu_flr_intr_handler, 0, 2926 &rvu->irq_name[offset * NAME_SIZE], rvu); 2927 if (ret) { 2928 dev_err(rvu->dev, 2929 "RVUAF: IRQ registration failed for RVUAFVF FLR0\n"); 2930 goto fail; 2931 } 2932 rvu->irq_allocated[offset] = true; 2933 2934 offset = pf_vec_start + RVU_PF_INT_VEC_VFFLR1; 2935 sprintf(&rvu->irq_name[offset * NAME_SIZE], "RVUAFVF FLR1"); 2936 ret = request_irq(pci_irq_vector(rvu->pdev, offset), 2937 rvu_flr_intr_handler, 0, 2938 &rvu->irq_name[offset * NAME_SIZE], rvu); 2939 if (ret) { 2940 dev_err(rvu->dev, 2941 "RVUAF: IRQ registration failed for RVUAFVF FLR1\n"); 2942 goto fail; 2943 } 2944 rvu->irq_allocated[offset] = true; 2945 2946 /* Register ME interrupt handler for AF's VFs */ 2947 offset = pf_vec_start + RVU_PF_INT_VEC_VFME0; 2948 sprintf(&rvu->irq_name[offset * NAME_SIZE], "RVUAFVF ME0"); 2949 ret = request_irq(pci_irq_vector(rvu->pdev, offset), 2950 rvu_me_vf_intr_handler, 0, 2951 &rvu->irq_name[offset * NAME_SIZE], rvu); 2952 if (ret) { 2953 dev_err(rvu->dev, 2954 "RVUAF: IRQ registration failed for RVUAFVF ME0\n"); 2955 goto fail; 2956 } 2957 rvu->irq_allocated[offset] = true; 2958 2959 offset = pf_vec_start + RVU_PF_INT_VEC_VFME1; 2960 sprintf(&rvu->irq_name[offset * NAME_SIZE], "RVUAFVF ME1"); 2961 ret = request_irq(pci_irq_vector(rvu->pdev, offset), 2962 rvu_me_vf_intr_handler, 0, 2963 &rvu->irq_name[offset * NAME_SIZE], rvu); 2964 if (ret) { 2965 dev_err(rvu->dev, 2966 "RVUAF: IRQ registration failed for RVUAFVF ME1\n"); 2967 goto fail; 2968 } 2969 rvu->irq_allocated[offset] = true; 2970 2971 ret = rvu_cpt_register_interrupts(rvu); 2972 if (ret) 2973 goto fail; 2974 2975 return 0; 2976 2977 fail: 2978 rvu_unregister_interrupts(rvu); 2979 return ret; 2980 } 2981 2982 static void rvu_flr_wq_destroy(struct rvu *rvu) 2983 { 2984 if (rvu->flr_wq) { 2985 destroy_workqueue(rvu->flr_wq); 2986 rvu->flr_wq = NULL; 2987 } 2988 } 2989 2990 static int rvu_flr_init(struct rvu *rvu) 2991 { 2992 int dev, num_devs; 2993 u64 cfg; 2994 int pf; 2995 2996 /* Enable FLR for all PFs*/ 2997 for (pf = 0; pf < rvu->hw->total_pfs; pf++) { 2998 cfg = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_PFX_CFG(pf)); 2999 rvu_write64(rvu, BLKADDR_RVUM, RVU_PRIV_PFX_CFG(pf), 3000 cfg | BIT_ULL(22)); 3001 } 3002 3003 rvu->flr_wq = alloc_workqueue("rvu_afpf_flr", 3004 WQ_UNBOUND | WQ_HIGHPRI | WQ_MEM_RECLAIM, 3005 1); 3006 if (!rvu->flr_wq) 3007 return -ENOMEM; 3008 3009 num_devs = rvu->hw->total_pfs + pci_sriov_get_totalvfs(rvu->pdev); 3010 rvu->flr_wrk = devm_kcalloc(rvu->dev, num_devs, 3011 sizeof(struct rvu_work), GFP_KERNEL); 3012 if (!rvu->flr_wrk) { 3013 destroy_workqueue(rvu->flr_wq); 3014 return -ENOMEM; 3015 } 3016 3017 for (dev = 0; dev < num_devs; dev++) { 3018 rvu->flr_wrk[dev].rvu = rvu; 3019 INIT_WORK(&rvu->flr_wrk[dev].work, rvu_flr_handler); 3020 } 3021 3022 mutex_init(&rvu->flr_lock); 3023 3024 return 0; 3025 } 3026 3027 static void rvu_disable_afvf_intr(struct rvu *rvu) 3028 { 3029 int vfs = rvu->vfs; 3030 3031 rvupf_write64(rvu, RVU_PF_VFPF_MBOX_INT_ENA_W1CX(0), INTR_MASK(vfs)); 3032 rvupf_write64(rvu, RVU_PF_VFFLR_INT_ENA_W1CX(0), INTR_MASK(vfs)); 3033 rvupf_write64(rvu, RVU_PF_VFME_INT_ENA_W1CX(0), INTR_MASK(vfs)); 3034 if (vfs <= 64) 3035 return; 3036 3037 rvupf_write64(rvu, RVU_PF_VFPF_MBOX_INT_ENA_W1CX(1), 3038 INTR_MASK(vfs - 64)); 3039 rvupf_write64(rvu, RVU_PF_VFFLR_INT_ENA_W1CX(1), INTR_MASK(vfs - 64)); 3040 rvupf_write64(rvu, RVU_PF_VFME_INT_ENA_W1CX(1), INTR_MASK(vfs - 64)); 3041 } 3042 3043 static void rvu_enable_afvf_intr(struct rvu *rvu) 3044 { 3045 int vfs = rvu->vfs; 3046 3047 /* Clear any pending interrupts and enable AF VF interrupts for 3048 * the first 64 VFs. 3049 */ 3050 /* Mbox */ 3051 rvupf_write64(rvu, RVU_PF_VFPF_MBOX_INTX(0), INTR_MASK(vfs)); 3052 rvupf_write64(rvu, RVU_PF_VFPF_MBOX_INT_ENA_W1SX(0), INTR_MASK(vfs)); 3053 3054 /* FLR */ 3055 rvupf_write64(rvu, RVU_PF_VFFLR_INTX(0), INTR_MASK(vfs)); 3056 rvupf_write64(rvu, RVU_PF_VFFLR_INT_ENA_W1SX(0), INTR_MASK(vfs)); 3057 rvupf_write64(rvu, RVU_PF_VFME_INT_ENA_W1SX(0), INTR_MASK(vfs)); 3058 3059 /* Same for remaining VFs, if any. */ 3060 if (vfs <= 64) 3061 return; 3062 3063 rvupf_write64(rvu, RVU_PF_VFPF_MBOX_INTX(1), INTR_MASK(vfs - 64)); 3064 rvupf_write64(rvu, RVU_PF_VFPF_MBOX_INT_ENA_W1SX(1), 3065 INTR_MASK(vfs - 64)); 3066 3067 rvupf_write64(rvu, RVU_PF_VFFLR_INTX(1), INTR_MASK(vfs - 64)); 3068 rvupf_write64(rvu, RVU_PF_VFFLR_INT_ENA_W1SX(1), INTR_MASK(vfs - 64)); 3069 rvupf_write64(rvu, RVU_PF_VFME_INT_ENA_W1SX(1), INTR_MASK(vfs - 64)); 3070 } 3071 3072 int rvu_get_num_lbk_chans(void) 3073 { 3074 struct pci_dev *pdev; 3075 void __iomem *base; 3076 int ret = -EIO; 3077 3078 pdev = pci_get_device(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_OCTEONTX2_LBK, 3079 NULL); 3080 if (!pdev) 3081 goto err; 3082 3083 base = pci_ioremap_bar(pdev, 0); 3084 if (!base) 3085 goto err_put; 3086 3087 /* Read number of available LBK channels from LBK(0)_CONST register. */ 3088 ret = (readq(base + 0x10) >> 32) & 0xffff; 3089 iounmap(base); 3090 err_put: 3091 pci_dev_put(pdev); 3092 err: 3093 return ret; 3094 } 3095 3096 static int rvu_enable_sriov(struct rvu *rvu) 3097 { 3098 struct pci_dev *pdev = rvu->pdev; 3099 int err, chans, vfs; 3100 3101 if (!rvu_afvf_msix_vectors_num_ok(rvu)) { 3102 dev_warn(&pdev->dev, 3103 "Skipping SRIOV enablement since not enough IRQs are available\n"); 3104 return 0; 3105 } 3106 3107 chans = rvu_get_num_lbk_chans(); 3108 if (chans < 0) 3109 return chans; 3110 3111 vfs = pci_sriov_get_totalvfs(pdev); 3112 3113 /* Limit VFs in case we have more VFs than LBK channels available. */ 3114 if (vfs > chans) 3115 vfs = chans; 3116 3117 if (!vfs) 3118 return 0; 3119 3120 /* LBK channel number 63 is used for switching packets between 3121 * CGX mapped VFs. Hence limit LBK pairs till 62 only. 3122 */ 3123 if (vfs > 62) 3124 vfs = 62; 3125 3126 /* Save VFs number for reference in VF interrupts handlers. 3127 * Since interrupts might start arriving during SRIOV enablement 3128 * ordinary API cannot be used to get number of enabled VFs. 3129 */ 3130 rvu->vfs = vfs; 3131 3132 err = rvu_mbox_init(rvu, &rvu->afvf_wq_info, TYPE_AFVF, vfs, 3133 rvu_afvf_mbox_handler, rvu_afvf_mbox_up_handler); 3134 if (err) 3135 return err; 3136 3137 rvu_enable_afvf_intr(rvu); 3138 /* Make sure IRQs are enabled before SRIOV. */ 3139 mb(); 3140 3141 err = pci_enable_sriov(pdev, vfs); 3142 if (err) { 3143 rvu_disable_afvf_intr(rvu); 3144 rvu_mbox_destroy(&rvu->afvf_wq_info); 3145 return err; 3146 } 3147 3148 return 0; 3149 } 3150 3151 static void rvu_disable_sriov(struct rvu *rvu) 3152 { 3153 rvu_disable_afvf_intr(rvu); 3154 rvu_mbox_destroy(&rvu->afvf_wq_info); 3155 pci_disable_sriov(rvu->pdev); 3156 } 3157 3158 static void rvu_update_module_params(struct rvu *rvu) 3159 { 3160 const char *default_pfl_name = "default"; 3161 3162 strscpy(rvu->mkex_pfl_name, 3163 mkex_profile ? mkex_profile : default_pfl_name, MKEX_NAME_LEN); 3164 strscpy(rvu->kpu_pfl_name, 3165 kpu_profile ? kpu_profile : default_pfl_name, KPU_NAME_LEN); 3166 } 3167 3168 static int rvu_probe(struct pci_dev *pdev, const struct pci_device_id *id) 3169 { 3170 struct device *dev = &pdev->dev; 3171 struct rvu *rvu; 3172 int err; 3173 3174 rvu = devm_kzalloc(dev, sizeof(*rvu), GFP_KERNEL); 3175 if (!rvu) 3176 return -ENOMEM; 3177 3178 rvu->hw = devm_kzalloc(dev, sizeof(struct rvu_hwinfo), GFP_KERNEL); 3179 if (!rvu->hw) { 3180 devm_kfree(dev, rvu); 3181 return -ENOMEM; 3182 } 3183 3184 pci_set_drvdata(pdev, rvu); 3185 rvu->pdev = pdev; 3186 rvu->dev = &pdev->dev; 3187 3188 err = pci_enable_device(pdev); 3189 if (err) { 3190 dev_err(dev, "Failed to enable PCI device\n"); 3191 goto err_freemem; 3192 } 3193 3194 err = pci_request_regions(pdev, DRV_NAME); 3195 if (err) { 3196 dev_err(dev, "PCI request regions failed 0x%x\n", err); 3197 goto err_disable_device; 3198 } 3199 3200 err = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(48)); 3201 if (err) { 3202 dev_err(dev, "DMA mask config failed, abort\n"); 3203 goto err_release_regions; 3204 } 3205 3206 pci_set_master(pdev); 3207 3208 rvu->ptp = ptp_get(); 3209 if (IS_ERR(rvu->ptp)) { 3210 err = PTR_ERR(rvu->ptp); 3211 if (err == -EPROBE_DEFER) 3212 goto err_release_regions; 3213 rvu->ptp = NULL; 3214 } 3215 3216 /* Map Admin function CSRs */ 3217 rvu->afreg_base = pcim_iomap(pdev, PCI_AF_REG_BAR_NUM, 0); 3218 rvu->pfreg_base = pcim_iomap(pdev, PCI_PF_REG_BAR_NUM, 0); 3219 if (!rvu->afreg_base || !rvu->pfreg_base) { 3220 dev_err(dev, "Unable to map admin function CSRs, aborting\n"); 3221 err = -ENOMEM; 3222 goto err_put_ptp; 3223 } 3224 3225 /* Store module params in rvu structure */ 3226 rvu_update_module_params(rvu); 3227 3228 /* Check which blocks the HW supports */ 3229 rvu_check_block_implemented(rvu); 3230 3231 rvu_reset_all_blocks(rvu); 3232 3233 rvu_setup_hw_capabilities(rvu); 3234 3235 err = rvu_setup_hw_resources(rvu); 3236 if (err) 3237 goto err_put_ptp; 3238 3239 /* Init mailbox btw AF and PFs */ 3240 err = rvu_mbox_init(rvu, &rvu->afpf_wq_info, TYPE_AFPF, 3241 rvu->hw->total_pfs, rvu_afpf_mbox_handler, 3242 rvu_afpf_mbox_up_handler); 3243 if (err) { 3244 dev_err(dev, "%s: Failed to initialize mbox\n", __func__); 3245 goto err_hwsetup; 3246 } 3247 3248 err = rvu_flr_init(rvu); 3249 if (err) { 3250 dev_err(dev, "%s: Failed to initialize flr\n", __func__); 3251 goto err_mbox; 3252 } 3253 3254 err = rvu_register_interrupts(rvu); 3255 if (err) { 3256 dev_err(dev, "%s: Failed to register interrupts\n", __func__); 3257 goto err_flr; 3258 } 3259 3260 err = rvu_register_dl(rvu); 3261 if (err) { 3262 dev_err(dev, "%s: Failed to register devlink\n", __func__); 3263 goto err_irq; 3264 } 3265 3266 rvu_setup_rvum_blk_revid(rvu); 3267 3268 /* Enable AF's VFs (if any) */ 3269 err = rvu_enable_sriov(rvu); 3270 if (err) { 3271 dev_err(dev, "%s: Failed to enable sriov\n", __func__); 3272 goto err_dl; 3273 } 3274 3275 /* Initialize debugfs */ 3276 rvu_dbg_init(rvu); 3277 3278 mutex_init(&rvu->rswitch.switch_lock); 3279 3280 if (rvu->fwdata) 3281 ptp_start(rvu->ptp, rvu->fwdata->sclk, rvu->fwdata->ptp_ext_clk_rate, 3282 rvu->fwdata->ptp_ext_tstamp); 3283 3284 return 0; 3285 err_dl: 3286 rvu_unregister_dl(rvu); 3287 err_irq: 3288 rvu_unregister_interrupts(rvu); 3289 err_flr: 3290 rvu_flr_wq_destroy(rvu); 3291 err_mbox: 3292 rvu_mbox_destroy(&rvu->afpf_wq_info); 3293 err_hwsetup: 3294 rvu_cgx_exit(rvu); 3295 rvu_fwdata_exit(rvu); 3296 rvu_reset_all_blocks(rvu); 3297 rvu_free_hw_resources(rvu); 3298 rvu_clear_rvum_blk_revid(rvu); 3299 err_put_ptp: 3300 ptp_put(rvu->ptp); 3301 err_release_regions: 3302 pci_release_regions(pdev); 3303 err_disable_device: 3304 pci_disable_device(pdev); 3305 err_freemem: 3306 pci_set_drvdata(pdev, NULL); 3307 devm_kfree(&pdev->dev, rvu->hw); 3308 devm_kfree(dev, rvu); 3309 return err; 3310 } 3311 3312 static void rvu_remove(struct pci_dev *pdev) 3313 { 3314 struct rvu *rvu = pci_get_drvdata(pdev); 3315 3316 rvu_dbg_exit(rvu); 3317 rvu_unregister_dl(rvu); 3318 rvu_unregister_interrupts(rvu); 3319 rvu_flr_wq_destroy(rvu); 3320 rvu_cgx_exit(rvu); 3321 rvu_fwdata_exit(rvu); 3322 rvu_mbox_destroy(&rvu->afpf_wq_info); 3323 rvu_disable_sriov(rvu); 3324 rvu_reset_all_blocks(rvu); 3325 rvu_free_hw_resources(rvu); 3326 rvu_clear_rvum_blk_revid(rvu); 3327 ptp_put(rvu->ptp); 3328 pci_release_regions(pdev); 3329 pci_disable_device(pdev); 3330 pci_set_drvdata(pdev, NULL); 3331 3332 devm_kfree(&pdev->dev, rvu->hw); 3333 devm_kfree(&pdev->dev, rvu); 3334 } 3335 3336 static struct pci_driver rvu_driver = { 3337 .name = DRV_NAME, 3338 .id_table = rvu_id_table, 3339 .probe = rvu_probe, 3340 .remove = rvu_remove, 3341 }; 3342 3343 static int __init rvu_init_module(void) 3344 { 3345 int err; 3346 3347 pr_info("%s: %s\n", DRV_NAME, DRV_STRING); 3348 3349 err = pci_register_driver(&cgx_driver); 3350 if (err < 0) 3351 return err; 3352 3353 err = pci_register_driver(&ptp_driver); 3354 if (err < 0) 3355 goto ptp_err; 3356 3357 err = pci_register_driver(&rvu_driver); 3358 if (err < 0) 3359 goto rvu_err; 3360 3361 return 0; 3362 rvu_err: 3363 pci_unregister_driver(&ptp_driver); 3364 ptp_err: 3365 pci_unregister_driver(&cgx_driver); 3366 3367 return err; 3368 } 3369 3370 static void __exit rvu_cleanup_module(void) 3371 { 3372 pci_unregister_driver(&rvu_driver); 3373 pci_unregister_driver(&ptp_driver); 3374 pci_unregister_driver(&cgx_driver); 3375 } 3376 3377 module_init(rvu_init_module); 3378 module_exit(rvu_cleanup_module); 3379