1 // SPDX-License-Identifier: GPL-2.0 2 /* Marvell OcteonTx2 RVU Admin Function driver 3 * 4 * Copyright (C) 2018 Marvell International Ltd. 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 */ 10 11 #include <linux/module.h> 12 #include <linux/interrupt.h> 13 #include <linux/delay.h> 14 #include <linux/irq.h> 15 #include <linux/pci.h> 16 #include <linux/sysfs.h> 17 18 #include "cgx.h" 19 #include "rvu.h" 20 #include "rvu_reg.h" 21 22 #define DRV_NAME "octeontx2-af" 23 #define DRV_STRING "Marvell OcteonTX2 RVU Admin Function Driver" 24 #define DRV_VERSION "1.0" 25 26 static int rvu_get_hwvf(struct rvu *rvu, int pcifunc); 27 28 static void rvu_set_msix_offset(struct rvu *rvu, struct rvu_pfvf *pfvf, 29 struct rvu_block *block, int lf); 30 static void rvu_clear_msix_offset(struct rvu *rvu, struct rvu_pfvf *pfvf, 31 struct rvu_block *block, int lf); 32 static void __rvu_flr_handler(struct rvu *rvu, u16 pcifunc); 33 34 static int rvu_mbox_init(struct rvu *rvu, struct mbox_wq_info *mw, 35 int type, int num, 36 void (mbox_handler)(struct work_struct *), 37 void (mbox_up_handler)(struct work_struct *)); 38 enum { 39 TYPE_AFVF, 40 TYPE_AFPF, 41 }; 42 43 /* Supported devices */ 44 static const struct pci_device_id rvu_id_table[] = { 45 { PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_OCTEONTX2_RVU_AF) }, 46 { 0, } /* end of table */ 47 }; 48 49 MODULE_AUTHOR("Marvell International Ltd."); 50 MODULE_DESCRIPTION(DRV_STRING); 51 MODULE_LICENSE("GPL v2"); 52 MODULE_VERSION(DRV_VERSION); 53 MODULE_DEVICE_TABLE(pci, rvu_id_table); 54 55 /* Poll a RVU block's register 'offset', for a 'zero' 56 * or 'nonzero' at bits specified by 'mask' 57 */ 58 int rvu_poll_reg(struct rvu *rvu, u64 block, u64 offset, u64 mask, bool zero) 59 { 60 unsigned long timeout = jiffies + usecs_to_jiffies(100); 61 void __iomem *reg; 62 u64 reg_val; 63 64 reg = rvu->afreg_base + ((block << 28) | offset); 65 while (time_before(jiffies, timeout)) { 66 reg_val = readq(reg); 67 if (zero && !(reg_val & mask)) 68 return 0; 69 if (!zero && (reg_val & mask)) 70 return 0; 71 usleep_range(1, 5); 72 timeout--; 73 } 74 return -EBUSY; 75 } 76 77 int rvu_alloc_rsrc(struct rsrc_bmap *rsrc) 78 { 79 int id; 80 81 if (!rsrc->bmap) 82 return -EINVAL; 83 84 id = find_first_zero_bit(rsrc->bmap, rsrc->max); 85 if (id >= rsrc->max) 86 return -ENOSPC; 87 88 __set_bit(id, rsrc->bmap); 89 90 return id; 91 } 92 93 int rvu_alloc_rsrc_contig(struct rsrc_bmap *rsrc, int nrsrc) 94 { 95 int start; 96 97 if (!rsrc->bmap) 98 return -EINVAL; 99 100 start = bitmap_find_next_zero_area(rsrc->bmap, rsrc->max, 0, nrsrc, 0); 101 if (start >= rsrc->max) 102 return -ENOSPC; 103 104 bitmap_set(rsrc->bmap, start, nrsrc); 105 return start; 106 } 107 108 static void rvu_free_rsrc_contig(struct rsrc_bmap *rsrc, int nrsrc, int start) 109 { 110 if (!rsrc->bmap) 111 return; 112 if (start >= rsrc->max) 113 return; 114 115 bitmap_clear(rsrc->bmap, start, nrsrc); 116 } 117 118 bool rvu_rsrc_check_contig(struct rsrc_bmap *rsrc, int nrsrc) 119 { 120 int start; 121 122 if (!rsrc->bmap) 123 return false; 124 125 start = bitmap_find_next_zero_area(rsrc->bmap, rsrc->max, 0, nrsrc, 0); 126 if (start >= rsrc->max) 127 return false; 128 129 return true; 130 } 131 132 void rvu_free_rsrc(struct rsrc_bmap *rsrc, int id) 133 { 134 if (!rsrc->bmap) 135 return; 136 137 __clear_bit(id, rsrc->bmap); 138 } 139 140 int rvu_rsrc_free_count(struct rsrc_bmap *rsrc) 141 { 142 int used; 143 144 if (!rsrc->bmap) 145 return 0; 146 147 used = bitmap_weight(rsrc->bmap, rsrc->max); 148 return (rsrc->max - used); 149 } 150 151 int rvu_alloc_bitmap(struct rsrc_bmap *rsrc) 152 { 153 rsrc->bmap = kcalloc(BITS_TO_LONGS(rsrc->max), 154 sizeof(long), GFP_KERNEL); 155 if (!rsrc->bmap) 156 return -ENOMEM; 157 return 0; 158 } 159 160 /* Get block LF's HW index from a PF_FUNC's block slot number */ 161 int rvu_get_lf(struct rvu *rvu, struct rvu_block *block, u16 pcifunc, u16 slot) 162 { 163 u16 match = 0; 164 int lf; 165 166 mutex_lock(&rvu->rsrc_lock); 167 for (lf = 0; lf < block->lf.max; lf++) { 168 if (block->fn_map[lf] == pcifunc) { 169 if (slot == match) { 170 mutex_unlock(&rvu->rsrc_lock); 171 return lf; 172 } 173 match++; 174 } 175 } 176 mutex_unlock(&rvu->rsrc_lock); 177 return -ENODEV; 178 } 179 180 /* Convert BLOCK_TYPE_E to a BLOCK_ADDR_E. 181 * Some silicon variants of OcteonTX2 supports 182 * multiple blocks of same type. 183 * 184 * @pcifunc has to be zero when no LF is yet attached. 185 */ 186 int rvu_get_blkaddr(struct rvu *rvu, int blktype, u16 pcifunc) 187 { 188 int devnum, blkaddr = -ENODEV; 189 u64 cfg, reg; 190 bool is_pf; 191 192 switch (blktype) { 193 case BLKTYPE_NPC: 194 blkaddr = BLKADDR_NPC; 195 goto exit; 196 case BLKTYPE_NPA: 197 blkaddr = BLKADDR_NPA; 198 goto exit; 199 case BLKTYPE_NIX: 200 /* For now assume NIX0 */ 201 if (!pcifunc) { 202 blkaddr = BLKADDR_NIX0; 203 goto exit; 204 } 205 break; 206 case BLKTYPE_SSO: 207 blkaddr = BLKADDR_SSO; 208 goto exit; 209 case BLKTYPE_SSOW: 210 blkaddr = BLKADDR_SSOW; 211 goto exit; 212 case BLKTYPE_TIM: 213 blkaddr = BLKADDR_TIM; 214 goto exit; 215 case BLKTYPE_CPT: 216 /* For now assume CPT0 */ 217 if (!pcifunc) { 218 blkaddr = BLKADDR_CPT0; 219 goto exit; 220 } 221 break; 222 } 223 224 /* Check if this is a RVU PF or VF */ 225 if (pcifunc & RVU_PFVF_FUNC_MASK) { 226 is_pf = false; 227 devnum = rvu_get_hwvf(rvu, pcifunc); 228 } else { 229 is_pf = true; 230 devnum = rvu_get_pf(pcifunc); 231 } 232 233 /* Check if the 'pcifunc' has a NIX LF from 'BLKADDR_NIX0' */ 234 if (blktype == BLKTYPE_NIX) { 235 reg = is_pf ? RVU_PRIV_PFX_NIX0_CFG : RVU_PRIV_HWVFX_NIX0_CFG; 236 cfg = rvu_read64(rvu, BLKADDR_RVUM, reg | (devnum << 16)); 237 if (cfg) 238 blkaddr = BLKADDR_NIX0; 239 } 240 241 /* Check if the 'pcifunc' has a CPT LF from 'BLKADDR_CPT0' */ 242 if (blktype == BLKTYPE_CPT) { 243 reg = is_pf ? RVU_PRIV_PFX_CPT0_CFG : RVU_PRIV_HWVFX_CPT0_CFG; 244 cfg = rvu_read64(rvu, BLKADDR_RVUM, reg | (devnum << 16)); 245 if (cfg) 246 blkaddr = BLKADDR_CPT0; 247 } 248 249 exit: 250 if (is_block_implemented(rvu->hw, blkaddr)) 251 return blkaddr; 252 return -ENODEV; 253 } 254 255 static void rvu_update_rsrc_map(struct rvu *rvu, struct rvu_pfvf *pfvf, 256 struct rvu_block *block, u16 pcifunc, 257 u16 lf, bool attach) 258 { 259 int devnum, num_lfs = 0; 260 bool is_pf; 261 u64 reg; 262 263 if (lf >= block->lf.max) { 264 dev_err(&rvu->pdev->dev, 265 "%s: FATAL: LF %d is >= %s's max lfs i.e %d\n", 266 __func__, lf, block->name, block->lf.max); 267 return; 268 } 269 270 /* Check if this is for a RVU PF or VF */ 271 if (pcifunc & RVU_PFVF_FUNC_MASK) { 272 is_pf = false; 273 devnum = rvu_get_hwvf(rvu, pcifunc); 274 } else { 275 is_pf = true; 276 devnum = rvu_get_pf(pcifunc); 277 } 278 279 block->fn_map[lf] = attach ? pcifunc : 0; 280 281 switch (block->type) { 282 case BLKTYPE_NPA: 283 pfvf->npalf = attach ? true : false; 284 num_lfs = pfvf->npalf; 285 break; 286 case BLKTYPE_NIX: 287 pfvf->nixlf = attach ? true : false; 288 num_lfs = pfvf->nixlf; 289 break; 290 case BLKTYPE_SSO: 291 attach ? pfvf->sso++ : pfvf->sso--; 292 num_lfs = pfvf->sso; 293 break; 294 case BLKTYPE_SSOW: 295 attach ? pfvf->ssow++ : pfvf->ssow--; 296 num_lfs = pfvf->ssow; 297 break; 298 case BLKTYPE_TIM: 299 attach ? pfvf->timlfs++ : pfvf->timlfs--; 300 num_lfs = pfvf->timlfs; 301 break; 302 case BLKTYPE_CPT: 303 attach ? pfvf->cptlfs++ : pfvf->cptlfs--; 304 num_lfs = pfvf->cptlfs; 305 break; 306 } 307 308 reg = is_pf ? block->pf_lfcnt_reg : block->vf_lfcnt_reg; 309 rvu_write64(rvu, BLKADDR_RVUM, reg | (devnum << 16), num_lfs); 310 } 311 312 inline int rvu_get_pf(u16 pcifunc) 313 { 314 return (pcifunc >> RVU_PFVF_PF_SHIFT) & RVU_PFVF_PF_MASK; 315 } 316 317 void rvu_get_pf_numvfs(struct rvu *rvu, int pf, int *numvfs, int *hwvf) 318 { 319 u64 cfg; 320 321 /* Get numVFs attached to this PF and first HWVF */ 322 cfg = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_PFX_CFG(pf)); 323 *numvfs = (cfg >> 12) & 0xFF; 324 *hwvf = cfg & 0xFFF; 325 } 326 327 static int rvu_get_hwvf(struct rvu *rvu, int pcifunc) 328 { 329 int pf, func; 330 u64 cfg; 331 332 pf = rvu_get_pf(pcifunc); 333 func = pcifunc & RVU_PFVF_FUNC_MASK; 334 335 /* Get first HWVF attached to this PF */ 336 cfg = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_PFX_CFG(pf)); 337 338 return ((cfg & 0xFFF) + func - 1); 339 } 340 341 struct rvu_pfvf *rvu_get_pfvf(struct rvu *rvu, int pcifunc) 342 { 343 /* Check if it is a PF or VF */ 344 if (pcifunc & RVU_PFVF_FUNC_MASK) 345 return &rvu->hwvf[rvu_get_hwvf(rvu, pcifunc)]; 346 else 347 return &rvu->pf[rvu_get_pf(pcifunc)]; 348 } 349 350 static bool is_pf_func_valid(struct rvu *rvu, u16 pcifunc) 351 { 352 int pf, vf, nvfs; 353 u64 cfg; 354 355 pf = rvu_get_pf(pcifunc); 356 if (pf >= rvu->hw->total_pfs) 357 return false; 358 359 if (!(pcifunc & RVU_PFVF_FUNC_MASK)) 360 return true; 361 362 /* Check if VF is within number of VFs attached to this PF */ 363 vf = (pcifunc & RVU_PFVF_FUNC_MASK) - 1; 364 cfg = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_PFX_CFG(pf)); 365 nvfs = (cfg >> 12) & 0xFF; 366 if (vf >= nvfs) 367 return false; 368 369 return true; 370 } 371 372 bool is_block_implemented(struct rvu_hwinfo *hw, int blkaddr) 373 { 374 struct rvu_block *block; 375 376 if (blkaddr < BLKADDR_RVUM || blkaddr >= BLK_COUNT) 377 return false; 378 379 block = &hw->block[blkaddr]; 380 return block->implemented; 381 } 382 383 static void rvu_check_block_implemented(struct rvu *rvu) 384 { 385 struct rvu_hwinfo *hw = rvu->hw; 386 struct rvu_block *block; 387 int blkid; 388 u64 cfg; 389 390 /* For each block check if 'implemented' bit is set */ 391 for (blkid = 0; blkid < BLK_COUNT; blkid++) { 392 block = &hw->block[blkid]; 393 cfg = rvupf_read64(rvu, RVU_PF_BLOCK_ADDRX_DISC(blkid)); 394 if (cfg & BIT_ULL(11)) 395 block->implemented = true; 396 } 397 } 398 399 int rvu_lf_reset(struct rvu *rvu, struct rvu_block *block, int lf) 400 { 401 int err; 402 403 if (!block->implemented) 404 return 0; 405 406 rvu_write64(rvu, block->addr, block->lfreset_reg, lf | BIT_ULL(12)); 407 err = rvu_poll_reg(rvu, block->addr, block->lfreset_reg, BIT_ULL(12), 408 true); 409 return err; 410 } 411 412 static void rvu_block_reset(struct rvu *rvu, int blkaddr, u64 rst_reg) 413 { 414 struct rvu_block *block = &rvu->hw->block[blkaddr]; 415 416 if (!block->implemented) 417 return; 418 419 rvu_write64(rvu, blkaddr, rst_reg, BIT_ULL(0)); 420 rvu_poll_reg(rvu, blkaddr, rst_reg, BIT_ULL(63), true); 421 } 422 423 static void rvu_reset_all_blocks(struct rvu *rvu) 424 { 425 /* Do a HW reset of all RVU blocks */ 426 rvu_block_reset(rvu, BLKADDR_NPA, NPA_AF_BLK_RST); 427 rvu_block_reset(rvu, BLKADDR_NIX0, NIX_AF_BLK_RST); 428 rvu_block_reset(rvu, BLKADDR_NPC, NPC_AF_BLK_RST); 429 rvu_block_reset(rvu, BLKADDR_SSO, SSO_AF_BLK_RST); 430 rvu_block_reset(rvu, BLKADDR_TIM, TIM_AF_BLK_RST); 431 rvu_block_reset(rvu, BLKADDR_CPT0, CPT_AF_BLK_RST); 432 rvu_block_reset(rvu, BLKADDR_NDC0, NDC_AF_BLK_RST); 433 rvu_block_reset(rvu, BLKADDR_NDC1, NDC_AF_BLK_RST); 434 rvu_block_reset(rvu, BLKADDR_NDC2, NDC_AF_BLK_RST); 435 } 436 437 static void rvu_scan_block(struct rvu *rvu, struct rvu_block *block) 438 { 439 struct rvu_pfvf *pfvf; 440 u64 cfg; 441 int lf; 442 443 for (lf = 0; lf < block->lf.max; lf++) { 444 cfg = rvu_read64(rvu, block->addr, 445 block->lfcfg_reg | (lf << block->lfshift)); 446 if (!(cfg & BIT_ULL(63))) 447 continue; 448 449 /* Set this resource as being used */ 450 __set_bit(lf, block->lf.bmap); 451 452 /* Get, to whom this LF is attached */ 453 pfvf = rvu_get_pfvf(rvu, (cfg >> 8) & 0xFFFF); 454 rvu_update_rsrc_map(rvu, pfvf, block, 455 (cfg >> 8) & 0xFFFF, lf, true); 456 457 /* Set start MSIX vector for this LF within this PF/VF */ 458 rvu_set_msix_offset(rvu, pfvf, block, lf); 459 } 460 } 461 462 static void rvu_check_min_msix_vec(struct rvu *rvu, int nvecs, int pf, int vf) 463 { 464 int min_vecs; 465 466 if (!vf) 467 goto check_pf; 468 469 if (!nvecs) { 470 dev_warn(rvu->dev, 471 "PF%d:VF%d is configured with zero msix vectors, %d\n", 472 pf, vf - 1, nvecs); 473 } 474 return; 475 476 check_pf: 477 if (pf == 0) 478 min_vecs = RVU_AF_INT_VEC_CNT + RVU_PF_INT_VEC_CNT; 479 else 480 min_vecs = RVU_PF_INT_VEC_CNT; 481 482 if (!(nvecs < min_vecs)) 483 return; 484 dev_warn(rvu->dev, 485 "PF%d is configured with too few vectors, %d, min is %d\n", 486 pf, nvecs, min_vecs); 487 } 488 489 static int rvu_setup_msix_resources(struct rvu *rvu) 490 { 491 struct rvu_hwinfo *hw = rvu->hw; 492 int pf, vf, numvfs, hwvf, err; 493 int nvecs, offset, max_msix; 494 struct rvu_pfvf *pfvf; 495 u64 cfg, phy_addr; 496 dma_addr_t iova; 497 498 for (pf = 0; pf < hw->total_pfs; pf++) { 499 cfg = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_PFX_CFG(pf)); 500 /* If PF is not enabled, nothing to do */ 501 if (!((cfg >> 20) & 0x01)) 502 continue; 503 504 rvu_get_pf_numvfs(rvu, pf, &numvfs, &hwvf); 505 506 pfvf = &rvu->pf[pf]; 507 /* Get num of MSIX vectors attached to this PF */ 508 cfg = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_PFX_MSIX_CFG(pf)); 509 pfvf->msix.max = ((cfg >> 32) & 0xFFF) + 1; 510 rvu_check_min_msix_vec(rvu, pfvf->msix.max, pf, 0); 511 512 /* Alloc msix bitmap for this PF */ 513 err = rvu_alloc_bitmap(&pfvf->msix); 514 if (err) 515 return err; 516 517 /* Allocate memory for MSIX vector to RVU block LF mapping */ 518 pfvf->msix_lfmap = devm_kcalloc(rvu->dev, pfvf->msix.max, 519 sizeof(u16), GFP_KERNEL); 520 if (!pfvf->msix_lfmap) 521 return -ENOMEM; 522 523 /* For PF0 (AF) firmware will set msix vector offsets for 524 * AF, block AF and PF0_INT vectors, so jump to VFs. 525 */ 526 if (!pf) 527 goto setup_vfmsix; 528 529 /* Set MSIX offset for PF's 'RVU_PF_INT_VEC' vectors. 530 * These are allocated on driver init and never freed, 531 * so no need to set 'msix_lfmap' for these. 532 */ 533 cfg = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_PFX_INT_CFG(pf)); 534 nvecs = (cfg >> 12) & 0xFF; 535 cfg &= ~0x7FFULL; 536 offset = rvu_alloc_rsrc_contig(&pfvf->msix, nvecs); 537 rvu_write64(rvu, BLKADDR_RVUM, 538 RVU_PRIV_PFX_INT_CFG(pf), cfg | offset); 539 setup_vfmsix: 540 /* Alloc msix bitmap for VFs */ 541 for (vf = 0; vf < numvfs; vf++) { 542 pfvf = &rvu->hwvf[hwvf + vf]; 543 /* Get num of MSIX vectors attached to this VF */ 544 cfg = rvu_read64(rvu, BLKADDR_RVUM, 545 RVU_PRIV_PFX_MSIX_CFG(pf)); 546 pfvf->msix.max = (cfg & 0xFFF) + 1; 547 rvu_check_min_msix_vec(rvu, pfvf->msix.max, pf, vf + 1); 548 549 /* Alloc msix bitmap for this VF */ 550 err = rvu_alloc_bitmap(&pfvf->msix); 551 if (err) 552 return err; 553 554 pfvf->msix_lfmap = 555 devm_kcalloc(rvu->dev, pfvf->msix.max, 556 sizeof(u16), GFP_KERNEL); 557 if (!pfvf->msix_lfmap) 558 return -ENOMEM; 559 560 /* Set MSIX offset for HWVF's 'RVU_VF_INT_VEC' vectors. 561 * These are allocated on driver init and never freed, 562 * so no need to set 'msix_lfmap' for these. 563 */ 564 cfg = rvu_read64(rvu, BLKADDR_RVUM, 565 RVU_PRIV_HWVFX_INT_CFG(hwvf + vf)); 566 nvecs = (cfg >> 12) & 0xFF; 567 cfg &= ~0x7FFULL; 568 offset = rvu_alloc_rsrc_contig(&pfvf->msix, nvecs); 569 rvu_write64(rvu, BLKADDR_RVUM, 570 RVU_PRIV_HWVFX_INT_CFG(hwvf + vf), 571 cfg | offset); 572 } 573 } 574 575 /* HW interprets RVU_AF_MSIXTR_BASE address as an IOVA, hence 576 * create a IOMMU mapping for the physcial address configured by 577 * firmware and reconfig RVU_AF_MSIXTR_BASE with IOVA. 578 */ 579 cfg = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_CONST); 580 max_msix = cfg & 0xFFFFF; 581 phy_addr = rvu_read64(rvu, BLKADDR_RVUM, RVU_AF_MSIXTR_BASE); 582 iova = dma_map_resource(rvu->dev, phy_addr, 583 max_msix * PCI_MSIX_ENTRY_SIZE, 584 DMA_BIDIRECTIONAL, 0); 585 586 if (dma_mapping_error(rvu->dev, iova)) 587 return -ENOMEM; 588 589 rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_MSIXTR_BASE, (u64)iova); 590 rvu->msix_base_iova = iova; 591 592 return 0; 593 } 594 595 static void rvu_free_hw_resources(struct rvu *rvu) 596 { 597 struct rvu_hwinfo *hw = rvu->hw; 598 struct rvu_block *block; 599 struct rvu_pfvf *pfvf; 600 int id, max_msix; 601 u64 cfg; 602 603 rvu_npa_freemem(rvu); 604 rvu_npc_freemem(rvu); 605 rvu_nix_freemem(rvu); 606 607 /* Free block LF bitmaps */ 608 for (id = 0; id < BLK_COUNT; id++) { 609 block = &hw->block[id]; 610 kfree(block->lf.bmap); 611 } 612 613 /* Free MSIX bitmaps */ 614 for (id = 0; id < hw->total_pfs; id++) { 615 pfvf = &rvu->pf[id]; 616 kfree(pfvf->msix.bmap); 617 } 618 619 for (id = 0; id < hw->total_vfs; id++) { 620 pfvf = &rvu->hwvf[id]; 621 kfree(pfvf->msix.bmap); 622 } 623 624 /* Unmap MSIX vector base IOVA mapping */ 625 if (!rvu->msix_base_iova) 626 return; 627 cfg = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_CONST); 628 max_msix = cfg & 0xFFFFF; 629 dma_unmap_resource(rvu->dev, rvu->msix_base_iova, 630 max_msix * PCI_MSIX_ENTRY_SIZE, 631 DMA_BIDIRECTIONAL, 0); 632 633 mutex_destroy(&rvu->rsrc_lock); 634 } 635 636 static int rvu_setup_hw_resources(struct rvu *rvu) 637 { 638 struct rvu_hwinfo *hw = rvu->hw; 639 struct rvu_block *block; 640 int blkid, err; 641 u64 cfg; 642 643 /* Get HW supported max RVU PF & VF count */ 644 cfg = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_CONST); 645 hw->total_pfs = (cfg >> 32) & 0xFF; 646 hw->total_vfs = (cfg >> 20) & 0xFFF; 647 hw->max_vfs_per_pf = (cfg >> 40) & 0xFF; 648 649 /* Init NPA LF's bitmap */ 650 block = &hw->block[BLKADDR_NPA]; 651 if (!block->implemented) 652 goto nix; 653 cfg = rvu_read64(rvu, BLKADDR_NPA, NPA_AF_CONST); 654 block->lf.max = (cfg >> 16) & 0xFFF; 655 block->addr = BLKADDR_NPA; 656 block->type = BLKTYPE_NPA; 657 block->lfshift = 8; 658 block->lookup_reg = NPA_AF_RVU_LF_CFG_DEBUG; 659 block->pf_lfcnt_reg = RVU_PRIV_PFX_NPA_CFG; 660 block->vf_lfcnt_reg = RVU_PRIV_HWVFX_NPA_CFG; 661 block->lfcfg_reg = NPA_PRIV_LFX_CFG; 662 block->msixcfg_reg = NPA_PRIV_LFX_INT_CFG; 663 block->lfreset_reg = NPA_AF_LF_RST; 664 sprintf(block->name, "NPA"); 665 err = rvu_alloc_bitmap(&block->lf); 666 if (err) 667 return err; 668 669 nix: 670 /* Init NIX LF's bitmap */ 671 block = &hw->block[BLKADDR_NIX0]; 672 if (!block->implemented) 673 goto sso; 674 cfg = rvu_read64(rvu, BLKADDR_NIX0, NIX_AF_CONST2); 675 block->lf.max = cfg & 0xFFF; 676 block->addr = BLKADDR_NIX0; 677 block->type = BLKTYPE_NIX; 678 block->lfshift = 8; 679 block->lookup_reg = NIX_AF_RVU_LF_CFG_DEBUG; 680 block->pf_lfcnt_reg = RVU_PRIV_PFX_NIX0_CFG; 681 block->vf_lfcnt_reg = RVU_PRIV_HWVFX_NIX0_CFG; 682 block->lfcfg_reg = NIX_PRIV_LFX_CFG; 683 block->msixcfg_reg = NIX_PRIV_LFX_INT_CFG; 684 block->lfreset_reg = NIX_AF_LF_RST; 685 sprintf(block->name, "NIX"); 686 err = rvu_alloc_bitmap(&block->lf); 687 if (err) 688 return err; 689 690 sso: 691 /* Init SSO group's bitmap */ 692 block = &hw->block[BLKADDR_SSO]; 693 if (!block->implemented) 694 goto ssow; 695 cfg = rvu_read64(rvu, BLKADDR_SSO, SSO_AF_CONST); 696 block->lf.max = cfg & 0xFFFF; 697 block->addr = BLKADDR_SSO; 698 block->type = BLKTYPE_SSO; 699 block->multislot = true; 700 block->lfshift = 3; 701 block->lookup_reg = SSO_AF_RVU_LF_CFG_DEBUG; 702 block->pf_lfcnt_reg = RVU_PRIV_PFX_SSO_CFG; 703 block->vf_lfcnt_reg = RVU_PRIV_HWVFX_SSO_CFG; 704 block->lfcfg_reg = SSO_PRIV_LFX_HWGRP_CFG; 705 block->msixcfg_reg = SSO_PRIV_LFX_HWGRP_INT_CFG; 706 block->lfreset_reg = SSO_AF_LF_HWGRP_RST; 707 sprintf(block->name, "SSO GROUP"); 708 err = rvu_alloc_bitmap(&block->lf); 709 if (err) 710 return err; 711 712 ssow: 713 /* Init SSO workslot's bitmap */ 714 block = &hw->block[BLKADDR_SSOW]; 715 if (!block->implemented) 716 goto tim; 717 block->lf.max = (cfg >> 56) & 0xFF; 718 block->addr = BLKADDR_SSOW; 719 block->type = BLKTYPE_SSOW; 720 block->multislot = true; 721 block->lfshift = 3; 722 block->lookup_reg = SSOW_AF_RVU_LF_HWS_CFG_DEBUG; 723 block->pf_lfcnt_reg = RVU_PRIV_PFX_SSOW_CFG; 724 block->vf_lfcnt_reg = RVU_PRIV_HWVFX_SSOW_CFG; 725 block->lfcfg_reg = SSOW_PRIV_LFX_HWS_CFG; 726 block->msixcfg_reg = SSOW_PRIV_LFX_HWS_INT_CFG; 727 block->lfreset_reg = SSOW_AF_LF_HWS_RST; 728 sprintf(block->name, "SSOWS"); 729 err = rvu_alloc_bitmap(&block->lf); 730 if (err) 731 return err; 732 733 tim: 734 /* Init TIM LF's bitmap */ 735 block = &hw->block[BLKADDR_TIM]; 736 if (!block->implemented) 737 goto cpt; 738 cfg = rvu_read64(rvu, BLKADDR_TIM, TIM_AF_CONST); 739 block->lf.max = cfg & 0xFFFF; 740 block->addr = BLKADDR_TIM; 741 block->type = BLKTYPE_TIM; 742 block->multislot = true; 743 block->lfshift = 3; 744 block->lookup_reg = TIM_AF_RVU_LF_CFG_DEBUG; 745 block->pf_lfcnt_reg = RVU_PRIV_PFX_TIM_CFG; 746 block->vf_lfcnt_reg = RVU_PRIV_HWVFX_TIM_CFG; 747 block->lfcfg_reg = TIM_PRIV_LFX_CFG; 748 block->msixcfg_reg = TIM_PRIV_LFX_INT_CFG; 749 block->lfreset_reg = TIM_AF_LF_RST; 750 sprintf(block->name, "TIM"); 751 err = rvu_alloc_bitmap(&block->lf); 752 if (err) 753 return err; 754 755 cpt: 756 /* Init CPT LF's bitmap */ 757 block = &hw->block[BLKADDR_CPT0]; 758 if (!block->implemented) 759 goto init; 760 cfg = rvu_read64(rvu, BLKADDR_CPT0, CPT_AF_CONSTANTS0); 761 block->lf.max = cfg & 0xFF; 762 block->addr = BLKADDR_CPT0; 763 block->type = BLKTYPE_CPT; 764 block->multislot = true; 765 block->lfshift = 3; 766 block->lookup_reg = CPT_AF_RVU_LF_CFG_DEBUG; 767 block->pf_lfcnt_reg = RVU_PRIV_PFX_CPT0_CFG; 768 block->vf_lfcnt_reg = RVU_PRIV_HWVFX_CPT0_CFG; 769 block->lfcfg_reg = CPT_PRIV_LFX_CFG; 770 block->msixcfg_reg = CPT_PRIV_LFX_INT_CFG; 771 block->lfreset_reg = CPT_AF_LF_RST; 772 sprintf(block->name, "CPT"); 773 err = rvu_alloc_bitmap(&block->lf); 774 if (err) 775 return err; 776 777 init: 778 /* Allocate memory for PFVF data */ 779 rvu->pf = devm_kcalloc(rvu->dev, hw->total_pfs, 780 sizeof(struct rvu_pfvf), GFP_KERNEL); 781 if (!rvu->pf) 782 return -ENOMEM; 783 784 rvu->hwvf = devm_kcalloc(rvu->dev, hw->total_vfs, 785 sizeof(struct rvu_pfvf), GFP_KERNEL); 786 if (!rvu->hwvf) 787 return -ENOMEM; 788 789 mutex_init(&rvu->rsrc_lock); 790 791 err = rvu_setup_msix_resources(rvu); 792 if (err) 793 return err; 794 795 for (blkid = 0; blkid < BLK_COUNT; blkid++) { 796 block = &hw->block[blkid]; 797 if (!block->lf.bmap) 798 continue; 799 800 /* Allocate memory for block LF/slot to pcifunc mapping info */ 801 block->fn_map = devm_kcalloc(rvu->dev, block->lf.max, 802 sizeof(u16), GFP_KERNEL); 803 if (!block->fn_map) 804 return -ENOMEM; 805 806 /* Scan all blocks to check if low level firmware has 807 * already provisioned any of the resources to a PF/VF. 808 */ 809 rvu_scan_block(rvu, block); 810 } 811 812 err = rvu_npc_init(rvu); 813 if (err) 814 return err; 815 816 err = rvu_npa_init(rvu); 817 if (err) 818 return err; 819 820 err = rvu_nix_init(rvu); 821 if (err) 822 return err; 823 824 return 0; 825 } 826 827 /* NPA and NIX admin queue APIs */ 828 void rvu_aq_free(struct rvu *rvu, struct admin_queue *aq) 829 { 830 if (!aq) 831 return; 832 833 qmem_free(rvu->dev, aq->inst); 834 qmem_free(rvu->dev, aq->res); 835 devm_kfree(rvu->dev, aq); 836 } 837 838 int rvu_aq_alloc(struct rvu *rvu, struct admin_queue **ad_queue, 839 int qsize, int inst_size, int res_size) 840 { 841 struct admin_queue *aq; 842 int err; 843 844 *ad_queue = devm_kzalloc(rvu->dev, sizeof(*aq), GFP_KERNEL); 845 if (!*ad_queue) 846 return -ENOMEM; 847 aq = *ad_queue; 848 849 /* Alloc memory for instructions i.e AQ */ 850 err = qmem_alloc(rvu->dev, &aq->inst, qsize, inst_size); 851 if (err) { 852 devm_kfree(rvu->dev, aq); 853 return err; 854 } 855 856 /* Alloc memory for results */ 857 err = qmem_alloc(rvu->dev, &aq->res, qsize, res_size); 858 if (err) { 859 rvu_aq_free(rvu, aq); 860 return err; 861 } 862 863 spin_lock_init(&aq->lock); 864 return 0; 865 } 866 867 static int rvu_mbox_handler_ready(struct rvu *rvu, struct msg_req *req, 868 struct ready_msg_rsp *rsp) 869 { 870 return 0; 871 } 872 873 /* Get current count of a RVU block's LF/slots 874 * provisioned to a given RVU func. 875 */ 876 static u16 rvu_get_rsrc_mapcount(struct rvu_pfvf *pfvf, int blktype) 877 { 878 switch (blktype) { 879 case BLKTYPE_NPA: 880 return pfvf->npalf ? 1 : 0; 881 case BLKTYPE_NIX: 882 return pfvf->nixlf ? 1 : 0; 883 case BLKTYPE_SSO: 884 return pfvf->sso; 885 case BLKTYPE_SSOW: 886 return pfvf->ssow; 887 case BLKTYPE_TIM: 888 return pfvf->timlfs; 889 case BLKTYPE_CPT: 890 return pfvf->cptlfs; 891 } 892 return 0; 893 } 894 895 bool is_pffunc_map_valid(struct rvu *rvu, u16 pcifunc, int blktype) 896 { 897 struct rvu_pfvf *pfvf; 898 899 if (!is_pf_func_valid(rvu, pcifunc)) 900 return false; 901 902 pfvf = rvu_get_pfvf(rvu, pcifunc); 903 904 /* Check if this PFFUNC has a LF of type blktype attached */ 905 if (!rvu_get_rsrc_mapcount(pfvf, blktype)) 906 return false; 907 908 return true; 909 } 910 911 static int rvu_lookup_rsrc(struct rvu *rvu, struct rvu_block *block, 912 int pcifunc, int slot) 913 { 914 u64 val; 915 916 val = ((u64)pcifunc << 24) | (slot << 16) | (1ULL << 13); 917 rvu_write64(rvu, block->addr, block->lookup_reg, val); 918 /* Wait for the lookup to finish */ 919 /* TODO: put some timeout here */ 920 while (rvu_read64(rvu, block->addr, block->lookup_reg) & (1ULL << 13)) 921 ; 922 923 val = rvu_read64(rvu, block->addr, block->lookup_reg); 924 925 /* Check LF valid bit */ 926 if (!(val & (1ULL << 12))) 927 return -1; 928 929 return (val & 0xFFF); 930 } 931 932 static void rvu_detach_block(struct rvu *rvu, int pcifunc, int blktype) 933 { 934 struct rvu_pfvf *pfvf = rvu_get_pfvf(rvu, pcifunc); 935 struct rvu_hwinfo *hw = rvu->hw; 936 struct rvu_block *block; 937 int slot, lf, num_lfs; 938 int blkaddr; 939 940 blkaddr = rvu_get_blkaddr(rvu, blktype, pcifunc); 941 if (blkaddr < 0) 942 return; 943 944 block = &hw->block[blkaddr]; 945 946 num_lfs = rvu_get_rsrc_mapcount(pfvf, block->type); 947 if (!num_lfs) 948 return; 949 950 for (slot = 0; slot < num_lfs; slot++) { 951 lf = rvu_lookup_rsrc(rvu, block, pcifunc, slot); 952 if (lf < 0) /* This should never happen */ 953 continue; 954 955 /* Disable the LF */ 956 rvu_write64(rvu, blkaddr, block->lfcfg_reg | 957 (lf << block->lfshift), 0x00ULL); 958 959 /* Update SW maintained mapping info as well */ 960 rvu_update_rsrc_map(rvu, pfvf, block, 961 pcifunc, lf, false); 962 963 /* Free the resource */ 964 rvu_free_rsrc(&block->lf, lf); 965 966 /* Clear MSIX vector offset for this LF */ 967 rvu_clear_msix_offset(rvu, pfvf, block, lf); 968 } 969 } 970 971 static int rvu_detach_rsrcs(struct rvu *rvu, struct rsrc_detach *detach, 972 u16 pcifunc) 973 { 974 struct rvu_hwinfo *hw = rvu->hw; 975 bool detach_all = true; 976 struct rvu_block *block; 977 int blkid; 978 979 mutex_lock(&rvu->rsrc_lock); 980 981 /* Check for partial resource detach */ 982 if (detach && detach->partial) 983 detach_all = false; 984 985 /* Check for RVU block's LFs attached to this func, 986 * if so, detach them. 987 */ 988 for (blkid = 0; blkid < BLK_COUNT; blkid++) { 989 block = &hw->block[blkid]; 990 if (!block->lf.bmap) 991 continue; 992 if (!detach_all && detach) { 993 if (blkid == BLKADDR_NPA && !detach->npalf) 994 continue; 995 else if ((blkid == BLKADDR_NIX0) && !detach->nixlf) 996 continue; 997 else if ((blkid == BLKADDR_SSO) && !detach->sso) 998 continue; 999 else if ((blkid == BLKADDR_SSOW) && !detach->ssow) 1000 continue; 1001 else if ((blkid == BLKADDR_TIM) && !detach->timlfs) 1002 continue; 1003 else if ((blkid == BLKADDR_CPT0) && !detach->cptlfs) 1004 continue; 1005 } 1006 rvu_detach_block(rvu, pcifunc, block->type); 1007 } 1008 1009 mutex_unlock(&rvu->rsrc_lock); 1010 return 0; 1011 } 1012 1013 static int rvu_mbox_handler_detach_resources(struct rvu *rvu, 1014 struct rsrc_detach *detach, 1015 struct msg_rsp *rsp) 1016 { 1017 return rvu_detach_rsrcs(rvu, detach, detach->hdr.pcifunc); 1018 } 1019 1020 static void rvu_attach_block(struct rvu *rvu, int pcifunc, 1021 int blktype, int num_lfs) 1022 { 1023 struct rvu_pfvf *pfvf = rvu_get_pfvf(rvu, pcifunc); 1024 struct rvu_hwinfo *hw = rvu->hw; 1025 struct rvu_block *block; 1026 int slot, lf; 1027 int blkaddr; 1028 u64 cfg; 1029 1030 if (!num_lfs) 1031 return; 1032 1033 blkaddr = rvu_get_blkaddr(rvu, blktype, 0); 1034 if (blkaddr < 0) 1035 return; 1036 1037 block = &hw->block[blkaddr]; 1038 if (!block->lf.bmap) 1039 return; 1040 1041 for (slot = 0; slot < num_lfs; slot++) { 1042 /* Allocate the resource */ 1043 lf = rvu_alloc_rsrc(&block->lf); 1044 if (lf < 0) 1045 return; 1046 1047 cfg = (1ULL << 63) | (pcifunc << 8) | slot; 1048 rvu_write64(rvu, blkaddr, block->lfcfg_reg | 1049 (lf << block->lfshift), cfg); 1050 rvu_update_rsrc_map(rvu, pfvf, block, 1051 pcifunc, lf, true); 1052 1053 /* Set start MSIX vector for this LF within this PF/VF */ 1054 rvu_set_msix_offset(rvu, pfvf, block, lf); 1055 } 1056 } 1057 1058 static int rvu_check_rsrc_availability(struct rvu *rvu, 1059 struct rsrc_attach *req, u16 pcifunc) 1060 { 1061 struct rvu_pfvf *pfvf = rvu_get_pfvf(rvu, pcifunc); 1062 struct rvu_hwinfo *hw = rvu->hw; 1063 struct rvu_block *block; 1064 int free_lfs, mappedlfs; 1065 1066 /* Only one NPA LF can be attached */ 1067 if (req->npalf && !rvu_get_rsrc_mapcount(pfvf, BLKTYPE_NPA)) { 1068 block = &hw->block[BLKADDR_NPA]; 1069 free_lfs = rvu_rsrc_free_count(&block->lf); 1070 if (!free_lfs) 1071 goto fail; 1072 } else if (req->npalf) { 1073 dev_err(&rvu->pdev->dev, 1074 "Func 0x%x: Invalid req, already has NPA\n", 1075 pcifunc); 1076 return -EINVAL; 1077 } 1078 1079 /* Only one NIX LF can be attached */ 1080 if (req->nixlf && !rvu_get_rsrc_mapcount(pfvf, BLKTYPE_NIX)) { 1081 block = &hw->block[BLKADDR_NIX0]; 1082 free_lfs = rvu_rsrc_free_count(&block->lf); 1083 if (!free_lfs) 1084 goto fail; 1085 } else if (req->nixlf) { 1086 dev_err(&rvu->pdev->dev, 1087 "Func 0x%x: Invalid req, already has NIX\n", 1088 pcifunc); 1089 return -EINVAL; 1090 } 1091 1092 if (req->sso) { 1093 block = &hw->block[BLKADDR_SSO]; 1094 /* Is request within limits ? */ 1095 if (req->sso > block->lf.max) { 1096 dev_err(&rvu->pdev->dev, 1097 "Func 0x%x: Invalid SSO req, %d > max %d\n", 1098 pcifunc, req->sso, block->lf.max); 1099 return -EINVAL; 1100 } 1101 mappedlfs = rvu_get_rsrc_mapcount(pfvf, block->type); 1102 free_lfs = rvu_rsrc_free_count(&block->lf); 1103 /* Check if additional resources are available */ 1104 if (req->sso > mappedlfs && 1105 ((req->sso - mappedlfs) > free_lfs)) 1106 goto fail; 1107 } 1108 1109 if (req->ssow) { 1110 block = &hw->block[BLKADDR_SSOW]; 1111 if (req->ssow > block->lf.max) { 1112 dev_err(&rvu->pdev->dev, 1113 "Func 0x%x: Invalid SSOW req, %d > max %d\n", 1114 pcifunc, req->sso, block->lf.max); 1115 return -EINVAL; 1116 } 1117 mappedlfs = rvu_get_rsrc_mapcount(pfvf, block->type); 1118 free_lfs = rvu_rsrc_free_count(&block->lf); 1119 if (req->ssow > mappedlfs && 1120 ((req->ssow - mappedlfs) > free_lfs)) 1121 goto fail; 1122 } 1123 1124 if (req->timlfs) { 1125 block = &hw->block[BLKADDR_TIM]; 1126 if (req->timlfs > block->lf.max) { 1127 dev_err(&rvu->pdev->dev, 1128 "Func 0x%x: Invalid TIMLF req, %d > max %d\n", 1129 pcifunc, req->timlfs, block->lf.max); 1130 return -EINVAL; 1131 } 1132 mappedlfs = rvu_get_rsrc_mapcount(pfvf, block->type); 1133 free_lfs = rvu_rsrc_free_count(&block->lf); 1134 if (req->timlfs > mappedlfs && 1135 ((req->timlfs - mappedlfs) > free_lfs)) 1136 goto fail; 1137 } 1138 1139 if (req->cptlfs) { 1140 block = &hw->block[BLKADDR_CPT0]; 1141 if (req->cptlfs > block->lf.max) { 1142 dev_err(&rvu->pdev->dev, 1143 "Func 0x%x: Invalid CPTLF req, %d > max %d\n", 1144 pcifunc, req->cptlfs, block->lf.max); 1145 return -EINVAL; 1146 } 1147 mappedlfs = rvu_get_rsrc_mapcount(pfvf, block->type); 1148 free_lfs = rvu_rsrc_free_count(&block->lf); 1149 if (req->cptlfs > mappedlfs && 1150 ((req->cptlfs - mappedlfs) > free_lfs)) 1151 goto fail; 1152 } 1153 1154 return 0; 1155 1156 fail: 1157 dev_info(rvu->dev, "Request for %s failed\n", block->name); 1158 return -ENOSPC; 1159 } 1160 1161 static int rvu_mbox_handler_attach_resources(struct rvu *rvu, 1162 struct rsrc_attach *attach, 1163 struct msg_rsp *rsp) 1164 { 1165 u16 pcifunc = attach->hdr.pcifunc; 1166 int err; 1167 1168 /* If first request, detach all existing attached resources */ 1169 if (!attach->modify) 1170 rvu_detach_rsrcs(rvu, NULL, pcifunc); 1171 1172 mutex_lock(&rvu->rsrc_lock); 1173 1174 /* Check if the request can be accommodated */ 1175 err = rvu_check_rsrc_availability(rvu, attach, pcifunc); 1176 if (err) 1177 goto exit; 1178 1179 /* Now attach the requested resources */ 1180 if (attach->npalf) 1181 rvu_attach_block(rvu, pcifunc, BLKTYPE_NPA, 1); 1182 1183 if (attach->nixlf) 1184 rvu_attach_block(rvu, pcifunc, BLKTYPE_NIX, 1); 1185 1186 if (attach->sso) { 1187 /* RVU func doesn't know which exact LF or slot is attached 1188 * to it, it always sees as slot 0,1,2. So for a 'modify' 1189 * request, simply detach all existing attached LFs/slots 1190 * and attach a fresh. 1191 */ 1192 if (attach->modify) 1193 rvu_detach_block(rvu, pcifunc, BLKTYPE_SSO); 1194 rvu_attach_block(rvu, pcifunc, BLKTYPE_SSO, attach->sso); 1195 } 1196 1197 if (attach->ssow) { 1198 if (attach->modify) 1199 rvu_detach_block(rvu, pcifunc, BLKTYPE_SSOW); 1200 rvu_attach_block(rvu, pcifunc, BLKTYPE_SSOW, attach->ssow); 1201 } 1202 1203 if (attach->timlfs) { 1204 if (attach->modify) 1205 rvu_detach_block(rvu, pcifunc, BLKTYPE_TIM); 1206 rvu_attach_block(rvu, pcifunc, BLKTYPE_TIM, attach->timlfs); 1207 } 1208 1209 if (attach->cptlfs) { 1210 if (attach->modify) 1211 rvu_detach_block(rvu, pcifunc, BLKTYPE_CPT); 1212 rvu_attach_block(rvu, pcifunc, BLKTYPE_CPT, attach->cptlfs); 1213 } 1214 1215 exit: 1216 mutex_unlock(&rvu->rsrc_lock); 1217 return err; 1218 } 1219 1220 static u16 rvu_get_msix_offset(struct rvu *rvu, struct rvu_pfvf *pfvf, 1221 int blkaddr, int lf) 1222 { 1223 u16 vec; 1224 1225 if (lf < 0) 1226 return MSIX_VECTOR_INVALID; 1227 1228 for (vec = 0; vec < pfvf->msix.max; vec++) { 1229 if (pfvf->msix_lfmap[vec] == MSIX_BLKLF(blkaddr, lf)) 1230 return vec; 1231 } 1232 return MSIX_VECTOR_INVALID; 1233 } 1234 1235 static void rvu_set_msix_offset(struct rvu *rvu, struct rvu_pfvf *pfvf, 1236 struct rvu_block *block, int lf) 1237 { 1238 u16 nvecs, vec, offset; 1239 u64 cfg; 1240 1241 cfg = rvu_read64(rvu, block->addr, block->msixcfg_reg | 1242 (lf << block->lfshift)); 1243 nvecs = (cfg >> 12) & 0xFF; 1244 1245 /* Check and alloc MSIX vectors, must be contiguous */ 1246 if (!rvu_rsrc_check_contig(&pfvf->msix, nvecs)) 1247 return; 1248 1249 offset = rvu_alloc_rsrc_contig(&pfvf->msix, nvecs); 1250 1251 /* Config MSIX offset in LF */ 1252 rvu_write64(rvu, block->addr, block->msixcfg_reg | 1253 (lf << block->lfshift), (cfg & ~0x7FFULL) | offset); 1254 1255 /* Update the bitmap as well */ 1256 for (vec = 0; vec < nvecs; vec++) 1257 pfvf->msix_lfmap[offset + vec] = MSIX_BLKLF(block->addr, lf); 1258 } 1259 1260 static void rvu_clear_msix_offset(struct rvu *rvu, struct rvu_pfvf *pfvf, 1261 struct rvu_block *block, int lf) 1262 { 1263 u16 nvecs, vec, offset; 1264 u64 cfg; 1265 1266 cfg = rvu_read64(rvu, block->addr, block->msixcfg_reg | 1267 (lf << block->lfshift)); 1268 nvecs = (cfg >> 12) & 0xFF; 1269 1270 /* Clear MSIX offset in LF */ 1271 rvu_write64(rvu, block->addr, block->msixcfg_reg | 1272 (lf << block->lfshift), cfg & ~0x7FFULL); 1273 1274 offset = rvu_get_msix_offset(rvu, pfvf, block->addr, lf); 1275 1276 /* Update the mapping */ 1277 for (vec = 0; vec < nvecs; vec++) 1278 pfvf->msix_lfmap[offset + vec] = 0; 1279 1280 /* Free the same in MSIX bitmap */ 1281 rvu_free_rsrc_contig(&pfvf->msix, nvecs, offset); 1282 } 1283 1284 static int rvu_mbox_handler_msix_offset(struct rvu *rvu, struct msg_req *req, 1285 struct msix_offset_rsp *rsp) 1286 { 1287 struct rvu_hwinfo *hw = rvu->hw; 1288 u16 pcifunc = req->hdr.pcifunc; 1289 struct rvu_pfvf *pfvf; 1290 int lf, slot; 1291 1292 pfvf = rvu_get_pfvf(rvu, pcifunc); 1293 if (!pfvf->msix.bmap) 1294 return 0; 1295 1296 /* Set MSIX offsets for each block's LFs attached to this PF/VF */ 1297 lf = rvu_get_lf(rvu, &hw->block[BLKADDR_NPA], pcifunc, 0); 1298 rsp->npa_msixoff = rvu_get_msix_offset(rvu, pfvf, BLKADDR_NPA, lf); 1299 1300 lf = rvu_get_lf(rvu, &hw->block[BLKADDR_NIX0], pcifunc, 0); 1301 rsp->nix_msixoff = rvu_get_msix_offset(rvu, pfvf, BLKADDR_NIX0, lf); 1302 1303 rsp->sso = pfvf->sso; 1304 for (slot = 0; slot < rsp->sso; slot++) { 1305 lf = rvu_get_lf(rvu, &hw->block[BLKADDR_SSO], pcifunc, slot); 1306 rsp->sso_msixoff[slot] = 1307 rvu_get_msix_offset(rvu, pfvf, BLKADDR_SSO, lf); 1308 } 1309 1310 rsp->ssow = pfvf->ssow; 1311 for (slot = 0; slot < rsp->ssow; slot++) { 1312 lf = rvu_get_lf(rvu, &hw->block[BLKADDR_SSOW], pcifunc, slot); 1313 rsp->ssow_msixoff[slot] = 1314 rvu_get_msix_offset(rvu, pfvf, BLKADDR_SSOW, lf); 1315 } 1316 1317 rsp->timlfs = pfvf->timlfs; 1318 for (slot = 0; slot < rsp->timlfs; slot++) { 1319 lf = rvu_get_lf(rvu, &hw->block[BLKADDR_TIM], pcifunc, slot); 1320 rsp->timlf_msixoff[slot] = 1321 rvu_get_msix_offset(rvu, pfvf, BLKADDR_TIM, lf); 1322 } 1323 1324 rsp->cptlfs = pfvf->cptlfs; 1325 for (slot = 0; slot < rsp->cptlfs; slot++) { 1326 lf = rvu_get_lf(rvu, &hw->block[BLKADDR_CPT0], pcifunc, slot); 1327 rsp->cptlf_msixoff[slot] = 1328 rvu_get_msix_offset(rvu, pfvf, BLKADDR_CPT0, lf); 1329 } 1330 return 0; 1331 } 1332 1333 static int rvu_mbox_handler_vf_flr(struct rvu *rvu, struct msg_req *req, 1334 struct msg_rsp *rsp) 1335 { 1336 u16 pcifunc = req->hdr.pcifunc; 1337 u16 vf, numvfs; 1338 u64 cfg; 1339 1340 vf = pcifunc & RVU_PFVF_FUNC_MASK; 1341 cfg = rvu_read64(rvu, BLKADDR_RVUM, 1342 RVU_PRIV_PFX_CFG(rvu_get_pf(pcifunc))); 1343 numvfs = (cfg >> 12) & 0xFF; 1344 1345 if (vf && vf <= numvfs) 1346 __rvu_flr_handler(rvu, pcifunc); 1347 else 1348 return RVU_INVALID_VF_ID; 1349 1350 return 0; 1351 } 1352 1353 static int rvu_process_mbox_msg(struct otx2_mbox *mbox, int devid, 1354 struct mbox_msghdr *req) 1355 { 1356 struct rvu *rvu = pci_get_drvdata(mbox->pdev); 1357 1358 /* Check if valid, if not reply with a invalid msg */ 1359 if (req->sig != OTX2_MBOX_REQ_SIG) 1360 goto bad_message; 1361 1362 switch (req->id) { 1363 #define M(_name, _id, _fn_name, _req_type, _rsp_type) \ 1364 case _id: { \ 1365 struct _rsp_type *rsp; \ 1366 int err; \ 1367 \ 1368 rsp = (struct _rsp_type *)otx2_mbox_alloc_msg( \ 1369 mbox, devid, \ 1370 sizeof(struct _rsp_type)); \ 1371 /* some handlers should complete even if reply */ \ 1372 /* could not be allocated */ \ 1373 if (!rsp && \ 1374 _id != MBOX_MSG_DETACH_RESOURCES && \ 1375 _id != MBOX_MSG_NIX_TXSCH_FREE && \ 1376 _id != MBOX_MSG_VF_FLR) \ 1377 return -ENOMEM; \ 1378 if (rsp) { \ 1379 rsp->hdr.id = _id; \ 1380 rsp->hdr.sig = OTX2_MBOX_RSP_SIG; \ 1381 rsp->hdr.pcifunc = req->pcifunc; \ 1382 rsp->hdr.rc = 0; \ 1383 } \ 1384 \ 1385 err = rvu_mbox_handler_ ## _fn_name(rvu, \ 1386 (struct _req_type *)req, \ 1387 rsp); \ 1388 if (rsp && err) \ 1389 rsp->hdr.rc = err; \ 1390 \ 1391 return rsp ? err : -ENOMEM; \ 1392 } 1393 MBOX_MESSAGES 1394 #undef M 1395 1396 bad_message: 1397 default: 1398 otx2_reply_invalid_msg(mbox, devid, req->pcifunc, req->id); 1399 return -ENODEV; 1400 } 1401 } 1402 1403 static void __rvu_mbox_handler(struct rvu_work *mwork, int type) 1404 { 1405 struct rvu *rvu = mwork->rvu; 1406 int offset, err, id, devid; 1407 struct otx2_mbox_dev *mdev; 1408 struct mbox_hdr *req_hdr; 1409 struct mbox_msghdr *msg; 1410 struct mbox_wq_info *mw; 1411 struct otx2_mbox *mbox; 1412 1413 switch (type) { 1414 case TYPE_AFPF: 1415 mw = &rvu->afpf_wq_info; 1416 break; 1417 case TYPE_AFVF: 1418 mw = &rvu->afvf_wq_info; 1419 break; 1420 default: 1421 return; 1422 } 1423 1424 devid = mwork - mw->mbox_wrk; 1425 mbox = &mw->mbox; 1426 mdev = &mbox->dev[devid]; 1427 1428 /* Process received mbox messages */ 1429 req_hdr = mdev->mbase + mbox->rx_start; 1430 if (req_hdr->num_msgs == 0) 1431 return; 1432 1433 offset = mbox->rx_start + ALIGN(sizeof(*req_hdr), MBOX_MSG_ALIGN); 1434 1435 for (id = 0; id < req_hdr->num_msgs; id++) { 1436 msg = mdev->mbase + offset; 1437 1438 /* Set which PF/VF sent this message based on mbox IRQ */ 1439 switch (type) { 1440 case TYPE_AFPF: 1441 msg->pcifunc &= 1442 ~(RVU_PFVF_PF_MASK << RVU_PFVF_PF_SHIFT); 1443 msg->pcifunc |= (devid << RVU_PFVF_PF_SHIFT); 1444 break; 1445 case TYPE_AFVF: 1446 msg->pcifunc &= 1447 ~(RVU_PFVF_FUNC_MASK << RVU_PFVF_FUNC_SHIFT); 1448 msg->pcifunc |= (devid << RVU_PFVF_FUNC_SHIFT) + 1; 1449 break; 1450 } 1451 1452 err = rvu_process_mbox_msg(mbox, devid, msg); 1453 if (!err) { 1454 offset = mbox->rx_start + msg->next_msgoff; 1455 continue; 1456 } 1457 1458 if (msg->pcifunc & RVU_PFVF_FUNC_MASK) 1459 dev_warn(rvu->dev, "Error %d when processing message %s (0x%x) from PF%d:VF%d\n", 1460 err, otx2_mbox_id2name(msg->id), 1461 msg->id, devid, 1462 (msg->pcifunc & RVU_PFVF_FUNC_MASK) - 1); 1463 else 1464 dev_warn(rvu->dev, "Error %d when processing message %s (0x%x) from PF%d\n", 1465 err, otx2_mbox_id2name(msg->id), 1466 msg->id, devid); 1467 } 1468 1469 /* Send mbox responses to VF/PF */ 1470 otx2_mbox_msg_send(mbox, devid); 1471 } 1472 1473 static inline void rvu_afpf_mbox_handler(struct work_struct *work) 1474 { 1475 struct rvu_work *mwork = container_of(work, struct rvu_work, work); 1476 1477 __rvu_mbox_handler(mwork, TYPE_AFPF); 1478 } 1479 1480 static inline void rvu_afvf_mbox_handler(struct work_struct *work) 1481 { 1482 struct rvu_work *mwork = container_of(work, struct rvu_work, work); 1483 1484 __rvu_mbox_handler(mwork, TYPE_AFVF); 1485 } 1486 1487 static void __rvu_mbox_up_handler(struct rvu_work *mwork, int type) 1488 { 1489 struct rvu *rvu = mwork->rvu; 1490 struct otx2_mbox_dev *mdev; 1491 struct mbox_hdr *rsp_hdr; 1492 struct mbox_msghdr *msg; 1493 struct mbox_wq_info *mw; 1494 struct otx2_mbox *mbox; 1495 int offset, id, devid; 1496 1497 switch (type) { 1498 case TYPE_AFPF: 1499 mw = &rvu->afpf_wq_info; 1500 break; 1501 case TYPE_AFVF: 1502 mw = &rvu->afvf_wq_info; 1503 break; 1504 default: 1505 return; 1506 } 1507 1508 devid = mwork - mw->mbox_wrk_up; 1509 mbox = &mw->mbox_up; 1510 mdev = &mbox->dev[devid]; 1511 1512 rsp_hdr = mdev->mbase + mbox->rx_start; 1513 if (rsp_hdr->num_msgs == 0) { 1514 dev_warn(rvu->dev, "mbox up handler: num_msgs = 0\n"); 1515 return; 1516 } 1517 1518 offset = mbox->rx_start + ALIGN(sizeof(*rsp_hdr), MBOX_MSG_ALIGN); 1519 1520 for (id = 0; id < rsp_hdr->num_msgs; id++) { 1521 msg = mdev->mbase + offset; 1522 1523 if (msg->id >= MBOX_MSG_MAX) { 1524 dev_err(rvu->dev, 1525 "Mbox msg with unknown ID 0x%x\n", msg->id); 1526 goto end; 1527 } 1528 1529 if (msg->sig != OTX2_MBOX_RSP_SIG) { 1530 dev_err(rvu->dev, 1531 "Mbox msg with wrong signature %x, ID 0x%x\n", 1532 msg->sig, msg->id); 1533 goto end; 1534 } 1535 1536 switch (msg->id) { 1537 case MBOX_MSG_CGX_LINK_EVENT: 1538 break; 1539 default: 1540 if (msg->rc) 1541 dev_err(rvu->dev, 1542 "Mbox msg response has err %d, ID 0x%x\n", 1543 msg->rc, msg->id); 1544 break; 1545 } 1546 end: 1547 offset = mbox->rx_start + msg->next_msgoff; 1548 mdev->msgs_acked++; 1549 } 1550 1551 otx2_mbox_reset(mbox, devid); 1552 } 1553 1554 static inline void rvu_afpf_mbox_up_handler(struct work_struct *work) 1555 { 1556 struct rvu_work *mwork = container_of(work, struct rvu_work, work); 1557 1558 __rvu_mbox_up_handler(mwork, TYPE_AFPF); 1559 } 1560 1561 static inline void rvu_afvf_mbox_up_handler(struct work_struct *work) 1562 { 1563 struct rvu_work *mwork = container_of(work, struct rvu_work, work); 1564 1565 __rvu_mbox_up_handler(mwork, TYPE_AFVF); 1566 } 1567 1568 static int rvu_mbox_init(struct rvu *rvu, struct mbox_wq_info *mw, 1569 int type, int num, 1570 void (mbox_handler)(struct work_struct *), 1571 void (mbox_up_handler)(struct work_struct *)) 1572 { 1573 void __iomem *hwbase = NULL, *reg_base; 1574 int err, i, dir, dir_up; 1575 struct rvu_work *mwork; 1576 const char *name; 1577 u64 bar4_addr; 1578 1579 switch (type) { 1580 case TYPE_AFPF: 1581 name = "rvu_afpf_mailbox"; 1582 bar4_addr = rvu_read64(rvu, BLKADDR_RVUM, RVU_AF_PF_BAR4_ADDR); 1583 dir = MBOX_DIR_AFPF; 1584 dir_up = MBOX_DIR_AFPF_UP; 1585 reg_base = rvu->afreg_base; 1586 break; 1587 case TYPE_AFVF: 1588 name = "rvu_afvf_mailbox"; 1589 bar4_addr = rvupf_read64(rvu, RVU_PF_VF_BAR4_ADDR); 1590 dir = MBOX_DIR_PFVF; 1591 dir_up = MBOX_DIR_PFVF_UP; 1592 reg_base = rvu->pfreg_base; 1593 break; 1594 default: 1595 return -EINVAL; 1596 } 1597 1598 mw->mbox_wq = alloc_workqueue(name, 1599 WQ_UNBOUND | WQ_HIGHPRI | WQ_MEM_RECLAIM, 1600 num); 1601 if (!mw->mbox_wq) 1602 return -ENOMEM; 1603 1604 mw->mbox_wrk = devm_kcalloc(rvu->dev, num, 1605 sizeof(struct rvu_work), GFP_KERNEL); 1606 if (!mw->mbox_wrk) { 1607 err = -ENOMEM; 1608 goto exit; 1609 } 1610 1611 mw->mbox_wrk_up = devm_kcalloc(rvu->dev, num, 1612 sizeof(struct rvu_work), GFP_KERNEL); 1613 if (!mw->mbox_wrk_up) { 1614 err = -ENOMEM; 1615 goto exit; 1616 } 1617 1618 /* Mailbox is a reserved memory (in RAM) region shared between 1619 * RVU devices, shouldn't be mapped as device memory to allow 1620 * unaligned accesses. 1621 */ 1622 hwbase = ioremap_wc(bar4_addr, MBOX_SIZE * num); 1623 if (!hwbase) { 1624 dev_err(rvu->dev, "Unable to map mailbox region\n"); 1625 err = -ENOMEM; 1626 goto exit; 1627 } 1628 1629 err = otx2_mbox_init(&mw->mbox, hwbase, rvu->pdev, reg_base, dir, num); 1630 if (err) 1631 goto exit; 1632 1633 err = otx2_mbox_init(&mw->mbox_up, hwbase, rvu->pdev, 1634 reg_base, dir_up, num); 1635 if (err) 1636 goto exit; 1637 1638 for (i = 0; i < num; i++) { 1639 mwork = &mw->mbox_wrk[i]; 1640 mwork->rvu = rvu; 1641 INIT_WORK(&mwork->work, mbox_handler); 1642 1643 mwork = &mw->mbox_wrk_up[i]; 1644 mwork->rvu = rvu; 1645 INIT_WORK(&mwork->work, mbox_up_handler); 1646 } 1647 1648 return 0; 1649 exit: 1650 if (hwbase) 1651 iounmap((void __iomem *)hwbase); 1652 destroy_workqueue(mw->mbox_wq); 1653 return err; 1654 } 1655 1656 static void rvu_mbox_destroy(struct mbox_wq_info *mw) 1657 { 1658 if (mw->mbox_wq) { 1659 flush_workqueue(mw->mbox_wq); 1660 destroy_workqueue(mw->mbox_wq); 1661 mw->mbox_wq = NULL; 1662 } 1663 1664 if (mw->mbox.hwbase) 1665 iounmap((void __iomem *)mw->mbox.hwbase); 1666 1667 otx2_mbox_destroy(&mw->mbox); 1668 otx2_mbox_destroy(&mw->mbox_up); 1669 } 1670 1671 static void rvu_queue_work(struct mbox_wq_info *mw, int first, 1672 int mdevs, u64 intr) 1673 { 1674 struct otx2_mbox_dev *mdev; 1675 struct otx2_mbox *mbox; 1676 struct mbox_hdr *hdr; 1677 int i; 1678 1679 for (i = first; i < mdevs; i++) { 1680 /* start from 0 */ 1681 if (!(intr & BIT_ULL(i - first))) 1682 continue; 1683 1684 mbox = &mw->mbox; 1685 mdev = &mbox->dev[i]; 1686 hdr = mdev->mbase + mbox->rx_start; 1687 if (hdr->num_msgs) 1688 queue_work(mw->mbox_wq, &mw->mbox_wrk[i].work); 1689 1690 mbox = &mw->mbox_up; 1691 mdev = &mbox->dev[i]; 1692 hdr = mdev->mbase + mbox->rx_start; 1693 if (hdr->num_msgs) 1694 queue_work(mw->mbox_wq, &mw->mbox_wrk_up[i].work); 1695 } 1696 } 1697 1698 static irqreturn_t rvu_mbox_intr_handler(int irq, void *rvu_irq) 1699 { 1700 struct rvu *rvu = (struct rvu *)rvu_irq; 1701 int vfs = rvu->vfs; 1702 u64 intr; 1703 1704 intr = rvu_read64(rvu, BLKADDR_RVUM, RVU_AF_PFAF_MBOX_INT); 1705 /* Clear interrupts */ 1706 rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_PFAF_MBOX_INT, intr); 1707 1708 /* Sync with mbox memory region */ 1709 rmb(); 1710 1711 rvu_queue_work(&rvu->afpf_wq_info, 0, rvu->hw->total_pfs, intr); 1712 1713 /* Handle VF interrupts */ 1714 if (vfs > 64) { 1715 intr = rvupf_read64(rvu, RVU_PF_VFPF_MBOX_INTX(1)); 1716 rvupf_write64(rvu, RVU_PF_VFPF_MBOX_INTX(1), intr); 1717 1718 rvu_queue_work(&rvu->afvf_wq_info, 64, vfs, intr); 1719 vfs -= 64; 1720 } 1721 1722 intr = rvupf_read64(rvu, RVU_PF_VFPF_MBOX_INTX(0)); 1723 rvupf_write64(rvu, RVU_PF_VFPF_MBOX_INTX(0), intr); 1724 1725 rvu_queue_work(&rvu->afvf_wq_info, 0, vfs, intr); 1726 1727 return IRQ_HANDLED; 1728 } 1729 1730 static void rvu_enable_mbox_intr(struct rvu *rvu) 1731 { 1732 struct rvu_hwinfo *hw = rvu->hw; 1733 1734 /* Clear spurious irqs, if any */ 1735 rvu_write64(rvu, BLKADDR_RVUM, 1736 RVU_AF_PFAF_MBOX_INT, INTR_MASK(hw->total_pfs)); 1737 1738 /* Enable mailbox interrupt for all PFs except PF0 i.e AF itself */ 1739 rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_PFAF_MBOX_INT_ENA_W1S, 1740 INTR_MASK(hw->total_pfs) & ~1ULL); 1741 } 1742 1743 static void rvu_blklf_teardown(struct rvu *rvu, u16 pcifunc, u8 blkaddr) 1744 { 1745 struct rvu_block *block; 1746 int slot, lf, num_lfs; 1747 int err; 1748 1749 block = &rvu->hw->block[blkaddr]; 1750 num_lfs = rvu_get_rsrc_mapcount(rvu_get_pfvf(rvu, pcifunc), 1751 block->type); 1752 if (!num_lfs) 1753 return; 1754 for (slot = 0; slot < num_lfs; slot++) { 1755 lf = rvu_get_lf(rvu, block, pcifunc, slot); 1756 if (lf < 0) 1757 continue; 1758 1759 /* Cleanup LF and reset it */ 1760 if (block->addr == BLKADDR_NIX0) 1761 rvu_nix_lf_teardown(rvu, pcifunc, block->addr, lf); 1762 else if (block->addr == BLKADDR_NPA) 1763 rvu_npa_lf_teardown(rvu, pcifunc, lf); 1764 1765 err = rvu_lf_reset(rvu, block, lf); 1766 if (err) { 1767 dev_err(rvu->dev, "Failed to reset blkaddr %d LF%d\n", 1768 block->addr, lf); 1769 } 1770 } 1771 } 1772 1773 static void __rvu_flr_handler(struct rvu *rvu, u16 pcifunc) 1774 { 1775 mutex_lock(&rvu->flr_lock); 1776 /* Reset order should reflect inter-block dependencies: 1777 * 1. Reset any packet/work sources (NIX, CPT, TIM) 1778 * 2. Flush and reset SSO/SSOW 1779 * 3. Cleanup pools (NPA) 1780 */ 1781 rvu_blklf_teardown(rvu, pcifunc, BLKADDR_NIX0); 1782 rvu_blklf_teardown(rvu, pcifunc, BLKADDR_CPT0); 1783 rvu_blklf_teardown(rvu, pcifunc, BLKADDR_TIM); 1784 rvu_blklf_teardown(rvu, pcifunc, BLKADDR_SSOW); 1785 rvu_blklf_teardown(rvu, pcifunc, BLKADDR_SSO); 1786 rvu_blklf_teardown(rvu, pcifunc, BLKADDR_NPA); 1787 rvu_detach_rsrcs(rvu, NULL, pcifunc); 1788 mutex_unlock(&rvu->flr_lock); 1789 } 1790 1791 static void rvu_afvf_flr_handler(struct rvu *rvu, int vf) 1792 { 1793 int reg = 0; 1794 1795 /* pcifunc = 0(PF0) | (vf + 1) */ 1796 __rvu_flr_handler(rvu, vf + 1); 1797 1798 if (vf >= 64) { 1799 reg = 1; 1800 vf = vf - 64; 1801 } 1802 1803 /* Signal FLR finish and enable IRQ */ 1804 rvupf_write64(rvu, RVU_PF_VFTRPENDX(reg), BIT_ULL(vf)); 1805 rvupf_write64(rvu, RVU_PF_VFFLR_INT_ENA_W1SX(reg), BIT_ULL(vf)); 1806 } 1807 1808 static void rvu_flr_handler(struct work_struct *work) 1809 { 1810 struct rvu_work *flrwork = container_of(work, struct rvu_work, work); 1811 struct rvu *rvu = flrwork->rvu; 1812 u16 pcifunc, numvfs, vf; 1813 u64 cfg; 1814 int pf; 1815 1816 pf = flrwork - rvu->flr_wrk; 1817 if (pf >= rvu->hw->total_pfs) { 1818 rvu_afvf_flr_handler(rvu, pf - rvu->hw->total_pfs); 1819 return; 1820 } 1821 1822 cfg = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_PFX_CFG(pf)); 1823 numvfs = (cfg >> 12) & 0xFF; 1824 pcifunc = pf << RVU_PFVF_PF_SHIFT; 1825 1826 for (vf = 0; vf < numvfs; vf++) 1827 __rvu_flr_handler(rvu, (pcifunc | (vf + 1))); 1828 1829 __rvu_flr_handler(rvu, pcifunc); 1830 1831 /* Signal FLR finish */ 1832 rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_PFTRPEND, BIT_ULL(pf)); 1833 1834 /* Enable interrupt */ 1835 rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_PFFLR_INT_ENA_W1S, BIT_ULL(pf)); 1836 } 1837 1838 static void rvu_afvf_queue_flr_work(struct rvu *rvu, int start_vf, int numvfs) 1839 { 1840 int dev, vf, reg = 0; 1841 u64 intr; 1842 1843 if (start_vf >= 64) 1844 reg = 1; 1845 1846 intr = rvupf_read64(rvu, RVU_PF_VFFLR_INTX(reg)); 1847 if (!intr) 1848 return; 1849 1850 for (vf = 0; vf < numvfs; vf++) { 1851 if (!(intr & BIT_ULL(vf))) 1852 continue; 1853 dev = vf + start_vf + rvu->hw->total_pfs; 1854 queue_work(rvu->flr_wq, &rvu->flr_wrk[dev].work); 1855 /* Clear and disable the interrupt */ 1856 rvupf_write64(rvu, RVU_PF_VFFLR_INTX(reg), BIT_ULL(vf)); 1857 rvupf_write64(rvu, RVU_PF_VFFLR_INT_ENA_W1CX(reg), BIT_ULL(vf)); 1858 } 1859 } 1860 1861 static irqreturn_t rvu_flr_intr_handler(int irq, void *rvu_irq) 1862 { 1863 struct rvu *rvu = (struct rvu *)rvu_irq; 1864 u64 intr; 1865 u8 pf; 1866 1867 intr = rvu_read64(rvu, BLKADDR_RVUM, RVU_AF_PFFLR_INT); 1868 if (!intr) 1869 goto afvf_flr; 1870 1871 for (pf = 0; pf < rvu->hw->total_pfs; pf++) { 1872 if (intr & (1ULL << pf)) { 1873 /* PF is already dead do only AF related operations */ 1874 queue_work(rvu->flr_wq, &rvu->flr_wrk[pf].work); 1875 /* clear interrupt */ 1876 rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_PFFLR_INT, 1877 BIT_ULL(pf)); 1878 /* Disable the interrupt */ 1879 rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_PFFLR_INT_ENA_W1C, 1880 BIT_ULL(pf)); 1881 } 1882 } 1883 1884 afvf_flr: 1885 rvu_afvf_queue_flr_work(rvu, 0, 64); 1886 if (rvu->vfs > 64) 1887 rvu_afvf_queue_flr_work(rvu, 64, rvu->vfs - 64); 1888 1889 return IRQ_HANDLED; 1890 } 1891 1892 static void rvu_me_handle_vfset(struct rvu *rvu, int idx, u64 intr) 1893 { 1894 int vf; 1895 1896 /* Nothing to be done here other than clearing the 1897 * TRPEND bit. 1898 */ 1899 for (vf = 0; vf < 64; vf++) { 1900 if (intr & (1ULL << vf)) { 1901 /* clear the trpend due to ME(master enable) */ 1902 rvupf_write64(rvu, RVU_PF_VFTRPENDX(idx), BIT_ULL(vf)); 1903 /* clear interrupt */ 1904 rvupf_write64(rvu, RVU_PF_VFME_INTX(idx), BIT_ULL(vf)); 1905 } 1906 } 1907 } 1908 1909 /* Handles ME interrupts from VFs of AF */ 1910 static irqreturn_t rvu_me_vf_intr_handler(int irq, void *rvu_irq) 1911 { 1912 struct rvu *rvu = (struct rvu *)rvu_irq; 1913 int vfset; 1914 u64 intr; 1915 1916 intr = rvu_read64(rvu, BLKADDR_RVUM, RVU_AF_PFME_INT); 1917 1918 for (vfset = 0; vfset <= 1; vfset++) { 1919 intr = rvupf_read64(rvu, RVU_PF_VFME_INTX(vfset)); 1920 if (intr) 1921 rvu_me_handle_vfset(rvu, vfset, intr); 1922 } 1923 1924 return IRQ_HANDLED; 1925 } 1926 1927 /* Handles ME interrupts from PFs */ 1928 static irqreturn_t rvu_me_pf_intr_handler(int irq, void *rvu_irq) 1929 { 1930 struct rvu *rvu = (struct rvu *)rvu_irq; 1931 u64 intr; 1932 u8 pf; 1933 1934 intr = rvu_read64(rvu, BLKADDR_RVUM, RVU_AF_PFME_INT); 1935 1936 /* Nothing to be done here other than clearing the 1937 * TRPEND bit. 1938 */ 1939 for (pf = 0; pf < rvu->hw->total_pfs; pf++) { 1940 if (intr & (1ULL << pf)) { 1941 /* clear the trpend due to ME(master enable) */ 1942 rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_PFTRPEND, 1943 BIT_ULL(pf)); 1944 /* clear interrupt */ 1945 rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_PFME_INT, 1946 BIT_ULL(pf)); 1947 } 1948 } 1949 1950 return IRQ_HANDLED; 1951 } 1952 1953 static void rvu_unregister_interrupts(struct rvu *rvu) 1954 { 1955 int irq; 1956 1957 /* Disable the Mbox interrupt */ 1958 rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_PFAF_MBOX_INT_ENA_W1C, 1959 INTR_MASK(rvu->hw->total_pfs) & ~1ULL); 1960 1961 /* Disable the PF FLR interrupt */ 1962 rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_PFFLR_INT_ENA_W1C, 1963 INTR_MASK(rvu->hw->total_pfs) & ~1ULL); 1964 1965 /* Disable the PF ME interrupt */ 1966 rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_PFME_INT_ENA_W1C, 1967 INTR_MASK(rvu->hw->total_pfs) & ~1ULL); 1968 1969 for (irq = 0; irq < rvu->num_vec; irq++) { 1970 if (rvu->irq_allocated[irq]) 1971 free_irq(pci_irq_vector(rvu->pdev, irq), rvu); 1972 } 1973 1974 pci_free_irq_vectors(rvu->pdev); 1975 rvu->num_vec = 0; 1976 } 1977 1978 static int rvu_afvf_msix_vectors_num_ok(struct rvu *rvu) 1979 { 1980 struct rvu_pfvf *pfvf = &rvu->pf[0]; 1981 int offset; 1982 1983 pfvf = &rvu->pf[0]; 1984 offset = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_PFX_INT_CFG(0)) & 0x3ff; 1985 1986 /* Make sure there are enough MSIX vectors configured so that 1987 * VF interrupts can be handled. Offset equal to zero means 1988 * that PF vectors are not configured and overlapping AF vectors. 1989 */ 1990 return (pfvf->msix.max >= RVU_AF_INT_VEC_CNT + RVU_PF_INT_VEC_CNT) && 1991 offset; 1992 } 1993 1994 static int rvu_register_interrupts(struct rvu *rvu) 1995 { 1996 int ret, offset, pf_vec_start; 1997 1998 rvu->num_vec = pci_msix_vec_count(rvu->pdev); 1999 2000 rvu->irq_name = devm_kmalloc_array(rvu->dev, rvu->num_vec, 2001 NAME_SIZE, GFP_KERNEL); 2002 if (!rvu->irq_name) 2003 return -ENOMEM; 2004 2005 rvu->irq_allocated = devm_kcalloc(rvu->dev, rvu->num_vec, 2006 sizeof(bool), GFP_KERNEL); 2007 if (!rvu->irq_allocated) 2008 return -ENOMEM; 2009 2010 /* Enable MSI-X */ 2011 ret = pci_alloc_irq_vectors(rvu->pdev, rvu->num_vec, 2012 rvu->num_vec, PCI_IRQ_MSIX); 2013 if (ret < 0) { 2014 dev_err(rvu->dev, 2015 "RVUAF: Request for %d msix vectors failed, ret %d\n", 2016 rvu->num_vec, ret); 2017 return ret; 2018 } 2019 2020 /* Register mailbox interrupt handler */ 2021 sprintf(&rvu->irq_name[RVU_AF_INT_VEC_MBOX * NAME_SIZE], "RVUAF Mbox"); 2022 ret = request_irq(pci_irq_vector(rvu->pdev, RVU_AF_INT_VEC_MBOX), 2023 rvu_mbox_intr_handler, 0, 2024 &rvu->irq_name[RVU_AF_INT_VEC_MBOX * NAME_SIZE], rvu); 2025 if (ret) { 2026 dev_err(rvu->dev, 2027 "RVUAF: IRQ registration failed for mbox irq\n"); 2028 goto fail; 2029 } 2030 2031 rvu->irq_allocated[RVU_AF_INT_VEC_MBOX] = true; 2032 2033 /* Enable mailbox interrupts from all PFs */ 2034 rvu_enable_mbox_intr(rvu); 2035 2036 /* Register FLR interrupt handler */ 2037 sprintf(&rvu->irq_name[RVU_AF_INT_VEC_PFFLR * NAME_SIZE], 2038 "RVUAF FLR"); 2039 ret = request_irq(pci_irq_vector(rvu->pdev, RVU_AF_INT_VEC_PFFLR), 2040 rvu_flr_intr_handler, 0, 2041 &rvu->irq_name[RVU_AF_INT_VEC_PFFLR * NAME_SIZE], 2042 rvu); 2043 if (ret) { 2044 dev_err(rvu->dev, 2045 "RVUAF: IRQ registration failed for FLR\n"); 2046 goto fail; 2047 } 2048 rvu->irq_allocated[RVU_AF_INT_VEC_PFFLR] = true; 2049 2050 /* Enable FLR interrupt for all PFs*/ 2051 rvu_write64(rvu, BLKADDR_RVUM, 2052 RVU_AF_PFFLR_INT, INTR_MASK(rvu->hw->total_pfs)); 2053 2054 rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_PFFLR_INT_ENA_W1S, 2055 INTR_MASK(rvu->hw->total_pfs) & ~1ULL); 2056 2057 /* Register ME interrupt handler */ 2058 sprintf(&rvu->irq_name[RVU_AF_INT_VEC_PFME * NAME_SIZE], 2059 "RVUAF ME"); 2060 ret = request_irq(pci_irq_vector(rvu->pdev, RVU_AF_INT_VEC_PFME), 2061 rvu_me_pf_intr_handler, 0, 2062 &rvu->irq_name[RVU_AF_INT_VEC_PFME * NAME_SIZE], 2063 rvu); 2064 if (ret) { 2065 dev_err(rvu->dev, 2066 "RVUAF: IRQ registration failed for ME\n"); 2067 } 2068 rvu->irq_allocated[RVU_AF_INT_VEC_PFME] = true; 2069 2070 /* Enable ME interrupt for all PFs*/ 2071 rvu_write64(rvu, BLKADDR_RVUM, 2072 RVU_AF_PFME_INT, INTR_MASK(rvu->hw->total_pfs)); 2073 2074 rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_PFME_INT_ENA_W1S, 2075 INTR_MASK(rvu->hw->total_pfs) & ~1ULL); 2076 2077 if (!rvu_afvf_msix_vectors_num_ok(rvu)) 2078 return 0; 2079 2080 /* Get PF MSIX vectors offset. */ 2081 pf_vec_start = rvu_read64(rvu, BLKADDR_RVUM, 2082 RVU_PRIV_PFX_INT_CFG(0)) & 0x3ff; 2083 2084 /* Register MBOX0 interrupt. */ 2085 offset = pf_vec_start + RVU_PF_INT_VEC_VFPF_MBOX0; 2086 sprintf(&rvu->irq_name[offset * NAME_SIZE], "RVUAFVF Mbox0"); 2087 ret = request_irq(pci_irq_vector(rvu->pdev, offset), 2088 rvu_mbox_intr_handler, 0, 2089 &rvu->irq_name[offset * NAME_SIZE], 2090 rvu); 2091 if (ret) 2092 dev_err(rvu->dev, 2093 "RVUAF: IRQ registration failed for Mbox0\n"); 2094 2095 rvu->irq_allocated[offset] = true; 2096 2097 /* Register MBOX1 interrupt. MBOX1 IRQ number follows MBOX0 so 2098 * simply increment current offset by 1. 2099 */ 2100 offset = pf_vec_start + RVU_PF_INT_VEC_VFPF_MBOX1; 2101 sprintf(&rvu->irq_name[offset * NAME_SIZE], "RVUAFVF Mbox1"); 2102 ret = request_irq(pci_irq_vector(rvu->pdev, offset), 2103 rvu_mbox_intr_handler, 0, 2104 &rvu->irq_name[offset * NAME_SIZE], 2105 rvu); 2106 if (ret) 2107 dev_err(rvu->dev, 2108 "RVUAF: IRQ registration failed for Mbox1\n"); 2109 2110 rvu->irq_allocated[offset] = true; 2111 2112 /* Register FLR interrupt handler for AF's VFs */ 2113 offset = pf_vec_start + RVU_PF_INT_VEC_VFFLR0; 2114 sprintf(&rvu->irq_name[offset * NAME_SIZE], "RVUAFVF FLR0"); 2115 ret = request_irq(pci_irq_vector(rvu->pdev, offset), 2116 rvu_flr_intr_handler, 0, 2117 &rvu->irq_name[offset * NAME_SIZE], rvu); 2118 if (ret) { 2119 dev_err(rvu->dev, 2120 "RVUAF: IRQ registration failed for RVUAFVF FLR0\n"); 2121 goto fail; 2122 } 2123 rvu->irq_allocated[offset] = true; 2124 2125 offset = pf_vec_start + RVU_PF_INT_VEC_VFFLR1; 2126 sprintf(&rvu->irq_name[offset * NAME_SIZE], "RVUAFVF FLR1"); 2127 ret = request_irq(pci_irq_vector(rvu->pdev, offset), 2128 rvu_flr_intr_handler, 0, 2129 &rvu->irq_name[offset * NAME_SIZE], rvu); 2130 if (ret) { 2131 dev_err(rvu->dev, 2132 "RVUAF: IRQ registration failed for RVUAFVF FLR1\n"); 2133 goto fail; 2134 } 2135 rvu->irq_allocated[offset] = true; 2136 2137 /* Register ME interrupt handler for AF's VFs */ 2138 offset = pf_vec_start + RVU_PF_INT_VEC_VFME0; 2139 sprintf(&rvu->irq_name[offset * NAME_SIZE], "RVUAFVF ME0"); 2140 ret = request_irq(pci_irq_vector(rvu->pdev, offset), 2141 rvu_me_vf_intr_handler, 0, 2142 &rvu->irq_name[offset * NAME_SIZE], rvu); 2143 if (ret) { 2144 dev_err(rvu->dev, 2145 "RVUAF: IRQ registration failed for RVUAFVF ME0\n"); 2146 goto fail; 2147 } 2148 rvu->irq_allocated[offset] = true; 2149 2150 offset = pf_vec_start + RVU_PF_INT_VEC_VFME1; 2151 sprintf(&rvu->irq_name[offset * NAME_SIZE], "RVUAFVF ME1"); 2152 ret = request_irq(pci_irq_vector(rvu->pdev, offset), 2153 rvu_me_vf_intr_handler, 0, 2154 &rvu->irq_name[offset * NAME_SIZE], rvu); 2155 if (ret) { 2156 dev_err(rvu->dev, 2157 "RVUAF: IRQ registration failed for RVUAFVF ME1\n"); 2158 goto fail; 2159 } 2160 rvu->irq_allocated[offset] = true; 2161 return 0; 2162 2163 fail: 2164 rvu_unregister_interrupts(rvu); 2165 return ret; 2166 } 2167 2168 static void rvu_flr_wq_destroy(struct rvu *rvu) 2169 { 2170 if (rvu->flr_wq) { 2171 flush_workqueue(rvu->flr_wq); 2172 destroy_workqueue(rvu->flr_wq); 2173 rvu->flr_wq = NULL; 2174 } 2175 } 2176 2177 static int rvu_flr_init(struct rvu *rvu) 2178 { 2179 int dev, num_devs; 2180 u64 cfg; 2181 int pf; 2182 2183 /* Enable FLR for all PFs*/ 2184 for (pf = 0; pf < rvu->hw->total_pfs; pf++) { 2185 cfg = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_PFX_CFG(pf)); 2186 rvu_write64(rvu, BLKADDR_RVUM, RVU_PRIV_PFX_CFG(pf), 2187 cfg | BIT_ULL(22)); 2188 } 2189 2190 rvu->flr_wq = alloc_workqueue("rvu_afpf_flr", 2191 WQ_UNBOUND | WQ_HIGHPRI | WQ_MEM_RECLAIM, 2192 1); 2193 if (!rvu->flr_wq) 2194 return -ENOMEM; 2195 2196 num_devs = rvu->hw->total_pfs + pci_sriov_get_totalvfs(rvu->pdev); 2197 rvu->flr_wrk = devm_kcalloc(rvu->dev, num_devs, 2198 sizeof(struct rvu_work), GFP_KERNEL); 2199 if (!rvu->flr_wrk) { 2200 destroy_workqueue(rvu->flr_wq); 2201 return -ENOMEM; 2202 } 2203 2204 for (dev = 0; dev < num_devs; dev++) { 2205 rvu->flr_wrk[dev].rvu = rvu; 2206 INIT_WORK(&rvu->flr_wrk[dev].work, rvu_flr_handler); 2207 } 2208 2209 mutex_init(&rvu->flr_lock); 2210 2211 return 0; 2212 } 2213 2214 static void rvu_disable_afvf_intr(struct rvu *rvu) 2215 { 2216 int vfs = rvu->vfs; 2217 2218 rvupf_write64(rvu, RVU_PF_VFPF_MBOX_INT_ENA_W1CX(0), INTR_MASK(vfs)); 2219 rvupf_write64(rvu, RVU_PF_VFFLR_INT_ENA_W1CX(0), INTR_MASK(vfs)); 2220 rvupf_write64(rvu, RVU_PF_VFME_INT_ENA_W1CX(0), INTR_MASK(vfs)); 2221 if (vfs <= 64) 2222 return; 2223 2224 rvupf_write64(rvu, RVU_PF_VFPF_MBOX_INT_ENA_W1CX(1), 2225 INTR_MASK(vfs - 64)); 2226 rvupf_write64(rvu, RVU_PF_VFFLR_INT_ENA_W1CX(1), INTR_MASK(vfs - 64)); 2227 rvupf_write64(rvu, RVU_PF_VFME_INT_ENA_W1CX(1), INTR_MASK(vfs - 64)); 2228 } 2229 2230 static void rvu_enable_afvf_intr(struct rvu *rvu) 2231 { 2232 int vfs = rvu->vfs; 2233 2234 /* Clear any pending interrupts and enable AF VF interrupts for 2235 * the first 64 VFs. 2236 */ 2237 /* Mbox */ 2238 rvupf_write64(rvu, RVU_PF_VFPF_MBOX_INTX(0), INTR_MASK(vfs)); 2239 rvupf_write64(rvu, RVU_PF_VFPF_MBOX_INT_ENA_W1SX(0), INTR_MASK(vfs)); 2240 2241 /* FLR */ 2242 rvupf_write64(rvu, RVU_PF_VFFLR_INTX(0), INTR_MASK(vfs)); 2243 rvupf_write64(rvu, RVU_PF_VFFLR_INT_ENA_W1SX(0), INTR_MASK(vfs)); 2244 rvupf_write64(rvu, RVU_PF_VFME_INT_ENA_W1SX(0), INTR_MASK(vfs)); 2245 2246 /* Same for remaining VFs, if any. */ 2247 if (vfs <= 64) 2248 return; 2249 2250 rvupf_write64(rvu, RVU_PF_VFPF_MBOX_INTX(1), INTR_MASK(vfs - 64)); 2251 rvupf_write64(rvu, RVU_PF_VFPF_MBOX_INT_ENA_W1SX(1), 2252 INTR_MASK(vfs - 64)); 2253 2254 rvupf_write64(rvu, RVU_PF_VFFLR_INTX(1), INTR_MASK(vfs - 64)); 2255 rvupf_write64(rvu, RVU_PF_VFFLR_INT_ENA_W1SX(1), INTR_MASK(vfs - 64)); 2256 rvupf_write64(rvu, RVU_PF_VFME_INT_ENA_W1SX(1), INTR_MASK(vfs - 64)); 2257 } 2258 2259 #define PCI_DEVID_OCTEONTX2_LBK 0xA061 2260 2261 static int lbk_get_num_chans(void) 2262 { 2263 struct pci_dev *pdev; 2264 void __iomem *base; 2265 int ret = -EIO; 2266 2267 pdev = pci_get_device(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_OCTEONTX2_LBK, 2268 NULL); 2269 if (!pdev) 2270 goto err; 2271 2272 base = pci_ioremap_bar(pdev, 0); 2273 if (!base) 2274 goto err_put; 2275 2276 /* Read number of available LBK channels from LBK(0)_CONST register. */ 2277 ret = (readq(base + 0x10) >> 32) & 0xffff; 2278 iounmap(base); 2279 err_put: 2280 pci_dev_put(pdev); 2281 err: 2282 return ret; 2283 } 2284 2285 static int rvu_enable_sriov(struct rvu *rvu) 2286 { 2287 struct pci_dev *pdev = rvu->pdev; 2288 int err, chans, vfs; 2289 2290 if (!rvu_afvf_msix_vectors_num_ok(rvu)) { 2291 dev_warn(&pdev->dev, 2292 "Skipping SRIOV enablement since not enough IRQs are available\n"); 2293 return 0; 2294 } 2295 2296 chans = lbk_get_num_chans(); 2297 if (chans < 0) 2298 return chans; 2299 2300 vfs = pci_sriov_get_totalvfs(pdev); 2301 2302 /* Limit VFs in case we have more VFs than LBK channels available. */ 2303 if (vfs > chans) 2304 vfs = chans; 2305 2306 /* AF's VFs work in pairs and talk over consecutive loopback channels. 2307 * Thus we want to enable maximum even number of VFs. In case 2308 * odd number of VFs are available then the last VF on the list 2309 * remains disabled. 2310 */ 2311 if (vfs & 0x1) { 2312 dev_warn(&pdev->dev, 2313 "Number of VFs should be even. Enabling %d out of %d.\n", 2314 vfs - 1, vfs); 2315 vfs--; 2316 } 2317 2318 if (!vfs) 2319 return 0; 2320 2321 /* Save VFs number for reference in VF interrupts handlers. 2322 * Since interrupts might start arriving during SRIOV enablement 2323 * ordinary API cannot be used to get number of enabled VFs. 2324 */ 2325 rvu->vfs = vfs; 2326 2327 err = rvu_mbox_init(rvu, &rvu->afvf_wq_info, TYPE_AFVF, vfs, 2328 rvu_afvf_mbox_handler, rvu_afvf_mbox_up_handler); 2329 if (err) 2330 return err; 2331 2332 rvu_enable_afvf_intr(rvu); 2333 /* Make sure IRQs are enabled before SRIOV. */ 2334 mb(); 2335 2336 err = pci_enable_sriov(pdev, vfs); 2337 if (err) { 2338 rvu_disable_afvf_intr(rvu); 2339 rvu_mbox_destroy(&rvu->afvf_wq_info); 2340 return err; 2341 } 2342 2343 return 0; 2344 } 2345 2346 static void rvu_disable_sriov(struct rvu *rvu) 2347 { 2348 rvu_disable_afvf_intr(rvu); 2349 rvu_mbox_destroy(&rvu->afvf_wq_info); 2350 pci_disable_sriov(rvu->pdev); 2351 } 2352 2353 static int rvu_probe(struct pci_dev *pdev, const struct pci_device_id *id) 2354 { 2355 struct device *dev = &pdev->dev; 2356 struct rvu *rvu; 2357 int err; 2358 2359 rvu = devm_kzalloc(dev, sizeof(*rvu), GFP_KERNEL); 2360 if (!rvu) 2361 return -ENOMEM; 2362 2363 rvu->hw = devm_kzalloc(dev, sizeof(struct rvu_hwinfo), GFP_KERNEL); 2364 if (!rvu->hw) { 2365 devm_kfree(dev, rvu); 2366 return -ENOMEM; 2367 } 2368 2369 pci_set_drvdata(pdev, rvu); 2370 rvu->pdev = pdev; 2371 rvu->dev = &pdev->dev; 2372 2373 err = pci_enable_device(pdev); 2374 if (err) { 2375 dev_err(dev, "Failed to enable PCI device\n"); 2376 goto err_freemem; 2377 } 2378 2379 err = pci_request_regions(pdev, DRV_NAME); 2380 if (err) { 2381 dev_err(dev, "PCI request regions failed 0x%x\n", err); 2382 goto err_disable_device; 2383 } 2384 2385 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(48)); 2386 if (err) { 2387 dev_err(dev, "Unable to set DMA mask\n"); 2388 goto err_release_regions; 2389 } 2390 2391 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(48)); 2392 if (err) { 2393 dev_err(dev, "Unable to set consistent DMA mask\n"); 2394 goto err_release_regions; 2395 } 2396 2397 /* Map Admin function CSRs */ 2398 rvu->afreg_base = pcim_iomap(pdev, PCI_AF_REG_BAR_NUM, 0); 2399 rvu->pfreg_base = pcim_iomap(pdev, PCI_PF_REG_BAR_NUM, 0); 2400 if (!rvu->afreg_base || !rvu->pfreg_base) { 2401 dev_err(dev, "Unable to map admin function CSRs, aborting\n"); 2402 err = -ENOMEM; 2403 goto err_release_regions; 2404 } 2405 2406 /* Check which blocks the HW supports */ 2407 rvu_check_block_implemented(rvu); 2408 2409 rvu_reset_all_blocks(rvu); 2410 2411 err = rvu_setup_hw_resources(rvu); 2412 if (err) 2413 goto err_release_regions; 2414 2415 /* Init mailbox btw AF and PFs */ 2416 err = rvu_mbox_init(rvu, &rvu->afpf_wq_info, TYPE_AFPF, 2417 rvu->hw->total_pfs, rvu_afpf_mbox_handler, 2418 rvu_afpf_mbox_up_handler); 2419 if (err) 2420 goto err_hwsetup; 2421 2422 err = rvu_cgx_probe(rvu); 2423 if (err) 2424 goto err_mbox; 2425 2426 err = rvu_flr_init(rvu); 2427 if (err) 2428 goto err_cgx; 2429 2430 err = rvu_register_interrupts(rvu); 2431 if (err) 2432 goto err_flr; 2433 2434 /* Enable AF's VFs (if any) */ 2435 err = rvu_enable_sriov(rvu); 2436 if (err) 2437 goto err_irq; 2438 2439 return 0; 2440 err_irq: 2441 rvu_unregister_interrupts(rvu); 2442 err_flr: 2443 rvu_flr_wq_destroy(rvu); 2444 err_cgx: 2445 rvu_cgx_wq_destroy(rvu); 2446 err_mbox: 2447 rvu_mbox_destroy(&rvu->afpf_wq_info); 2448 err_hwsetup: 2449 rvu_reset_all_blocks(rvu); 2450 rvu_free_hw_resources(rvu); 2451 err_release_regions: 2452 pci_release_regions(pdev); 2453 err_disable_device: 2454 pci_disable_device(pdev); 2455 err_freemem: 2456 pci_set_drvdata(pdev, NULL); 2457 devm_kfree(&pdev->dev, rvu->hw); 2458 devm_kfree(dev, rvu); 2459 return err; 2460 } 2461 2462 static void rvu_remove(struct pci_dev *pdev) 2463 { 2464 struct rvu *rvu = pci_get_drvdata(pdev); 2465 2466 rvu_unregister_interrupts(rvu); 2467 rvu_flr_wq_destroy(rvu); 2468 rvu_cgx_wq_destroy(rvu); 2469 rvu_mbox_destroy(&rvu->afpf_wq_info); 2470 rvu_disable_sriov(rvu); 2471 rvu_reset_all_blocks(rvu); 2472 rvu_free_hw_resources(rvu); 2473 2474 pci_release_regions(pdev); 2475 pci_disable_device(pdev); 2476 pci_set_drvdata(pdev, NULL); 2477 2478 devm_kfree(&pdev->dev, rvu->hw); 2479 devm_kfree(&pdev->dev, rvu); 2480 } 2481 2482 static struct pci_driver rvu_driver = { 2483 .name = DRV_NAME, 2484 .id_table = rvu_id_table, 2485 .probe = rvu_probe, 2486 .remove = rvu_remove, 2487 }; 2488 2489 static int __init rvu_init_module(void) 2490 { 2491 int err; 2492 2493 pr_info("%s: %s\n", DRV_NAME, DRV_STRING); 2494 2495 err = pci_register_driver(&cgx_driver); 2496 if (err < 0) 2497 return err; 2498 2499 err = pci_register_driver(&rvu_driver); 2500 if (err < 0) 2501 pci_unregister_driver(&cgx_driver); 2502 2503 return err; 2504 } 2505 2506 static void __exit rvu_cleanup_module(void) 2507 { 2508 pci_unregister_driver(&rvu_driver); 2509 pci_unregister_driver(&cgx_driver); 2510 } 2511 2512 module_init(rvu_init_module); 2513 module_exit(rvu_cleanup_module); 2514