1 // SPDX-License-Identifier: GPL-2.0 2 /* Marvell OcteonTx2 RVU Admin Function driver 3 * 4 * Copyright (C) 2018 Marvell International Ltd. 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 */ 10 11 #include <linux/module.h> 12 #include <linux/interrupt.h> 13 #include <linux/delay.h> 14 #include <linux/irq.h> 15 #include <linux/pci.h> 16 #include <linux/sysfs.h> 17 18 #include "cgx.h" 19 #include "rvu.h" 20 #include "rvu_reg.h" 21 #include "ptp.h" 22 23 #include "rvu_trace.h" 24 25 #define DRV_NAME "rvu_af" 26 #define DRV_STRING "Marvell OcteonTX2 RVU Admin Function Driver" 27 28 static int rvu_get_hwvf(struct rvu *rvu, int pcifunc); 29 30 static void rvu_set_msix_offset(struct rvu *rvu, struct rvu_pfvf *pfvf, 31 struct rvu_block *block, int lf); 32 static void rvu_clear_msix_offset(struct rvu *rvu, struct rvu_pfvf *pfvf, 33 struct rvu_block *block, int lf); 34 static void __rvu_flr_handler(struct rvu *rvu, u16 pcifunc); 35 36 static int rvu_mbox_init(struct rvu *rvu, struct mbox_wq_info *mw, 37 int type, int num, 38 void (mbox_handler)(struct work_struct *), 39 void (mbox_up_handler)(struct work_struct *)); 40 enum { 41 TYPE_AFVF, 42 TYPE_AFPF, 43 }; 44 45 /* Supported devices */ 46 static const struct pci_device_id rvu_id_table[] = { 47 { PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_OCTEONTX2_RVU_AF) }, 48 { 0, } /* end of table */ 49 }; 50 51 MODULE_AUTHOR("Sunil Goutham <sgoutham@marvell.com>"); 52 MODULE_DESCRIPTION(DRV_STRING); 53 MODULE_LICENSE("GPL v2"); 54 MODULE_DEVICE_TABLE(pci, rvu_id_table); 55 56 static char *mkex_profile; /* MKEX profile name */ 57 module_param(mkex_profile, charp, 0000); 58 MODULE_PARM_DESC(mkex_profile, "MKEX profile name string"); 59 60 static void rvu_setup_hw_capabilities(struct rvu *rvu) 61 { 62 struct rvu_hwinfo *hw = rvu->hw; 63 64 hw->cap.nix_tx_aggr_lvl = NIX_TXSCH_LVL_TL1; 65 hw->cap.nix_fixed_txschq_mapping = false; 66 hw->cap.nix_shaping = true; 67 hw->cap.nix_tx_link_bp = true; 68 hw->cap.nix_rx_multicast = true; 69 hw->rvu = rvu; 70 71 if (is_rvu_96xx_B0(rvu)) { 72 hw->cap.nix_fixed_txschq_mapping = true; 73 hw->cap.nix_txsch_per_cgx_lmac = 4; 74 hw->cap.nix_txsch_per_lbk_lmac = 132; 75 hw->cap.nix_txsch_per_sdp_lmac = 76; 76 hw->cap.nix_shaping = false; 77 hw->cap.nix_tx_link_bp = false; 78 if (is_rvu_96xx_A0(rvu)) 79 hw->cap.nix_rx_multicast = false; 80 } 81 82 if (!is_rvu_otx2(rvu)) 83 hw->cap.per_pf_mbox_regs = true; 84 } 85 86 /* Poll a RVU block's register 'offset', for a 'zero' 87 * or 'nonzero' at bits specified by 'mask' 88 */ 89 int rvu_poll_reg(struct rvu *rvu, u64 block, u64 offset, u64 mask, bool zero) 90 { 91 unsigned long timeout = jiffies + usecs_to_jiffies(10000); 92 void __iomem *reg; 93 u64 reg_val; 94 95 reg = rvu->afreg_base + ((block << 28) | offset); 96 again: 97 reg_val = readq(reg); 98 if (zero && !(reg_val & mask)) 99 return 0; 100 if (!zero && (reg_val & mask)) 101 return 0; 102 if (time_before(jiffies, timeout)) { 103 usleep_range(1, 5); 104 goto again; 105 } 106 return -EBUSY; 107 } 108 109 int rvu_alloc_rsrc(struct rsrc_bmap *rsrc) 110 { 111 int id; 112 113 if (!rsrc->bmap) 114 return -EINVAL; 115 116 id = find_first_zero_bit(rsrc->bmap, rsrc->max); 117 if (id >= rsrc->max) 118 return -ENOSPC; 119 120 __set_bit(id, rsrc->bmap); 121 122 return id; 123 } 124 125 int rvu_alloc_rsrc_contig(struct rsrc_bmap *rsrc, int nrsrc) 126 { 127 int start; 128 129 if (!rsrc->bmap) 130 return -EINVAL; 131 132 start = bitmap_find_next_zero_area(rsrc->bmap, rsrc->max, 0, nrsrc, 0); 133 if (start >= rsrc->max) 134 return -ENOSPC; 135 136 bitmap_set(rsrc->bmap, start, nrsrc); 137 return start; 138 } 139 140 static void rvu_free_rsrc_contig(struct rsrc_bmap *rsrc, int nrsrc, int start) 141 { 142 if (!rsrc->bmap) 143 return; 144 if (start >= rsrc->max) 145 return; 146 147 bitmap_clear(rsrc->bmap, start, nrsrc); 148 } 149 150 bool rvu_rsrc_check_contig(struct rsrc_bmap *rsrc, int nrsrc) 151 { 152 int start; 153 154 if (!rsrc->bmap) 155 return false; 156 157 start = bitmap_find_next_zero_area(rsrc->bmap, rsrc->max, 0, nrsrc, 0); 158 if (start >= rsrc->max) 159 return false; 160 161 return true; 162 } 163 164 void rvu_free_rsrc(struct rsrc_bmap *rsrc, int id) 165 { 166 if (!rsrc->bmap) 167 return; 168 169 __clear_bit(id, rsrc->bmap); 170 } 171 172 int rvu_rsrc_free_count(struct rsrc_bmap *rsrc) 173 { 174 int used; 175 176 if (!rsrc->bmap) 177 return 0; 178 179 used = bitmap_weight(rsrc->bmap, rsrc->max); 180 return (rsrc->max - used); 181 } 182 183 int rvu_alloc_bitmap(struct rsrc_bmap *rsrc) 184 { 185 rsrc->bmap = kcalloc(BITS_TO_LONGS(rsrc->max), 186 sizeof(long), GFP_KERNEL); 187 if (!rsrc->bmap) 188 return -ENOMEM; 189 return 0; 190 } 191 192 /* Get block LF's HW index from a PF_FUNC's block slot number */ 193 int rvu_get_lf(struct rvu *rvu, struct rvu_block *block, u16 pcifunc, u16 slot) 194 { 195 u16 match = 0; 196 int lf; 197 198 mutex_lock(&rvu->rsrc_lock); 199 for (lf = 0; lf < block->lf.max; lf++) { 200 if (block->fn_map[lf] == pcifunc) { 201 if (slot == match) { 202 mutex_unlock(&rvu->rsrc_lock); 203 return lf; 204 } 205 match++; 206 } 207 } 208 mutex_unlock(&rvu->rsrc_lock); 209 return -ENODEV; 210 } 211 212 /* Convert BLOCK_TYPE_E to a BLOCK_ADDR_E. 213 * Some silicon variants of OcteonTX2 supports 214 * multiple blocks of same type. 215 * 216 * @pcifunc has to be zero when no LF is yet attached. 217 * 218 * For a pcifunc if LFs are attached from multiple blocks of same type, then 219 * return blkaddr of first encountered block. 220 */ 221 int rvu_get_blkaddr(struct rvu *rvu, int blktype, u16 pcifunc) 222 { 223 int devnum, blkaddr = -ENODEV; 224 u64 cfg, reg; 225 bool is_pf; 226 227 switch (blktype) { 228 case BLKTYPE_NPC: 229 blkaddr = BLKADDR_NPC; 230 goto exit; 231 case BLKTYPE_NPA: 232 blkaddr = BLKADDR_NPA; 233 goto exit; 234 case BLKTYPE_NIX: 235 /* For now assume NIX0 */ 236 if (!pcifunc) { 237 blkaddr = BLKADDR_NIX0; 238 goto exit; 239 } 240 break; 241 case BLKTYPE_SSO: 242 blkaddr = BLKADDR_SSO; 243 goto exit; 244 case BLKTYPE_SSOW: 245 blkaddr = BLKADDR_SSOW; 246 goto exit; 247 case BLKTYPE_TIM: 248 blkaddr = BLKADDR_TIM; 249 goto exit; 250 case BLKTYPE_CPT: 251 /* For now assume CPT0 */ 252 if (!pcifunc) { 253 blkaddr = BLKADDR_CPT0; 254 goto exit; 255 } 256 break; 257 } 258 259 /* Check if this is a RVU PF or VF */ 260 if (pcifunc & RVU_PFVF_FUNC_MASK) { 261 is_pf = false; 262 devnum = rvu_get_hwvf(rvu, pcifunc); 263 } else { 264 is_pf = true; 265 devnum = rvu_get_pf(pcifunc); 266 } 267 268 /* Check if the 'pcifunc' has a NIX LF from 'BLKADDR_NIX0' or 269 * 'BLKADDR_NIX1'. 270 */ 271 if (blktype == BLKTYPE_NIX) { 272 reg = is_pf ? RVU_PRIV_PFX_NIXX_CFG(0) : 273 RVU_PRIV_HWVFX_NIXX_CFG(0); 274 cfg = rvu_read64(rvu, BLKADDR_RVUM, reg | (devnum << 16)); 275 if (cfg) { 276 blkaddr = BLKADDR_NIX0; 277 goto exit; 278 } 279 280 reg = is_pf ? RVU_PRIV_PFX_NIXX_CFG(1) : 281 RVU_PRIV_HWVFX_NIXX_CFG(1); 282 cfg = rvu_read64(rvu, BLKADDR_RVUM, reg | (devnum << 16)); 283 if (cfg) 284 blkaddr = BLKADDR_NIX1; 285 } 286 287 if (blktype == BLKTYPE_CPT) { 288 reg = is_pf ? RVU_PRIV_PFX_CPTX_CFG(0) : 289 RVU_PRIV_HWVFX_CPTX_CFG(0); 290 cfg = rvu_read64(rvu, BLKADDR_RVUM, reg | (devnum << 16)); 291 if (cfg) { 292 blkaddr = BLKADDR_CPT0; 293 goto exit; 294 } 295 296 reg = is_pf ? RVU_PRIV_PFX_CPTX_CFG(1) : 297 RVU_PRIV_HWVFX_CPTX_CFG(1); 298 cfg = rvu_read64(rvu, BLKADDR_RVUM, reg | (devnum << 16)); 299 if (cfg) 300 blkaddr = BLKADDR_CPT1; 301 } 302 303 exit: 304 if (is_block_implemented(rvu->hw, blkaddr)) 305 return blkaddr; 306 return -ENODEV; 307 } 308 309 static void rvu_update_rsrc_map(struct rvu *rvu, struct rvu_pfvf *pfvf, 310 struct rvu_block *block, u16 pcifunc, 311 u16 lf, bool attach) 312 { 313 int devnum, num_lfs = 0; 314 bool is_pf; 315 u64 reg; 316 317 if (lf >= block->lf.max) { 318 dev_err(&rvu->pdev->dev, 319 "%s: FATAL: LF %d is >= %s's max lfs i.e %d\n", 320 __func__, lf, block->name, block->lf.max); 321 return; 322 } 323 324 /* Check if this is for a RVU PF or VF */ 325 if (pcifunc & RVU_PFVF_FUNC_MASK) { 326 is_pf = false; 327 devnum = rvu_get_hwvf(rvu, pcifunc); 328 } else { 329 is_pf = true; 330 devnum = rvu_get_pf(pcifunc); 331 } 332 333 block->fn_map[lf] = attach ? pcifunc : 0; 334 335 switch (block->addr) { 336 case BLKADDR_NPA: 337 pfvf->npalf = attach ? true : false; 338 num_lfs = pfvf->npalf; 339 break; 340 case BLKADDR_NIX0: 341 case BLKADDR_NIX1: 342 pfvf->nixlf = attach ? true : false; 343 num_lfs = pfvf->nixlf; 344 break; 345 case BLKADDR_SSO: 346 attach ? pfvf->sso++ : pfvf->sso--; 347 num_lfs = pfvf->sso; 348 break; 349 case BLKADDR_SSOW: 350 attach ? pfvf->ssow++ : pfvf->ssow--; 351 num_lfs = pfvf->ssow; 352 break; 353 case BLKADDR_TIM: 354 attach ? pfvf->timlfs++ : pfvf->timlfs--; 355 num_lfs = pfvf->timlfs; 356 break; 357 case BLKADDR_CPT0: 358 attach ? pfvf->cptlfs++ : pfvf->cptlfs--; 359 num_lfs = pfvf->cptlfs; 360 break; 361 case BLKADDR_CPT1: 362 attach ? pfvf->cpt1_lfs++ : pfvf->cpt1_lfs--; 363 num_lfs = pfvf->cpt1_lfs; 364 break; 365 } 366 367 reg = is_pf ? block->pf_lfcnt_reg : block->vf_lfcnt_reg; 368 rvu_write64(rvu, BLKADDR_RVUM, reg | (devnum << 16), num_lfs); 369 } 370 371 inline int rvu_get_pf(u16 pcifunc) 372 { 373 return (pcifunc >> RVU_PFVF_PF_SHIFT) & RVU_PFVF_PF_MASK; 374 } 375 376 void rvu_get_pf_numvfs(struct rvu *rvu, int pf, int *numvfs, int *hwvf) 377 { 378 u64 cfg; 379 380 /* Get numVFs attached to this PF and first HWVF */ 381 cfg = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_PFX_CFG(pf)); 382 *numvfs = (cfg >> 12) & 0xFF; 383 *hwvf = cfg & 0xFFF; 384 } 385 386 static int rvu_get_hwvf(struct rvu *rvu, int pcifunc) 387 { 388 int pf, func; 389 u64 cfg; 390 391 pf = rvu_get_pf(pcifunc); 392 func = pcifunc & RVU_PFVF_FUNC_MASK; 393 394 /* Get first HWVF attached to this PF */ 395 cfg = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_PFX_CFG(pf)); 396 397 return ((cfg & 0xFFF) + func - 1); 398 } 399 400 struct rvu_pfvf *rvu_get_pfvf(struct rvu *rvu, int pcifunc) 401 { 402 /* Check if it is a PF or VF */ 403 if (pcifunc & RVU_PFVF_FUNC_MASK) 404 return &rvu->hwvf[rvu_get_hwvf(rvu, pcifunc)]; 405 else 406 return &rvu->pf[rvu_get_pf(pcifunc)]; 407 } 408 409 static bool is_pf_func_valid(struct rvu *rvu, u16 pcifunc) 410 { 411 int pf, vf, nvfs; 412 u64 cfg; 413 414 pf = rvu_get_pf(pcifunc); 415 if (pf >= rvu->hw->total_pfs) 416 return false; 417 418 if (!(pcifunc & RVU_PFVF_FUNC_MASK)) 419 return true; 420 421 /* Check if VF is within number of VFs attached to this PF */ 422 vf = (pcifunc & RVU_PFVF_FUNC_MASK) - 1; 423 cfg = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_PFX_CFG(pf)); 424 nvfs = (cfg >> 12) & 0xFF; 425 if (vf >= nvfs) 426 return false; 427 428 return true; 429 } 430 431 bool is_block_implemented(struct rvu_hwinfo *hw, int blkaddr) 432 { 433 struct rvu_block *block; 434 435 if (blkaddr < BLKADDR_RVUM || blkaddr >= BLK_COUNT) 436 return false; 437 438 block = &hw->block[blkaddr]; 439 return block->implemented; 440 } 441 442 static void rvu_check_block_implemented(struct rvu *rvu) 443 { 444 struct rvu_hwinfo *hw = rvu->hw; 445 struct rvu_block *block; 446 int blkid; 447 u64 cfg; 448 449 /* For each block check if 'implemented' bit is set */ 450 for (blkid = 0; blkid < BLK_COUNT; blkid++) { 451 block = &hw->block[blkid]; 452 cfg = rvupf_read64(rvu, RVU_PF_BLOCK_ADDRX_DISC(blkid)); 453 if (cfg & BIT_ULL(11)) 454 block->implemented = true; 455 } 456 } 457 458 static void rvu_setup_rvum_blk_revid(struct rvu *rvu) 459 { 460 rvu_write64(rvu, BLKADDR_RVUM, 461 RVU_PRIV_BLOCK_TYPEX_REV(BLKTYPE_RVUM), 462 RVU_BLK_RVUM_REVID); 463 } 464 465 static void rvu_clear_rvum_blk_revid(struct rvu *rvu) 466 { 467 rvu_write64(rvu, BLKADDR_RVUM, 468 RVU_PRIV_BLOCK_TYPEX_REV(BLKTYPE_RVUM), 0x00); 469 } 470 471 int rvu_lf_reset(struct rvu *rvu, struct rvu_block *block, int lf) 472 { 473 int err; 474 475 if (!block->implemented) 476 return 0; 477 478 rvu_write64(rvu, block->addr, block->lfreset_reg, lf | BIT_ULL(12)); 479 err = rvu_poll_reg(rvu, block->addr, block->lfreset_reg, BIT_ULL(12), 480 true); 481 return err; 482 } 483 484 static void rvu_block_reset(struct rvu *rvu, int blkaddr, u64 rst_reg) 485 { 486 struct rvu_block *block = &rvu->hw->block[blkaddr]; 487 488 if (!block->implemented) 489 return; 490 491 rvu_write64(rvu, blkaddr, rst_reg, BIT_ULL(0)); 492 rvu_poll_reg(rvu, blkaddr, rst_reg, BIT_ULL(63), true); 493 } 494 495 static void rvu_reset_all_blocks(struct rvu *rvu) 496 { 497 /* Do a HW reset of all RVU blocks */ 498 rvu_block_reset(rvu, BLKADDR_NPA, NPA_AF_BLK_RST); 499 rvu_block_reset(rvu, BLKADDR_NIX0, NIX_AF_BLK_RST); 500 rvu_block_reset(rvu, BLKADDR_NIX1, NIX_AF_BLK_RST); 501 rvu_block_reset(rvu, BLKADDR_NPC, NPC_AF_BLK_RST); 502 rvu_block_reset(rvu, BLKADDR_SSO, SSO_AF_BLK_RST); 503 rvu_block_reset(rvu, BLKADDR_TIM, TIM_AF_BLK_RST); 504 rvu_block_reset(rvu, BLKADDR_CPT0, CPT_AF_BLK_RST); 505 rvu_block_reset(rvu, BLKADDR_CPT1, CPT_AF_BLK_RST); 506 rvu_block_reset(rvu, BLKADDR_NDC_NIX0_RX, NDC_AF_BLK_RST); 507 rvu_block_reset(rvu, BLKADDR_NDC_NIX0_TX, NDC_AF_BLK_RST); 508 rvu_block_reset(rvu, BLKADDR_NDC_NIX1_RX, NDC_AF_BLK_RST); 509 rvu_block_reset(rvu, BLKADDR_NDC_NIX1_TX, NDC_AF_BLK_RST); 510 rvu_block_reset(rvu, BLKADDR_NDC_NPA0, NDC_AF_BLK_RST); 511 } 512 513 static void rvu_scan_block(struct rvu *rvu, struct rvu_block *block) 514 { 515 struct rvu_pfvf *pfvf; 516 u64 cfg; 517 int lf; 518 519 for (lf = 0; lf < block->lf.max; lf++) { 520 cfg = rvu_read64(rvu, block->addr, 521 block->lfcfg_reg | (lf << block->lfshift)); 522 if (!(cfg & BIT_ULL(63))) 523 continue; 524 525 /* Set this resource as being used */ 526 __set_bit(lf, block->lf.bmap); 527 528 /* Get, to whom this LF is attached */ 529 pfvf = rvu_get_pfvf(rvu, (cfg >> 8) & 0xFFFF); 530 rvu_update_rsrc_map(rvu, pfvf, block, 531 (cfg >> 8) & 0xFFFF, lf, true); 532 533 /* Set start MSIX vector for this LF within this PF/VF */ 534 rvu_set_msix_offset(rvu, pfvf, block, lf); 535 } 536 } 537 538 static void rvu_check_min_msix_vec(struct rvu *rvu, int nvecs, int pf, int vf) 539 { 540 int min_vecs; 541 542 if (!vf) 543 goto check_pf; 544 545 if (!nvecs) { 546 dev_warn(rvu->dev, 547 "PF%d:VF%d is configured with zero msix vectors, %d\n", 548 pf, vf - 1, nvecs); 549 } 550 return; 551 552 check_pf: 553 if (pf == 0) 554 min_vecs = RVU_AF_INT_VEC_CNT + RVU_PF_INT_VEC_CNT; 555 else 556 min_vecs = RVU_PF_INT_VEC_CNT; 557 558 if (!(nvecs < min_vecs)) 559 return; 560 dev_warn(rvu->dev, 561 "PF%d is configured with too few vectors, %d, min is %d\n", 562 pf, nvecs, min_vecs); 563 } 564 565 static int rvu_setup_msix_resources(struct rvu *rvu) 566 { 567 struct rvu_hwinfo *hw = rvu->hw; 568 int pf, vf, numvfs, hwvf, err; 569 int nvecs, offset, max_msix; 570 struct rvu_pfvf *pfvf; 571 u64 cfg, phy_addr; 572 dma_addr_t iova; 573 574 for (pf = 0; pf < hw->total_pfs; pf++) { 575 cfg = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_PFX_CFG(pf)); 576 /* If PF is not enabled, nothing to do */ 577 if (!((cfg >> 20) & 0x01)) 578 continue; 579 580 rvu_get_pf_numvfs(rvu, pf, &numvfs, &hwvf); 581 582 pfvf = &rvu->pf[pf]; 583 /* Get num of MSIX vectors attached to this PF */ 584 cfg = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_PFX_MSIX_CFG(pf)); 585 pfvf->msix.max = ((cfg >> 32) & 0xFFF) + 1; 586 rvu_check_min_msix_vec(rvu, pfvf->msix.max, pf, 0); 587 588 /* Alloc msix bitmap for this PF */ 589 err = rvu_alloc_bitmap(&pfvf->msix); 590 if (err) 591 return err; 592 593 /* Allocate memory for MSIX vector to RVU block LF mapping */ 594 pfvf->msix_lfmap = devm_kcalloc(rvu->dev, pfvf->msix.max, 595 sizeof(u16), GFP_KERNEL); 596 if (!pfvf->msix_lfmap) 597 return -ENOMEM; 598 599 /* For PF0 (AF) firmware will set msix vector offsets for 600 * AF, block AF and PF0_INT vectors, so jump to VFs. 601 */ 602 if (!pf) 603 goto setup_vfmsix; 604 605 /* Set MSIX offset for PF's 'RVU_PF_INT_VEC' vectors. 606 * These are allocated on driver init and never freed, 607 * so no need to set 'msix_lfmap' for these. 608 */ 609 cfg = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_PFX_INT_CFG(pf)); 610 nvecs = (cfg >> 12) & 0xFF; 611 cfg &= ~0x7FFULL; 612 offset = rvu_alloc_rsrc_contig(&pfvf->msix, nvecs); 613 rvu_write64(rvu, BLKADDR_RVUM, 614 RVU_PRIV_PFX_INT_CFG(pf), cfg | offset); 615 setup_vfmsix: 616 /* Alloc msix bitmap for VFs */ 617 for (vf = 0; vf < numvfs; vf++) { 618 pfvf = &rvu->hwvf[hwvf + vf]; 619 /* Get num of MSIX vectors attached to this VF */ 620 cfg = rvu_read64(rvu, BLKADDR_RVUM, 621 RVU_PRIV_PFX_MSIX_CFG(pf)); 622 pfvf->msix.max = (cfg & 0xFFF) + 1; 623 rvu_check_min_msix_vec(rvu, pfvf->msix.max, pf, vf + 1); 624 625 /* Alloc msix bitmap for this VF */ 626 err = rvu_alloc_bitmap(&pfvf->msix); 627 if (err) 628 return err; 629 630 pfvf->msix_lfmap = 631 devm_kcalloc(rvu->dev, pfvf->msix.max, 632 sizeof(u16), GFP_KERNEL); 633 if (!pfvf->msix_lfmap) 634 return -ENOMEM; 635 636 /* Set MSIX offset for HWVF's 'RVU_VF_INT_VEC' vectors. 637 * These are allocated on driver init and never freed, 638 * so no need to set 'msix_lfmap' for these. 639 */ 640 cfg = rvu_read64(rvu, BLKADDR_RVUM, 641 RVU_PRIV_HWVFX_INT_CFG(hwvf + vf)); 642 nvecs = (cfg >> 12) & 0xFF; 643 cfg &= ~0x7FFULL; 644 offset = rvu_alloc_rsrc_contig(&pfvf->msix, nvecs); 645 rvu_write64(rvu, BLKADDR_RVUM, 646 RVU_PRIV_HWVFX_INT_CFG(hwvf + vf), 647 cfg | offset); 648 } 649 } 650 651 /* HW interprets RVU_AF_MSIXTR_BASE address as an IOVA, hence 652 * create an IOMMU mapping for the physical address configured by 653 * firmware and reconfig RVU_AF_MSIXTR_BASE with IOVA. 654 */ 655 cfg = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_CONST); 656 max_msix = cfg & 0xFFFFF; 657 if (rvu->fwdata && rvu->fwdata->msixtr_base) 658 phy_addr = rvu->fwdata->msixtr_base; 659 else 660 phy_addr = rvu_read64(rvu, BLKADDR_RVUM, RVU_AF_MSIXTR_BASE); 661 662 iova = dma_map_resource(rvu->dev, phy_addr, 663 max_msix * PCI_MSIX_ENTRY_SIZE, 664 DMA_BIDIRECTIONAL, 0); 665 666 if (dma_mapping_error(rvu->dev, iova)) 667 return -ENOMEM; 668 669 rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_MSIXTR_BASE, (u64)iova); 670 rvu->msix_base_iova = iova; 671 rvu->msixtr_base_phy = phy_addr; 672 673 return 0; 674 } 675 676 static void rvu_reset_msix(struct rvu *rvu) 677 { 678 /* Restore msixtr base register */ 679 rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_MSIXTR_BASE, 680 rvu->msixtr_base_phy); 681 } 682 683 static void rvu_free_hw_resources(struct rvu *rvu) 684 { 685 struct rvu_hwinfo *hw = rvu->hw; 686 struct rvu_block *block; 687 struct rvu_pfvf *pfvf; 688 int id, max_msix; 689 u64 cfg; 690 691 rvu_npa_freemem(rvu); 692 rvu_npc_freemem(rvu); 693 rvu_nix_freemem(rvu); 694 695 /* Free block LF bitmaps */ 696 for (id = 0; id < BLK_COUNT; id++) { 697 block = &hw->block[id]; 698 kfree(block->lf.bmap); 699 } 700 701 /* Free MSIX bitmaps */ 702 for (id = 0; id < hw->total_pfs; id++) { 703 pfvf = &rvu->pf[id]; 704 kfree(pfvf->msix.bmap); 705 } 706 707 for (id = 0; id < hw->total_vfs; id++) { 708 pfvf = &rvu->hwvf[id]; 709 kfree(pfvf->msix.bmap); 710 } 711 712 /* Unmap MSIX vector base IOVA mapping */ 713 if (!rvu->msix_base_iova) 714 return; 715 cfg = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_CONST); 716 max_msix = cfg & 0xFFFFF; 717 dma_unmap_resource(rvu->dev, rvu->msix_base_iova, 718 max_msix * PCI_MSIX_ENTRY_SIZE, 719 DMA_BIDIRECTIONAL, 0); 720 721 rvu_reset_msix(rvu); 722 mutex_destroy(&rvu->rsrc_lock); 723 } 724 725 static void rvu_setup_pfvf_macaddress(struct rvu *rvu) 726 { 727 struct rvu_hwinfo *hw = rvu->hw; 728 int pf, vf, numvfs, hwvf; 729 struct rvu_pfvf *pfvf; 730 u64 *mac; 731 732 for (pf = 0; pf < hw->total_pfs; pf++) { 733 /* For PF0(AF), Assign MAC address to only VFs (LBKVFs) */ 734 if (!pf) 735 goto lbkvf; 736 737 if (!is_pf_cgxmapped(rvu, pf)) 738 continue; 739 /* Assign MAC address to PF */ 740 pfvf = &rvu->pf[pf]; 741 if (rvu->fwdata && pf < PF_MACNUM_MAX) { 742 mac = &rvu->fwdata->pf_macs[pf]; 743 if (*mac) 744 u64_to_ether_addr(*mac, pfvf->mac_addr); 745 else 746 eth_random_addr(pfvf->mac_addr); 747 } else { 748 eth_random_addr(pfvf->mac_addr); 749 } 750 ether_addr_copy(pfvf->default_mac, pfvf->mac_addr); 751 752 lbkvf: 753 /* Assign MAC address to VFs*/ 754 rvu_get_pf_numvfs(rvu, pf, &numvfs, &hwvf); 755 for (vf = 0; vf < numvfs; vf++, hwvf++) { 756 pfvf = &rvu->hwvf[hwvf]; 757 if (rvu->fwdata && hwvf < VF_MACNUM_MAX) { 758 mac = &rvu->fwdata->vf_macs[hwvf]; 759 if (*mac) 760 u64_to_ether_addr(*mac, pfvf->mac_addr); 761 else 762 eth_random_addr(pfvf->mac_addr); 763 } else { 764 eth_random_addr(pfvf->mac_addr); 765 } 766 ether_addr_copy(pfvf->default_mac, pfvf->mac_addr); 767 } 768 } 769 } 770 771 static int rvu_fwdata_init(struct rvu *rvu) 772 { 773 u64 fwdbase; 774 int err; 775 776 /* Get firmware data base address */ 777 err = cgx_get_fwdata_base(&fwdbase); 778 if (err) 779 goto fail; 780 rvu->fwdata = ioremap_wc(fwdbase, sizeof(struct rvu_fwdata)); 781 if (!rvu->fwdata) 782 goto fail; 783 if (!is_rvu_fwdata_valid(rvu)) { 784 dev_err(rvu->dev, 785 "Mismatch in 'fwdata' struct btw kernel and firmware\n"); 786 iounmap(rvu->fwdata); 787 rvu->fwdata = NULL; 788 return -EINVAL; 789 } 790 return 0; 791 fail: 792 dev_info(rvu->dev, "Unable to fetch 'fwdata' from firmware\n"); 793 return -EIO; 794 } 795 796 static void rvu_fwdata_exit(struct rvu *rvu) 797 { 798 if (rvu->fwdata) 799 iounmap(rvu->fwdata); 800 } 801 802 static int rvu_setup_nix_hw_resource(struct rvu *rvu, int blkaddr) 803 { 804 struct rvu_hwinfo *hw = rvu->hw; 805 struct rvu_block *block; 806 int blkid; 807 u64 cfg; 808 809 /* Init NIX LF's bitmap */ 810 block = &hw->block[blkaddr]; 811 if (!block->implemented) 812 return 0; 813 blkid = (blkaddr == BLKADDR_NIX0) ? 0 : 1; 814 cfg = rvu_read64(rvu, blkaddr, NIX_AF_CONST2); 815 block->lf.max = cfg & 0xFFF; 816 block->addr = blkaddr; 817 block->type = BLKTYPE_NIX; 818 block->lfshift = 8; 819 block->lookup_reg = NIX_AF_RVU_LF_CFG_DEBUG; 820 block->pf_lfcnt_reg = RVU_PRIV_PFX_NIXX_CFG(blkid); 821 block->vf_lfcnt_reg = RVU_PRIV_HWVFX_NIXX_CFG(blkid); 822 block->lfcfg_reg = NIX_PRIV_LFX_CFG; 823 block->msixcfg_reg = NIX_PRIV_LFX_INT_CFG; 824 block->lfreset_reg = NIX_AF_LF_RST; 825 sprintf(block->name, "NIX%d", blkid); 826 rvu->nix_blkaddr[blkid] = blkaddr; 827 return rvu_alloc_bitmap(&block->lf); 828 } 829 830 static int rvu_setup_cpt_hw_resource(struct rvu *rvu, int blkaddr) 831 { 832 struct rvu_hwinfo *hw = rvu->hw; 833 struct rvu_block *block; 834 int blkid; 835 u64 cfg; 836 837 /* Init CPT LF's bitmap */ 838 block = &hw->block[blkaddr]; 839 if (!block->implemented) 840 return 0; 841 blkid = (blkaddr == BLKADDR_CPT0) ? 0 : 1; 842 cfg = rvu_read64(rvu, blkaddr, CPT_AF_CONSTANTS0); 843 block->lf.max = cfg & 0xFF; 844 block->addr = blkaddr; 845 block->type = BLKTYPE_CPT; 846 block->multislot = true; 847 block->lfshift = 3; 848 block->lookup_reg = CPT_AF_RVU_LF_CFG_DEBUG; 849 block->pf_lfcnt_reg = RVU_PRIV_PFX_CPTX_CFG(blkid); 850 block->vf_lfcnt_reg = RVU_PRIV_HWVFX_CPTX_CFG(blkid); 851 block->lfcfg_reg = CPT_PRIV_LFX_CFG; 852 block->msixcfg_reg = CPT_PRIV_LFX_INT_CFG; 853 block->lfreset_reg = CPT_AF_LF_RST; 854 sprintf(block->name, "CPT%d", blkid); 855 return rvu_alloc_bitmap(&block->lf); 856 } 857 858 static void rvu_get_lbk_bufsize(struct rvu *rvu) 859 { 860 struct pci_dev *pdev = NULL; 861 void __iomem *base; 862 u64 lbk_const; 863 864 pdev = pci_get_device(PCI_VENDOR_ID_CAVIUM, 865 PCI_DEVID_OCTEONTX2_LBK, pdev); 866 if (!pdev) 867 return; 868 869 base = pci_ioremap_bar(pdev, 0); 870 if (!base) 871 goto err_put; 872 873 lbk_const = readq(base + LBK_CONST); 874 875 /* cache fifo size */ 876 rvu->hw->lbk_bufsize = FIELD_GET(LBK_CONST_BUF_SIZE, lbk_const); 877 878 iounmap(base); 879 err_put: 880 pci_dev_put(pdev); 881 } 882 883 static int rvu_setup_hw_resources(struct rvu *rvu) 884 { 885 struct rvu_hwinfo *hw = rvu->hw; 886 struct rvu_block *block; 887 int blkid, err; 888 u64 cfg; 889 890 /* Get HW supported max RVU PF & VF count */ 891 cfg = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_CONST); 892 hw->total_pfs = (cfg >> 32) & 0xFF; 893 hw->total_vfs = (cfg >> 20) & 0xFFF; 894 hw->max_vfs_per_pf = (cfg >> 40) & 0xFF; 895 896 /* Init NPA LF's bitmap */ 897 block = &hw->block[BLKADDR_NPA]; 898 if (!block->implemented) 899 goto nix; 900 cfg = rvu_read64(rvu, BLKADDR_NPA, NPA_AF_CONST); 901 block->lf.max = (cfg >> 16) & 0xFFF; 902 block->addr = BLKADDR_NPA; 903 block->type = BLKTYPE_NPA; 904 block->lfshift = 8; 905 block->lookup_reg = NPA_AF_RVU_LF_CFG_DEBUG; 906 block->pf_lfcnt_reg = RVU_PRIV_PFX_NPA_CFG; 907 block->vf_lfcnt_reg = RVU_PRIV_HWVFX_NPA_CFG; 908 block->lfcfg_reg = NPA_PRIV_LFX_CFG; 909 block->msixcfg_reg = NPA_PRIV_LFX_INT_CFG; 910 block->lfreset_reg = NPA_AF_LF_RST; 911 sprintf(block->name, "NPA"); 912 err = rvu_alloc_bitmap(&block->lf); 913 if (err) 914 return err; 915 916 nix: 917 err = rvu_setup_nix_hw_resource(rvu, BLKADDR_NIX0); 918 if (err) 919 return err; 920 err = rvu_setup_nix_hw_resource(rvu, BLKADDR_NIX1); 921 if (err) 922 return err; 923 924 /* Init SSO group's bitmap */ 925 block = &hw->block[BLKADDR_SSO]; 926 if (!block->implemented) 927 goto ssow; 928 cfg = rvu_read64(rvu, BLKADDR_SSO, SSO_AF_CONST); 929 block->lf.max = cfg & 0xFFFF; 930 block->addr = BLKADDR_SSO; 931 block->type = BLKTYPE_SSO; 932 block->multislot = true; 933 block->lfshift = 3; 934 block->lookup_reg = SSO_AF_RVU_LF_CFG_DEBUG; 935 block->pf_lfcnt_reg = RVU_PRIV_PFX_SSO_CFG; 936 block->vf_lfcnt_reg = RVU_PRIV_HWVFX_SSO_CFG; 937 block->lfcfg_reg = SSO_PRIV_LFX_HWGRP_CFG; 938 block->msixcfg_reg = SSO_PRIV_LFX_HWGRP_INT_CFG; 939 block->lfreset_reg = SSO_AF_LF_HWGRP_RST; 940 sprintf(block->name, "SSO GROUP"); 941 err = rvu_alloc_bitmap(&block->lf); 942 if (err) 943 return err; 944 945 ssow: 946 /* Init SSO workslot's bitmap */ 947 block = &hw->block[BLKADDR_SSOW]; 948 if (!block->implemented) 949 goto tim; 950 block->lf.max = (cfg >> 56) & 0xFF; 951 block->addr = BLKADDR_SSOW; 952 block->type = BLKTYPE_SSOW; 953 block->multislot = true; 954 block->lfshift = 3; 955 block->lookup_reg = SSOW_AF_RVU_LF_HWS_CFG_DEBUG; 956 block->pf_lfcnt_reg = RVU_PRIV_PFX_SSOW_CFG; 957 block->vf_lfcnt_reg = RVU_PRIV_HWVFX_SSOW_CFG; 958 block->lfcfg_reg = SSOW_PRIV_LFX_HWS_CFG; 959 block->msixcfg_reg = SSOW_PRIV_LFX_HWS_INT_CFG; 960 block->lfreset_reg = SSOW_AF_LF_HWS_RST; 961 sprintf(block->name, "SSOWS"); 962 err = rvu_alloc_bitmap(&block->lf); 963 if (err) 964 return err; 965 966 tim: 967 /* Init TIM LF's bitmap */ 968 block = &hw->block[BLKADDR_TIM]; 969 if (!block->implemented) 970 goto cpt; 971 cfg = rvu_read64(rvu, BLKADDR_TIM, TIM_AF_CONST); 972 block->lf.max = cfg & 0xFFFF; 973 block->addr = BLKADDR_TIM; 974 block->type = BLKTYPE_TIM; 975 block->multislot = true; 976 block->lfshift = 3; 977 block->lookup_reg = TIM_AF_RVU_LF_CFG_DEBUG; 978 block->pf_lfcnt_reg = RVU_PRIV_PFX_TIM_CFG; 979 block->vf_lfcnt_reg = RVU_PRIV_HWVFX_TIM_CFG; 980 block->lfcfg_reg = TIM_PRIV_LFX_CFG; 981 block->msixcfg_reg = TIM_PRIV_LFX_INT_CFG; 982 block->lfreset_reg = TIM_AF_LF_RST; 983 sprintf(block->name, "TIM"); 984 err = rvu_alloc_bitmap(&block->lf); 985 if (err) 986 return err; 987 988 cpt: 989 err = rvu_setup_cpt_hw_resource(rvu, BLKADDR_CPT0); 990 if (err) 991 return err; 992 err = rvu_setup_cpt_hw_resource(rvu, BLKADDR_CPT1); 993 if (err) 994 return err; 995 996 /* Allocate memory for PFVF data */ 997 rvu->pf = devm_kcalloc(rvu->dev, hw->total_pfs, 998 sizeof(struct rvu_pfvf), GFP_KERNEL); 999 if (!rvu->pf) 1000 return -ENOMEM; 1001 1002 rvu->hwvf = devm_kcalloc(rvu->dev, hw->total_vfs, 1003 sizeof(struct rvu_pfvf), GFP_KERNEL); 1004 if (!rvu->hwvf) 1005 return -ENOMEM; 1006 1007 mutex_init(&rvu->rsrc_lock); 1008 1009 rvu_fwdata_init(rvu); 1010 1011 err = rvu_setup_msix_resources(rvu); 1012 if (err) 1013 return err; 1014 1015 for (blkid = 0; blkid < BLK_COUNT; blkid++) { 1016 block = &hw->block[blkid]; 1017 if (!block->lf.bmap) 1018 continue; 1019 1020 /* Allocate memory for block LF/slot to pcifunc mapping info */ 1021 block->fn_map = devm_kcalloc(rvu->dev, block->lf.max, 1022 sizeof(u16), GFP_KERNEL); 1023 if (!block->fn_map) { 1024 err = -ENOMEM; 1025 goto msix_err; 1026 } 1027 1028 /* Scan all blocks to check if low level firmware has 1029 * already provisioned any of the resources to a PF/VF. 1030 */ 1031 rvu_scan_block(rvu, block); 1032 } 1033 1034 err = rvu_set_channels_base(rvu); 1035 if (err) 1036 goto msix_err; 1037 1038 err = rvu_npc_init(rvu); 1039 if (err) 1040 goto npc_err; 1041 1042 err = rvu_cgx_init(rvu); 1043 if (err) 1044 goto cgx_err; 1045 1046 /* Assign MACs for CGX mapped functions */ 1047 rvu_setup_pfvf_macaddress(rvu); 1048 1049 err = rvu_npa_init(rvu); 1050 if (err) 1051 goto npa_err; 1052 1053 rvu_get_lbk_bufsize(rvu); 1054 1055 err = rvu_nix_init(rvu); 1056 if (err) 1057 goto nix_err; 1058 1059 rvu_program_channels(rvu); 1060 1061 return 0; 1062 1063 nix_err: 1064 rvu_nix_freemem(rvu); 1065 npa_err: 1066 rvu_npa_freemem(rvu); 1067 cgx_err: 1068 rvu_cgx_exit(rvu); 1069 npc_err: 1070 rvu_npc_freemem(rvu); 1071 rvu_fwdata_exit(rvu); 1072 msix_err: 1073 rvu_reset_msix(rvu); 1074 return err; 1075 } 1076 1077 /* NPA and NIX admin queue APIs */ 1078 void rvu_aq_free(struct rvu *rvu, struct admin_queue *aq) 1079 { 1080 if (!aq) 1081 return; 1082 1083 qmem_free(rvu->dev, aq->inst); 1084 qmem_free(rvu->dev, aq->res); 1085 devm_kfree(rvu->dev, aq); 1086 } 1087 1088 int rvu_aq_alloc(struct rvu *rvu, struct admin_queue **ad_queue, 1089 int qsize, int inst_size, int res_size) 1090 { 1091 struct admin_queue *aq; 1092 int err; 1093 1094 *ad_queue = devm_kzalloc(rvu->dev, sizeof(*aq), GFP_KERNEL); 1095 if (!*ad_queue) 1096 return -ENOMEM; 1097 aq = *ad_queue; 1098 1099 /* Alloc memory for instructions i.e AQ */ 1100 err = qmem_alloc(rvu->dev, &aq->inst, qsize, inst_size); 1101 if (err) { 1102 devm_kfree(rvu->dev, aq); 1103 return err; 1104 } 1105 1106 /* Alloc memory for results */ 1107 err = qmem_alloc(rvu->dev, &aq->res, qsize, res_size); 1108 if (err) { 1109 rvu_aq_free(rvu, aq); 1110 return err; 1111 } 1112 1113 spin_lock_init(&aq->lock); 1114 return 0; 1115 } 1116 1117 int rvu_mbox_handler_ready(struct rvu *rvu, struct msg_req *req, 1118 struct ready_msg_rsp *rsp) 1119 { 1120 if (rvu->fwdata) { 1121 rsp->rclk_freq = rvu->fwdata->rclk; 1122 rsp->sclk_freq = rvu->fwdata->sclk; 1123 } 1124 return 0; 1125 } 1126 1127 /* Get current count of a RVU block's LF/slots 1128 * provisioned to a given RVU func. 1129 */ 1130 u16 rvu_get_rsrc_mapcount(struct rvu_pfvf *pfvf, int blkaddr) 1131 { 1132 switch (blkaddr) { 1133 case BLKADDR_NPA: 1134 return pfvf->npalf ? 1 : 0; 1135 case BLKADDR_NIX0: 1136 case BLKADDR_NIX1: 1137 return pfvf->nixlf ? 1 : 0; 1138 case BLKADDR_SSO: 1139 return pfvf->sso; 1140 case BLKADDR_SSOW: 1141 return pfvf->ssow; 1142 case BLKADDR_TIM: 1143 return pfvf->timlfs; 1144 case BLKADDR_CPT0: 1145 return pfvf->cptlfs; 1146 case BLKADDR_CPT1: 1147 return pfvf->cpt1_lfs; 1148 } 1149 return 0; 1150 } 1151 1152 /* Return true if LFs of block type are attached to pcifunc */ 1153 static bool is_blktype_attached(struct rvu_pfvf *pfvf, int blktype) 1154 { 1155 switch (blktype) { 1156 case BLKTYPE_NPA: 1157 return pfvf->npalf ? 1 : 0; 1158 case BLKTYPE_NIX: 1159 return pfvf->nixlf ? 1 : 0; 1160 case BLKTYPE_SSO: 1161 return !!pfvf->sso; 1162 case BLKTYPE_SSOW: 1163 return !!pfvf->ssow; 1164 case BLKTYPE_TIM: 1165 return !!pfvf->timlfs; 1166 case BLKTYPE_CPT: 1167 return pfvf->cptlfs || pfvf->cpt1_lfs; 1168 } 1169 1170 return false; 1171 } 1172 1173 bool is_pffunc_map_valid(struct rvu *rvu, u16 pcifunc, int blktype) 1174 { 1175 struct rvu_pfvf *pfvf; 1176 1177 if (!is_pf_func_valid(rvu, pcifunc)) 1178 return false; 1179 1180 pfvf = rvu_get_pfvf(rvu, pcifunc); 1181 1182 /* Check if this PFFUNC has a LF of type blktype attached */ 1183 if (!is_blktype_attached(pfvf, blktype)) 1184 return false; 1185 1186 return true; 1187 } 1188 1189 static int rvu_lookup_rsrc(struct rvu *rvu, struct rvu_block *block, 1190 int pcifunc, int slot) 1191 { 1192 u64 val; 1193 1194 val = ((u64)pcifunc << 24) | (slot << 16) | (1ULL << 13); 1195 rvu_write64(rvu, block->addr, block->lookup_reg, val); 1196 /* Wait for the lookup to finish */ 1197 /* TODO: put some timeout here */ 1198 while (rvu_read64(rvu, block->addr, block->lookup_reg) & (1ULL << 13)) 1199 ; 1200 1201 val = rvu_read64(rvu, block->addr, block->lookup_reg); 1202 1203 /* Check LF valid bit */ 1204 if (!(val & (1ULL << 12))) 1205 return -1; 1206 1207 return (val & 0xFFF); 1208 } 1209 1210 static void rvu_detach_block(struct rvu *rvu, int pcifunc, int blktype) 1211 { 1212 struct rvu_pfvf *pfvf = rvu_get_pfvf(rvu, pcifunc); 1213 struct rvu_hwinfo *hw = rvu->hw; 1214 struct rvu_block *block; 1215 int slot, lf, num_lfs; 1216 int blkaddr; 1217 1218 blkaddr = rvu_get_blkaddr(rvu, blktype, pcifunc); 1219 if (blkaddr < 0) 1220 return; 1221 1222 if (blktype == BLKTYPE_NIX) 1223 rvu_nix_reset_mac(pfvf, pcifunc); 1224 1225 block = &hw->block[blkaddr]; 1226 1227 num_lfs = rvu_get_rsrc_mapcount(pfvf, block->addr); 1228 if (!num_lfs) 1229 return; 1230 1231 for (slot = 0; slot < num_lfs; slot++) { 1232 lf = rvu_lookup_rsrc(rvu, block, pcifunc, slot); 1233 if (lf < 0) /* This should never happen */ 1234 continue; 1235 1236 /* Disable the LF */ 1237 rvu_write64(rvu, blkaddr, block->lfcfg_reg | 1238 (lf << block->lfshift), 0x00ULL); 1239 1240 /* Update SW maintained mapping info as well */ 1241 rvu_update_rsrc_map(rvu, pfvf, block, 1242 pcifunc, lf, false); 1243 1244 /* Free the resource */ 1245 rvu_free_rsrc(&block->lf, lf); 1246 1247 /* Clear MSIX vector offset for this LF */ 1248 rvu_clear_msix_offset(rvu, pfvf, block, lf); 1249 } 1250 } 1251 1252 static int rvu_detach_rsrcs(struct rvu *rvu, struct rsrc_detach *detach, 1253 u16 pcifunc) 1254 { 1255 struct rvu_hwinfo *hw = rvu->hw; 1256 bool detach_all = true; 1257 struct rvu_block *block; 1258 int blkid; 1259 1260 mutex_lock(&rvu->rsrc_lock); 1261 1262 /* Check for partial resource detach */ 1263 if (detach && detach->partial) 1264 detach_all = false; 1265 1266 /* Check for RVU block's LFs attached to this func, 1267 * if so, detach them. 1268 */ 1269 for (blkid = 0; blkid < BLK_COUNT; blkid++) { 1270 block = &hw->block[blkid]; 1271 if (!block->lf.bmap) 1272 continue; 1273 if (!detach_all && detach) { 1274 if (blkid == BLKADDR_NPA && !detach->npalf) 1275 continue; 1276 else if ((blkid == BLKADDR_NIX0) && !detach->nixlf) 1277 continue; 1278 else if ((blkid == BLKADDR_NIX1) && !detach->nixlf) 1279 continue; 1280 else if ((blkid == BLKADDR_SSO) && !detach->sso) 1281 continue; 1282 else if ((blkid == BLKADDR_SSOW) && !detach->ssow) 1283 continue; 1284 else if ((blkid == BLKADDR_TIM) && !detach->timlfs) 1285 continue; 1286 else if ((blkid == BLKADDR_CPT0) && !detach->cptlfs) 1287 continue; 1288 else if ((blkid == BLKADDR_CPT1) && !detach->cptlfs) 1289 continue; 1290 } 1291 rvu_detach_block(rvu, pcifunc, block->type); 1292 } 1293 1294 mutex_unlock(&rvu->rsrc_lock); 1295 return 0; 1296 } 1297 1298 int rvu_mbox_handler_detach_resources(struct rvu *rvu, 1299 struct rsrc_detach *detach, 1300 struct msg_rsp *rsp) 1301 { 1302 return rvu_detach_rsrcs(rvu, detach, detach->hdr.pcifunc); 1303 } 1304 1305 static int rvu_get_nix_blkaddr(struct rvu *rvu, u16 pcifunc) 1306 { 1307 struct rvu_pfvf *pfvf = rvu_get_pfvf(rvu, pcifunc); 1308 int blkaddr = BLKADDR_NIX0, vf; 1309 struct rvu_pfvf *pf; 1310 1311 /* All CGX mapped PFs are set with assigned NIX block during init */ 1312 if (is_pf_cgxmapped(rvu, rvu_get_pf(pcifunc))) { 1313 pf = rvu_get_pfvf(rvu, pcifunc & ~RVU_PFVF_FUNC_MASK); 1314 blkaddr = pf->nix_blkaddr; 1315 } else if (is_afvf(pcifunc)) { 1316 vf = pcifunc - 1; 1317 /* Assign NIX based on VF number. All even numbered VFs get 1318 * NIX0 and odd numbered gets NIX1 1319 */ 1320 blkaddr = (vf & 1) ? BLKADDR_NIX1 : BLKADDR_NIX0; 1321 /* NIX1 is not present on all silicons */ 1322 if (!is_block_implemented(rvu->hw, BLKADDR_NIX1)) 1323 blkaddr = BLKADDR_NIX0; 1324 } 1325 1326 switch (blkaddr) { 1327 case BLKADDR_NIX1: 1328 pfvf->nix_blkaddr = BLKADDR_NIX1; 1329 pfvf->nix_rx_intf = NIX_INTFX_RX(1); 1330 pfvf->nix_tx_intf = NIX_INTFX_TX(1); 1331 break; 1332 case BLKADDR_NIX0: 1333 default: 1334 pfvf->nix_blkaddr = BLKADDR_NIX0; 1335 pfvf->nix_rx_intf = NIX_INTFX_RX(0); 1336 pfvf->nix_tx_intf = NIX_INTFX_TX(0); 1337 break; 1338 } 1339 1340 return pfvf->nix_blkaddr; 1341 } 1342 1343 static int rvu_get_attach_blkaddr(struct rvu *rvu, int blktype, 1344 u16 pcifunc, struct rsrc_attach *attach) 1345 { 1346 int blkaddr; 1347 1348 switch (blktype) { 1349 case BLKTYPE_NIX: 1350 blkaddr = rvu_get_nix_blkaddr(rvu, pcifunc); 1351 break; 1352 case BLKTYPE_CPT: 1353 if (attach->hdr.ver < RVU_MULTI_BLK_VER) 1354 return rvu_get_blkaddr(rvu, blktype, 0); 1355 blkaddr = attach->cpt_blkaddr ? attach->cpt_blkaddr : 1356 BLKADDR_CPT0; 1357 if (blkaddr != BLKADDR_CPT0 && blkaddr != BLKADDR_CPT1) 1358 return -ENODEV; 1359 break; 1360 default: 1361 return rvu_get_blkaddr(rvu, blktype, 0); 1362 } 1363 1364 if (is_block_implemented(rvu->hw, blkaddr)) 1365 return blkaddr; 1366 1367 return -ENODEV; 1368 } 1369 1370 static void rvu_attach_block(struct rvu *rvu, int pcifunc, int blktype, 1371 int num_lfs, struct rsrc_attach *attach) 1372 { 1373 struct rvu_pfvf *pfvf = rvu_get_pfvf(rvu, pcifunc); 1374 struct rvu_hwinfo *hw = rvu->hw; 1375 struct rvu_block *block; 1376 int slot, lf; 1377 int blkaddr; 1378 u64 cfg; 1379 1380 if (!num_lfs) 1381 return; 1382 1383 blkaddr = rvu_get_attach_blkaddr(rvu, blktype, pcifunc, attach); 1384 if (blkaddr < 0) 1385 return; 1386 1387 block = &hw->block[blkaddr]; 1388 if (!block->lf.bmap) 1389 return; 1390 1391 for (slot = 0; slot < num_lfs; slot++) { 1392 /* Allocate the resource */ 1393 lf = rvu_alloc_rsrc(&block->lf); 1394 if (lf < 0) 1395 return; 1396 1397 cfg = (1ULL << 63) | (pcifunc << 8) | slot; 1398 rvu_write64(rvu, blkaddr, block->lfcfg_reg | 1399 (lf << block->lfshift), cfg); 1400 rvu_update_rsrc_map(rvu, pfvf, block, 1401 pcifunc, lf, true); 1402 1403 /* Set start MSIX vector for this LF within this PF/VF */ 1404 rvu_set_msix_offset(rvu, pfvf, block, lf); 1405 } 1406 } 1407 1408 static int rvu_check_rsrc_availability(struct rvu *rvu, 1409 struct rsrc_attach *req, u16 pcifunc) 1410 { 1411 struct rvu_pfvf *pfvf = rvu_get_pfvf(rvu, pcifunc); 1412 int free_lfs, mappedlfs, blkaddr; 1413 struct rvu_hwinfo *hw = rvu->hw; 1414 struct rvu_block *block; 1415 1416 /* Only one NPA LF can be attached */ 1417 if (req->npalf && !is_blktype_attached(pfvf, BLKTYPE_NPA)) { 1418 block = &hw->block[BLKADDR_NPA]; 1419 free_lfs = rvu_rsrc_free_count(&block->lf); 1420 if (!free_lfs) 1421 goto fail; 1422 } else if (req->npalf) { 1423 dev_err(&rvu->pdev->dev, 1424 "Func 0x%x: Invalid req, already has NPA\n", 1425 pcifunc); 1426 return -EINVAL; 1427 } 1428 1429 /* Only one NIX LF can be attached */ 1430 if (req->nixlf && !is_blktype_attached(pfvf, BLKTYPE_NIX)) { 1431 blkaddr = rvu_get_attach_blkaddr(rvu, BLKTYPE_NIX, 1432 pcifunc, req); 1433 if (blkaddr < 0) 1434 return blkaddr; 1435 block = &hw->block[blkaddr]; 1436 free_lfs = rvu_rsrc_free_count(&block->lf); 1437 if (!free_lfs) 1438 goto fail; 1439 } else if (req->nixlf) { 1440 dev_err(&rvu->pdev->dev, 1441 "Func 0x%x: Invalid req, already has NIX\n", 1442 pcifunc); 1443 return -EINVAL; 1444 } 1445 1446 if (req->sso) { 1447 block = &hw->block[BLKADDR_SSO]; 1448 /* Is request within limits ? */ 1449 if (req->sso > block->lf.max) { 1450 dev_err(&rvu->pdev->dev, 1451 "Func 0x%x: Invalid SSO req, %d > max %d\n", 1452 pcifunc, req->sso, block->lf.max); 1453 return -EINVAL; 1454 } 1455 mappedlfs = rvu_get_rsrc_mapcount(pfvf, block->addr); 1456 free_lfs = rvu_rsrc_free_count(&block->lf); 1457 /* Check if additional resources are available */ 1458 if (req->sso > mappedlfs && 1459 ((req->sso - mappedlfs) > free_lfs)) 1460 goto fail; 1461 } 1462 1463 if (req->ssow) { 1464 block = &hw->block[BLKADDR_SSOW]; 1465 if (req->ssow > block->lf.max) { 1466 dev_err(&rvu->pdev->dev, 1467 "Func 0x%x: Invalid SSOW req, %d > max %d\n", 1468 pcifunc, req->sso, block->lf.max); 1469 return -EINVAL; 1470 } 1471 mappedlfs = rvu_get_rsrc_mapcount(pfvf, block->addr); 1472 free_lfs = rvu_rsrc_free_count(&block->lf); 1473 if (req->ssow > mappedlfs && 1474 ((req->ssow - mappedlfs) > free_lfs)) 1475 goto fail; 1476 } 1477 1478 if (req->timlfs) { 1479 block = &hw->block[BLKADDR_TIM]; 1480 if (req->timlfs > block->lf.max) { 1481 dev_err(&rvu->pdev->dev, 1482 "Func 0x%x: Invalid TIMLF req, %d > max %d\n", 1483 pcifunc, req->timlfs, block->lf.max); 1484 return -EINVAL; 1485 } 1486 mappedlfs = rvu_get_rsrc_mapcount(pfvf, block->addr); 1487 free_lfs = rvu_rsrc_free_count(&block->lf); 1488 if (req->timlfs > mappedlfs && 1489 ((req->timlfs - mappedlfs) > free_lfs)) 1490 goto fail; 1491 } 1492 1493 if (req->cptlfs) { 1494 blkaddr = rvu_get_attach_blkaddr(rvu, BLKTYPE_CPT, 1495 pcifunc, req); 1496 if (blkaddr < 0) 1497 return blkaddr; 1498 block = &hw->block[blkaddr]; 1499 if (req->cptlfs > block->lf.max) { 1500 dev_err(&rvu->pdev->dev, 1501 "Func 0x%x: Invalid CPTLF req, %d > max %d\n", 1502 pcifunc, req->cptlfs, block->lf.max); 1503 return -EINVAL; 1504 } 1505 mappedlfs = rvu_get_rsrc_mapcount(pfvf, block->addr); 1506 free_lfs = rvu_rsrc_free_count(&block->lf); 1507 if (req->cptlfs > mappedlfs && 1508 ((req->cptlfs - mappedlfs) > free_lfs)) 1509 goto fail; 1510 } 1511 1512 return 0; 1513 1514 fail: 1515 dev_info(rvu->dev, "Request for %s failed\n", block->name); 1516 return -ENOSPC; 1517 } 1518 1519 static bool rvu_attach_from_same_block(struct rvu *rvu, int blktype, 1520 struct rsrc_attach *attach) 1521 { 1522 int blkaddr, num_lfs; 1523 1524 blkaddr = rvu_get_attach_blkaddr(rvu, blktype, 1525 attach->hdr.pcifunc, attach); 1526 if (blkaddr < 0) 1527 return false; 1528 1529 num_lfs = rvu_get_rsrc_mapcount(rvu_get_pfvf(rvu, attach->hdr.pcifunc), 1530 blkaddr); 1531 /* Requester already has LFs from given block ? */ 1532 return !!num_lfs; 1533 } 1534 1535 int rvu_mbox_handler_attach_resources(struct rvu *rvu, 1536 struct rsrc_attach *attach, 1537 struct msg_rsp *rsp) 1538 { 1539 u16 pcifunc = attach->hdr.pcifunc; 1540 int err; 1541 1542 /* If first request, detach all existing attached resources */ 1543 if (!attach->modify) 1544 rvu_detach_rsrcs(rvu, NULL, pcifunc); 1545 1546 mutex_lock(&rvu->rsrc_lock); 1547 1548 /* Check if the request can be accommodated */ 1549 err = rvu_check_rsrc_availability(rvu, attach, pcifunc); 1550 if (err) 1551 goto exit; 1552 1553 /* Now attach the requested resources */ 1554 if (attach->npalf) 1555 rvu_attach_block(rvu, pcifunc, BLKTYPE_NPA, 1, attach); 1556 1557 if (attach->nixlf) 1558 rvu_attach_block(rvu, pcifunc, BLKTYPE_NIX, 1, attach); 1559 1560 if (attach->sso) { 1561 /* RVU func doesn't know which exact LF or slot is attached 1562 * to it, it always sees as slot 0,1,2. So for a 'modify' 1563 * request, simply detach all existing attached LFs/slots 1564 * and attach a fresh. 1565 */ 1566 if (attach->modify) 1567 rvu_detach_block(rvu, pcifunc, BLKTYPE_SSO); 1568 rvu_attach_block(rvu, pcifunc, BLKTYPE_SSO, 1569 attach->sso, attach); 1570 } 1571 1572 if (attach->ssow) { 1573 if (attach->modify) 1574 rvu_detach_block(rvu, pcifunc, BLKTYPE_SSOW); 1575 rvu_attach_block(rvu, pcifunc, BLKTYPE_SSOW, 1576 attach->ssow, attach); 1577 } 1578 1579 if (attach->timlfs) { 1580 if (attach->modify) 1581 rvu_detach_block(rvu, pcifunc, BLKTYPE_TIM); 1582 rvu_attach_block(rvu, pcifunc, BLKTYPE_TIM, 1583 attach->timlfs, attach); 1584 } 1585 1586 if (attach->cptlfs) { 1587 if (attach->modify && 1588 rvu_attach_from_same_block(rvu, BLKTYPE_CPT, attach)) 1589 rvu_detach_block(rvu, pcifunc, BLKTYPE_CPT); 1590 rvu_attach_block(rvu, pcifunc, BLKTYPE_CPT, 1591 attach->cptlfs, attach); 1592 } 1593 1594 exit: 1595 mutex_unlock(&rvu->rsrc_lock); 1596 return err; 1597 } 1598 1599 static u16 rvu_get_msix_offset(struct rvu *rvu, struct rvu_pfvf *pfvf, 1600 int blkaddr, int lf) 1601 { 1602 u16 vec; 1603 1604 if (lf < 0) 1605 return MSIX_VECTOR_INVALID; 1606 1607 for (vec = 0; vec < pfvf->msix.max; vec++) { 1608 if (pfvf->msix_lfmap[vec] == MSIX_BLKLF(blkaddr, lf)) 1609 return vec; 1610 } 1611 return MSIX_VECTOR_INVALID; 1612 } 1613 1614 static void rvu_set_msix_offset(struct rvu *rvu, struct rvu_pfvf *pfvf, 1615 struct rvu_block *block, int lf) 1616 { 1617 u16 nvecs, vec, offset; 1618 u64 cfg; 1619 1620 cfg = rvu_read64(rvu, block->addr, block->msixcfg_reg | 1621 (lf << block->lfshift)); 1622 nvecs = (cfg >> 12) & 0xFF; 1623 1624 /* Check and alloc MSIX vectors, must be contiguous */ 1625 if (!rvu_rsrc_check_contig(&pfvf->msix, nvecs)) 1626 return; 1627 1628 offset = rvu_alloc_rsrc_contig(&pfvf->msix, nvecs); 1629 1630 /* Config MSIX offset in LF */ 1631 rvu_write64(rvu, block->addr, block->msixcfg_reg | 1632 (lf << block->lfshift), (cfg & ~0x7FFULL) | offset); 1633 1634 /* Update the bitmap as well */ 1635 for (vec = 0; vec < nvecs; vec++) 1636 pfvf->msix_lfmap[offset + vec] = MSIX_BLKLF(block->addr, lf); 1637 } 1638 1639 static void rvu_clear_msix_offset(struct rvu *rvu, struct rvu_pfvf *pfvf, 1640 struct rvu_block *block, int lf) 1641 { 1642 u16 nvecs, vec, offset; 1643 u64 cfg; 1644 1645 cfg = rvu_read64(rvu, block->addr, block->msixcfg_reg | 1646 (lf << block->lfshift)); 1647 nvecs = (cfg >> 12) & 0xFF; 1648 1649 /* Clear MSIX offset in LF */ 1650 rvu_write64(rvu, block->addr, block->msixcfg_reg | 1651 (lf << block->lfshift), cfg & ~0x7FFULL); 1652 1653 offset = rvu_get_msix_offset(rvu, pfvf, block->addr, lf); 1654 1655 /* Update the mapping */ 1656 for (vec = 0; vec < nvecs; vec++) 1657 pfvf->msix_lfmap[offset + vec] = 0; 1658 1659 /* Free the same in MSIX bitmap */ 1660 rvu_free_rsrc_contig(&pfvf->msix, nvecs, offset); 1661 } 1662 1663 int rvu_mbox_handler_msix_offset(struct rvu *rvu, struct msg_req *req, 1664 struct msix_offset_rsp *rsp) 1665 { 1666 struct rvu_hwinfo *hw = rvu->hw; 1667 u16 pcifunc = req->hdr.pcifunc; 1668 struct rvu_pfvf *pfvf; 1669 int lf, slot, blkaddr; 1670 1671 pfvf = rvu_get_pfvf(rvu, pcifunc); 1672 if (!pfvf->msix.bmap) 1673 return 0; 1674 1675 /* Set MSIX offsets for each block's LFs attached to this PF/VF */ 1676 lf = rvu_get_lf(rvu, &hw->block[BLKADDR_NPA], pcifunc, 0); 1677 rsp->npa_msixoff = rvu_get_msix_offset(rvu, pfvf, BLKADDR_NPA, lf); 1678 1679 /* Get BLKADDR from which LFs are attached to pcifunc */ 1680 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NIX, pcifunc); 1681 if (blkaddr < 0) { 1682 rsp->nix_msixoff = MSIX_VECTOR_INVALID; 1683 } else { 1684 lf = rvu_get_lf(rvu, &hw->block[blkaddr], pcifunc, 0); 1685 rsp->nix_msixoff = rvu_get_msix_offset(rvu, pfvf, blkaddr, lf); 1686 } 1687 1688 rsp->sso = pfvf->sso; 1689 for (slot = 0; slot < rsp->sso; slot++) { 1690 lf = rvu_get_lf(rvu, &hw->block[BLKADDR_SSO], pcifunc, slot); 1691 rsp->sso_msixoff[slot] = 1692 rvu_get_msix_offset(rvu, pfvf, BLKADDR_SSO, lf); 1693 } 1694 1695 rsp->ssow = pfvf->ssow; 1696 for (slot = 0; slot < rsp->ssow; slot++) { 1697 lf = rvu_get_lf(rvu, &hw->block[BLKADDR_SSOW], pcifunc, slot); 1698 rsp->ssow_msixoff[slot] = 1699 rvu_get_msix_offset(rvu, pfvf, BLKADDR_SSOW, lf); 1700 } 1701 1702 rsp->timlfs = pfvf->timlfs; 1703 for (slot = 0; slot < rsp->timlfs; slot++) { 1704 lf = rvu_get_lf(rvu, &hw->block[BLKADDR_TIM], pcifunc, slot); 1705 rsp->timlf_msixoff[slot] = 1706 rvu_get_msix_offset(rvu, pfvf, BLKADDR_TIM, lf); 1707 } 1708 1709 rsp->cptlfs = pfvf->cptlfs; 1710 for (slot = 0; slot < rsp->cptlfs; slot++) { 1711 lf = rvu_get_lf(rvu, &hw->block[BLKADDR_CPT0], pcifunc, slot); 1712 rsp->cptlf_msixoff[slot] = 1713 rvu_get_msix_offset(rvu, pfvf, BLKADDR_CPT0, lf); 1714 } 1715 1716 rsp->cpt1_lfs = pfvf->cpt1_lfs; 1717 for (slot = 0; slot < rsp->cpt1_lfs; slot++) { 1718 lf = rvu_get_lf(rvu, &hw->block[BLKADDR_CPT1], pcifunc, slot); 1719 rsp->cpt1_lf_msixoff[slot] = 1720 rvu_get_msix_offset(rvu, pfvf, BLKADDR_CPT1, lf); 1721 } 1722 1723 return 0; 1724 } 1725 1726 int rvu_mbox_handler_vf_flr(struct rvu *rvu, struct msg_req *req, 1727 struct msg_rsp *rsp) 1728 { 1729 u16 pcifunc = req->hdr.pcifunc; 1730 u16 vf, numvfs; 1731 u64 cfg; 1732 1733 vf = pcifunc & RVU_PFVF_FUNC_MASK; 1734 cfg = rvu_read64(rvu, BLKADDR_RVUM, 1735 RVU_PRIV_PFX_CFG(rvu_get_pf(pcifunc))); 1736 numvfs = (cfg >> 12) & 0xFF; 1737 1738 if (vf && vf <= numvfs) 1739 __rvu_flr_handler(rvu, pcifunc); 1740 else 1741 return RVU_INVALID_VF_ID; 1742 1743 return 0; 1744 } 1745 1746 int rvu_mbox_handler_get_hw_cap(struct rvu *rvu, struct msg_req *req, 1747 struct get_hw_cap_rsp *rsp) 1748 { 1749 struct rvu_hwinfo *hw = rvu->hw; 1750 1751 rsp->nix_fixed_txschq_mapping = hw->cap.nix_fixed_txschq_mapping; 1752 rsp->nix_shaping = hw->cap.nix_shaping; 1753 1754 return 0; 1755 } 1756 1757 static int rvu_process_mbox_msg(struct otx2_mbox *mbox, int devid, 1758 struct mbox_msghdr *req) 1759 { 1760 struct rvu *rvu = pci_get_drvdata(mbox->pdev); 1761 1762 /* Check if valid, if not reply with a invalid msg */ 1763 if (req->sig != OTX2_MBOX_REQ_SIG) 1764 goto bad_message; 1765 1766 switch (req->id) { 1767 #define M(_name, _id, _fn_name, _req_type, _rsp_type) \ 1768 case _id: { \ 1769 struct _rsp_type *rsp; \ 1770 int err; \ 1771 \ 1772 rsp = (struct _rsp_type *)otx2_mbox_alloc_msg( \ 1773 mbox, devid, \ 1774 sizeof(struct _rsp_type)); \ 1775 /* some handlers should complete even if reply */ \ 1776 /* could not be allocated */ \ 1777 if (!rsp && \ 1778 _id != MBOX_MSG_DETACH_RESOURCES && \ 1779 _id != MBOX_MSG_NIX_TXSCH_FREE && \ 1780 _id != MBOX_MSG_VF_FLR) \ 1781 return -ENOMEM; \ 1782 if (rsp) { \ 1783 rsp->hdr.id = _id; \ 1784 rsp->hdr.sig = OTX2_MBOX_RSP_SIG; \ 1785 rsp->hdr.pcifunc = req->pcifunc; \ 1786 rsp->hdr.rc = 0; \ 1787 } \ 1788 \ 1789 err = rvu_mbox_handler_ ## _fn_name(rvu, \ 1790 (struct _req_type *)req, \ 1791 rsp); \ 1792 if (rsp && err) \ 1793 rsp->hdr.rc = err; \ 1794 \ 1795 trace_otx2_msg_process(mbox->pdev, _id, err); \ 1796 return rsp ? err : -ENOMEM; \ 1797 } 1798 MBOX_MESSAGES 1799 #undef M 1800 1801 bad_message: 1802 default: 1803 otx2_reply_invalid_msg(mbox, devid, req->pcifunc, req->id); 1804 return -ENODEV; 1805 } 1806 } 1807 1808 static void __rvu_mbox_handler(struct rvu_work *mwork, int type) 1809 { 1810 struct rvu *rvu = mwork->rvu; 1811 int offset, err, id, devid; 1812 struct otx2_mbox_dev *mdev; 1813 struct mbox_hdr *req_hdr; 1814 struct mbox_msghdr *msg; 1815 struct mbox_wq_info *mw; 1816 struct otx2_mbox *mbox; 1817 1818 switch (type) { 1819 case TYPE_AFPF: 1820 mw = &rvu->afpf_wq_info; 1821 break; 1822 case TYPE_AFVF: 1823 mw = &rvu->afvf_wq_info; 1824 break; 1825 default: 1826 return; 1827 } 1828 1829 devid = mwork - mw->mbox_wrk; 1830 mbox = &mw->mbox; 1831 mdev = &mbox->dev[devid]; 1832 1833 /* Process received mbox messages */ 1834 req_hdr = mdev->mbase + mbox->rx_start; 1835 if (mw->mbox_wrk[devid].num_msgs == 0) 1836 return; 1837 1838 offset = mbox->rx_start + ALIGN(sizeof(*req_hdr), MBOX_MSG_ALIGN); 1839 1840 for (id = 0; id < mw->mbox_wrk[devid].num_msgs; id++) { 1841 msg = mdev->mbase + offset; 1842 1843 /* Set which PF/VF sent this message based on mbox IRQ */ 1844 switch (type) { 1845 case TYPE_AFPF: 1846 msg->pcifunc &= 1847 ~(RVU_PFVF_PF_MASK << RVU_PFVF_PF_SHIFT); 1848 msg->pcifunc |= (devid << RVU_PFVF_PF_SHIFT); 1849 break; 1850 case TYPE_AFVF: 1851 msg->pcifunc &= 1852 ~(RVU_PFVF_FUNC_MASK << RVU_PFVF_FUNC_SHIFT); 1853 msg->pcifunc |= (devid << RVU_PFVF_FUNC_SHIFT) + 1; 1854 break; 1855 } 1856 1857 err = rvu_process_mbox_msg(mbox, devid, msg); 1858 if (!err) { 1859 offset = mbox->rx_start + msg->next_msgoff; 1860 continue; 1861 } 1862 1863 if (msg->pcifunc & RVU_PFVF_FUNC_MASK) 1864 dev_warn(rvu->dev, "Error %d when processing message %s (0x%x) from PF%d:VF%d\n", 1865 err, otx2_mbox_id2name(msg->id), 1866 msg->id, rvu_get_pf(msg->pcifunc), 1867 (msg->pcifunc & RVU_PFVF_FUNC_MASK) - 1); 1868 else 1869 dev_warn(rvu->dev, "Error %d when processing message %s (0x%x) from PF%d\n", 1870 err, otx2_mbox_id2name(msg->id), 1871 msg->id, devid); 1872 } 1873 mw->mbox_wrk[devid].num_msgs = 0; 1874 1875 /* Send mbox responses to VF/PF */ 1876 otx2_mbox_msg_send(mbox, devid); 1877 } 1878 1879 static inline void rvu_afpf_mbox_handler(struct work_struct *work) 1880 { 1881 struct rvu_work *mwork = container_of(work, struct rvu_work, work); 1882 1883 __rvu_mbox_handler(mwork, TYPE_AFPF); 1884 } 1885 1886 static inline void rvu_afvf_mbox_handler(struct work_struct *work) 1887 { 1888 struct rvu_work *mwork = container_of(work, struct rvu_work, work); 1889 1890 __rvu_mbox_handler(mwork, TYPE_AFVF); 1891 } 1892 1893 static void __rvu_mbox_up_handler(struct rvu_work *mwork, int type) 1894 { 1895 struct rvu *rvu = mwork->rvu; 1896 struct otx2_mbox_dev *mdev; 1897 struct mbox_hdr *rsp_hdr; 1898 struct mbox_msghdr *msg; 1899 struct mbox_wq_info *mw; 1900 struct otx2_mbox *mbox; 1901 int offset, id, devid; 1902 1903 switch (type) { 1904 case TYPE_AFPF: 1905 mw = &rvu->afpf_wq_info; 1906 break; 1907 case TYPE_AFVF: 1908 mw = &rvu->afvf_wq_info; 1909 break; 1910 default: 1911 return; 1912 } 1913 1914 devid = mwork - mw->mbox_wrk_up; 1915 mbox = &mw->mbox_up; 1916 mdev = &mbox->dev[devid]; 1917 1918 rsp_hdr = mdev->mbase + mbox->rx_start; 1919 if (mw->mbox_wrk_up[devid].up_num_msgs == 0) { 1920 dev_warn(rvu->dev, "mbox up handler: num_msgs = 0\n"); 1921 return; 1922 } 1923 1924 offset = mbox->rx_start + ALIGN(sizeof(*rsp_hdr), MBOX_MSG_ALIGN); 1925 1926 for (id = 0; id < mw->mbox_wrk_up[devid].up_num_msgs; id++) { 1927 msg = mdev->mbase + offset; 1928 1929 if (msg->id >= MBOX_MSG_MAX) { 1930 dev_err(rvu->dev, 1931 "Mbox msg with unknown ID 0x%x\n", msg->id); 1932 goto end; 1933 } 1934 1935 if (msg->sig != OTX2_MBOX_RSP_SIG) { 1936 dev_err(rvu->dev, 1937 "Mbox msg with wrong signature %x, ID 0x%x\n", 1938 msg->sig, msg->id); 1939 goto end; 1940 } 1941 1942 switch (msg->id) { 1943 case MBOX_MSG_CGX_LINK_EVENT: 1944 break; 1945 default: 1946 if (msg->rc) 1947 dev_err(rvu->dev, 1948 "Mbox msg response has err %d, ID 0x%x\n", 1949 msg->rc, msg->id); 1950 break; 1951 } 1952 end: 1953 offset = mbox->rx_start + msg->next_msgoff; 1954 mdev->msgs_acked++; 1955 } 1956 mw->mbox_wrk_up[devid].up_num_msgs = 0; 1957 1958 otx2_mbox_reset(mbox, devid); 1959 } 1960 1961 static inline void rvu_afpf_mbox_up_handler(struct work_struct *work) 1962 { 1963 struct rvu_work *mwork = container_of(work, struct rvu_work, work); 1964 1965 __rvu_mbox_up_handler(mwork, TYPE_AFPF); 1966 } 1967 1968 static inline void rvu_afvf_mbox_up_handler(struct work_struct *work) 1969 { 1970 struct rvu_work *mwork = container_of(work, struct rvu_work, work); 1971 1972 __rvu_mbox_up_handler(mwork, TYPE_AFVF); 1973 } 1974 1975 static int rvu_get_mbox_regions(struct rvu *rvu, void **mbox_addr, 1976 int num, int type) 1977 { 1978 struct rvu_hwinfo *hw = rvu->hw; 1979 int region; 1980 u64 bar4; 1981 1982 /* For cn10k platform VF mailbox regions of a PF follows after the 1983 * PF <-> AF mailbox region. Whereas for Octeontx2 it is read from 1984 * RVU_PF_VF_BAR4_ADDR register. 1985 */ 1986 if (type == TYPE_AFVF) { 1987 for (region = 0; region < num; region++) { 1988 if (hw->cap.per_pf_mbox_regs) { 1989 bar4 = rvu_read64(rvu, BLKADDR_RVUM, 1990 RVU_AF_PFX_BAR4_ADDR(0)) + 1991 MBOX_SIZE; 1992 bar4 += region * MBOX_SIZE; 1993 } else { 1994 bar4 = rvupf_read64(rvu, RVU_PF_VF_BAR4_ADDR); 1995 bar4 += region * MBOX_SIZE; 1996 } 1997 mbox_addr[region] = (void *)ioremap_wc(bar4, MBOX_SIZE); 1998 if (!mbox_addr[region]) 1999 goto error; 2000 } 2001 return 0; 2002 } 2003 2004 /* For cn10k platform AF <-> PF mailbox region of a PF is read from per 2005 * PF registers. Whereas for Octeontx2 it is read from 2006 * RVU_AF_PF_BAR4_ADDR register. 2007 */ 2008 for (region = 0; region < num; region++) { 2009 if (hw->cap.per_pf_mbox_regs) { 2010 bar4 = rvu_read64(rvu, BLKADDR_RVUM, 2011 RVU_AF_PFX_BAR4_ADDR(region)); 2012 } else { 2013 bar4 = rvu_read64(rvu, BLKADDR_RVUM, 2014 RVU_AF_PF_BAR4_ADDR); 2015 bar4 += region * MBOX_SIZE; 2016 } 2017 mbox_addr[region] = (void *)ioremap_wc(bar4, MBOX_SIZE); 2018 if (!mbox_addr[region]) 2019 goto error; 2020 } 2021 return 0; 2022 2023 error: 2024 while (region--) 2025 iounmap((void __iomem *)mbox_addr[region]); 2026 return -ENOMEM; 2027 } 2028 2029 static int rvu_mbox_init(struct rvu *rvu, struct mbox_wq_info *mw, 2030 int type, int num, 2031 void (mbox_handler)(struct work_struct *), 2032 void (mbox_up_handler)(struct work_struct *)) 2033 { 2034 int err = -EINVAL, i, dir, dir_up; 2035 void __iomem *reg_base; 2036 struct rvu_work *mwork; 2037 void **mbox_regions; 2038 const char *name; 2039 2040 mbox_regions = kcalloc(num, sizeof(void *), GFP_KERNEL); 2041 if (!mbox_regions) 2042 return -ENOMEM; 2043 2044 switch (type) { 2045 case TYPE_AFPF: 2046 name = "rvu_afpf_mailbox"; 2047 dir = MBOX_DIR_AFPF; 2048 dir_up = MBOX_DIR_AFPF_UP; 2049 reg_base = rvu->afreg_base; 2050 err = rvu_get_mbox_regions(rvu, mbox_regions, num, TYPE_AFPF); 2051 if (err) 2052 goto free_regions; 2053 break; 2054 case TYPE_AFVF: 2055 name = "rvu_afvf_mailbox"; 2056 dir = MBOX_DIR_PFVF; 2057 dir_up = MBOX_DIR_PFVF_UP; 2058 reg_base = rvu->pfreg_base; 2059 err = rvu_get_mbox_regions(rvu, mbox_regions, num, TYPE_AFVF); 2060 if (err) 2061 goto free_regions; 2062 break; 2063 default: 2064 return err; 2065 } 2066 2067 mw->mbox_wq = alloc_workqueue(name, 2068 WQ_UNBOUND | WQ_HIGHPRI | WQ_MEM_RECLAIM, 2069 num); 2070 if (!mw->mbox_wq) { 2071 err = -ENOMEM; 2072 goto unmap_regions; 2073 } 2074 2075 mw->mbox_wrk = devm_kcalloc(rvu->dev, num, 2076 sizeof(struct rvu_work), GFP_KERNEL); 2077 if (!mw->mbox_wrk) { 2078 err = -ENOMEM; 2079 goto exit; 2080 } 2081 2082 mw->mbox_wrk_up = devm_kcalloc(rvu->dev, num, 2083 sizeof(struct rvu_work), GFP_KERNEL); 2084 if (!mw->mbox_wrk_up) { 2085 err = -ENOMEM; 2086 goto exit; 2087 } 2088 2089 err = otx2_mbox_regions_init(&mw->mbox, mbox_regions, rvu->pdev, 2090 reg_base, dir, num); 2091 if (err) 2092 goto exit; 2093 2094 err = otx2_mbox_regions_init(&mw->mbox_up, mbox_regions, rvu->pdev, 2095 reg_base, dir_up, num); 2096 if (err) 2097 goto exit; 2098 2099 for (i = 0; i < num; i++) { 2100 mwork = &mw->mbox_wrk[i]; 2101 mwork->rvu = rvu; 2102 INIT_WORK(&mwork->work, mbox_handler); 2103 2104 mwork = &mw->mbox_wrk_up[i]; 2105 mwork->rvu = rvu; 2106 INIT_WORK(&mwork->work, mbox_up_handler); 2107 } 2108 kfree(mbox_regions); 2109 return 0; 2110 2111 exit: 2112 destroy_workqueue(mw->mbox_wq); 2113 unmap_regions: 2114 while (num--) 2115 iounmap((void __iomem *)mbox_regions[num]); 2116 free_regions: 2117 kfree(mbox_regions); 2118 return err; 2119 } 2120 2121 static void rvu_mbox_destroy(struct mbox_wq_info *mw) 2122 { 2123 struct otx2_mbox *mbox = &mw->mbox; 2124 struct otx2_mbox_dev *mdev; 2125 int devid; 2126 2127 if (mw->mbox_wq) { 2128 flush_workqueue(mw->mbox_wq); 2129 destroy_workqueue(mw->mbox_wq); 2130 mw->mbox_wq = NULL; 2131 } 2132 2133 for (devid = 0; devid < mbox->ndevs; devid++) { 2134 mdev = &mbox->dev[devid]; 2135 if (mdev->hwbase) 2136 iounmap((void __iomem *)mdev->hwbase); 2137 } 2138 2139 otx2_mbox_destroy(&mw->mbox); 2140 otx2_mbox_destroy(&mw->mbox_up); 2141 } 2142 2143 static void rvu_queue_work(struct mbox_wq_info *mw, int first, 2144 int mdevs, u64 intr) 2145 { 2146 struct otx2_mbox_dev *mdev; 2147 struct otx2_mbox *mbox; 2148 struct mbox_hdr *hdr; 2149 int i; 2150 2151 for (i = first; i < mdevs; i++) { 2152 /* start from 0 */ 2153 if (!(intr & BIT_ULL(i - first))) 2154 continue; 2155 2156 mbox = &mw->mbox; 2157 mdev = &mbox->dev[i]; 2158 hdr = mdev->mbase + mbox->rx_start; 2159 2160 /*The hdr->num_msgs is set to zero immediately in the interrupt 2161 * handler to ensure that it holds a correct value next time 2162 * when the interrupt handler is called. 2163 * pf->mbox.num_msgs holds the data for use in pfaf_mbox_handler 2164 * pf>mbox.up_num_msgs holds the data for use in 2165 * pfaf_mbox_up_handler. 2166 */ 2167 2168 if (hdr->num_msgs) { 2169 mw->mbox_wrk[i].num_msgs = hdr->num_msgs; 2170 hdr->num_msgs = 0; 2171 queue_work(mw->mbox_wq, &mw->mbox_wrk[i].work); 2172 } 2173 mbox = &mw->mbox_up; 2174 mdev = &mbox->dev[i]; 2175 hdr = mdev->mbase + mbox->rx_start; 2176 if (hdr->num_msgs) { 2177 mw->mbox_wrk_up[i].up_num_msgs = hdr->num_msgs; 2178 hdr->num_msgs = 0; 2179 queue_work(mw->mbox_wq, &mw->mbox_wrk_up[i].work); 2180 } 2181 } 2182 } 2183 2184 static irqreturn_t rvu_mbox_intr_handler(int irq, void *rvu_irq) 2185 { 2186 struct rvu *rvu = (struct rvu *)rvu_irq; 2187 int vfs = rvu->vfs; 2188 u64 intr; 2189 2190 intr = rvu_read64(rvu, BLKADDR_RVUM, RVU_AF_PFAF_MBOX_INT); 2191 /* Clear interrupts */ 2192 rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_PFAF_MBOX_INT, intr); 2193 if (intr) 2194 trace_otx2_msg_interrupt(rvu->pdev, "PF(s) to AF", intr); 2195 2196 /* Sync with mbox memory region */ 2197 rmb(); 2198 2199 rvu_queue_work(&rvu->afpf_wq_info, 0, rvu->hw->total_pfs, intr); 2200 2201 /* Handle VF interrupts */ 2202 if (vfs > 64) { 2203 intr = rvupf_read64(rvu, RVU_PF_VFPF_MBOX_INTX(1)); 2204 rvupf_write64(rvu, RVU_PF_VFPF_MBOX_INTX(1), intr); 2205 2206 rvu_queue_work(&rvu->afvf_wq_info, 64, vfs, intr); 2207 vfs -= 64; 2208 } 2209 2210 intr = rvupf_read64(rvu, RVU_PF_VFPF_MBOX_INTX(0)); 2211 rvupf_write64(rvu, RVU_PF_VFPF_MBOX_INTX(0), intr); 2212 if (intr) 2213 trace_otx2_msg_interrupt(rvu->pdev, "VF(s) to AF", intr); 2214 2215 rvu_queue_work(&rvu->afvf_wq_info, 0, vfs, intr); 2216 2217 return IRQ_HANDLED; 2218 } 2219 2220 static void rvu_enable_mbox_intr(struct rvu *rvu) 2221 { 2222 struct rvu_hwinfo *hw = rvu->hw; 2223 2224 /* Clear spurious irqs, if any */ 2225 rvu_write64(rvu, BLKADDR_RVUM, 2226 RVU_AF_PFAF_MBOX_INT, INTR_MASK(hw->total_pfs)); 2227 2228 /* Enable mailbox interrupt for all PFs except PF0 i.e AF itself */ 2229 rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_PFAF_MBOX_INT_ENA_W1S, 2230 INTR_MASK(hw->total_pfs) & ~1ULL); 2231 } 2232 2233 static void rvu_blklf_teardown(struct rvu *rvu, u16 pcifunc, u8 blkaddr) 2234 { 2235 struct rvu_block *block; 2236 int slot, lf, num_lfs; 2237 int err; 2238 2239 block = &rvu->hw->block[blkaddr]; 2240 num_lfs = rvu_get_rsrc_mapcount(rvu_get_pfvf(rvu, pcifunc), 2241 block->addr); 2242 if (!num_lfs) 2243 return; 2244 for (slot = 0; slot < num_lfs; slot++) { 2245 lf = rvu_get_lf(rvu, block, pcifunc, slot); 2246 if (lf < 0) 2247 continue; 2248 2249 /* Cleanup LF and reset it */ 2250 if (block->addr == BLKADDR_NIX0 || block->addr == BLKADDR_NIX1) 2251 rvu_nix_lf_teardown(rvu, pcifunc, block->addr, lf); 2252 else if (block->addr == BLKADDR_NPA) 2253 rvu_npa_lf_teardown(rvu, pcifunc, lf); 2254 else if ((block->addr == BLKADDR_CPT0) || 2255 (block->addr == BLKADDR_CPT1)) 2256 rvu_cpt_lf_teardown(rvu, pcifunc, lf, slot); 2257 2258 err = rvu_lf_reset(rvu, block, lf); 2259 if (err) { 2260 dev_err(rvu->dev, "Failed to reset blkaddr %d LF%d\n", 2261 block->addr, lf); 2262 } 2263 } 2264 } 2265 2266 static void __rvu_flr_handler(struct rvu *rvu, u16 pcifunc) 2267 { 2268 mutex_lock(&rvu->flr_lock); 2269 /* Reset order should reflect inter-block dependencies: 2270 * 1. Reset any packet/work sources (NIX, CPT, TIM) 2271 * 2. Flush and reset SSO/SSOW 2272 * 3. Cleanup pools (NPA) 2273 */ 2274 rvu_blklf_teardown(rvu, pcifunc, BLKADDR_NIX0); 2275 rvu_blklf_teardown(rvu, pcifunc, BLKADDR_NIX1); 2276 rvu_blklf_teardown(rvu, pcifunc, BLKADDR_CPT0); 2277 rvu_blklf_teardown(rvu, pcifunc, BLKADDR_CPT1); 2278 rvu_blklf_teardown(rvu, pcifunc, BLKADDR_TIM); 2279 rvu_blklf_teardown(rvu, pcifunc, BLKADDR_SSOW); 2280 rvu_blklf_teardown(rvu, pcifunc, BLKADDR_SSO); 2281 rvu_blklf_teardown(rvu, pcifunc, BLKADDR_NPA); 2282 rvu_detach_rsrcs(rvu, NULL, pcifunc); 2283 mutex_unlock(&rvu->flr_lock); 2284 } 2285 2286 static void rvu_afvf_flr_handler(struct rvu *rvu, int vf) 2287 { 2288 int reg = 0; 2289 2290 /* pcifunc = 0(PF0) | (vf + 1) */ 2291 __rvu_flr_handler(rvu, vf + 1); 2292 2293 if (vf >= 64) { 2294 reg = 1; 2295 vf = vf - 64; 2296 } 2297 2298 /* Signal FLR finish and enable IRQ */ 2299 rvupf_write64(rvu, RVU_PF_VFTRPENDX(reg), BIT_ULL(vf)); 2300 rvupf_write64(rvu, RVU_PF_VFFLR_INT_ENA_W1SX(reg), BIT_ULL(vf)); 2301 } 2302 2303 static void rvu_flr_handler(struct work_struct *work) 2304 { 2305 struct rvu_work *flrwork = container_of(work, struct rvu_work, work); 2306 struct rvu *rvu = flrwork->rvu; 2307 u16 pcifunc, numvfs, vf; 2308 u64 cfg; 2309 int pf; 2310 2311 pf = flrwork - rvu->flr_wrk; 2312 if (pf >= rvu->hw->total_pfs) { 2313 rvu_afvf_flr_handler(rvu, pf - rvu->hw->total_pfs); 2314 return; 2315 } 2316 2317 cfg = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_PFX_CFG(pf)); 2318 numvfs = (cfg >> 12) & 0xFF; 2319 pcifunc = pf << RVU_PFVF_PF_SHIFT; 2320 2321 for (vf = 0; vf < numvfs; vf++) 2322 __rvu_flr_handler(rvu, (pcifunc | (vf + 1))); 2323 2324 __rvu_flr_handler(rvu, pcifunc); 2325 2326 /* Signal FLR finish */ 2327 rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_PFTRPEND, BIT_ULL(pf)); 2328 2329 /* Enable interrupt */ 2330 rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_PFFLR_INT_ENA_W1S, BIT_ULL(pf)); 2331 } 2332 2333 static void rvu_afvf_queue_flr_work(struct rvu *rvu, int start_vf, int numvfs) 2334 { 2335 int dev, vf, reg = 0; 2336 u64 intr; 2337 2338 if (start_vf >= 64) 2339 reg = 1; 2340 2341 intr = rvupf_read64(rvu, RVU_PF_VFFLR_INTX(reg)); 2342 if (!intr) 2343 return; 2344 2345 for (vf = 0; vf < numvfs; vf++) { 2346 if (!(intr & BIT_ULL(vf))) 2347 continue; 2348 dev = vf + start_vf + rvu->hw->total_pfs; 2349 queue_work(rvu->flr_wq, &rvu->flr_wrk[dev].work); 2350 /* Clear and disable the interrupt */ 2351 rvupf_write64(rvu, RVU_PF_VFFLR_INTX(reg), BIT_ULL(vf)); 2352 rvupf_write64(rvu, RVU_PF_VFFLR_INT_ENA_W1CX(reg), BIT_ULL(vf)); 2353 } 2354 } 2355 2356 static irqreturn_t rvu_flr_intr_handler(int irq, void *rvu_irq) 2357 { 2358 struct rvu *rvu = (struct rvu *)rvu_irq; 2359 u64 intr; 2360 u8 pf; 2361 2362 intr = rvu_read64(rvu, BLKADDR_RVUM, RVU_AF_PFFLR_INT); 2363 if (!intr) 2364 goto afvf_flr; 2365 2366 for (pf = 0; pf < rvu->hw->total_pfs; pf++) { 2367 if (intr & (1ULL << pf)) { 2368 /* PF is already dead do only AF related operations */ 2369 queue_work(rvu->flr_wq, &rvu->flr_wrk[pf].work); 2370 /* clear interrupt */ 2371 rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_PFFLR_INT, 2372 BIT_ULL(pf)); 2373 /* Disable the interrupt */ 2374 rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_PFFLR_INT_ENA_W1C, 2375 BIT_ULL(pf)); 2376 } 2377 } 2378 2379 afvf_flr: 2380 rvu_afvf_queue_flr_work(rvu, 0, 64); 2381 if (rvu->vfs > 64) 2382 rvu_afvf_queue_flr_work(rvu, 64, rvu->vfs - 64); 2383 2384 return IRQ_HANDLED; 2385 } 2386 2387 static void rvu_me_handle_vfset(struct rvu *rvu, int idx, u64 intr) 2388 { 2389 int vf; 2390 2391 /* Nothing to be done here other than clearing the 2392 * TRPEND bit. 2393 */ 2394 for (vf = 0; vf < 64; vf++) { 2395 if (intr & (1ULL << vf)) { 2396 /* clear the trpend due to ME(master enable) */ 2397 rvupf_write64(rvu, RVU_PF_VFTRPENDX(idx), BIT_ULL(vf)); 2398 /* clear interrupt */ 2399 rvupf_write64(rvu, RVU_PF_VFME_INTX(idx), BIT_ULL(vf)); 2400 } 2401 } 2402 } 2403 2404 /* Handles ME interrupts from VFs of AF */ 2405 static irqreturn_t rvu_me_vf_intr_handler(int irq, void *rvu_irq) 2406 { 2407 struct rvu *rvu = (struct rvu *)rvu_irq; 2408 int vfset; 2409 u64 intr; 2410 2411 intr = rvu_read64(rvu, BLKADDR_RVUM, RVU_AF_PFME_INT); 2412 2413 for (vfset = 0; vfset <= 1; vfset++) { 2414 intr = rvupf_read64(rvu, RVU_PF_VFME_INTX(vfset)); 2415 if (intr) 2416 rvu_me_handle_vfset(rvu, vfset, intr); 2417 } 2418 2419 return IRQ_HANDLED; 2420 } 2421 2422 /* Handles ME interrupts from PFs */ 2423 static irqreturn_t rvu_me_pf_intr_handler(int irq, void *rvu_irq) 2424 { 2425 struct rvu *rvu = (struct rvu *)rvu_irq; 2426 u64 intr; 2427 u8 pf; 2428 2429 intr = rvu_read64(rvu, BLKADDR_RVUM, RVU_AF_PFME_INT); 2430 2431 /* Nothing to be done here other than clearing the 2432 * TRPEND bit. 2433 */ 2434 for (pf = 0; pf < rvu->hw->total_pfs; pf++) { 2435 if (intr & (1ULL << pf)) { 2436 /* clear the trpend due to ME(master enable) */ 2437 rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_PFTRPEND, 2438 BIT_ULL(pf)); 2439 /* clear interrupt */ 2440 rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_PFME_INT, 2441 BIT_ULL(pf)); 2442 } 2443 } 2444 2445 return IRQ_HANDLED; 2446 } 2447 2448 static void rvu_unregister_interrupts(struct rvu *rvu) 2449 { 2450 int irq; 2451 2452 /* Disable the Mbox interrupt */ 2453 rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_PFAF_MBOX_INT_ENA_W1C, 2454 INTR_MASK(rvu->hw->total_pfs) & ~1ULL); 2455 2456 /* Disable the PF FLR interrupt */ 2457 rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_PFFLR_INT_ENA_W1C, 2458 INTR_MASK(rvu->hw->total_pfs) & ~1ULL); 2459 2460 /* Disable the PF ME interrupt */ 2461 rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_PFME_INT_ENA_W1C, 2462 INTR_MASK(rvu->hw->total_pfs) & ~1ULL); 2463 2464 for (irq = 0; irq < rvu->num_vec; irq++) { 2465 if (rvu->irq_allocated[irq]) 2466 free_irq(pci_irq_vector(rvu->pdev, irq), rvu); 2467 } 2468 2469 pci_free_irq_vectors(rvu->pdev); 2470 rvu->num_vec = 0; 2471 } 2472 2473 static int rvu_afvf_msix_vectors_num_ok(struct rvu *rvu) 2474 { 2475 struct rvu_pfvf *pfvf = &rvu->pf[0]; 2476 int offset; 2477 2478 pfvf = &rvu->pf[0]; 2479 offset = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_PFX_INT_CFG(0)) & 0x3ff; 2480 2481 /* Make sure there are enough MSIX vectors configured so that 2482 * VF interrupts can be handled. Offset equal to zero means 2483 * that PF vectors are not configured and overlapping AF vectors. 2484 */ 2485 return (pfvf->msix.max >= RVU_AF_INT_VEC_CNT + RVU_PF_INT_VEC_CNT) && 2486 offset; 2487 } 2488 2489 static int rvu_register_interrupts(struct rvu *rvu) 2490 { 2491 int ret, offset, pf_vec_start; 2492 2493 rvu->num_vec = pci_msix_vec_count(rvu->pdev); 2494 2495 rvu->irq_name = devm_kmalloc_array(rvu->dev, rvu->num_vec, 2496 NAME_SIZE, GFP_KERNEL); 2497 if (!rvu->irq_name) 2498 return -ENOMEM; 2499 2500 rvu->irq_allocated = devm_kcalloc(rvu->dev, rvu->num_vec, 2501 sizeof(bool), GFP_KERNEL); 2502 if (!rvu->irq_allocated) 2503 return -ENOMEM; 2504 2505 /* Enable MSI-X */ 2506 ret = pci_alloc_irq_vectors(rvu->pdev, rvu->num_vec, 2507 rvu->num_vec, PCI_IRQ_MSIX); 2508 if (ret < 0) { 2509 dev_err(rvu->dev, 2510 "RVUAF: Request for %d msix vectors failed, ret %d\n", 2511 rvu->num_vec, ret); 2512 return ret; 2513 } 2514 2515 /* Register mailbox interrupt handler */ 2516 sprintf(&rvu->irq_name[RVU_AF_INT_VEC_MBOX * NAME_SIZE], "RVUAF Mbox"); 2517 ret = request_irq(pci_irq_vector(rvu->pdev, RVU_AF_INT_VEC_MBOX), 2518 rvu_mbox_intr_handler, 0, 2519 &rvu->irq_name[RVU_AF_INT_VEC_MBOX * NAME_SIZE], rvu); 2520 if (ret) { 2521 dev_err(rvu->dev, 2522 "RVUAF: IRQ registration failed for mbox irq\n"); 2523 goto fail; 2524 } 2525 2526 rvu->irq_allocated[RVU_AF_INT_VEC_MBOX] = true; 2527 2528 /* Enable mailbox interrupts from all PFs */ 2529 rvu_enable_mbox_intr(rvu); 2530 2531 /* Register FLR interrupt handler */ 2532 sprintf(&rvu->irq_name[RVU_AF_INT_VEC_PFFLR * NAME_SIZE], 2533 "RVUAF FLR"); 2534 ret = request_irq(pci_irq_vector(rvu->pdev, RVU_AF_INT_VEC_PFFLR), 2535 rvu_flr_intr_handler, 0, 2536 &rvu->irq_name[RVU_AF_INT_VEC_PFFLR * NAME_SIZE], 2537 rvu); 2538 if (ret) { 2539 dev_err(rvu->dev, 2540 "RVUAF: IRQ registration failed for FLR\n"); 2541 goto fail; 2542 } 2543 rvu->irq_allocated[RVU_AF_INT_VEC_PFFLR] = true; 2544 2545 /* Enable FLR interrupt for all PFs*/ 2546 rvu_write64(rvu, BLKADDR_RVUM, 2547 RVU_AF_PFFLR_INT, INTR_MASK(rvu->hw->total_pfs)); 2548 2549 rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_PFFLR_INT_ENA_W1S, 2550 INTR_MASK(rvu->hw->total_pfs) & ~1ULL); 2551 2552 /* Register ME interrupt handler */ 2553 sprintf(&rvu->irq_name[RVU_AF_INT_VEC_PFME * NAME_SIZE], 2554 "RVUAF ME"); 2555 ret = request_irq(pci_irq_vector(rvu->pdev, RVU_AF_INT_VEC_PFME), 2556 rvu_me_pf_intr_handler, 0, 2557 &rvu->irq_name[RVU_AF_INT_VEC_PFME * NAME_SIZE], 2558 rvu); 2559 if (ret) { 2560 dev_err(rvu->dev, 2561 "RVUAF: IRQ registration failed for ME\n"); 2562 } 2563 rvu->irq_allocated[RVU_AF_INT_VEC_PFME] = true; 2564 2565 /* Clear TRPEND bit for all PF */ 2566 rvu_write64(rvu, BLKADDR_RVUM, 2567 RVU_AF_PFTRPEND, INTR_MASK(rvu->hw->total_pfs)); 2568 /* Enable ME interrupt for all PFs*/ 2569 rvu_write64(rvu, BLKADDR_RVUM, 2570 RVU_AF_PFME_INT, INTR_MASK(rvu->hw->total_pfs)); 2571 2572 rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_PFME_INT_ENA_W1S, 2573 INTR_MASK(rvu->hw->total_pfs) & ~1ULL); 2574 2575 if (!rvu_afvf_msix_vectors_num_ok(rvu)) 2576 return 0; 2577 2578 /* Get PF MSIX vectors offset. */ 2579 pf_vec_start = rvu_read64(rvu, BLKADDR_RVUM, 2580 RVU_PRIV_PFX_INT_CFG(0)) & 0x3ff; 2581 2582 /* Register MBOX0 interrupt. */ 2583 offset = pf_vec_start + RVU_PF_INT_VEC_VFPF_MBOX0; 2584 sprintf(&rvu->irq_name[offset * NAME_SIZE], "RVUAFVF Mbox0"); 2585 ret = request_irq(pci_irq_vector(rvu->pdev, offset), 2586 rvu_mbox_intr_handler, 0, 2587 &rvu->irq_name[offset * NAME_SIZE], 2588 rvu); 2589 if (ret) 2590 dev_err(rvu->dev, 2591 "RVUAF: IRQ registration failed for Mbox0\n"); 2592 2593 rvu->irq_allocated[offset] = true; 2594 2595 /* Register MBOX1 interrupt. MBOX1 IRQ number follows MBOX0 so 2596 * simply increment current offset by 1. 2597 */ 2598 offset = pf_vec_start + RVU_PF_INT_VEC_VFPF_MBOX1; 2599 sprintf(&rvu->irq_name[offset * NAME_SIZE], "RVUAFVF Mbox1"); 2600 ret = request_irq(pci_irq_vector(rvu->pdev, offset), 2601 rvu_mbox_intr_handler, 0, 2602 &rvu->irq_name[offset * NAME_SIZE], 2603 rvu); 2604 if (ret) 2605 dev_err(rvu->dev, 2606 "RVUAF: IRQ registration failed for Mbox1\n"); 2607 2608 rvu->irq_allocated[offset] = true; 2609 2610 /* Register FLR interrupt handler for AF's VFs */ 2611 offset = pf_vec_start + RVU_PF_INT_VEC_VFFLR0; 2612 sprintf(&rvu->irq_name[offset * NAME_SIZE], "RVUAFVF FLR0"); 2613 ret = request_irq(pci_irq_vector(rvu->pdev, offset), 2614 rvu_flr_intr_handler, 0, 2615 &rvu->irq_name[offset * NAME_SIZE], rvu); 2616 if (ret) { 2617 dev_err(rvu->dev, 2618 "RVUAF: IRQ registration failed for RVUAFVF FLR0\n"); 2619 goto fail; 2620 } 2621 rvu->irq_allocated[offset] = true; 2622 2623 offset = pf_vec_start + RVU_PF_INT_VEC_VFFLR1; 2624 sprintf(&rvu->irq_name[offset * NAME_SIZE], "RVUAFVF FLR1"); 2625 ret = request_irq(pci_irq_vector(rvu->pdev, offset), 2626 rvu_flr_intr_handler, 0, 2627 &rvu->irq_name[offset * NAME_SIZE], rvu); 2628 if (ret) { 2629 dev_err(rvu->dev, 2630 "RVUAF: IRQ registration failed for RVUAFVF FLR1\n"); 2631 goto fail; 2632 } 2633 rvu->irq_allocated[offset] = true; 2634 2635 /* Register ME interrupt handler for AF's VFs */ 2636 offset = pf_vec_start + RVU_PF_INT_VEC_VFME0; 2637 sprintf(&rvu->irq_name[offset * NAME_SIZE], "RVUAFVF ME0"); 2638 ret = request_irq(pci_irq_vector(rvu->pdev, offset), 2639 rvu_me_vf_intr_handler, 0, 2640 &rvu->irq_name[offset * NAME_SIZE], rvu); 2641 if (ret) { 2642 dev_err(rvu->dev, 2643 "RVUAF: IRQ registration failed for RVUAFVF ME0\n"); 2644 goto fail; 2645 } 2646 rvu->irq_allocated[offset] = true; 2647 2648 offset = pf_vec_start + RVU_PF_INT_VEC_VFME1; 2649 sprintf(&rvu->irq_name[offset * NAME_SIZE], "RVUAFVF ME1"); 2650 ret = request_irq(pci_irq_vector(rvu->pdev, offset), 2651 rvu_me_vf_intr_handler, 0, 2652 &rvu->irq_name[offset * NAME_SIZE], rvu); 2653 if (ret) { 2654 dev_err(rvu->dev, 2655 "RVUAF: IRQ registration failed for RVUAFVF ME1\n"); 2656 goto fail; 2657 } 2658 rvu->irq_allocated[offset] = true; 2659 return 0; 2660 2661 fail: 2662 rvu_unregister_interrupts(rvu); 2663 return ret; 2664 } 2665 2666 static void rvu_flr_wq_destroy(struct rvu *rvu) 2667 { 2668 if (rvu->flr_wq) { 2669 flush_workqueue(rvu->flr_wq); 2670 destroy_workqueue(rvu->flr_wq); 2671 rvu->flr_wq = NULL; 2672 } 2673 } 2674 2675 static int rvu_flr_init(struct rvu *rvu) 2676 { 2677 int dev, num_devs; 2678 u64 cfg; 2679 int pf; 2680 2681 /* Enable FLR for all PFs*/ 2682 for (pf = 0; pf < rvu->hw->total_pfs; pf++) { 2683 cfg = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_PFX_CFG(pf)); 2684 rvu_write64(rvu, BLKADDR_RVUM, RVU_PRIV_PFX_CFG(pf), 2685 cfg | BIT_ULL(22)); 2686 } 2687 2688 rvu->flr_wq = alloc_workqueue("rvu_afpf_flr", 2689 WQ_UNBOUND | WQ_HIGHPRI | WQ_MEM_RECLAIM, 2690 1); 2691 if (!rvu->flr_wq) 2692 return -ENOMEM; 2693 2694 num_devs = rvu->hw->total_pfs + pci_sriov_get_totalvfs(rvu->pdev); 2695 rvu->flr_wrk = devm_kcalloc(rvu->dev, num_devs, 2696 sizeof(struct rvu_work), GFP_KERNEL); 2697 if (!rvu->flr_wrk) { 2698 destroy_workqueue(rvu->flr_wq); 2699 return -ENOMEM; 2700 } 2701 2702 for (dev = 0; dev < num_devs; dev++) { 2703 rvu->flr_wrk[dev].rvu = rvu; 2704 INIT_WORK(&rvu->flr_wrk[dev].work, rvu_flr_handler); 2705 } 2706 2707 mutex_init(&rvu->flr_lock); 2708 2709 return 0; 2710 } 2711 2712 static void rvu_disable_afvf_intr(struct rvu *rvu) 2713 { 2714 int vfs = rvu->vfs; 2715 2716 rvupf_write64(rvu, RVU_PF_VFPF_MBOX_INT_ENA_W1CX(0), INTR_MASK(vfs)); 2717 rvupf_write64(rvu, RVU_PF_VFFLR_INT_ENA_W1CX(0), INTR_MASK(vfs)); 2718 rvupf_write64(rvu, RVU_PF_VFME_INT_ENA_W1CX(0), INTR_MASK(vfs)); 2719 if (vfs <= 64) 2720 return; 2721 2722 rvupf_write64(rvu, RVU_PF_VFPF_MBOX_INT_ENA_W1CX(1), 2723 INTR_MASK(vfs - 64)); 2724 rvupf_write64(rvu, RVU_PF_VFFLR_INT_ENA_W1CX(1), INTR_MASK(vfs - 64)); 2725 rvupf_write64(rvu, RVU_PF_VFME_INT_ENA_W1CX(1), INTR_MASK(vfs - 64)); 2726 } 2727 2728 static void rvu_enable_afvf_intr(struct rvu *rvu) 2729 { 2730 int vfs = rvu->vfs; 2731 2732 /* Clear any pending interrupts and enable AF VF interrupts for 2733 * the first 64 VFs. 2734 */ 2735 /* Mbox */ 2736 rvupf_write64(rvu, RVU_PF_VFPF_MBOX_INTX(0), INTR_MASK(vfs)); 2737 rvupf_write64(rvu, RVU_PF_VFPF_MBOX_INT_ENA_W1SX(0), INTR_MASK(vfs)); 2738 2739 /* FLR */ 2740 rvupf_write64(rvu, RVU_PF_VFFLR_INTX(0), INTR_MASK(vfs)); 2741 rvupf_write64(rvu, RVU_PF_VFFLR_INT_ENA_W1SX(0), INTR_MASK(vfs)); 2742 rvupf_write64(rvu, RVU_PF_VFME_INT_ENA_W1SX(0), INTR_MASK(vfs)); 2743 2744 /* Same for remaining VFs, if any. */ 2745 if (vfs <= 64) 2746 return; 2747 2748 rvupf_write64(rvu, RVU_PF_VFPF_MBOX_INTX(1), INTR_MASK(vfs - 64)); 2749 rvupf_write64(rvu, RVU_PF_VFPF_MBOX_INT_ENA_W1SX(1), 2750 INTR_MASK(vfs - 64)); 2751 2752 rvupf_write64(rvu, RVU_PF_VFFLR_INTX(1), INTR_MASK(vfs - 64)); 2753 rvupf_write64(rvu, RVU_PF_VFFLR_INT_ENA_W1SX(1), INTR_MASK(vfs - 64)); 2754 rvupf_write64(rvu, RVU_PF_VFME_INT_ENA_W1SX(1), INTR_MASK(vfs - 64)); 2755 } 2756 2757 int rvu_get_num_lbk_chans(void) 2758 { 2759 struct pci_dev *pdev; 2760 void __iomem *base; 2761 int ret = -EIO; 2762 2763 pdev = pci_get_device(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_OCTEONTX2_LBK, 2764 NULL); 2765 if (!pdev) 2766 goto err; 2767 2768 base = pci_ioremap_bar(pdev, 0); 2769 if (!base) 2770 goto err_put; 2771 2772 /* Read number of available LBK channels from LBK(0)_CONST register. */ 2773 ret = (readq(base + 0x10) >> 32) & 0xffff; 2774 iounmap(base); 2775 err_put: 2776 pci_dev_put(pdev); 2777 err: 2778 return ret; 2779 } 2780 2781 static int rvu_enable_sriov(struct rvu *rvu) 2782 { 2783 struct pci_dev *pdev = rvu->pdev; 2784 int err, chans, vfs; 2785 2786 if (!rvu_afvf_msix_vectors_num_ok(rvu)) { 2787 dev_warn(&pdev->dev, 2788 "Skipping SRIOV enablement since not enough IRQs are available\n"); 2789 return 0; 2790 } 2791 2792 chans = rvu_get_num_lbk_chans(); 2793 if (chans < 0) 2794 return chans; 2795 2796 vfs = pci_sriov_get_totalvfs(pdev); 2797 2798 /* Limit VFs in case we have more VFs than LBK channels available. */ 2799 if (vfs > chans) 2800 vfs = chans; 2801 2802 if (!vfs) 2803 return 0; 2804 2805 /* Save VFs number for reference in VF interrupts handlers. 2806 * Since interrupts might start arriving during SRIOV enablement 2807 * ordinary API cannot be used to get number of enabled VFs. 2808 */ 2809 rvu->vfs = vfs; 2810 2811 err = rvu_mbox_init(rvu, &rvu->afvf_wq_info, TYPE_AFVF, vfs, 2812 rvu_afvf_mbox_handler, rvu_afvf_mbox_up_handler); 2813 if (err) 2814 return err; 2815 2816 rvu_enable_afvf_intr(rvu); 2817 /* Make sure IRQs are enabled before SRIOV. */ 2818 mb(); 2819 2820 err = pci_enable_sriov(pdev, vfs); 2821 if (err) { 2822 rvu_disable_afvf_intr(rvu); 2823 rvu_mbox_destroy(&rvu->afvf_wq_info); 2824 return err; 2825 } 2826 2827 return 0; 2828 } 2829 2830 static void rvu_disable_sriov(struct rvu *rvu) 2831 { 2832 rvu_disable_afvf_intr(rvu); 2833 rvu_mbox_destroy(&rvu->afvf_wq_info); 2834 pci_disable_sriov(rvu->pdev); 2835 } 2836 2837 static void rvu_update_module_params(struct rvu *rvu) 2838 { 2839 const char *default_pfl_name = "default"; 2840 2841 strscpy(rvu->mkex_pfl_name, 2842 mkex_profile ? mkex_profile : default_pfl_name, MKEX_NAME_LEN); 2843 } 2844 2845 static int rvu_probe(struct pci_dev *pdev, const struct pci_device_id *id) 2846 { 2847 struct device *dev = &pdev->dev; 2848 struct rvu *rvu; 2849 int err; 2850 2851 rvu = devm_kzalloc(dev, sizeof(*rvu), GFP_KERNEL); 2852 if (!rvu) 2853 return -ENOMEM; 2854 2855 rvu->hw = devm_kzalloc(dev, sizeof(struct rvu_hwinfo), GFP_KERNEL); 2856 if (!rvu->hw) { 2857 devm_kfree(dev, rvu); 2858 return -ENOMEM; 2859 } 2860 2861 pci_set_drvdata(pdev, rvu); 2862 rvu->pdev = pdev; 2863 rvu->dev = &pdev->dev; 2864 2865 err = pci_enable_device(pdev); 2866 if (err) { 2867 dev_err(dev, "Failed to enable PCI device\n"); 2868 goto err_freemem; 2869 } 2870 2871 err = pci_request_regions(pdev, DRV_NAME); 2872 if (err) { 2873 dev_err(dev, "PCI request regions failed 0x%x\n", err); 2874 goto err_disable_device; 2875 } 2876 2877 err = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(48)); 2878 if (err) { 2879 dev_err(dev, "DMA mask config failed, abort\n"); 2880 goto err_release_regions; 2881 } 2882 2883 pci_set_master(pdev); 2884 2885 rvu->ptp = ptp_get(); 2886 if (IS_ERR(rvu->ptp)) { 2887 err = PTR_ERR(rvu->ptp); 2888 if (err == -EPROBE_DEFER) 2889 goto err_release_regions; 2890 rvu->ptp = NULL; 2891 } 2892 2893 /* Map Admin function CSRs */ 2894 rvu->afreg_base = pcim_iomap(pdev, PCI_AF_REG_BAR_NUM, 0); 2895 rvu->pfreg_base = pcim_iomap(pdev, PCI_PF_REG_BAR_NUM, 0); 2896 if (!rvu->afreg_base || !rvu->pfreg_base) { 2897 dev_err(dev, "Unable to map admin function CSRs, aborting\n"); 2898 err = -ENOMEM; 2899 goto err_put_ptp; 2900 } 2901 2902 /* Store module params in rvu structure */ 2903 rvu_update_module_params(rvu); 2904 2905 /* Check which blocks the HW supports */ 2906 rvu_check_block_implemented(rvu); 2907 2908 rvu_reset_all_blocks(rvu); 2909 2910 rvu_setup_hw_capabilities(rvu); 2911 2912 err = rvu_setup_hw_resources(rvu); 2913 if (err) 2914 goto err_put_ptp; 2915 2916 /* Init mailbox btw AF and PFs */ 2917 err = rvu_mbox_init(rvu, &rvu->afpf_wq_info, TYPE_AFPF, 2918 rvu->hw->total_pfs, rvu_afpf_mbox_handler, 2919 rvu_afpf_mbox_up_handler); 2920 if (err) 2921 goto err_hwsetup; 2922 2923 err = rvu_flr_init(rvu); 2924 if (err) 2925 goto err_mbox; 2926 2927 err = rvu_register_interrupts(rvu); 2928 if (err) 2929 goto err_flr; 2930 2931 err = rvu_register_dl(rvu); 2932 if (err) 2933 goto err_irq; 2934 2935 rvu_setup_rvum_blk_revid(rvu); 2936 2937 /* Enable AF's VFs (if any) */ 2938 err = rvu_enable_sriov(rvu); 2939 if (err) 2940 goto err_dl; 2941 2942 /* Initialize debugfs */ 2943 rvu_dbg_init(rvu); 2944 2945 return 0; 2946 err_dl: 2947 rvu_unregister_dl(rvu); 2948 err_irq: 2949 rvu_unregister_interrupts(rvu); 2950 err_flr: 2951 rvu_flr_wq_destroy(rvu); 2952 err_mbox: 2953 rvu_mbox_destroy(&rvu->afpf_wq_info); 2954 err_hwsetup: 2955 rvu_cgx_exit(rvu); 2956 rvu_fwdata_exit(rvu); 2957 rvu_reset_all_blocks(rvu); 2958 rvu_free_hw_resources(rvu); 2959 rvu_clear_rvum_blk_revid(rvu); 2960 err_put_ptp: 2961 ptp_put(rvu->ptp); 2962 err_release_regions: 2963 pci_release_regions(pdev); 2964 err_disable_device: 2965 pci_disable_device(pdev); 2966 err_freemem: 2967 pci_set_drvdata(pdev, NULL); 2968 devm_kfree(&pdev->dev, rvu->hw); 2969 devm_kfree(dev, rvu); 2970 return err; 2971 } 2972 2973 static void rvu_remove(struct pci_dev *pdev) 2974 { 2975 struct rvu *rvu = pci_get_drvdata(pdev); 2976 2977 rvu_dbg_exit(rvu); 2978 rvu_unregister_interrupts(rvu); 2979 rvu_unregister_dl(rvu); 2980 rvu_flr_wq_destroy(rvu); 2981 rvu_cgx_exit(rvu); 2982 rvu_fwdata_exit(rvu); 2983 rvu_mbox_destroy(&rvu->afpf_wq_info); 2984 rvu_disable_sriov(rvu); 2985 rvu_reset_all_blocks(rvu); 2986 rvu_free_hw_resources(rvu); 2987 rvu_clear_rvum_blk_revid(rvu); 2988 ptp_put(rvu->ptp); 2989 pci_release_regions(pdev); 2990 pci_disable_device(pdev); 2991 pci_set_drvdata(pdev, NULL); 2992 2993 devm_kfree(&pdev->dev, rvu->hw); 2994 devm_kfree(&pdev->dev, rvu); 2995 } 2996 2997 static struct pci_driver rvu_driver = { 2998 .name = DRV_NAME, 2999 .id_table = rvu_id_table, 3000 .probe = rvu_probe, 3001 .remove = rvu_remove, 3002 }; 3003 3004 static int __init rvu_init_module(void) 3005 { 3006 int err; 3007 3008 pr_info("%s: %s\n", DRV_NAME, DRV_STRING); 3009 3010 err = pci_register_driver(&cgx_driver); 3011 if (err < 0) 3012 return err; 3013 3014 err = pci_register_driver(&ptp_driver); 3015 if (err < 0) 3016 goto ptp_err; 3017 3018 err = pci_register_driver(&rvu_driver); 3019 if (err < 0) 3020 goto rvu_err; 3021 3022 return 0; 3023 rvu_err: 3024 pci_unregister_driver(&ptp_driver); 3025 ptp_err: 3026 pci_unregister_driver(&cgx_driver); 3027 3028 return err; 3029 } 3030 3031 static void __exit rvu_cleanup_module(void) 3032 { 3033 pci_unregister_driver(&rvu_driver); 3034 pci_unregister_driver(&ptp_driver); 3035 pci_unregister_driver(&cgx_driver); 3036 } 3037 3038 module_init(rvu_init_module); 3039 module_exit(rvu_cleanup_module); 3040