1 // SPDX-License-Identifier: GPL-2.0 2 /* Marvell CN10K RPM driver 3 * 4 * Copyright (C) 2020 Marvell. 5 * 6 */ 7 8 #include "cgx.h" 9 #include "lmac_common.h" 10 11 static struct mac_ops rpm_mac_ops = { 12 .name = "rpm", 13 .csr_offset = 0x4e00, 14 .lmac_offset = 20, 15 .int_register = RPMX_CMRX_SW_INT, 16 .int_set_reg = RPMX_CMRX_SW_INT_ENA_W1S, 17 .irq_offset = 1, 18 .int_ena_bit = BIT_ULL(0), 19 .lmac_fwi = RPM_LMAC_FWI, 20 .non_contiguous_serdes_lane = true, 21 .rx_stats_cnt = 43, 22 .tx_stats_cnt = 34, 23 .get_nr_lmacs = rpm_get_nr_lmacs, 24 .get_lmac_type = rpm_get_lmac_type, 25 .mac_lmac_intl_lbk = rpm_lmac_internal_loopback, 26 .mac_get_rx_stats = rpm_get_rx_stats, 27 .mac_get_tx_stats = rpm_get_tx_stats, 28 .mac_enadis_rx_pause_fwding = rpm_lmac_enadis_rx_pause_fwding, 29 .mac_get_pause_frm_status = rpm_lmac_get_pause_frm_status, 30 .mac_enadis_pause_frm = rpm_lmac_enadis_pause_frm, 31 .mac_pause_frm_config = rpm_lmac_pause_frm_config, 32 .mac_enadis_ptp_config = rpm_lmac_ptp_config, 33 .mac_rx_tx_enable = rpm_lmac_rx_tx_enable, 34 .mac_tx_enable = rpm_lmac_tx_enable, 35 .pfc_config = rpm_lmac_pfc_config, 36 .mac_get_pfc_frm_cfg = rpm_lmac_get_pfc_frm_cfg, 37 }; 38 39 struct mac_ops *rpm_get_mac_ops(void) 40 { 41 return &rpm_mac_ops; 42 } 43 44 static void rpm_write(rpm_t *rpm, u64 lmac, u64 offset, u64 val) 45 { 46 cgx_write(rpm, lmac, offset, val); 47 } 48 49 static u64 rpm_read(rpm_t *rpm, u64 lmac, u64 offset) 50 { 51 return cgx_read(rpm, lmac, offset); 52 } 53 54 int rpm_get_nr_lmacs(void *rpmd) 55 { 56 rpm_t *rpm = rpmd; 57 58 return hweight8(rpm_read(rpm, 0, CGXX_CMRX_RX_LMACS) & 0xFULL); 59 } 60 61 int rpm_lmac_tx_enable(void *rpmd, int lmac_id, bool enable) 62 { 63 rpm_t *rpm = rpmd; 64 u64 cfg, last; 65 66 if (!is_lmac_valid(rpm, lmac_id)) 67 return -ENODEV; 68 69 cfg = rpm_read(rpm, lmac_id, RPMX_MTI_MAC100X_COMMAND_CONFIG); 70 last = cfg; 71 if (enable) 72 cfg |= RPM_TX_EN; 73 else 74 cfg &= ~(RPM_TX_EN); 75 76 if (cfg != last) 77 rpm_write(rpm, lmac_id, RPMX_MTI_MAC100X_COMMAND_CONFIG, cfg); 78 return !!(last & RPM_TX_EN); 79 } 80 81 int rpm_lmac_rx_tx_enable(void *rpmd, int lmac_id, bool enable) 82 { 83 rpm_t *rpm = rpmd; 84 u64 cfg; 85 86 if (!is_lmac_valid(rpm, lmac_id)) 87 return -ENODEV; 88 89 cfg = rpm_read(rpm, lmac_id, RPMX_MTI_MAC100X_COMMAND_CONFIG); 90 if (enable) 91 cfg |= RPM_RX_EN | RPM_TX_EN; 92 else 93 cfg &= ~(RPM_RX_EN | RPM_TX_EN); 94 rpm_write(rpm, lmac_id, RPMX_MTI_MAC100X_COMMAND_CONFIG, cfg); 95 return 0; 96 } 97 98 void rpm_lmac_enadis_rx_pause_fwding(void *rpmd, int lmac_id, bool enable) 99 { 100 rpm_t *rpm = rpmd; 101 struct lmac *lmac; 102 u64 cfg; 103 104 if (!rpm) 105 return; 106 107 lmac = lmac_pdata(lmac_id, rpm); 108 if (!lmac) 109 return; 110 111 /* Pause frames are not enabled just return */ 112 if (!bitmap_weight(lmac->rx_fc_pfvf_bmap.bmap, lmac->rx_fc_pfvf_bmap.max)) 113 return; 114 115 if (enable) { 116 cfg = rpm_read(rpm, lmac_id, RPMX_MTI_MAC100X_COMMAND_CONFIG); 117 cfg &= ~RPMX_MTI_MAC100X_COMMAND_CONFIG_PAUSE_IGNORE; 118 rpm_write(rpm, lmac_id, RPMX_MTI_MAC100X_COMMAND_CONFIG, cfg); 119 } else { 120 cfg = rpm_read(rpm, lmac_id, RPMX_MTI_MAC100X_COMMAND_CONFIG); 121 cfg |= RPMX_MTI_MAC100X_COMMAND_CONFIG_PAUSE_IGNORE; 122 rpm_write(rpm, lmac_id, RPMX_MTI_MAC100X_COMMAND_CONFIG, cfg); 123 } 124 } 125 126 int rpm_lmac_get_pause_frm_status(void *rpmd, int lmac_id, 127 u8 *tx_pause, u8 *rx_pause) 128 { 129 rpm_t *rpm = rpmd; 130 u64 cfg; 131 132 if (!is_lmac_valid(rpm, lmac_id)) 133 return -ENODEV; 134 135 cfg = rpm_read(rpm, lmac_id, RPMX_MTI_MAC100X_COMMAND_CONFIG); 136 if (!(cfg & RPMX_MTI_MAC100X_COMMAND_CONFIG_PFC_MODE)) { 137 *rx_pause = !(cfg & RPMX_MTI_MAC100X_COMMAND_CONFIG_RX_P_DISABLE); 138 *tx_pause = !(cfg & RPMX_MTI_MAC100X_COMMAND_CONFIG_TX_P_DISABLE); 139 } 140 141 return 0; 142 } 143 144 static void rpm_cfg_pfc_quanta_thresh(rpm_t *rpm, int lmac_id, 145 unsigned long pfc_en, 146 bool enable) 147 { 148 u64 quanta_offset = 0, quanta_thresh = 0, cfg; 149 int i, shift; 150 151 /* Set pause time and interval */ 152 for_each_set_bit(i, &pfc_en, 16) { 153 switch (i) { 154 case 0: 155 case 1: 156 quanta_offset = RPMX_MTI_MAC100X_CL01_PAUSE_QUANTA; 157 quanta_thresh = RPMX_MTI_MAC100X_CL01_QUANTA_THRESH; 158 break; 159 case 2: 160 case 3: 161 quanta_offset = RPMX_MTI_MAC100X_CL23_PAUSE_QUANTA; 162 quanta_thresh = RPMX_MTI_MAC100X_CL23_QUANTA_THRESH; 163 break; 164 case 4: 165 case 5: 166 quanta_offset = RPMX_MTI_MAC100X_CL45_PAUSE_QUANTA; 167 quanta_thresh = RPMX_MTI_MAC100X_CL45_QUANTA_THRESH; 168 break; 169 case 6: 170 case 7: 171 quanta_offset = RPMX_MTI_MAC100X_CL67_PAUSE_QUANTA; 172 quanta_thresh = RPMX_MTI_MAC100X_CL67_QUANTA_THRESH; 173 break; 174 case 8: 175 case 9: 176 quanta_offset = RPMX_MTI_MAC100X_CL89_PAUSE_QUANTA; 177 quanta_thresh = RPMX_MTI_MAC100X_CL89_QUANTA_THRESH; 178 break; 179 case 10: 180 case 11: 181 quanta_offset = RPMX_MTI_MAC100X_CL1011_PAUSE_QUANTA; 182 quanta_thresh = RPMX_MTI_MAC100X_CL1011_QUANTA_THRESH; 183 break; 184 case 12: 185 case 13: 186 quanta_offset = RPMX_MTI_MAC100X_CL1213_PAUSE_QUANTA; 187 quanta_thresh = RPMX_MTI_MAC100X_CL1213_QUANTA_THRESH; 188 break; 189 case 14: 190 case 15: 191 quanta_offset = RPMX_MTI_MAC100X_CL1415_PAUSE_QUANTA; 192 quanta_thresh = RPMX_MTI_MAC100X_CL1415_QUANTA_THRESH; 193 break; 194 } 195 196 if (!quanta_offset || !quanta_thresh) 197 continue; 198 199 shift = (i % 2) ? 1 : 0; 200 cfg = rpm_read(rpm, lmac_id, quanta_offset); 201 if (enable) { 202 cfg |= ((u64)RPM_DEFAULT_PAUSE_TIME << shift * 16); 203 } else { 204 if (!shift) 205 cfg &= ~GENMASK_ULL(15, 0); 206 else 207 cfg &= ~GENMASK_ULL(31, 16); 208 } 209 rpm_write(rpm, lmac_id, quanta_offset, cfg); 210 211 cfg = rpm_read(rpm, lmac_id, quanta_thresh); 212 if (enable) { 213 cfg |= ((u64)(RPM_DEFAULT_PAUSE_TIME / 2) << shift * 16); 214 } else { 215 if (!shift) 216 cfg &= ~GENMASK_ULL(15, 0); 217 else 218 cfg &= ~GENMASK_ULL(31, 16); 219 } 220 rpm_write(rpm, lmac_id, quanta_thresh, cfg); 221 } 222 } 223 224 int rpm_lmac_enadis_pause_frm(void *rpmd, int lmac_id, u8 tx_pause, 225 u8 rx_pause) 226 { 227 rpm_t *rpm = rpmd; 228 u64 cfg; 229 230 if (!is_lmac_valid(rpm, lmac_id)) 231 return -ENODEV; 232 233 cfg = rpm_read(rpm, lmac_id, RPMX_MTI_MAC100X_COMMAND_CONFIG); 234 cfg &= ~RPMX_MTI_MAC100X_COMMAND_CONFIG_RX_P_DISABLE; 235 cfg |= rx_pause ? 0x0 : RPMX_MTI_MAC100X_COMMAND_CONFIG_RX_P_DISABLE; 236 cfg &= ~RPMX_MTI_MAC100X_COMMAND_CONFIG_PAUSE_IGNORE; 237 cfg |= rx_pause ? 0x0 : RPMX_MTI_MAC100X_COMMAND_CONFIG_PAUSE_IGNORE; 238 rpm_write(rpm, lmac_id, RPMX_MTI_MAC100X_COMMAND_CONFIG, cfg); 239 240 cfg = rpm_read(rpm, lmac_id, RPMX_MTI_MAC100X_COMMAND_CONFIG); 241 cfg &= ~RPMX_MTI_MAC100X_COMMAND_CONFIG_TX_P_DISABLE; 242 cfg |= tx_pause ? 0x0 : RPMX_MTI_MAC100X_COMMAND_CONFIG_TX_P_DISABLE; 243 rpm_write(rpm, lmac_id, RPMX_MTI_MAC100X_COMMAND_CONFIG, cfg); 244 245 cfg = rpm_read(rpm, 0, RPMX_CMR_RX_OVR_BP); 246 if (tx_pause) { 247 /* Configure CL0 Pause Quanta & threshold for 802.3X frames */ 248 rpm_cfg_pfc_quanta_thresh(rpm, lmac_id, 1, true); 249 cfg &= ~RPMX_CMR_RX_OVR_BP_EN(lmac_id); 250 } else { 251 /* Disable all Pause Quanta & threshold values */ 252 rpm_cfg_pfc_quanta_thresh(rpm, lmac_id, 0xffff, false); 253 cfg |= RPMX_CMR_RX_OVR_BP_EN(lmac_id); 254 cfg &= ~RPMX_CMR_RX_OVR_BP_BP(lmac_id); 255 } 256 rpm_write(rpm, 0, RPMX_CMR_RX_OVR_BP, cfg); 257 return 0; 258 } 259 260 void rpm_lmac_pause_frm_config(void *rpmd, int lmac_id, bool enable) 261 { 262 rpm_t *rpm = rpmd; 263 u64 cfg; 264 265 /* ALL pause frames received are completely ignored */ 266 cfg = rpm_read(rpm, lmac_id, RPMX_MTI_MAC100X_COMMAND_CONFIG); 267 cfg |= RPMX_MTI_MAC100X_COMMAND_CONFIG_RX_P_DISABLE; 268 rpm_write(rpm, lmac_id, RPMX_MTI_MAC100X_COMMAND_CONFIG, cfg); 269 270 /* Disable forward pause to TX block */ 271 cfg = rpm_read(rpm, lmac_id, RPMX_MTI_MAC100X_COMMAND_CONFIG); 272 cfg |= RPMX_MTI_MAC100X_COMMAND_CONFIG_PAUSE_IGNORE; 273 rpm_write(rpm, lmac_id, RPMX_MTI_MAC100X_COMMAND_CONFIG, cfg); 274 275 /* Disable pause frames transmission */ 276 cfg = rpm_read(rpm, lmac_id, RPMX_MTI_MAC100X_COMMAND_CONFIG); 277 cfg |= RPMX_MTI_MAC100X_COMMAND_CONFIG_TX_P_DISABLE; 278 rpm_write(rpm, lmac_id, RPMX_MTI_MAC100X_COMMAND_CONFIG, cfg); 279 } 280 281 int rpm_get_rx_stats(void *rpmd, int lmac_id, int idx, u64 *rx_stat) 282 { 283 rpm_t *rpm = rpmd; 284 u64 val_lo, val_hi; 285 286 if (!rpm || lmac_id >= rpm->lmac_count) 287 return -ENODEV; 288 289 mutex_lock(&rpm->lock); 290 291 /* Update idx to point per lmac Rx statistics page */ 292 idx += lmac_id * rpm->mac_ops->rx_stats_cnt; 293 294 /* Read lower 32 bits of counter */ 295 val_lo = rpm_read(rpm, 0, RPMX_MTI_STAT_RX_STAT_PAGES_COUNTERX + 296 (idx * 8)); 297 298 /* upon read of lower 32 bits, higher 32 bits are written 299 * to RPMX_MTI_STAT_DATA_HI_CDC 300 */ 301 val_hi = rpm_read(rpm, 0, RPMX_MTI_STAT_DATA_HI_CDC); 302 303 *rx_stat = (val_hi << 32 | val_lo); 304 305 mutex_unlock(&rpm->lock); 306 return 0; 307 } 308 309 int rpm_get_tx_stats(void *rpmd, int lmac_id, int idx, u64 *tx_stat) 310 { 311 rpm_t *rpm = rpmd; 312 u64 val_lo, val_hi; 313 314 if (!rpm || lmac_id >= rpm->lmac_count) 315 return -ENODEV; 316 317 mutex_lock(&rpm->lock); 318 319 /* Update idx to point per lmac Tx statistics page */ 320 idx += lmac_id * rpm->mac_ops->tx_stats_cnt; 321 322 val_lo = rpm_read(rpm, 0, RPMX_MTI_STAT_TX_STAT_PAGES_COUNTERX + 323 (idx * 8)); 324 val_hi = rpm_read(rpm, 0, RPMX_MTI_STAT_DATA_HI_CDC); 325 326 *tx_stat = (val_hi << 32 | val_lo); 327 328 mutex_unlock(&rpm->lock); 329 return 0; 330 } 331 332 u8 rpm_get_lmac_type(void *rpmd, int lmac_id) 333 { 334 rpm_t *rpm = rpmd; 335 u64 req = 0, resp; 336 int err; 337 338 req = FIELD_SET(CMDREG_ID, CGX_CMD_GET_LINK_STS, req); 339 err = cgx_fwi_cmd_generic(req, &resp, rpm, 0); 340 if (!err) 341 return FIELD_GET(RESP_LINKSTAT_LMAC_TYPE, resp); 342 return err; 343 } 344 345 int rpm_lmac_internal_loopback(void *rpmd, int lmac_id, bool enable) 346 { 347 rpm_t *rpm = rpmd; 348 u8 lmac_type; 349 u64 cfg; 350 351 if (!rpm || lmac_id >= rpm->lmac_count) 352 return -ENODEV; 353 lmac_type = rpm->mac_ops->get_lmac_type(rpm, lmac_id); 354 355 if (lmac_type == LMAC_MODE_QSGMII || lmac_type == LMAC_MODE_SGMII) { 356 dev_err(&rpm->pdev->dev, "loopback not supported for LPC mode\n"); 357 return 0; 358 } 359 360 cfg = rpm_read(rpm, lmac_id, RPMX_MTI_PCS100X_CONTROL1); 361 362 if (enable) 363 cfg |= RPMX_MTI_PCS_LBK; 364 else 365 cfg &= ~RPMX_MTI_PCS_LBK; 366 rpm_write(rpm, lmac_id, RPMX_MTI_PCS100X_CONTROL1, cfg); 367 368 return 0; 369 } 370 371 void rpm_lmac_ptp_config(void *rpmd, int lmac_id, bool enable) 372 { 373 rpm_t *rpm = rpmd; 374 u64 cfg; 375 376 if (!is_lmac_valid(rpm, lmac_id)) 377 return; 378 379 cfg = rpm_read(rpm, lmac_id, RPMX_CMRX_CFG); 380 if (enable) 381 cfg |= RPMX_RX_TS_PREPEND; 382 else 383 cfg &= ~RPMX_RX_TS_PREPEND; 384 rpm_write(rpm, lmac_id, RPMX_CMRX_CFG, cfg); 385 } 386 387 int rpm_lmac_pfc_config(void *rpmd, int lmac_id, u8 tx_pause, u8 rx_pause, u16 pfc_en) 388 { 389 rpm_t *rpm = rpmd; 390 u64 cfg; 391 392 if (!is_lmac_valid(rpm, lmac_id)) 393 return -ENODEV; 394 395 /* reset PFC class quanta and threshold */ 396 rpm_cfg_pfc_quanta_thresh(rpm, lmac_id, 0xffff, false); 397 398 cfg = rpm_read(rpm, lmac_id, RPMX_MTI_MAC100X_COMMAND_CONFIG); 399 400 if (rx_pause) { 401 cfg &= ~(RPMX_MTI_MAC100X_COMMAND_CONFIG_RX_P_DISABLE | 402 RPMX_MTI_MAC100X_COMMAND_CONFIG_PAUSE_IGNORE | 403 RPMX_MTI_MAC100X_COMMAND_CONFIG_PAUSE_FWD); 404 } else { 405 cfg |= (RPMX_MTI_MAC100X_COMMAND_CONFIG_RX_P_DISABLE | 406 RPMX_MTI_MAC100X_COMMAND_CONFIG_PAUSE_IGNORE | 407 RPMX_MTI_MAC100X_COMMAND_CONFIG_PAUSE_FWD); 408 } 409 410 if (tx_pause) { 411 rpm_cfg_pfc_quanta_thresh(rpm, lmac_id, pfc_en, true); 412 cfg &= ~RPMX_MTI_MAC100X_COMMAND_CONFIG_TX_P_DISABLE; 413 } else { 414 rpm_cfg_pfc_quanta_thresh(rpm, lmac_id, 0xfff, false); 415 cfg |= RPMX_MTI_MAC100X_COMMAND_CONFIG_TX_P_DISABLE; 416 } 417 418 if (!rx_pause && !tx_pause) 419 cfg &= ~RPMX_MTI_MAC100X_COMMAND_CONFIG_PFC_MODE; 420 else 421 cfg |= RPMX_MTI_MAC100X_COMMAND_CONFIG_PFC_MODE; 422 423 rpm_write(rpm, lmac_id, RPMX_MTI_MAC100X_COMMAND_CONFIG, cfg); 424 425 cfg = rpm_read(rpm, lmac_id, RPMX_CMRX_PRT_CBFC_CTL); 426 cfg = FIELD_SET(RPM_PFC_CLASS_MASK, pfc_en, cfg); 427 rpm_write(rpm, lmac_id, RPMX_CMRX_PRT_CBFC_CTL, cfg); 428 429 return 0; 430 } 431 432 int rpm_lmac_get_pfc_frm_cfg(void *rpmd, int lmac_id, u8 *tx_pause, u8 *rx_pause) 433 { 434 rpm_t *rpm = rpmd; 435 u64 cfg; 436 437 if (!is_lmac_valid(rpm, lmac_id)) 438 return -ENODEV; 439 440 cfg = rpm_read(rpm, lmac_id, RPMX_MTI_MAC100X_COMMAND_CONFIG); 441 if (cfg & RPMX_MTI_MAC100X_COMMAND_CONFIG_PFC_MODE) { 442 *rx_pause = !(cfg & RPMX_MTI_MAC100X_COMMAND_CONFIG_RX_P_DISABLE); 443 *tx_pause = !(cfg & RPMX_MTI_MAC100X_COMMAND_CONFIG_TX_P_DISABLE); 444 } 445 446 return 0; 447 } 448