1 // SPDX-License-Identifier: GPL-2.0 2 /* Marvell CN10K RPM driver 3 * 4 * Copyright (C) 2020 Marvell. 5 * 6 */ 7 8 #include "cgx.h" 9 #include "lmac_common.h" 10 11 static struct mac_ops rpm_mac_ops = { 12 .name = "rpm", 13 .csr_offset = 0x4e00, 14 .lmac_offset = 20, 15 .int_register = RPMX_CMRX_SW_INT, 16 .int_set_reg = RPMX_CMRX_SW_INT_ENA_W1S, 17 .irq_offset = 1, 18 .int_ena_bit = BIT_ULL(0), 19 .lmac_fwi = RPM_LMAC_FWI, 20 .non_contiguous_serdes_lane = true, 21 .rx_stats_cnt = 43, 22 .tx_stats_cnt = 34, 23 .dmac_filter_count = 32, 24 .get_nr_lmacs = rpm_get_nr_lmacs, 25 .get_lmac_type = rpm_get_lmac_type, 26 .lmac_fifo_len = rpm_get_lmac_fifo_len, 27 .mac_lmac_intl_lbk = rpm_lmac_internal_loopback, 28 .mac_get_rx_stats = rpm_get_rx_stats, 29 .mac_get_tx_stats = rpm_get_tx_stats, 30 .get_fec_stats = rpm_get_fec_stats, 31 .mac_enadis_rx_pause_fwding = rpm_lmac_enadis_rx_pause_fwding, 32 .mac_get_pause_frm_status = rpm_lmac_get_pause_frm_status, 33 .mac_enadis_pause_frm = rpm_lmac_enadis_pause_frm, 34 .mac_pause_frm_config = rpm_lmac_pause_frm_config, 35 .mac_enadis_ptp_config = rpm_lmac_ptp_config, 36 .mac_rx_tx_enable = rpm_lmac_rx_tx_enable, 37 .mac_tx_enable = rpm_lmac_tx_enable, 38 .pfc_config = rpm_lmac_pfc_config, 39 .mac_get_pfc_frm_cfg = rpm_lmac_get_pfc_frm_cfg, 40 }; 41 42 static struct mac_ops rpm2_mac_ops = { 43 .name = "rpm", 44 .csr_offset = RPM2_CSR_OFFSET, 45 .lmac_offset = 20, 46 .int_register = RPM2_CMRX_SW_INT, 47 .int_set_reg = RPM2_CMRX_SW_INT_ENA_W1S, 48 .irq_offset = 1, 49 .int_ena_bit = BIT_ULL(0), 50 .lmac_fwi = RPM_LMAC_FWI, 51 .non_contiguous_serdes_lane = true, 52 .rx_stats_cnt = 43, 53 .tx_stats_cnt = 34, 54 .dmac_filter_count = 64, 55 .get_nr_lmacs = rpm2_get_nr_lmacs, 56 .get_lmac_type = rpm_get_lmac_type, 57 .lmac_fifo_len = rpm2_get_lmac_fifo_len, 58 .mac_lmac_intl_lbk = rpm_lmac_internal_loopback, 59 .mac_get_rx_stats = rpm_get_rx_stats, 60 .mac_get_tx_stats = rpm_get_tx_stats, 61 .get_fec_stats = rpm_get_fec_stats, 62 .mac_enadis_rx_pause_fwding = rpm_lmac_enadis_rx_pause_fwding, 63 .mac_get_pause_frm_status = rpm_lmac_get_pause_frm_status, 64 .mac_enadis_pause_frm = rpm_lmac_enadis_pause_frm, 65 .mac_pause_frm_config = rpm_lmac_pause_frm_config, 66 .mac_enadis_ptp_config = rpm_lmac_ptp_config, 67 .mac_rx_tx_enable = rpm_lmac_rx_tx_enable, 68 .mac_tx_enable = rpm_lmac_tx_enable, 69 .pfc_config = rpm_lmac_pfc_config, 70 .mac_get_pfc_frm_cfg = rpm_lmac_get_pfc_frm_cfg, 71 }; 72 73 bool is_dev_rpm2(void *rpmd) 74 { 75 rpm_t *rpm = rpmd; 76 77 return (rpm->pdev->device == PCI_DEVID_CN10KB_RPM); 78 } 79 80 struct mac_ops *rpm_get_mac_ops(rpm_t *rpm) 81 { 82 if (is_dev_rpm2(rpm)) 83 return &rpm2_mac_ops; 84 else 85 return &rpm_mac_ops; 86 } 87 88 static void rpm_write(rpm_t *rpm, u64 lmac, u64 offset, u64 val) 89 { 90 cgx_write(rpm, lmac, offset, val); 91 } 92 93 static u64 rpm_read(rpm_t *rpm, u64 lmac, u64 offset) 94 { 95 return cgx_read(rpm, lmac, offset); 96 } 97 98 /* Read HW major version to determine RPM 99 * MAC type 100/USX 100 */ 101 static bool is_mac_rpmusx(void *rpmd) 102 { 103 rpm_t *rpm = rpmd; 104 105 return rpm_read(rpm, 0, RPMX_CONST1) & 0x700ULL; 106 } 107 108 int rpm_get_nr_lmacs(void *rpmd) 109 { 110 rpm_t *rpm = rpmd; 111 112 return hweight8(rpm_read(rpm, 0, CGXX_CMRX_RX_LMACS) & 0xFULL); 113 } 114 115 int rpm2_get_nr_lmacs(void *rpmd) 116 { 117 rpm_t *rpm = rpmd; 118 119 return hweight8(rpm_read(rpm, 0, RPM2_CMRX_RX_LMACS) & 0xFFULL); 120 } 121 122 int rpm_lmac_tx_enable(void *rpmd, int lmac_id, bool enable) 123 { 124 rpm_t *rpm = rpmd; 125 u64 cfg, last; 126 127 if (!is_lmac_valid(rpm, lmac_id)) 128 return -ENODEV; 129 130 cfg = rpm_read(rpm, lmac_id, RPMX_MTI_MAC100X_COMMAND_CONFIG); 131 last = cfg; 132 if (enable) 133 cfg |= RPM_TX_EN; 134 else 135 cfg &= ~(RPM_TX_EN); 136 137 if (cfg != last) 138 rpm_write(rpm, lmac_id, RPMX_MTI_MAC100X_COMMAND_CONFIG, cfg); 139 return !!(last & RPM_TX_EN); 140 } 141 142 int rpm_lmac_rx_tx_enable(void *rpmd, int lmac_id, bool enable) 143 { 144 rpm_t *rpm = rpmd; 145 u64 cfg; 146 147 if (!is_lmac_valid(rpm, lmac_id)) 148 return -ENODEV; 149 150 cfg = rpm_read(rpm, lmac_id, RPMX_MTI_MAC100X_COMMAND_CONFIG); 151 if (enable) 152 cfg |= RPM_RX_EN | RPM_TX_EN; 153 else 154 cfg &= ~(RPM_RX_EN | RPM_TX_EN); 155 rpm_write(rpm, lmac_id, RPMX_MTI_MAC100X_COMMAND_CONFIG, cfg); 156 return 0; 157 } 158 159 void rpm_lmac_enadis_rx_pause_fwding(void *rpmd, int lmac_id, bool enable) 160 { 161 rpm_t *rpm = rpmd; 162 struct lmac *lmac; 163 u64 cfg; 164 165 if (!rpm) 166 return; 167 168 lmac = lmac_pdata(lmac_id, rpm); 169 if (!lmac) 170 return; 171 172 /* Pause frames are not enabled just return */ 173 if (!bitmap_weight(lmac->rx_fc_pfvf_bmap.bmap, lmac->rx_fc_pfvf_bmap.max)) 174 return; 175 176 if (enable) { 177 cfg = rpm_read(rpm, lmac_id, RPMX_MTI_MAC100X_COMMAND_CONFIG); 178 cfg &= ~RPMX_MTI_MAC100X_COMMAND_CONFIG_PAUSE_IGNORE; 179 rpm_write(rpm, lmac_id, RPMX_MTI_MAC100X_COMMAND_CONFIG, cfg); 180 } else { 181 cfg = rpm_read(rpm, lmac_id, RPMX_MTI_MAC100X_COMMAND_CONFIG); 182 cfg |= RPMX_MTI_MAC100X_COMMAND_CONFIG_PAUSE_IGNORE; 183 rpm_write(rpm, lmac_id, RPMX_MTI_MAC100X_COMMAND_CONFIG, cfg); 184 } 185 } 186 187 int rpm_lmac_get_pause_frm_status(void *rpmd, int lmac_id, 188 u8 *tx_pause, u8 *rx_pause) 189 { 190 rpm_t *rpm = rpmd; 191 u64 cfg; 192 193 if (!is_lmac_valid(rpm, lmac_id)) 194 return -ENODEV; 195 196 cfg = rpm_read(rpm, lmac_id, RPMX_MTI_MAC100X_COMMAND_CONFIG); 197 if (!(cfg & RPMX_MTI_MAC100X_COMMAND_CONFIG_PFC_MODE)) { 198 *rx_pause = !(cfg & RPMX_MTI_MAC100X_COMMAND_CONFIG_RX_P_DISABLE); 199 *tx_pause = !(cfg & RPMX_MTI_MAC100X_COMMAND_CONFIG_TX_P_DISABLE); 200 } 201 202 return 0; 203 } 204 205 static void rpm_cfg_pfc_quanta_thresh(rpm_t *rpm, int lmac_id, 206 unsigned long pfc_en, 207 bool enable) 208 { 209 u64 quanta_offset = 0, quanta_thresh = 0, cfg; 210 int i, shift; 211 212 /* Set pause time and interval */ 213 for_each_set_bit(i, &pfc_en, 16) { 214 switch (i) { 215 case 0: 216 case 1: 217 quanta_offset = RPMX_MTI_MAC100X_CL01_PAUSE_QUANTA; 218 quanta_thresh = RPMX_MTI_MAC100X_CL01_QUANTA_THRESH; 219 break; 220 case 2: 221 case 3: 222 quanta_offset = RPMX_MTI_MAC100X_CL23_PAUSE_QUANTA; 223 quanta_thresh = RPMX_MTI_MAC100X_CL23_QUANTA_THRESH; 224 break; 225 case 4: 226 case 5: 227 quanta_offset = RPMX_MTI_MAC100X_CL45_PAUSE_QUANTA; 228 quanta_thresh = RPMX_MTI_MAC100X_CL45_QUANTA_THRESH; 229 break; 230 case 6: 231 case 7: 232 quanta_offset = RPMX_MTI_MAC100X_CL67_PAUSE_QUANTA; 233 quanta_thresh = RPMX_MTI_MAC100X_CL67_QUANTA_THRESH; 234 break; 235 case 8: 236 case 9: 237 quanta_offset = RPMX_MTI_MAC100X_CL89_PAUSE_QUANTA; 238 quanta_thresh = RPMX_MTI_MAC100X_CL89_QUANTA_THRESH; 239 break; 240 case 10: 241 case 11: 242 quanta_offset = RPMX_MTI_MAC100X_CL1011_PAUSE_QUANTA; 243 quanta_thresh = RPMX_MTI_MAC100X_CL1011_QUANTA_THRESH; 244 break; 245 case 12: 246 case 13: 247 quanta_offset = RPMX_MTI_MAC100X_CL1213_PAUSE_QUANTA; 248 quanta_thresh = RPMX_MTI_MAC100X_CL1213_QUANTA_THRESH; 249 break; 250 case 14: 251 case 15: 252 quanta_offset = RPMX_MTI_MAC100X_CL1415_PAUSE_QUANTA; 253 quanta_thresh = RPMX_MTI_MAC100X_CL1415_QUANTA_THRESH; 254 break; 255 } 256 257 if (!quanta_offset || !quanta_thresh) 258 continue; 259 260 shift = (i % 2) ? 1 : 0; 261 cfg = rpm_read(rpm, lmac_id, quanta_offset); 262 if (enable) { 263 cfg |= ((u64)RPM_DEFAULT_PAUSE_TIME << shift * 16); 264 } else { 265 if (!shift) 266 cfg &= ~GENMASK_ULL(15, 0); 267 else 268 cfg &= ~GENMASK_ULL(31, 16); 269 } 270 rpm_write(rpm, lmac_id, quanta_offset, cfg); 271 272 cfg = rpm_read(rpm, lmac_id, quanta_thresh); 273 if (enable) { 274 cfg |= ((u64)(RPM_DEFAULT_PAUSE_TIME / 2) << shift * 16); 275 } else { 276 if (!shift) 277 cfg &= ~GENMASK_ULL(15, 0); 278 else 279 cfg &= ~GENMASK_ULL(31, 16); 280 } 281 rpm_write(rpm, lmac_id, quanta_thresh, cfg); 282 } 283 } 284 285 static void rpm2_lmac_cfg_bp(rpm_t *rpm, int lmac_id, u8 tx_pause, u8 rx_pause) 286 { 287 u64 cfg; 288 289 cfg = rpm_read(rpm, lmac_id, RPM2_CMR_RX_OVR_BP); 290 if (tx_pause) { 291 /* Configure CL0 Pause Quanta & threshold 292 * for 802.3X frames 293 */ 294 rpm_cfg_pfc_quanta_thresh(rpm, lmac_id, 1, true); 295 cfg &= ~RPM2_CMR_RX_OVR_BP_EN; 296 } else { 297 /* Disable all Pause Quanta & threshold values */ 298 rpm_cfg_pfc_quanta_thresh(rpm, lmac_id, 0xffff, false); 299 cfg |= RPM2_CMR_RX_OVR_BP_EN; 300 cfg &= ~RPM2_CMR_RX_OVR_BP_BP; 301 } 302 rpm_write(rpm, lmac_id, RPM2_CMR_RX_OVR_BP, cfg); 303 } 304 305 static void rpm_lmac_cfg_bp(rpm_t *rpm, int lmac_id, u8 tx_pause, u8 rx_pause) 306 { 307 u64 cfg; 308 309 cfg = rpm_read(rpm, 0, RPMX_CMR_RX_OVR_BP); 310 if (tx_pause) { 311 /* Configure CL0 Pause Quanta & threshold for 312 * 802.3X frames 313 */ 314 rpm_cfg_pfc_quanta_thresh(rpm, lmac_id, 1, true); 315 cfg &= ~RPMX_CMR_RX_OVR_BP_EN(lmac_id); 316 } else { 317 /* Disable all Pause Quanta & threshold values */ 318 rpm_cfg_pfc_quanta_thresh(rpm, lmac_id, 0xffff, false); 319 cfg |= RPMX_CMR_RX_OVR_BP_EN(lmac_id); 320 cfg &= ~RPMX_CMR_RX_OVR_BP_BP(lmac_id); 321 } 322 rpm_write(rpm, 0, RPMX_CMR_RX_OVR_BP, cfg); 323 } 324 325 int rpm_lmac_enadis_pause_frm(void *rpmd, int lmac_id, u8 tx_pause, 326 u8 rx_pause) 327 { 328 rpm_t *rpm = rpmd; 329 u64 cfg; 330 331 if (!is_lmac_valid(rpm, lmac_id)) 332 return -ENODEV; 333 334 cfg = rpm_read(rpm, lmac_id, RPMX_MTI_MAC100X_COMMAND_CONFIG); 335 cfg &= ~RPMX_MTI_MAC100X_COMMAND_CONFIG_RX_P_DISABLE; 336 cfg |= rx_pause ? 0x0 : RPMX_MTI_MAC100X_COMMAND_CONFIG_RX_P_DISABLE; 337 cfg &= ~RPMX_MTI_MAC100X_COMMAND_CONFIG_PAUSE_IGNORE; 338 cfg |= rx_pause ? 0x0 : RPMX_MTI_MAC100X_COMMAND_CONFIG_PAUSE_IGNORE; 339 rpm_write(rpm, lmac_id, RPMX_MTI_MAC100X_COMMAND_CONFIG, cfg); 340 341 cfg = rpm_read(rpm, lmac_id, RPMX_MTI_MAC100X_COMMAND_CONFIG); 342 cfg &= ~RPMX_MTI_MAC100X_COMMAND_CONFIG_TX_P_DISABLE; 343 cfg |= tx_pause ? 0x0 : RPMX_MTI_MAC100X_COMMAND_CONFIG_TX_P_DISABLE; 344 rpm_write(rpm, lmac_id, RPMX_MTI_MAC100X_COMMAND_CONFIG, cfg); 345 346 if (is_dev_rpm2(rpm)) 347 rpm2_lmac_cfg_bp(rpm, lmac_id, tx_pause, rx_pause); 348 else 349 rpm_lmac_cfg_bp(rpm, lmac_id, tx_pause, rx_pause); 350 351 return 0; 352 } 353 354 void rpm_lmac_pause_frm_config(void *rpmd, int lmac_id, bool enable) 355 { 356 rpm_t *rpm = rpmd; 357 u64 cfg; 358 359 /* ALL pause frames received are completely ignored */ 360 cfg = rpm_read(rpm, lmac_id, RPMX_MTI_MAC100X_COMMAND_CONFIG); 361 cfg |= RPMX_MTI_MAC100X_COMMAND_CONFIG_RX_P_DISABLE; 362 rpm_write(rpm, lmac_id, RPMX_MTI_MAC100X_COMMAND_CONFIG, cfg); 363 364 /* Disable forward pause to TX block */ 365 cfg = rpm_read(rpm, lmac_id, RPMX_MTI_MAC100X_COMMAND_CONFIG); 366 cfg |= RPMX_MTI_MAC100X_COMMAND_CONFIG_PAUSE_IGNORE; 367 rpm_write(rpm, lmac_id, RPMX_MTI_MAC100X_COMMAND_CONFIG, cfg); 368 369 /* Disable pause frames transmission */ 370 cfg = rpm_read(rpm, lmac_id, RPMX_MTI_MAC100X_COMMAND_CONFIG); 371 cfg |= RPMX_MTI_MAC100X_COMMAND_CONFIG_TX_P_DISABLE; 372 rpm_write(rpm, lmac_id, RPMX_MTI_MAC100X_COMMAND_CONFIG, cfg); 373 374 /* Enable channel mask for all LMACS */ 375 if (is_dev_rpm2(rpm)) 376 rpm_write(rpm, lmac_id, RPM2_CMR_CHAN_MSK_OR, 0xffff); 377 else 378 rpm_write(rpm, 0, RPMX_CMR_CHAN_MSK_OR, ~0ULL); 379 380 /* Disable all PFC classes */ 381 cfg = rpm_read(rpm, lmac_id, RPMX_CMRX_PRT_CBFC_CTL); 382 cfg = FIELD_SET(RPM_PFC_CLASS_MASK, 0, cfg); 383 rpm_write(rpm, lmac_id, RPMX_CMRX_PRT_CBFC_CTL, cfg); 384 } 385 386 int rpm_get_rx_stats(void *rpmd, int lmac_id, int idx, u64 *rx_stat) 387 { 388 rpm_t *rpm = rpmd; 389 u64 val_lo, val_hi; 390 391 if (!is_lmac_valid(rpm, lmac_id)) 392 return -ENODEV; 393 394 mutex_lock(&rpm->lock); 395 396 /* Update idx to point per lmac Rx statistics page */ 397 idx += lmac_id * rpm->mac_ops->rx_stats_cnt; 398 399 /* Read lower 32 bits of counter */ 400 val_lo = rpm_read(rpm, 0, RPMX_MTI_STAT_RX_STAT_PAGES_COUNTERX + 401 (idx * 8)); 402 403 /* upon read of lower 32 bits, higher 32 bits are written 404 * to RPMX_MTI_STAT_DATA_HI_CDC 405 */ 406 val_hi = rpm_read(rpm, 0, RPMX_MTI_STAT_DATA_HI_CDC); 407 408 *rx_stat = (val_hi << 32 | val_lo); 409 410 mutex_unlock(&rpm->lock); 411 return 0; 412 } 413 414 int rpm_get_tx_stats(void *rpmd, int lmac_id, int idx, u64 *tx_stat) 415 { 416 rpm_t *rpm = rpmd; 417 u64 val_lo, val_hi; 418 419 if (!is_lmac_valid(rpm, lmac_id)) 420 return -ENODEV; 421 422 mutex_lock(&rpm->lock); 423 424 /* Update idx to point per lmac Tx statistics page */ 425 idx += lmac_id * rpm->mac_ops->tx_stats_cnt; 426 427 val_lo = rpm_read(rpm, 0, RPMX_MTI_STAT_TX_STAT_PAGES_COUNTERX + 428 (idx * 8)); 429 val_hi = rpm_read(rpm, 0, RPMX_MTI_STAT_DATA_HI_CDC); 430 431 *tx_stat = (val_hi << 32 | val_lo); 432 433 mutex_unlock(&rpm->lock); 434 return 0; 435 } 436 437 u8 rpm_get_lmac_type(void *rpmd, int lmac_id) 438 { 439 rpm_t *rpm = rpmd; 440 u64 req = 0, resp; 441 int err; 442 443 req = FIELD_SET(CMDREG_ID, CGX_CMD_GET_LINK_STS, req); 444 err = cgx_fwi_cmd_generic(req, &resp, rpm, 0); 445 if (!err) 446 return FIELD_GET(RESP_LINKSTAT_LMAC_TYPE, resp); 447 return err; 448 } 449 450 u32 rpm_get_lmac_fifo_len(void *rpmd, int lmac_id) 451 { 452 rpm_t *rpm = rpmd; 453 u64 hi_perf_lmac; 454 u8 num_lmacs; 455 u32 fifo_len; 456 457 fifo_len = rpm->mac_ops->fifo_len; 458 num_lmacs = rpm->mac_ops->get_nr_lmacs(rpm); 459 460 switch (num_lmacs) { 461 case 1: 462 return fifo_len; 463 case 2: 464 return fifo_len / 2; 465 case 3: 466 /* LMAC marked as hi_perf gets half of the FIFO and rest 1/4th */ 467 hi_perf_lmac = rpm_read(rpm, 0, CGXX_CMRX_RX_LMACS); 468 hi_perf_lmac = (hi_perf_lmac >> 4) & 0x3ULL; 469 if (lmac_id == hi_perf_lmac) 470 return fifo_len / 2; 471 return fifo_len / 4; 472 case 4: 473 default: 474 return fifo_len / 4; 475 } 476 return 0; 477 } 478 479 static int rpmusx_lmac_internal_loopback(rpm_t *rpm, int lmac_id, bool enable) 480 { 481 u64 cfg; 482 483 cfg = rpm_read(rpm, lmac_id, RPM2_USX_PCSX_CONTROL1); 484 485 if (enable) 486 cfg |= RPM2_USX_PCS_LBK; 487 else 488 cfg &= ~RPM2_USX_PCS_LBK; 489 rpm_write(rpm, lmac_id, RPM2_USX_PCSX_CONTROL1, cfg); 490 491 return 0; 492 } 493 494 u32 rpm2_get_lmac_fifo_len(void *rpmd, int lmac_id) 495 { 496 u64 hi_perf_lmac, lmac_info; 497 rpm_t *rpm = rpmd; 498 u8 num_lmacs; 499 u32 fifo_len; 500 501 lmac_info = rpm_read(rpm, 0, RPM2_CMRX_RX_LMACS); 502 /* LMACs are divided into two groups and each group 503 * gets half of the FIFO 504 * Group0 lmac_id range {0..3} 505 * Group1 lmac_id range {4..7} 506 */ 507 fifo_len = rpm->mac_ops->fifo_len / 2; 508 509 if (lmac_id < 4) { 510 num_lmacs = hweight8(lmac_info & 0xF); 511 hi_perf_lmac = (lmac_info >> 8) & 0x3ULL; 512 } else { 513 num_lmacs = hweight8(lmac_info & 0xF0); 514 hi_perf_lmac = (lmac_info >> 10) & 0x3ULL; 515 hi_perf_lmac += 4; 516 } 517 518 switch (num_lmacs) { 519 case 1: 520 return fifo_len; 521 case 2: 522 return fifo_len / 2; 523 case 3: 524 /* LMAC marked as hi_perf gets half of the FIFO 525 * and rest 1/4th 526 */ 527 if (lmac_id == hi_perf_lmac) 528 return fifo_len / 2; 529 return fifo_len / 4; 530 case 4: 531 default: 532 return fifo_len / 4; 533 } 534 return 0; 535 } 536 537 int rpm_lmac_internal_loopback(void *rpmd, int lmac_id, bool enable) 538 { 539 rpm_t *rpm = rpmd; 540 u8 lmac_type; 541 u64 cfg; 542 543 if (!is_lmac_valid(rpm, lmac_id)) 544 return -ENODEV; 545 lmac_type = rpm->mac_ops->get_lmac_type(rpm, lmac_id); 546 547 if (lmac_type == LMAC_MODE_QSGMII || lmac_type == LMAC_MODE_SGMII) { 548 dev_err(&rpm->pdev->dev, "loopback not supported for LPC mode\n"); 549 return 0; 550 } 551 552 if (is_dev_rpm2(rpm) && is_mac_rpmusx(rpm)) 553 return rpmusx_lmac_internal_loopback(rpm, lmac_id, enable); 554 555 cfg = rpm_read(rpm, lmac_id, RPMX_MTI_PCS100X_CONTROL1); 556 557 if (enable) 558 cfg |= RPMX_MTI_PCS_LBK; 559 else 560 cfg &= ~RPMX_MTI_PCS_LBK; 561 rpm_write(rpm, lmac_id, RPMX_MTI_PCS100X_CONTROL1, cfg); 562 563 return 0; 564 } 565 566 void rpm_lmac_ptp_config(void *rpmd, int lmac_id, bool enable) 567 { 568 rpm_t *rpm = rpmd; 569 u64 cfg; 570 571 if (!is_lmac_valid(rpm, lmac_id)) 572 return; 573 574 cfg = rpm_read(rpm, lmac_id, RPMX_CMRX_CFG); 575 if (enable) { 576 cfg |= RPMX_RX_TS_PREPEND; 577 cfg |= RPMX_TX_PTP_1S_SUPPORT; 578 } else { 579 cfg &= ~RPMX_RX_TS_PREPEND; 580 cfg &= ~RPMX_TX_PTP_1S_SUPPORT; 581 } 582 583 rpm_write(rpm, lmac_id, RPMX_CMRX_CFG, cfg); 584 585 cfg = rpm_read(rpm, lmac_id, RPMX_MTI_MAC100X_XIF_MODE); 586 587 if (enable) { 588 cfg |= RPMX_ONESTEP_ENABLE; 589 cfg &= ~RPMX_TS_BINARY_MODE; 590 } else { 591 cfg &= ~RPMX_ONESTEP_ENABLE; 592 } 593 594 rpm_write(rpm, lmac_id, RPMX_MTI_MAC100X_XIF_MODE, cfg); 595 } 596 597 int rpm_lmac_pfc_config(void *rpmd, int lmac_id, u8 tx_pause, u8 rx_pause, u16 pfc_en) 598 { 599 u64 cfg, class_en, pfc_class_mask_cfg; 600 rpm_t *rpm = rpmd; 601 602 if (!is_lmac_valid(rpm, lmac_id)) 603 return -ENODEV; 604 605 cfg = rpm_read(rpm, lmac_id, RPMX_MTI_MAC100X_COMMAND_CONFIG); 606 class_en = rpm_read(rpm, lmac_id, RPMX_CMRX_PRT_CBFC_CTL); 607 pfc_en |= FIELD_GET(RPM_PFC_CLASS_MASK, class_en); 608 609 if (rx_pause) { 610 cfg &= ~(RPMX_MTI_MAC100X_COMMAND_CONFIG_RX_P_DISABLE | 611 RPMX_MTI_MAC100X_COMMAND_CONFIG_PAUSE_IGNORE | 612 RPMX_MTI_MAC100X_COMMAND_CONFIG_PAUSE_FWD); 613 } else { 614 cfg |= (RPMX_MTI_MAC100X_COMMAND_CONFIG_RX_P_DISABLE | 615 RPMX_MTI_MAC100X_COMMAND_CONFIG_PAUSE_IGNORE | 616 RPMX_MTI_MAC100X_COMMAND_CONFIG_PAUSE_FWD); 617 } 618 619 if (tx_pause) { 620 rpm_cfg_pfc_quanta_thresh(rpm, lmac_id, pfc_en, true); 621 cfg &= ~RPMX_MTI_MAC100X_COMMAND_CONFIG_TX_P_DISABLE; 622 class_en = FIELD_SET(RPM_PFC_CLASS_MASK, pfc_en, class_en); 623 } else { 624 rpm_cfg_pfc_quanta_thresh(rpm, lmac_id, 0xfff, false); 625 cfg |= RPMX_MTI_MAC100X_COMMAND_CONFIG_TX_P_DISABLE; 626 class_en = FIELD_SET(RPM_PFC_CLASS_MASK, 0, class_en); 627 } 628 629 if (!rx_pause && !tx_pause) 630 cfg &= ~RPMX_MTI_MAC100X_COMMAND_CONFIG_PFC_MODE; 631 else 632 cfg |= RPMX_MTI_MAC100X_COMMAND_CONFIG_PFC_MODE; 633 634 rpm_write(rpm, lmac_id, RPMX_MTI_MAC100X_COMMAND_CONFIG, cfg); 635 636 pfc_class_mask_cfg = is_dev_rpm2(rpm) ? RPM2_CMRX_PRT_CBFC_CTL : 637 RPMX_CMRX_PRT_CBFC_CTL; 638 639 rpm_write(rpm, lmac_id, pfc_class_mask_cfg, class_en); 640 641 return 0; 642 } 643 644 int rpm_lmac_get_pfc_frm_cfg(void *rpmd, int lmac_id, u8 *tx_pause, u8 *rx_pause) 645 { 646 rpm_t *rpm = rpmd; 647 u64 cfg; 648 649 if (!is_lmac_valid(rpm, lmac_id)) 650 return -ENODEV; 651 652 cfg = rpm_read(rpm, lmac_id, RPMX_MTI_MAC100X_COMMAND_CONFIG); 653 if (cfg & RPMX_MTI_MAC100X_COMMAND_CONFIG_PFC_MODE) { 654 *rx_pause = !(cfg & RPMX_MTI_MAC100X_COMMAND_CONFIG_RX_P_DISABLE); 655 *tx_pause = !(cfg & RPMX_MTI_MAC100X_COMMAND_CONFIG_TX_P_DISABLE); 656 } 657 658 return 0; 659 } 660 661 int rpm_get_fec_stats(void *rpmd, int lmac_id, struct cgx_fec_stats_rsp *rsp) 662 { 663 u64 val_lo, val_hi; 664 rpm_t *rpm = rpmd; 665 u64 cfg; 666 667 if (!is_lmac_valid(rpm, lmac_id)) 668 return -ENODEV; 669 670 if (rpm->lmac_idmap[lmac_id]->link_info.fec == OTX2_FEC_NONE) 671 return 0; 672 673 if (rpm->lmac_idmap[lmac_id]->link_info.fec == OTX2_FEC_BASER) { 674 val_lo = rpm_read(rpm, lmac_id, RPMX_MTI_FCFECX_VL0_CCW_LO); 675 val_hi = rpm_read(rpm, lmac_id, RPMX_MTI_FCFECX_CW_HI); 676 rsp->fec_corr_blks = (val_hi << 16 | val_lo); 677 678 val_lo = rpm_read(rpm, lmac_id, RPMX_MTI_FCFECX_VL0_NCCW_LO); 679 val_hi = rpm_read(rpm, lmac_id, RPMX_MTI_FCFECX_CW_HI); 680 rsp->fec_uncorr_blks = (val_hi << 16 | val_lo); 681 682 /* 50G uses 2 Physical serdes lines */ 683 if (rpm->lmac_idmap[lmac_id]->link_info.lmac_type_id == 684 LMAC_MODE_50G_R) { 685 val_lo = rpm_read(rpm, lmac_id, 686 RPMX_MTI_FCFECX_VL1_CCW_LO); 687 val_hi = rpm_read(rpm, lmac_id, 688 RPMX_MTI_FCFECX_CW_HI); 689 rsp->fec_corr_blks += (val_hi << 16 | val_lo); 690 691 val_lo = rpm_read(rpm, lmac_id, 692 RPMX_MTI_FCFECX_VL1_NCCW_LO); 693 val_hi = rpm_read(rpm, lmac_id, 694 RPMX_MTI_FCFECX_CW_HI); 695 rsp->fec_uncorr_blks += (val_hi << 16 | val_lo); 696 } 697 } else { 698 /* enable RS-FEC capture */ 699 cfg = rpm_read(rpm, 0, RPMX_MTI_STAT_STATN_CONTROL); 700 cfg |= RPMX_RSFEC_RX_CAPTURE | BIT(lmac_id); 701 rpm_write(rpm, 0, RPMX_MTI_STAT_STATN_CONTROL, cfg); 702 703 val_lo = rpm_read(rpm, 0, 704 RPMX_MTI_RSFEC_STAT_COUNTER_CAPTURE_2); 705 val_hi = rpm_read(rpm, 0, RPMX_MTI_STAT_DATA_HI_CDC); 706 rsp->fec_corr_blks = (val_hi << 32 | val_lo); 707 708 val_lo = rpm_read(rpm, 0, 709 RPMX_MTI_RSFEC_STAT_COUNTER_CAPTURE_3); 710 val_hi = rpm_read(rpm, 0, RPMX_MTI_STAT_DATA_HI_CDC); 711 rsp->fec_uncorr_blks = (val_hi << 32 | val_lo); 712 } 713 714 return 0; 715 } 716