1 // SPDX-License-Identifier: GPL-2.0 2 /* Marvell PTP driver 3 * 4 * Copyright (C) 2020 Marvell International Ltd. 5 */ 6 7 #include <linux/bitfield.h> 8 #include <linux/device.h> 9 #include <linux/module.h> 10 #include <linux/pci.h> 11 12 #include "ptp.h" 13 #include "mbox.h" 14 #include "rvu.h" 15 16 #define DRV_NAME "Marvell PTP Driver" 17 18 #define PCI_DEVID_OCTEONTX2_PTP 0xA00C 19 #define PCI_SUBSYS_DEVID_OCTX2_98xx_PTP 0xB100 20 #define PCI_SUBSYS_DEVID_OCTX2_96XX_PTP 0xB200 21 #define PCI_SUBSYS_DEVID_OCTX2_95XX_PTP 0xB300 22 #define PCI_SUBSYS_DEVID_OCTX2_95XXN_PTP 0xB400 23 #define PCI_SUBSYS_DEVID_OCTX2_95MM_PTP 0xB500 24 #define PCI_SUBSYS_DEVID_OCTX2_95XXO_PTP 0xB600 25 #define PCI_DEVID_OCTEONTX2_RST 0xA085 26 #define PCI_DEVID_CN10K_PTP 0xA09E 27 28 #define PCI_PTP_BAR_NO 0 29 #define PCI_RST_BAR_NO 0 30 31 #define PTP_CLOCK_CFG 0xF00ULL 32 #define PTP_CLOCK_CFG_PTP_EN BIT_ULL(0) 33 #define PTP_CLOCK_LO 0xF08ULL 34 #define PTP_CLOCK_HI 0xF10ULL 35 #define PTP_CLOCK_COMP 0xF18ULL 36 37 #define RST_BOOT 0x1600ULL 38 #define RST_MUL_BITS GENMASK_ULL(38, 33) 39 #define CLOCK_BASE_RATE 50000000ULL 40 41 static struct ptp *first_ptp_block; 42 static const struct pci_device_id ptp_id_table[]; 43 44 static u64 get_clock_rate(void) 45 { 46 u64 cfg, ret = CLOCK_BASE_RATE * 16; 47 struct pci_dev *pdev; 48 void __iomem *base; 49 50 /* To get the input clock frequency with which PTP co-processor 51 * block is running the base frequency(50 MHz) needs to be multiplied 52 * with multiplier bits present in RST_BOOT register of RESET block. 53 * Hence below code gets the multiplier bits from the RESET PCI 54 * device present in the system. 55 */ 56 pdev = pci_get_device(PCI_VENDOR_ID_CAVIUM, 57 PCI_DEVID_OCTEONTX2_RST, NULL); 58 if (!pdev) 59 goto error; 60 61 base = pci_ioremap_bar(pdev, PCI_RST_BAR_NO); 62 if (!base) 63 goto error_put_pdev; 64 65 cfg = readq(base + RST_BOOT); 66 ret = CLOCK_BASE_RATE * FIELD_GET(RST_MUL_BITS, cfg); 67 68 iounmap(base); 69 70 error_put_pdev: 71 pci_dev_put(pdev); 72 73 error: 74 return ret; 75 } 76 77 struct ptp *ptp_get(void) 78 { 79 struct ptp *ptp = first_ptp_block; 80 81 /* Check PTP block is present in hardware */ 82 if (!pci_dev_present(ptp_id_table)) 83 return ERR_PTR(-ENODEV); 84 /* Check driver is bound to PTP block */ 85 if (!ptp) 86 ptp = ERR_PTR(-EPROBE_DEFER); 87 88 return ptp; 89 } 90 91 void ptp_put(struct ptp *ptp) 92 { 93 if (!ptp) 94 return; 95 96 pci_dev_put(ptp->pdev); 97 } 98 99 static int ptp_adjfine(struct ptp *ptp, long scaled_ppm) 100 { 101 bool neg_adj = false; 102 u64 comp; 103 u64 adj; 104 s64 ppb; 105 106 if (scaled_ppm < 0) { 107 neg_adj = true; 108 scaled_ppm = -scaled_ppm; 109 } 110 111 /* The hardware adds the clock compensation value to the PTP clock 112 * on every coprocessor clock cycle. Typical convention is that it 113 * represent number of nanosecond betwen each cycle. In this 114 * convention compensation value is in 64 bit fixed-point 115 * representation where upper 32 bits are number of nanoseconds 116 * and lower is fractions of nanosecond. 117 * The scaled_ppm represent the ratio in "parts per million" by which 118 * the compensation value should be corrected. 119 * To calculate new compenstation value we use 64bit fixed point 120 * arithmetic on following formula 121 * comp = tbase + tbase * scaled_ppm / (1M * 2^16) 122 * where tbase is the basic compensation value calculated 123 * initialy in the probe function. 124 */ 125 comp = ((u64)1000000000ull << 32) / ptp->clock_rate; 126 /* convert scaled_ppm to ppb */ 127 ppb = 1 + scaled_ppm; 128 ppb *= 125; 129 ppb >>= 13; 130 adj = comp * ppb; 131 adj = div_u64(adj, 1000000000ull); 132 comp = neg_adj ? comp - adj : comp + adj; 133 134 writeq(comp, ptp->reg_base + PTP_CLOCK_COMP); 135 136 return 0; 137 } 138 139 static int ptp_get_clock(struct ptp *ptp, u64 *clk) 140 { 141 /* Return the current PTP clock */ 142 *clk = readq(ptp->reg_base + PTP_CLOCK_HI); 143 144 return 0; 145 } 146 147 static int ptp_probe(struct pci_dev *pdev, 148 const struct pci_device_id *ent) 149 { 150 struct device *dev = &pdev->dev; 151 struct ptp *ptp; 152 u64 clock_comp; 153 u64 clock_cfg; 154 int err; 155 156 ptp = devm_kzalloc(dev, sizeof(*ptp), GFP_KERNEL); 157 if (!ptp) { 158 err = -ENOMEM; 159 goto error; 160 } 161 162 ptp->pdev = pdev; 163 164 err = pcim_enable_device(pdev); 165 if (err) 166 goto error_free; 167 168 err = pcim_iomap_regions(pdev, 1 << PCI_PTP_BAR_NO, pci_name(pdev)); 169 if (err) 170 goto error_free; 171 172 ptp->reg_base = pcim_iomap_table(pdev)[PCI_PTP_BAR_NO]; 173 174 ptp->clock_rate = get_clock_rate(); 175 176 /* Enable PTP clock */ 177 clock_cfg = readq(ptp->reg_base + PTP_CLOCK_CFG); 178 clock_cfg |= PTP_CLOCK_CFG_PTP_EN; 179 writeq(clock_cfg, ptp->reg_base + PTP_CLOCK_CFG); 180 181 clock_comp = ((u64)1000000000ull << 32) / ptp->clock_rate; 182 /* Initial compensation value to start the nanosecs counter */ 183 writeq(clock_comp, ptp->reg_base + PTP_CLOCK_COMP); 184 185 pci_set_drvdata(pdev, ptp); 186 if (!first_ptp_block) 187 first_ptp_block = ptp; 188 189 return 0; 190 191 error_free: 192 devm_kfree(dev, ptp); 193 194 error: 195 /* For `ptp_get()` we need to differentiate between the case 196 * when the core has not tried to probe this device and the case when 197 * the probe failed. In the later case we pretend that the 198 * initialization was successful and keep the error in 199 * `dev->driver_data`. 200 */ 201 pci_set_drvdata(pdev, ERR_PTR(err)); 202 if (!first_ptp_block) 203 first_ptp_block = ERR_PTR(err); 204 205 return 0; 206 } 207 208 static void ptp_remove(struct pci_dev *pdev) 209 { 210 struct ptp *ptp = pci_get_drvdata(pdev); 211 u64 clock_cfg; 212 213 if (IS_ERR_OR_NULL(ptp)) 214 return; 215 216 /* Disable PTP clock */ 217 clock_cfg = readq(ptp->reg_base + PTP_CLOCK_CFG); 218 clock_cfg &= ~PTP_CLOCK_CFG_PTP_EN; 219 writeq(clock_cfg, ptp->reg_base + PTP_CLOCK_CFG); 220 } 221 222 static const struct pci_device_id ptp_id_table[] = { 223 { PCI_DEVICE_SUB(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_OCTEONTX2_PTP, 224 PCI_VENDOR_ID_CAVIUM, 225 PCI_SUBSYS_DEVID_OCTX2_98xx_PTP) }, 226 { PCI_DEVICE_SUB(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_OCTEONTX2_PTP, 227 PCI_VENDOR_ID_CAVIUM, 228 PCI_SUBSYS_DEVID_OCTX2_96XX_PTP) }, 229 { PCI_DEVICE_SUB(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_OCTEONTX2_PTP, 230 PCI_VENDOR_ID_CAVIUM, 231 PCI_SUBSYS_DEVID_OCTX2_95XX_PTP) }, 232 { PCI_DEVICE_SUB(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_OCTEONTX2_PTP, 233 PCI_VENDOR_ID_CAVIUM, 234 PCI_SUBSYS_DEVID_OCTX2_95XXN_PTP) }, 235 { PCI_DEVICE_SUB(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_OCTEONTX2_PTP, 236 PCI_VENDOR_ID_CAVIUM, 237 PCI_SUBSYS_DEVID_OCTX2_95MM_PTP) }, 238 { PCI_DEVICE_SUB(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_OCTEONTX2_PTP, 239 PCI_VENDOR_ID_CAVIUM, 240 PCI_SUBSYS_DEVID_OCTX2_95XXO_PTP) }, 241 { PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_CN10K_PTP) }, 242 { 0, } 243 }; 244 245 struct pci_driver ptp_driver = { 246 .name = DRV_NAME, 247 .id_table = ptp_id_table, 248 .probe = ptp_probe, 249 .remove = ptp_remove, 250 }; 251 252 int rvu_mbox_handler_ptp_op(struct rvu *rvu, struct ptp_req *req, 253 struct ptp_rsp *rsp) 254 { 255 int err = 0; 256 257 /* This function is the PTP mailbox handler invoked when 258 * called by AF consumers/netdev drivers via mailbox mechanism. 259 * It is used by netdev driver to get the PTP clock and to set 260 * frequency adjustments. Since mailbox can be called without 261 * notion of whether the driver is bound to ptp device below 262 * validation is needed as first step. 263 */ 264 if (!rvu->ptp) 265 return -ENODEV; 266 267 switch (req->op) { 268 case PTP_OP_ADJFINE: 269 err = ptp_adjfine(rvu->ptp, req->scaled_ppm); 270 break; 271 case PTP_OP_GET_CLOCK: 272 err = ptp_get_clock(rvu->ptp, &rsp->clk); 273 break; 274 default: 275 err = -EINVAL; 276 break; 277 } 278 279 return err; 280 } 281