1 // SPDX-License-Identifier: GPL-2.0 2 /* Marvell PTP driver 3 * 4 * Copyright (C) 2020 Marvell International Ltd. 5 */ 6 7 #include <linux/bitfield.h> 8 #include <linux/device.h> 9 #include <linux/module.h> 10 #include <linux/pci.h> 11 12 #include "ptp.h" 13 #include "mbox.h" 14 #include "rvu.h" 15 16 #define DRV_NAME "Marvell PTP Driver" 17 18 #define PCI_DEVID_OCTEONTX2_PTP 0xA00C 19 #define PCI_SUBSYS_DEVID_OCTX2_98xx_PTP 0xB100 20 #define PCI_SUBSYS_DEVID_OCTX2_96XX_PTP 0xB200 21 #define PCI_SUBSYS_DEVID_OCTX2_95XX_PTP 0xB300 22 #define PCI_SUBSYS_DEVID_OCTX2_LOKI_PTP 0xB400 23 #define PCI_SUBSYS_DEVID_OCTX2_95MM_PTP 0xB500 24 #define PCI_DEVID_OCTEONTX2_RST 0xA085 25 26 #define PCI_PTP_BAR_NO 0 27 #define PCI_RST_BAR_NO 0 28 29 #define PTP_CLOCK_CFG 0xF00ULL 30 #define PTP_CLOCK_CFG_PTP_EN BIT_ULL(0) 31 #define PTP_CLOCK_LO 0xF08ULL 32 #define PTP_CLOCK_HI 0xF10ULL 33 #define PTP_CLOCK_COMP 0xF18ULL 34 35 #define RST_BOOT 0x1600ULL 36 #define RST_MUL_BITS GENMASK_ULL(38, 33) 37 #define CLOCK_BASE_RATE 50000000ULL 38 39 static u64 get_clock_rate(void) 40 { 41 u64 cfg, ret = CLOCK_BASE_RATE * 16; 42 struct pci_dev *pdev; 43 void __iomem *base; 44 45 /* To get the input clock frequency with which PTP co-processor 46 * block is running the base frequency(50 MHz) needs to be multiplied 47 * with multiplier bits present in RST_BOOT register of RESET block. 48 * Hence below code gets the multiplier bits from the RESET PCI 49 * device present in the system. 50 */ 51 pdev = pci_get_device(PCI_VENDOR_ID_CAVIUM, 52 PCI_DEVID_OCTEONTX2_RST, NULL); 53 if (!pdev) 54 goto error; 55 56 base = pci_ioremap_bar(pdev, PCI_RST_BAR_NO); 57 if (!base) 58 goto error_put_pdev; 59 60 cfg = readq(base + RST_BOOT); 61 ret = CLOCK_BASE_RATE * FIELD_GET(RST_MUL_BITS, cfg); 62 63 iounmap(base); 64 65 error_put_pdev: 66 pci_dev_put(pdev); 67 68 error: 69 return ret; 70 } 71 72 struct ptp *ptp_get(void) 73 { 74 struct pci_dev *pdev; 75 struct ptp *ptp; 76 77 /* If the PTP pci device is found on the system and ptp 78 * driver is bound to it then the PTP pci device is returned 79 * to the caller(rvu driver). 80 */ 81 pdev = pci_get_device(PCI_VENDOR_ID_CAVIUM, 82 PCI_DEVID_OCTEONTX2_PTP, NULL); 83 if (!pdev) 84 return ERR_PTR(-ENODEV); 85 86 ptp = pci_get_drvdata(pdev); 87 if (!ptp) 88 ptp = ERR_PTR(-EPROBE_DEFER); 89 if (IS_ERR(ptp)) 90 pci_dev_put(pdev); 91 92 return ptp; 93 } 94 95 void ptp_put(struct ptp *ptp) 96 { 97 if (!ptp) 98 return; 99 100 pci_dev_put(ptp->pdev); 101 } 102 103 static int ptp_adjfine(struct ptp *ptp, long scaled_ppm) 104 { 105 bool neg_adj = false; 106 u64 comp; 107 u64 adj; 108 s64 ppb; 109 110 if (scaled_ppm < 0) { 111 neg_adj = true; 112 scaled_ppm = -scaled_ppm; 113 } 114 115 /* The hardware adds the clock compensation value to the PTP clock 116 * on every coprocessor clock cycle. Typical convention is that it 117 * represent number of nanosecond betwen each cycle. In this 118 * convention compensation value is in 64 bit fixed-point 119 * representation where upper 32 bits are number of nanoseconds 120 * and lower is fractions of nanosecond. 121 * The scaled_ppm represent the ratio in "parts per million" by which 122 * the compensation value should be corrected. 123 * To calculate new compenstation value we use 64bit fixed point 124 * arithmetic on following formula 125 * comp = tbase + tbase * scaled_ppm / (1M * 2^16) 126 * where tbase is the basic compensation value calculated 127 * initialy in the probe function. 128 */ 129 comp = ((u64)1000000000ull << 32) / ptp->clock_rate; 130 /* convert scaled_ppm to ppb */ 131 ppb = 1 + scaled_ppm; 132 ppb *= 125; 133 ppb >>= 13; 134 adj = comp * ppb; 135 adj = div_u64(adj, 1000000000ull); 136 comp = neg_adj ? comp - adj : comp + adj; 137 138 writeq(comp, ptp->reg_base + PTP_CLOCK_COMP); 139 140 return 0; 141 } 142 143 static int ptp_get_clock(struct ptp *ptp, u64 *clk) 144 { 145 /* Return the current PTP clock */ 146 *clk = readq(ptp->reg_base + PTP_CLOCK_HI); 147 148 return 0; 149 } 150 151 static int ptp_probe(struct pci_dev *pdev, 152 const struct pci_device_id *ent) 153 { 154 struct device *dev = &pdev->dev; 155 struct ptp *ptp; 156 u64 clock_comp; 157 u64 clock_cfg; 158 int err; 159 160 ptp = devm_kzalloc(dev, sizeof(*ptp), GFP_KERNEL); 161 if (!ptp) { 162 err = -ENOMEM; 163 goto error; 164 } 165 166 ptp->pdev = pdev; 167 168 err = pcim_enable_device(pdev); 169 if (err) 170 goto error_free; 171 172 err = pcim_iomap_regions(pdev, 1 << PCI_PTP_BAR_NO, pci_name(pdev)); 173 if (err) 174 goto error_free; 175 176 ptp->reg_base = pcim_iomap_table(pdev)[PCI_PTP_BAR_NO]; 177 178 ptp->clock_rate = get_clock_rate(); 179 180 /* Enable PTP clock */ 181 clock_cfg = readq(ptp->reg_base + PTP_CLOCK_CFG); 182 clock_cfg |= PTP_CLOCK_CFG_PTP_EN; 183 writeq(clock_cfg, ptp->reg_base + PTP_CLOCK_CFG); 184 185 clock_comp = ((u64)1000000000ull << 32) / ptp->clock_rate; 186 /* Initial compensation value to start the nanosecs counter */ 187 writeq(clock_comp, ptp->reg_base + PTP_CLOCK_COMP); 188 189 pci_set_drvdata(pdev, ptp); 190 191 return 0; 192 193 error_free: 194 devm_kfree(dev, ptp); 195 196 error: 197 /* For `ptp_get()` we need to differentiate between the case 198 * when the core has not tried to probe this device and the case when 199 * the probe failed. In the later case we pretend that the 200 * initialization was successful and keep the error in 201 * `dev->driver_data`. 202 */ 203 pci_set_drvdata(pdev, ERR_PTR(err)); 204 return 0; 205 } 206 207 static void ptp_remove(struct pci_dev *pdev) 208 { 209 struct ptp *ptp = pci_get_drvdata(pdev); 210 u64 clock_cfg; 211 212 if (IS_ERR_OR_NULL(ptp)) 213 return; 214 215 /* Disable PTP clock */ 216 clock_cfg = readq(ptp->reg_base + PTP_CLOCK_CFG); 217 clock_cfg &= ~PTP_CLOCK_CFG_PTP_EN; 218 writeq(clock_cfg, ptp->reg_base + PTP_CLOCK_CFG); 219 } 220 221 static const struct pci_device_id ptp_id_table[] = { 222 { PCI_DEVICE_SUB(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_OCTEONTX2_PTP, 223 PCI_VENDOR_ID_CAVIUM, 224 PCI_SUBSYS_DEVID_OCTX2_98xx_PTP) }, 225 { PCI_DEVICE_SUB(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_OCTEONTX2_PTP, 226 PCI_VENDOR_ID_CAVIUM, 227 PCI_SUBSYS_DEVID_OCTX2_96XX_PTP) }, 228 { PCI_DEVICE_SUB(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_OCTEONTX2_PTP, 229 PCI_VENDOR_ID_CAVIUM, 230 PCI_SUBSYS_DEVID_OCTX2_95XX_PTP) }, 231 { PCI_DEVICE_SUB(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_OCTEONTX2_PTP, 232 PCI_VENDOR_ID_CAVIUM, 233 PCI_SUBSYS_DEVID_OCTX2_LOKI_PTP) }, 234 { PCI_DEVICE_SUB(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_OCTEONTX2_PTP, 235 PCI_VENDOR_ID_CAVIUM, 236 PCI_SUBSYS_DEVID_OCTX2_95MM_PTP) }, 237 { 0, } 238 }; 239 240 struct pci_driver ptp_driver = { 241 .name = DRV_NAME, 242 .id_table = ptp_id_table, 243 .probe = ptp_probe, 244 .remove = ptp_remove, 245 }; 246 247 int rvu_mbox_handler_ptp_op(struct rvu *rvu, struct ptp_req *req, 248 struct ptp_rsp *rsp) 249 { 250 int err = 0; 251 252 /* This function is the PTP mailbox handler invoked when 253 * called by AF consumers/netdev drivers via mailbox mechanism. 254 * It is used by netdev driver to get the PTP clock and to set 255 * frequency adjustments. Since mailbox can be called without 256 * notion of whether the driver is bound to ptp device below 257 * validation is needed as first step. 258 */ 259 if (!rvu->ptp) 260 return -ENODEV; 261 262 switch (req->op) { 263 case PTP_OP_ADJFINE: 264 err = ptp_adjfine(rvu->ptp, req->scaled_ppm); 265 break; 266 case PTP_OP_GET_CLOCK: 267 err = ptp_get_clock(rvu->ptp, &rsp->clk); 268 break; 269 default: 270 err = -EINVAL; 271 break; 272 } 273 274 return err; 275 } 276