1 // SPDX-License-Identifier: GPL-2.0 2 /* Marvell PTP driver 3 * 4 * Copyright (C) 2020 Marvell. 5 * 6 */ 7 8 #include <linux/bitfield.h> 9 #include <linux/device.h> 10 #include <linux/module.h> 11 #include <linux/pci.h> 12 13 #include "ptp.h" 14 #include "mbox.h" 15 #include "rvu.h" 16 17 #define DRV_NAME "Marvell PTP Driver" 18 19 #define PCI_DEVID_OCTEONTX2_PTP 0xA00C 20 #define PCI_SUBSYS_DEVID_OCTX2_98xx_PTP 0xB100 21 #define PCI_SUBSYS_DEVID_OCTX2_96XX_PTP 0xB200 22 #define PCI_SUBSYS_DEVID_OCTX2_95XX_PTP 0xB300 23 #define PCI_SUBSYS_DEVID_OCTX2_95XXN_PTP 0xB400 24 #define PCI_SUBSYS_DEVID_OCTX2_95MM_PTP 0xB500 25 #define PCI_SUBSYS_DEVID_OCTX2_95XXO_PTP 0xB600 26 #define PCI_DEVID_OCTEONTX2_RST 0xA085 27 #define PCI_DEVID_CN10K_PTP 0xA09E 28 29 #define PCI_PTP_BAR_NO 0 30 31 #define PTP_CLOCK_CFG 0xF00ULL 32 #define PTP_CLOCK_CFG_PTP_EN BIT_ULL(0) 33 #define PTP_CLOCK_CFG_EXT_CLK_EN BIT_ULL(1) 34 #define PTP_CLOCK_CFG_EXT_CLK_IN_MASK GENMASK_ULL(7, 2) 35 #define PTP_CLOCK_CFG_TSTMP_EDGE BIT_ULL(9) 36 #define PTP_CLOCK_CFG_TSTMP_EN BIT_ULL(8) 37 #define PTP_CLOCK_CFG_TSTMP_IN_MASK GENMASK_ULL(15, 10) 38 #define PTP_CLOCK_CFG_PPS_EN BIT_ULL(30) 39 #define PTP_CLOCK_CFG_PPS_INV BIT_ULL(31) 40 41 #define PTP_PPS_HI_INCR 0xF60ULL 42 #define PTP_PPS_LO_INCR 0xF68ULL 43 #define PTP_PPS_THRESH_HI 0xF58ULL 44 45 #define PTP_CLOCK_LO 0xF08ULL 46 #define PTP_CLOCK_HI 0xF10ULL 47 #define PTP_CLOCK_COMP 0xF18ULL 48 #define PTP_TIMESTAMP 0xF20ULL 49 50 static struct ptp *first_ptp_block; 51 static const struct pci_device_id ptp_id_table[]; 52 53 struct ptp *ptp_get(void) 54 { 55 struct ptp *ptp = first_ptp_block; 56 57 /* Check PTP block is present in hardware */ 58 if (!pci_dev_present(ptp_id_table)) 59 return ERR_PTR(-ENODEV); 60 /* Check driver is bound to PTP block */ 61 if (!ptp) 62 ptp = ERR_PTR(-EPROBE_DEFER); 63 else 64 pci_dev_get(ptp->pdev); 65 66 return ptp; 67 } 68 69 void ptp_put(struct ptp *ptp) 70 { 71 if (!ptp) 72 return; 73 74 pci_dev_put(ptp->pdev); 75 } 76 77 static int ptp_adjfine(struct ptp *ptp, long scaled_ppm) 78 { 79 bool neg_adj = false; 80 u64 comp; 81 u64 adj; 82 s64 ppb; 83 84 if (scaled_ppm < 0) { 85 neg_adj = true; 86 scaled_ppm = -scaled_ppm; 87 } 88 89 /* The hardware adds the clock compensation value to the PTP clock 90 * on every coprocessor clock cycle. Typical convention is that it 91 * represent number of nanosecond betwen each cycle. In this 92 * convention compensation value is in 64 bit fixed-point 93 * representation where upper 32 bits are number of nanoseconds 94 * and lower is fractions of nanosecond. 95 * The scaled_ppm represent the ratio in "parts per million" by which 96 * the compensation value should be corrected. 97 * To calculate new compenstation value we use 64bit fixed point 98 * arithmetic on following formula 99 * comp = tbase + tbase * scaled_ppm / (1M * 2^16) 100 * where tbase is the basic compensation value calculated 101 * initialy in the probe function. 102 */ 103 comp = ((u64)1000000000ull << 32) / ptp->clock_rate; 104 /* convert scaled_ppm to ppb */ 105 ppb = 1 + scaled_ppm; 106 ppb *= 125; 107 ppb >>= 13; 108 adj = comp * ppb; 109 adj = div_u64(adj, 1000000000ull); 110 comp = neg_adj ? comp - adj : comp + adj; 111 112 writeq(comp, ptp->reg_base + PTP_CLOCK_COMP); 113 114 return 0; 115 } 116 117 static int ptp_get_clock(struct ptp *ptp, u64 *clk) 118 { 119 /* Return the current PTP clock */ 120 *clk = readq(ptp->reg_base + PTP_CLOCK_HI); 121 122 return 0; 123 } 124 125 void ptp_start(struct ptp *ptp, u64 sclk, u32 ext_clk_freq, u32 extts) 126 { 127 struct pci_dev *pdev; 128 u64 clock_comp; 129 u64 clock_cfg; 130 131 if (!ptp) 132 return; 133 134 pdev = ptp->pdev; 135 136 if (!sclk) { 137 dev_err(&pdev->dev, "PTP input clock cannot be zero\n"); 138 return; 139 } 140 141 /* sclk is in MHz */ 142 ptp->clock_rate = sclk * 1000000; 143 144 /* Enable PTP clock */ 145 clock_cfg = readq(ptp->reg_base + PTP_CLOCK_CFG); 146 147 if (ext_clk_freq) { 148 ptp->clock_rate = ext_clk_freq; 149 /* Set GPIO as PTP clock source */ 150 clock_cfg &= ~PTP_CLOCK_CFG_EXT_CLK_IN_MASK; 151 clock_cfg |= PTP_CLOCK_CFG_EXT_CLK_EN; 152 } 153 154 if (extts) { 155 clock_cfg |= PTP_CLOCK_CFG_TSTMP_EDGE; 156 /* Set GPIO as timestamping source */ 157 clock_cfg &= ~PTP_CLOCK_CFG_TSTMP_IN_MASK; 158 clock_cfg |= PTP_CLOCK_CFG_TSTMP_EN; 159 } 160 161 clock_cfg |= PTP_CLOCK_CFG_PTP_EN; 162 clock_cfg |= PTP_CLOCK_CFG_PPS_EN | PTP_CLOCK_CFG_PPS_INV; 163 writeq(clock_cfg, ptp->reg_base + PTP_CLOCK_CFG); 164 165 /* Set 50% duty cycle for 1Hz output */ 166 writeq(0x1dcd650000000000, ptp->reg_base + PTP_PPS_HI_INCR); 167 writeq(0x1dcd650000000000, ptp->reg_base + PTP_PPS_LO_INCR); 168 169 clock_comp = ((u64)1000000000ull << 32) / ptp->clock_rate; 170 /* Initial compensation value to start the nanosecs counter */ 171 writeq(clock_comp, ptp->reg_base + PTP_CLOCK_COMP); 172 } 173 174 static int ptp_get_tstmp(struct ptp *ptp, u64 *clk) 175 { 176 *clk = readq(ptp->reg_base + PTP_TIMESTAMP); 177 178 return 0; 179 } 180 181 static int ptp_set_thresh(struct ptp *ptp, u64 thresh) 182 { 183 writeq(thresh, ptp->reg_base + PTP_PPS_THRESH_HI); 184 185 return 0; 186 } 187 188 static int ptp_probe(struct pci_dev *pdev, 189 const struct pci_device_id *ent) 190 { 191 struct device *dev = &pdev->dev; 192 struct ptp *ptp; 193 int err; 194 195 ptp = devm_kzalloc(dev, sizeof(*ptp), GFP_KERNEL); 196 if (!ptp) { 197 err = -ENOMEM; 198 goto error; 199 } 200 201 ptp->pdev = pdev; 202 203 err = pcim_enable_device(pdev); 204 if (err) 205 goto error_free; 206 207 err = pcim_iomap_regions(pdev, 1 << PCI_PTP_BAR_NO, pci_name(pdev)); 208 if (err) 209 goto error_free; 210 211 ptp->reg_base = pcim_iomap_table(pdev)[PCI_PTP_BAR_NO]; 212 213 pci_set_drvdata(pdev, ptp); 214 if (!first_ptp_block) 215 first_ptp_block = ptp; 216 217 return 0; 218 219 error_free: 220 devm_kfree(dev, ptp); 221 222 error: 223 /* For `ptp_get()` we need to differentiate between the case 224 * when the core has not tried to probe this device and the case when 225 * the probe failed. In the later case we pretend that the 226 * initialization was successful and keep the error in 227 * `dev->driver_data`. 228 */ 229 pci_set_drvdata(pdev, ERR_PTR(err)); 230 if (!first_ptp_block) 231 first_ptp_block = ERR_PTR(err); 232 233 return 0; 234 } 235 236 static void ptp_remove(struct pci_dev *pdev) 237 { 238 struct ptp *ptp = pci_get_drvdata(pdev); 239 u64 clock_cfg; 240 241 if (IS_ERR_OR_NULL(ptp)) 242 return; 243 244 /* Disable PTP clock */ 245 clock_cfg = readq(ptp->reg_base + PTP_CLOCK_CFG); 246 clock_cfg &= ~PTP_CLOCK_CFG_PTP_EN; 247 writeq(clock_cfg, ptp->reg_base + PTP_CLOCK_CFG); 248 } 249 250 static const struct pci_device_id ptp_id_table[] = { 251 { PCI_DEVICE_SUB(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_OCTEONTX2_PTP, 252 PCI_VENDOR_ID_CAVIUM, 253 PCI_SUBSYS_DEVID_OCTX2_98xx_PTP) }, 254 { PCI_DEVICE_SUB(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_OCTEONTX2_PTP, 255 PCI_VENDOR_ID_CAVIUM, 256 PCI_SUBSYS_DEVID_OCTX2_96XX_PTP) }, 257 { PCI_DEVICE_SUB(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_OCTEONTX2_PTP, 258 PCI_VENDOR_ID_CAVIUM, 259 PCI_SUBSYS_DEVID_OCTX2_95XX_PTP) }, 260 { PCI_DEVICE_SUB(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_OCTEONTX2_PTP, 261 PCI_VENDOR_ID_CAVIUM, 262 PCI_SUBSYS_DEVID_OCTX2_95XXN_PTP) }, 263 { PCI_DEVICE_SUB(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_OCTEONTX2_PTP, 264 PCI_VENDOR_ID_CAVIUM, 265 PCI_SUBSYS_DEVID_OCTX2_95MM_PTP) }, 266 { PCI_DEVICE_SUB(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_OCTEONTX2_PTP, 267 PCI_VENDOR_ID_CAVIUM, 268 PCI_SUBSYS_DEVID_OCTX2_95XXO_PTP) }, 269 { PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_CN10K_PTP) }, 270 { 0, } 271 }; 272 273 struct pci_driver ptp_driver = { 274 .name = DRV_NAME, 275 .id_table = ptp_id_table, 276 .probe = ptp_probe, 277 .remove = ptp_remove, 278 }; 279 280 int rvu_mbox_handler_ptp_op(struct rvu *rvu, struct ptp_req *req, 281 struct ptp_rsp *rsp) 282 { 283 int err = 0; 284 285 /* This function is the PTP mailbox handler invoked when 286 * called by AF consumers/netdev drivers via mailbox mechanism. 287 * It is used by netdev driver to get the PTP clock and to set 288 * frequency adjustments. Since mailbox can be called without 289 * notion of whether the driver is bound to ptp device below 290 * validation is needed as first step. 291 */ 292 if (!rvu->ptp) 293 return -ENODEV; 294 295 switch (req->op) { 296 case PTP_OP_ADJFINE: 297 err = ptp_adjfine(rvu->ptp, req->scaled_ppm); 298 break; 299 case PTP_OP_GET_CLOCK: 300 err = ptp_get_clock(rvu->ptp, &rsp->clk); 301 break; 302 case PTP_OP_GET_TSTMP: 303 err = ptp_get_tstmp(rvu->ptp, &rsp->clk); 304 break; 305 case PTP_OP_SET_THRESH: 306 err = ptp_set_thresh(rvu->ptp, req->thresh); 307 break; 308 default: 309 err = -EINVAL; 310 break; 311 } 312 313 return err; 314 } 315