1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*  Marvell OcteonTx2 RVU Admin Function driver
3  *
4  * Copyright (C) 2018 Marvell International Ltd.
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License version 2 as
8  * published by the Free Software Foundation.
9  */
10 
11 #ifndef NPC_H
12 #define NPC_H
13 
14 enum NPC_LID_E {
15 	NPC_LID_LA = 0,
16 	NPC_LID_LB,
17 	NPC_LID_LC,
18 	NPC_LID_LD,
19 	NPC_LID_LE,
20 	NPC_LID_LF,
21 	NPC_LID_LG,
22 	NPC_LID_LH,
23 };
24 
25 #define NPC_LT_NA 0
26 
27 enum npc_kpu_la_ltype {
28 	NPC_LT_LA_8023 = 1,
29 	NPC_LT_LA_ETHER,
30 	NPC_LT_LA_IH_NIX_ETHER,
31 	NPC_LT_LA_IH_8_ETHER,
32 	NPC_LT_LA_IH_4_ETHER,
33 	NPC_LT_LA_IH_2_ETHER,
34 	NPC_LT_LA_HIGIG2_ETHER,
35 	NPC_LT_LA_IH_NIX_HIGIG2_ETHER,
36 	NPC_LT_LA_CUSTOM_L2_90B_ETHER,
37 	NPC_LT_LA_CH_LEN_90B_ETHER,
38 	NPC_LT_LA_CPT_HDR,
39 	NPC_LT_LA_CUSTOM_L2_24B_ETHER,
40 	NPC_LT_LA_CUSTOM0 = 0xE,
41 	NPC_LT_LA_CUSTOM1 = 0xF,
42 };
43 
44 enum npc_kpu_lb_ltype {
45 	NPC_LT_LB_ETAG = 1,
46 	NPC_LT_LB_CTAG,
47 	NPC_LT_LB_STAG_QINQ,
48 	NPC_LT_LB_BTAG,
49 	NPC_LT_LB_PPPOE,
50 	NPC_LT_LB_DSA,
51 	NPC_LT_LB_DSA_VLAN,
52 	NPC_LT_LB_EDSA,
53 	NPC_LT_LB_EDSA_VLAN,
54 	NPC_LT_LB_EXDSA,
55 	NPC_LT_LB_EXDSA_VLAN,
56 	NPC_LT_LB_FDSA,
57 	NPC_LT_LB_VLAN_EXDSA,
58 	NPC_LT_LB_CUSTOM0 = 0xE,
59 	NPC_LT_LB_CUSTOM1 = 0xF,
60 };
61 
62 enum npc_kpu_lc_ltype {
63 	NPC_LT_LC_IP = 1,
64 	NPC_LT_LC_IP_OPT,
65 	NPC_LT_LC_IP6,
66 	NPC_LT_LC_IP6_EXT,
67 	NPC_LT_LC_ARP,
68 	NPC_LT_LC_RARP,
69 	NPC_LT_LC_MPLS,
70 	NPC_LT_LC_NSH,
71 	NPC_LT_LC_PTP,
72 	NPC_LT_LC_FCOE,
73 	NPC_LT_LC_NGIO,
74 	NPC_LT_LC_CUSTOM0 = 0xE,
75 	NPC_LT_LC_CUSTOM1 = 0xF,
76 };
77 
78 /* Don't modify Ltypes upto SCTP, otherwise it will
79  * effect flow tag calculation and thus RSS.
80  */
81 enum npc_kpu_ld_ltype {
82 	NPC_LT_LD_TCP = 1,
83 	NPC_LT_LD_UDP,
84 	NPC_LT_LD_ICMP,
85 	NPC_LT_LD_SCTP,
86 	NPC_LT_LD_ICMP6,
87 	NPC_LT_LD_CUSTOM0,
88 	NPC_LT_LD_CUSTOM1,
89 	NPC_LT_LD_IGMP = 8,
90 	NPC_LT_LD_AH,
91 	NPC_LT_LD_GRE,
92 	NPC_LT_LD_NVGRE,
93 	NPC_LT_LD_NSH,
94 	NPC_LT_LD_TU_MPLS_IN_NSH,
95 	NPC_LT_LD_TU_MPLS_IN_IP,
96 };
97 
98 enum npc_kpu_le_ltype {
99 	NPC_LT_LE_VXLAN = 1,
100 	NPC_LT_LE_GENEVE,
101 	NPC_LT_LE_ESP,
102 	NPC_LT_LE_GTPU = 4,
103 	NPC_LT_LE_VXLANGPE,
104 	NPC_LT_LE_GTPC,
105 	NPC_LT_LE_NSH,
106 	NPC_LT_LE_TU_MPLS_IN_GRE,
107 	NPC_LT_LE_TU_NSH_IN_GRE,
108 	NPC_LT_LE_TU_MPLS_IN_UDP,
109 	NPC_LT_LE_CUSTOM0 = 0xE,
110 	NPC_LT_LE_CUSTOM1 = 0xF,
111 };
112 
113 enum npc_kpu_lf_ltype {
114 	NPC_LT_LF_TU_ETHER = 1,
115 	NPC_LT_LF_TU_PPP,
116 	NPC_LT_LF_TU_MPLS_IN_VXLANGPE,
117 	NPC_LT_LF_TU_NSH_IN_VXLANGPE,
118 	NPC_LT_LF_TU_MPLS_IN_NSH,
119 	NPC_LT_LF_TU_3RD_NSH,
120 	NPC_LT_LF_CUSTOM0 = 0xE,
121 	NPC_LT_LF_CUSTOM1 = 0xF,
122 };
123 
124 enum npc_kpu_lg_ltype {
125 	NPC_LT_LG_TU_IP = 1,
126 	NPC_LT_LG_TU_IP6,
127 	NPC_LT_LG_TU_ARP,
128 	NPC_LT_LG_TU_ETHER_IN_NSH,
129 	NPC_LT_LG_CUSTOM0 = 0xE,
130 	NPC_LT_LG_CUSTOM1 = 0xF,
131 };
132 
133 /* Don't modify Ltypes upto SCTP, otherwise it will
134  * effect flow tag calculation and thus RSS.
135  */
136 enum npc_kpu_lh_ltype {
137 	NPC_LT_LH_TU_TCP = 1,
138 	NPC_LT_LH_TU_UDP,
139 	NPC_LT_LH_TU_ICMP,
140 	NPC_LT_LH_TU_SCTP,
141 	NPC_LT_LH_TU_ICMP6,
142 	NPC_LT_LH_TU_IGMP = 8,
143 	NPC_LT_LH_TU_ESP,
144 	NPC_LT_LH_TU_AH,
145 	NPC_LT_LH_CUSTOM0 = 0xE,
146 	NPC_LT_LH_CUSTOM1 = 0xF,
147 };
148 
149 /* NPC port kind defines how the incoming or outgoing packets
150  * are processed. NPC accepts packets from up to 64 pkinds.
151  * Software assigns pkind for each incoming port such as CGX
152  * Ethernet interfaces, LBK interfaces, etc.
153  */
154 #define NPC_UNRESERVED_PKIND_COUNT NPC_RX_VLAN_EXDSA_PKIND
155 
156 enum npc_pkind_type {
157 	NPC_RX_LBK_PKIND = 0ULL,
158 	NPC_RX_VLAN_EXDSA_PKIND = 56ULL,
159 	NPC_RX_CHLEN24B_PKIND = 57ULL,
160 	NPC_RX_CPT_HDR_PKIND,
161 	NPC_RX_CHLEN90B_PKIND,
162 	NPC_TX_HIGIG_PKIND,
163 	NPC_RX_HIGIG_PKIND,
164 	NPC_RX_EDSA_PKIND,
165 	NPC_TX_DEF_PKIND,	/* NIX-TX PKIND */
166 };
167 
168 /* list of known and supported fields in packet header and
169  * fields present in key structure.
170  */
171 enum key_fields {
172 	NPC_DMAC,
173 	NPC_SMAC,
174 	NPC_ETYPE,
175 	NPC_OUTER_VID,
176 	NPC_TOS,
177 	NPC_SIP_IPV4,
178 	NPC_DIP_IPV4,
179 	NPC_SIP_IPV6,
180 	NPC_DIP_IPV6,
181 	NPC_IPPROTO_TCP,
182 	NPC_IPPROTO_UDP,
183 	NPC_IPPROTO_SCTP,
184 	NPC_IPPROTO_AH,
185 	NPC_IPPROTO_ESP,
186 	NPC_IPPROTO_ICMP,
187 	NPC_IPPROTO_ICMP6,
188 	NPC_SPORT_TCP,
189 	NPC_DPORT_TCP,
190 	NPC_SPORT_UDP,
191 	NPC_DPORT_UDP,
192 	NPC_SPORT_SCTP,
193 	NPC_DPORT_SCTP,
194 	NPC_HEADER_FIELDS_MAX,
195 	NPC_CHAN = NPC_HEADER_FIELDS_MAX, /* Valid when Rx */
196 	NPC_PF_FUNC, /* Valid when Tx */
197 	NPC_ERRLEV,
198 	NPC_ERRCODE,
199 	NPC_LXMB,
200 	NPC_LA,
201 	NPC_LB,
202 	NPC_LC,
203 	NPC_LD,
204 	NPC_LE,
205 	NPC_LF,
206 	NPC_LG,
207 	NPC_LH,
208 	/* Ethertype for untagged frame */
209 	NPC_ETYPE_ETHER,
210 	/* Ethertype for single tagged frame */
211 	NPC_ETYPE_TAG1,
212 	/* Ethertype for double tagged frame */
213 	NPC_ETYPE_TAG2,
214 	/* outer vlan tci for single tagged frame */
215 	NPC_VLAN_TAG1,
216 	/* outer vlan tci for double tagged frame */
217 	NPC_VLAN_TAG2,
218 	/* other header fields programmed to extract but not of our interest */
219 	NPC_UNKNOWN,
220 	NPC_KEY_FIELDS_MAX,
221 };
222 
223 struct npc_kpu_profile_cam {
224 	u8 state;
225 	u8 state_mask;
226 	u16 dp0;
227 	u16 dp0_mask;
228 	u16 dp1;
229 	u16 dp1_mask;
230 	u16 dp2;
231 	u16 dp2_mask;
232 } __packed;
233 
234 struct npc_kpu_profile_action {
235 	u8 errlev;
236 	u8 errcode;
237 	u8 dp0_offset;
238 	u8 dp1_offset;
239 	u8 dp2_offset;
240 	u8 bypass_count;
241 	u8 parse_done;
242 	u8 next_state;
243 	u8 ptr_advance;
244 	u8 cap_ena;
245 	u8 lid;
246 	u8 ltype;
247 	u8 flags;
248 	u8 offset;
249 	u8 mask;
250 	u8 right;
251 	u8 shift;
252 } __packed;
253 
254 struct npc_kpu_profile {
255 	int cam_entries;
256 	int action_entries;
257 	struct npc_kpu_profile_cam *cam;
258 	struct npc_kpu_profile_action *action;
259 };
260 
261 /* NPC KPU register formats */
262 struct npc_kpu_cam {
263 #if defined(__BIG_ENDIAN_BITFIELD)
264 	u64 rsvd_63_56     : 8;
265 	u64 state          : 8;
266 	u64 dp2_data       : 16;
267 	u64 dp1_data       : 16;
268 	u64 dp0_data       : 16;
269 #else
270 	u64 dp0_data       : 16;
271 	u64 dp1_data       : 16;
272 	u64 dp2_data       : 16;
273 	u64 state          : 8;
274 	u64 rsvd_63_56     : 8;
275 #endif
276 };
277 
278 struct npc_kpu_action0 {
279 #if defined(__BIG_ENDIAN_BITFIELD)
280 	u64 rsvd_63_57     : 7;
281 	u64 byp_count      : 3;
282 	u64 capture_ena    : 1;
283 	u64 parse_done     : 1;
284 	u64 next_state     : 8;
285 	u64 rsvd_43        : 1;
286 	u64 capture_lid    : 3;
287 	u64 capture_ltype  : 4;
288 	u64 capture_flags  : 8;
289 	u64 ptr_advance    : 8;
290 	u64 var_len_offset : 8;
291 	u64 var_len_mask   : 8;
292 	u64 var_len_right  : 1;
293 	u64 var_len_shift  : 3;
294 #else
295 	u64 var_len_shift  : 3;
296 	u64 var_len_right  : 1;
297 	u64 var_len_mask   : 8;
298 	u64 var_len_offset : 8;
299 	u64 ptr_advance    : 8;
300 	u64 capture_flags  : 8;
301 	u64 capture_ltype  : 4;
302 	u64 capture_lid    : 3;
303 	u64 rsvd_43        : 1;
304 	u64 next_state     : 8;
305 	u64 parse_done     : 1;
306 	u64 capture_ena    : 1;
307 	u64 byp_count      : 3;
308 	u64 rsvd_63_57     : 7;
309 #endif
310 };
311 
312 struct npc_kpu_action1 {
313 #if defined(__BIG_ENDIAN_BITFIELD)
314 	u64 rsvd_63_36     : 28;
315 	u64 errlev         : 4;
316 	u64 errcode        : 8;
317 	u64 dp2_offset     : 8;
318 	u64 dp1_offset     : 8;
319 	u64 dp0_offset     : 8;
320 #else
321 	u64 dp0_offset     : 8;
322 	u64 dp1_offset     : 8;
323 	u64 dp2_offset     : 8;
324 	u64 errcode        : 8;
325 	u64 errlev         : 4;
326 	u64 rsvd_63_36     : 28;
327 #endif
328 };
329 
330 struct npc_kpu_pkind_cpi_def {
331 #if defined(__BIG_ENDIAN_BITFIELD)
332 	u64 ena            : 1;
333 	u64 rsvd_62_59     : 4;
334 	u64 lid            : 3;
335 	u64 ltype_match    : 4;
336 	u64 ltype_mask     : 4;
337 	u64 flags_match    : 8;
338 	u64 flags_mask     : 8;
339 	u64 add_offset     : 8;
340 	u64 add_mask       : 8;
341 	u64 rsvd_15        : 1;
342 	u64 add_shift      : 3;
343 	u64 rsvd_11_10     : 2;
344 	u64 cpi_base       : 10;
345 #else
346 	u64 cpi_base       : 10;
347 	u64 rsvd_11_10     : 2;
348 	u64 add_shift      : 3;
349 	u64 rsvd_15        : 1;
350 	u64 add_mask       : 8;
351 	u64 add_offset     : 8;
352 	u64 flags_mask     : 8;
353 	u64 flags_match    : 8;
354 	u64 ltype_mask     : 4;
355 	u64 ltype_match    : 4;
356 	u64 lid            : 3;
357 	u64 rsvd_62_59     : 4;
358 	u64 ena            : 1;
359 #endif
360 };
361 
362 struct nix_rx_action {
363 #if defined(__BIG_ENDIAN_BITFIELD)
364 	u64	rsvd_63_61	:3;
365 	u64	flow_key_alg	:5;
366 	u64	match_id	:16;
367 	u64	index		:20;
368 	u64	pf_func		:16;
369 	u64	op		:4;
370 #else
371 	u64	op		:4;
372 	u64	pf_func		:16;
373 	u64	index		:20;
374 	u64	match_id	:16;
375 	u64	flow_key_alg	:5;
376 	u64	rsvd_63_61	:3;
377 #endif
378 };
379 
380 /* NPC_AF_INTFX_KEX_CFG field masks */
381 #define NPC_PARSE_NIBBLE		GENMASK_ULL(30, 0)
382 
383 /* NPC_PARSE_KEX_S nibble definitions for each field */
384 #define NPC_PARSE_NIBBLE_CHAN		GENMASK_ULL(2, 0)
385 #define NPC_PARSE_NIBBLE_ERRLEV		BIT_ULL(3)
386 #define NPC_PARSE_NIBBLE_ERRCODE	GENMASK_ULL(5, 4)
387 #define NPC_PARSE_NIBBLE_L2L3_BCAST	BIT_ULL(6)
388 #define NPC_PARSE_NIBBLE_LA_FLAGS	GENMASK_ULL(8, 7)
389 #define NPC_PARSE_NIBBLE_LA_LTYPE	BIT_ULL(9)
390 #define NPC_PARSE_NIBBLE_LB_FLAGS	GENMASK_ULL(11, 10)
391 #define NPC_PARSE_NIBBLE_LB_LTYPE	BIT_ULL(12)
392 #define NPC_PARSE_NIBBLE_LC_FLAGS	GENMASK_ULL(14, 13)
393 #define NPC_PARSE_NIBBLE_LC_LTYPE	BIT_ULL(15)
394 #define NPC_PARSE_NIBBLE_LD_FLAGS	GENMASK_ULL(17, 16)
395 #define NPC_PARSE_NIBBLE_LD_LTYPE	BIT_ULL(18)
396 #define NPC_PARSE_NIBBLE_LE_FLAGS	GENMASK_ULL(20, 19)
397 #define NPC_PARSE_NIBBLE_LE_LTYPE	BIT_ULL(21)
398 #define NPC_PARSE_NIBBLE_LF_FLAGS	GENMASK_ULL(23, 22)
399 #define NPC_PARSE_NIBBLE_LF_LTYPE	BIT_ULL(24)
400 #define NPC_PARSE_NIBBLE_LG_FLAGS	GENMASK_ULL(26, 25)
401 #define NPC_PARSE_NIBBLE_LG_LTYPE	BIT_ULL(27)
402 #define NPC_PARSE_NIBBLE_LH_FLAGS	GENMASK_ULL(29, 28)
403 #define NPC_PARSE_NIBBLE_LH_LTYPE	BIT_ULL(30)
404 
405 struct nix_tx_action {
406 #if defined(__BIG_ENDIAN_BITFIELD)
407 	u64	rsvd_63_48	:16;
408 	u64	match_id	:16;
409 	u64	index		:20;
410 	u64	rsvd_11_8	:8;
411 	u64	op		:4;
412 #else
413 	u64	op		:4;
414 	u64	rsvd_11_8	:8;
415 	u64	index		:20;
416 	u64	match_id	:16;
417 	u64	rsvd_63_48	:16;
418 #endif
419 };
420 
421 /* NIX Receive Vtag Action Structure */
422 #define RX_VTAG0_VALID_BIT		BIT_ULL(15)
423 #define RX_VTAG0_TYPE_MASK		GENMASK_ULL(14, 12)
424 #define RX_VTAG0_LID_MASK		GENMASK_ULL(10, 8)
425 #define RX_VTAG0_RELPTR_MASK		GENMASK_ULL(7, 0)
426 #define RX_VTAG1_VALID_BIT		BIT_ULL(47)
427 #define RX_VTAG1_TYPE_MASK		GENMASK_ULL(46, 44)
428 #define RX_VTAG1_LID_MASK		GENMASK_ULL(42, 40)
429 #define RX_VTAG1_RELPTR_MASK		GENMASK_ULL(39, 32)
430 
431 /* NIX Transmit Vtag Action Structure */
432 #define TX_VTAG0_DEF_MASK		GENMASK_ULL(25, 16)
433 #define TX_VTAG0_OP_MASK		GENMASK_ULL(13, 12)
434 #define TX_VTAG0_LID_MASK		GENMASK_ULL(10, 8)
435 #define TX_VTAG0_RELPTR_MASK		GENMASK_ULL(7, 0)
436 #define TX_VTAG1_DEF_MASK		GENMASK_ULL(57, 48)
437 #define TX_VTAG1_OP_MASK		GENMASK_ULL(45, 44)
438 #define TX_VTAG1_LID_MASK		GENMASK_ULL(42, 40)
439 #define TX_VTAG1_RELPTR_MASK		GENMASK_ULL(39, 32)
440 
441 /* NPC MCAM reserved entry index per nixlf */
442 #define NIXLF_UCAST_ENTRY	0
443 #define NIXLF_BCAST_ENTRY	1
444 #define NIXLF_ALLMULTI_ENTRY	2
445 #define NIXLF_PROMISC_ENTRY	3
446 
447 struct npc_coalesced_kpu_prfl {
448 #define NPC_SIGN	0x00666f727063706e
449 #define NPC_PRFL_NAME   "npc_prfls_array"
450 #define NPC_NAME_LEN	32
451 	__le64 signature; /* "npcprof\0" (8 bytes/ASCII characters) */
452 	u8 name[NPC_NAME_LEN]; /* KPU Profile name */
453 	u64 version; /* KPU firmware/profile version */
454 	u8 num_prfl; /* No of NPC profiles. */
455 	u16 prfl_sz[0];
456 };
457 
458 struct npc_mcam_kex {
459 	/* MKEX Profle Header */
460 	u64 mkex_sign; /* "mcam-kex-profile" (8 bytes/ASCII characters) */
461 	u8 name[MKEX_NAME_LEN];   /* MKEX Profile name */
462 	u64 cpu_model;   /* Format as profiled by CPU hardware */
463 	u64 kpu_version; /* KPU firmware/profile version */
464 	u64 reserved; /* Reserved for extension */
465 
466 	/* MKEX Profle Data */
467 	u64 keyx_cfg[NPC_MAX_INTF]; /* NPC_AF_INTF(0..1)_KEX_CFG */
468 	/* NPC_AF_KEX_LDATA(0..1)_FLAGS_CFG */
469 	u64 kex_ld_flags[NPC_MAX_LD];
470 	/* NPC_AF_INTF(0..1)_LID(0..7)_LT(0..15)_LD(0..1)_CFG */
471 	u64 intf_lid_lt_ld[NPC_MAX_INTF][NPC_MAX_LID][NPC_MAX_LT][NPC_MAX_LD];
472 	/* NPC_AF_INTF(0..1)_LDATA(0..1)_FLAGS(0..15)_CFG */
473 	u64 intf_ld_flags[NPC_MAX_INTF][NPC_MAX_LD][NPC_MAX_LFL];
474 } __packed;
475 
476 struct npc_kpu_fwdata {
477 	int	entries;
478 	/* What follows is:
479 	 * struct npc_kpu_profile_cam[entries];
480 	 * struct npc_kpu_profile_action[entries];
481 	 */
482 	u8	data[0];
483 } __packed;
484 
485 struct npc_lt_def {
486 	u8	ltype_mask;
487 	u8	ltype_match;
488 	u8	lid;
489 };
490 
491 struct npc_lt_def_ipsec {
492 	u8	ltype_mask;
493 	u8	ltype_match;
494 	u8	lid;
495 	u8	spi_offset;
496 	u8	spi_nz;
497 };
498 
499 struct npc_lt_def_apad {
500 	u8	ltype_mask;
501 	u8	ltype_match;
502 	u8	lid;
503 	u8	valid;
504 } __packed;
505 
506 struct npc_lt_def_color {
507 	u8	ltype_mask;
508 	u8	ltype_match;
509 	u8	lid;
510 	u8	noffset;
511 	u8	offset;
512 } __packed;
513 
514 struct npc_lt_def_et {
515 	u8	ltype_mask;
516 	u8	ltype_match;
517 	u8	lid;
518 	u8	valid;
519 	u8	offset;
520 } __packed;
521 
522 struct npc_lt_def_cfg {
523 	struct npc_lt_def	rx_ol2;
524 	struct npc_lt_def	rx_oip4;
525 	struct npc_lt_def	rx_iip4;
526 	struct npc_lt_def	rx_oip6;
527 	struct npc_lt_def	rx_iip6;
528 	struct npc_lt_def	rx_otcp;
529 	struct npc_lt_def	rx_itcp;
530 	struct npc_lt_def	rx_oudp;
531 	struct npc_lt_def	rx_iudp;
532 	struct npc_lt_def	rx_osctp;
533 	struct npc_lt_def	rx_isctp;
534 	struct npc_lt_def_ipsec	rx_ipsec[2];
535 	struct npc_lt_def	pck_ol2;
536 	struct npc_lt_def	pck_oip4;
537 	struct npc_lt_def	pck_oip6;
538 	struct npc_lt_def	pck_iip4;
539 	struct npc_lt_def_apad	rx_apad0;
540 	struct npc_lt_def_apad	rx_apad1;
541 	struct npc_lt_def_color	ovlan;
542 	struct npc_lt_def_color	ivlan;
543 	struct npc_lt_def_color	rx_gen0_color;
544 	struct npc_lt_def_color	rx_gen1_color;
545 	struct npc_lt_def_et	rx_et[2];
546 } __packed;
547 
548 /* Loadable KPU profile firmware data */
549 struct npc_kpu_profile_fwdata {
550 #define KPU_SIGN	0x00666f727075706b
551 #define KPU_NAME_LEN	32
552 /** Maximum number of custom KPU entries supported by the built-in profile. */
553 #define KPU_MAX_CST_ENT	2
554 	/* KPU Profle Header */
555 	__le64	signature; /* "kpuprof\0" (8 bytes/ASCII characters) */
556 	u8	name[KPU_NAME_LEN]; /* KPU Profile name */
557 	__le64	version; /* KPU profile version */
558 	u8	kpus;
559 	u8	reserved[7];
560 
561 	/* Default MKEX profile to be used with this KPU profile. May be
562 	 * overridden with mkex_profile module parameter. Format is same as for
563 	 * the MKEX profile to streamline processing.
564 	 */
565 	struct npc_mcam_kex	mkex;
566 	/* LTYPE values for specific HW offloaded protocols. */
567 	struct npc_lt_def_cfg	lt_def;
568 	/* Dynamically sized data:
569 	 *  Custom KPU CAM and ACTION configuration entries.
570 	 * struct npc_kpu_fwdata kpu[kpus];
571 	 */
572 	u8	data[0];
573 } __packed;
574 
575 struct rvu_npc_mcam_rule {
576 	struct flow_msg packet;
577 	struct flow_msg mask;
578 	u8 intf;
579 	union {
580 		struct nix_tx_action tx_action;
581 		struct nix_rx_action rx_action;
582 	};
583 	u64 vtag_action;
584 	struct list_head list;
585 	u64 features;
586 	u16 owner;
587 	u16 entry;
588 	u16 cntr;
589 	bool has_cntr;
590 	u8 default_rule;
591 	bool enable;
592 	bool vfvlan_cfg;
593 };
594 
595 #endif /* NPC_H */
596