1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Marvell RVU Admin Function driver 3 * 4 * Copyright (C) 2018 Marvell. 5 * 6 */ 7 8 #ifndef NPC_H 9 #define NPC_H 10 11 #define NPC_KEX_CHAN_MASK 0xFFFULL 12 13 #define SET_KEX_LD(intf, lid, ltype, ld, cfg) \ 14 rvu_write64(rvu, blkaddr, \ 15 NPC_AF_INTFX_LIDX_LTX_LDX_CFG(intf, lid, ltype, ld), cfg) 16 17 #define SET_KEX_LDFLAGS(intf, ld, flags, cfg) \ 18 rvu_write64(rvu, blkaddr, \ 19 NPC_AF_INTFX_LDATAX_FLAGSX_CFG(intf, ld, flags), cfg) 20 21 enum NPC_LID_E { 22 NPC_LID_LA = 0, 23 NPC_LID_LB, 24 NPC_LID_LC, 25 NPC_LID_LD, 26 NPC_LID_LE, 27 NPC_LID_LF, 28 NPC_LID_LG, 29 NPC_LID_LH, 30 }; 31 32 #define NPC_LT_NA 0 33 34 enum npc_kpu_la_ltype { 35 NPC_LT_LA_8023 = 1, 36 NPC_LT_LA_ETHER, 37 NPC_LT_LA_IH_NIX_ETHER, 38 NPC_LT_LA_HIGIG2_ETHER = 7, 39 NPC_LT_LA_IH_NIX_HIGIG2_ETHER, 40 NPC_LT_LA_CUSTOM_L2_90B_ETHER, 41 NPC_LT_LA_CPT_HDR, 42 NPC_LT_LA_CUSTOM_L2_24B_ETHER, 43 NPC_LT_LA_CUSTOM_PRE_L2_ETHER, 44 NPC_LT_LA_CUSTOM0 = 0xE, 45 NPC_LT_LA_CUSTOM1 = 0xF, 46 }; 47 48 enum npc_kpu_lb_ltype { 49 NPC_LT_LB_ETAG = 1, 50 NPC_LT_LB_CTAG, 51 NPC_LT_LB_STAG_QINQ, 52 NPC_LT_LB_BTAG, 53 NPC_LT_LB_PPPOE, 54 NPC_LT_LB_DSA, 55 NPC_LT_LB_DSA_VLAN, 56 NPC_LT_LB_EDSA, 57 NPC_LT_LB_EDSA_VLAN, 58 NPC_LT_LB_EXDSA, 59 NPC_LT_LB_EXDSA_VLAN, 60 NPC_LT_LB_FDSA, 61 NPC_LT_LB_VLAN_EXDSA, 62 NPC_LT_LB_CUSTOM0 = 0xE, 63 NPC_LT_LB_CUSTOM1 = 0xF, 64 }; 65 66 enum npc_kpu_lc_ltype { 67 NPC_LT_LC_IP = 1, 68 NPC_LT_LC_IP_OPT, 69 NPC_LT_LC_IP6, 70 NPC_LT_LC_IP6_EXT, 71 NPC_LT_LC_ARP, 72 NPC_LT_LC_RARP, 73 NPC_LT_LC_MPLS, 74 NPC_LT_LC_NSH, 75 NPC_LT_LC_PTP, 76 NPC_LT_LC_FCOE, 77 NPC_LT_LC_NGIO, 78 NPC_LT_LC_CUSTOM0 = 0xE, 79 NPC_LT_LC_CUSTOM1 = 0xF, 80 }; 81 82 /* Don't modify Ltypes upto SCTP, otherwise it will 83 * effect flow tag calculation and thus RSS. 84 */ 85 enum npc_kpu_ld_ltype { 86 NPC_LT_LD_TCP = 1, 87 NPC_LT_LD_UDP, 88 NPC_LT_LD_ICMP, 89 NPC_LT_LD_SCTP, 90 NPC_LT_LD_ICMP6, 91 NPC_LT_LD_CUSTOM0, 92 NPC_LT_LD_CUSTOM1, 93 NPC_LT_LD_IGMP = 8, 94 NPC_LT_LD_AH, 95 NPC_LT_LD_GRE, 96 NPC_LT_LD_NVGRE, 97 NPC_LT_LD_NSH, 98 NPC_LT_LD_TU_MPLS_IN_NSH, 99 NPC_LT_LD_TU_MPLS_IN_IP, 100 }; 101 102 enum npc_kpu_le_ltype { 103 NPC_LT_LE_VXLAN = 1, 104 NPC_LT_LE_GENEVE, 105 NPC_LT_LE_ESP, 106 NPC_LT_LE_GTPU = 4, 107 NPC_LT_LE_VXLANGPE, 108 NPC_LT_LE_GTPC, 109 NPC_LT_LE_NSH, 110 NPC_LT_LE_TU_MPLS_IN_GRE, 111 NPC_LT_LE_TU_NSH_IN_GRE, 112 NPC_LT_LE_TU_MPLS_IN_UDP, 113 NPC_LT_LE_CUSTOM0 = 0xE, 114 NPC_LT_LE_CUSTOM1 = 0xF, 115 }; 116 117 enum npc_kpu_lf_ltype { 118 NPC_LT_LF_TU_ETHER = 1, 119 NPC_LT_LF_TU_PPP, 120 NPC_LT_LF_TU_MPLS_IN_VXLANGPE, 121 NPC_LT_LF_TU_NSH_IN_VXLANGPE, 122 NPC_LT_LF_TU_MPLS_IN_NSH, 123 NPC_LT_LF_TU_3RD_NSH, 124 NPC_LT_LF_CUSTOM0 = 0xE, 125 NPC_LT_LF_CUSTOM1 = 0xF, 126 }; 127 128 enum npc_kpu_lg_ltype { 129 NPC_LT_LG_TU_IP = 1, 130 NPC_LT_LG_TU_IP6, 131 NPC_LT_LG_TU_ARP, 132 NPC_LT_LG_TU_ETHER_IN_NSH, 133 NPC_LT_LG_CUSTOM0 = 0xE, 134 NPC_LT_LG_CUSTOM1 = 0xF, 135 }; 136 137 /* Don't modify Ltypes upto SCTP, otherwise it will 138 * effect flow tag calculation and thus RSS. 139 */ 140 enum npc_kpu_lh_ltype { 141 NPC_LT_LH_TU_TCP = 1, 142 NPC_LT_LH_TU_UDP, 143 NPC_LT_LH_TU_ICMP, 144 NPC_LT_LH_TU_SCTP, 145 NPC_LT_LH_TU_ICMP6, 146 NPC_LT_LH_TU_IGMP = 8, 147 NPC_LT_LH_TU_ESP, 148 NPC_LT_LH_TU_AH, 149 NPC_LT_LH_CUSTOM0 = 0xE, 150 NPC_LT_LH_CUSTOM1 = 0xF, 151 }; 152 153 /* NPC port kind defines how the incoming or outgoing packets 154 * are processed. NPC accepts packets from up to 64 pkinds. 155 * Software assigns pkind for each incoming port such as CGX 156 * Ethernet interfaces, LBK interfaces, etc. 157 */ 158 #define NPC_UNRESERVED_PKIND_COUNT NPC_RX_CUSTOM_PRE_L2_PKIND 159 160 enum npc_pkind_type { 161 NPC_RX_LBK_PKIND = 0ULL, 162 NPC_RX_CUSTOM_PRE_L2_PKIND = 55ULL, 163 NPC_RX_VLAN_EXDSA_PKIND = 56ULL, 164 NPC_RX_CHLEN24B_PKIND = 57ULL, 165 NPC_RX_CPT_HDR_PKIND, 166 NPC_RX_CHLEN90B_PKIND, 167 NPC_TX_HIGIG_PKIND, 168 NPC_RX_HIGIG_PKIND, 169 NPC_RX_EDSA_PKIND, 170 NPC_TX_DEF_PKIND, /* NIX-TX PKIND */ 171 }; 172 173 enum npc_interface_type { 174 NPC_INTF_MODE_DEF, 175 }; 176 177 /* list of known and supported fields in packet header and 178 * fields present in key structure. 179 */ 180 enum key_fields { 181 NPC_DMAC, 182 NPC_SMAC, 183 NPC_ETYPE, 184 NPC_VLAN_ETYPE_CTAG, /* 0x8100 */ 185 NPC_VLAN_ETYPE_STAG, /* 0x88A8 */ 186 NPC_OUTER_VID, 187 NPC_TOS, 188 NPC_IPFRAG_IPV4, 189 NPC_SIP_IPV4, 190 NPC_DIP_IPV4, 191 NPC_IPFRAG_IPV6, 192 NPC_SIP_IPV6, 193 NPC_DIP_IPV6, 194 NPC_IPPROTO_TCP, 195 NPC_IPPROTO_UDP, 196 NPC_IPPROTO_SCTP, 197 NPC_IPPROTO_AH, 198 NPC_IPPROTO_ESP, 199 NPC_IPPROTO_ICMP, 200 NPC_IPPROTO_ICMP6, 201 NPC_SPORT_TCP, 202 NPC_DPORT_TCP, 203 NPC_SPORT_UDP, 204 NPC_DPORT_UDP, 205 NPC_SPORT_SCTP, 206 NPC_DPORT_SCTP, 207 NPC_IPSEC_SPI, 208 NPC_HEADER_FIELDS_MAX, 209 NPC_CHAN = NPC_HEADER_FIELDS_MAX, /* Valid when Rx */ 210 NPC_PF_FUNC, /* Valid when Tx */ 211 NPC_ERRLEV, 212 NPC_ERRCODE, 213 NPC_LXMB, 214 NPC_EXACT_RESULT, 215 NPC_LA, 216 NPC_LB, 217 NPC_LC, 218 NPC_LD, 219 NPC_LE, 220 NPC_LF, 221 NPC_LG, 222 NPC_LH, 223 /* Ethertype for untagged frame */ 224 NPC_ETYPE_ETHER, 225 /* Ethertype for single tagged frame */ 226 NPC_ETYPE_TAG1, 227 /* Ethertype for double tagged frame */ 228 NPC_ETYPE_TAG2, 229 /* outer vlan tci for single tagged frame */ 230 NPC_VLAN_TAG1, 231 /* outer vlan tci for double tagged frame */ 232 NPC_VLAN_TAG2, 233 /* other header fields programmed to extract but not of our interest */ 234 NPC_UNKNOWN, 235 NPC_KEY_FIELDS_MAX, 236 }; 237 238 struct npc_kpu_profile_cam { 239 u8 state; 240 u8 state_mask; 241 u16 dp0; 242 u16 dp0_mask; 243 u16 dp1; 244 u16 dp1_mask; 245 u16 dp2; 246 u16 dp2_mask; 247 } __packed; 248 249 struct npc_kpu_profile_action { 250 u8 errlev; 251 u8 errcode; 252 u8 dp0_offset; 253 u8 dp1_offset; 254 u8 dp2_offset; 255 u8 bypass_count; 256 u8 parse_done; 257 u8 next_state; 258 u8 ptr_advance; 259 u8 cap_ena; 260 u8 lid; 261 u8 ltype; 262 u8 flags; 263 u8 offset; 264 u8 mask; 265 u8 right; 266 u8 shift; 267 } __packed; 268 269 struct npc_kpu_profile { 270 int cam_entries; 271 int action_entries; 272 struct npc_kpu_profile_cam *cam; 273 struct npc_kpu_profile_action *action; 274 }; 275 276 /* NPC KPU register formats */ 277 struct npc_kpu_cam { 278 #if defined(__BIG_ENDIAN_BITFIELD) 279 u64 rsvd_63_56 : 8; 280 u64 state : 8; 281 u64 dp2_data : 16; 282 u64 dp1_data : 16; 283 u64 dp0_data : 16; 284 #else 285 u64 dp0_data : 16; 286 u64 dp1_data : 16; 287 u64 dp2_data : 16; 288 u64 state : 8; 289 u64 rsvd_63_56 : 8; 290 #endif 291 }; 292 293 struct npc_kpu_action0 { 294 #if defined(__BIG_ENDIAN_BITFIELD) 295 u64 rsvd_63_57 : 7; 296 u64 byp_count : 3; 297 u64 capture_ena : 1; 298 u64 parse_done : 1; 299 u64 next_state : 8; 300 u64 rsvd_43 : 1; 301 u64 capture_lid : 3; 302 u64 capture_ltype : 4; 303 u64 capture_flags : 8; 304 u64 ptr_advance : 8; 305 u64 var_len_offset : 8; 306 u64 var_len_mask : 8; 307 u64 var_len_right : 1; 308 u64 var_len_shift : 3; 309 #else 310 u64 var_len_shift : 3; 311 u64 var_len_right : 1; 312 u64 var_len_mask : 8; 313 u64 var_len_offset : 8; 314 u64 ptr_advance : 8; 315 u64 capture_flags : 8; 316 u64 capture_ltype : 4; 317 u64 capture_lid : 3; 318 u64 rsvd_43 : 1; 319 u64 next_state : 8; 320 u64 parse_done : 1; 321 u64 capture_ena : 1; 322 u64 byp_count : 3; 323 u64 rsvd_63_57 : 7; 324 #endif 325 }; 326 327 struct npc_kpu_action1 { 328 #if defined(__BIG_ENDIAN_BITFIELD) 329 u64 rsvd_63_36 : 28; 330 u64 errlev : 4; 331 u64 errcode : 8; 332 u64 dp2_offset : 8; 333 u64 dp1_offset : 8; 334 u64 dp0_offset : 8; 335 #else 336 u64 dp0_offset : 8; 337 u64 dp1_offset : 8; 338 u64 dp2_offset : 8; 339 u64 errcode : 8; 340 u64 errlev : 4; 341 u64 rsvd_63_36 : 28; 342 #endif 343 }; 344 345 struct npc_kpu_pkind_cpi_def { 346 #if defined(__BIG_ENDIAN_BITFIELD) 347 u64 ena : 1; 348 u64 rsvd_62_59 : 4; 349 u64 lid : 3; 350 u64 ltype_match : 4; 351 u64 ltype_mask : 4; 352 u64 flags_match : 8; 353 u64 flags_mask : 8; 354 u64 add_offset : 8; 355 u64 add_mask : 8; 356 u64 rsvd_15 : 1; 357 u64 add_shift : 3; 358 u64 rsvd_11_10 : 2; 359 u64 cpi_base : 10; 360 #else 361 u64 cpi_base : 10; 362 u64 rsvd_11_10 : 2; 363 u64 add_shift : 3; 364 u64 rsvd_15 : 1; 365 u64 add_mask : 8; 366 u64 add_offset : 8; 367 u64 flags_mask : 8; 368 u64 flags_match : 8; 369 u64 ltype_mask : 4; 370 u64 ltype_match : 4; 371 u64 lid : 3; 372 u64 rsvd_62_59 : 4; 373 u64 ena : 1; 374 #endif 375 }; 376 377 struct nix_rx_action { 378 #if defined(__BIG_ENDIAN_BITFIELD) 379 u64 rsvd_63_61 :3; 380 u64 flow_key_alg :5; 381 u64 match_id :16; 382 u64 index :20; 383 u64 pf_func :16; 384 u64 op :4; 385 #else 386 u64 op :4; 387 u64 pf_func :16; 388 u64 index :20; 389 u64 match_id :16; 390 u64 flow_key_alg :5; 391 u64 rsvd_63_61 :3; 392 #endif 393 }; 394 395 /* NPC_AF_INTFX_KEX_CFG field masks */ 396 #define NPC_EXACT_NIBBLE_START 40 397 #define NPC_EXACT_NIBBLE_END 43 398 #define NPC_EXACT_NIBBLE GENMASK_ULL(43, 40) 399 400 /* NPC_EXACT_KEX_S nibble definitions for each field */ 401 #define NPC_EXACT_NIBBLE_HIT BIT_ULL(40) 402 #define NPC_EXACT_NIBBLE_OPC BIT_ULL(40) 403 #define NPC_EXACT_NIBBLE_WAY BIT_ULL(40) 404 #define NPC_EXACT_NIBBLE_INDEX GENMASK_ULL(43, 41) 405 406 #define NPC_EXACT_RESULT_HIT BIT_ULL(0) 407 #define NPC_EXACT_RESULT_OPC GENMASK_ULL(2, 1) 408 #define NPC_EXACT_RESULT_WAY GENMASK_ULL(4, 3) 409 #define NPC_EXACT_RESULT_IDX GENMASK_ULL(15, 5) 410 411 /* NPC_AF_INTFX_KEX_CFG field masks */ 412 #define NPC_PARSE_NIBBLE GENMASK_ULL(30, 0) 413 414 /* NPC_PARSE_KEX_S nibble definitions for each field */ 415 #define NPC_PARSE_NIBBLE_CHAN GENMASK_ULL(2, 0) 416 #define NPC_PARSE_NIBBLE_ERRLEV BIT_ULL(3) 417 #define NPC_PARSE_NIBBLE_ERRCODE GENMASK_ULL(5, 4) 418 #define NPC_PARSE_NIBBLE_L2L3_BCAST BIT_ULL(6) 419 #define NPC_PARSE_NIBBLE_LA_FLAGS GENMASK_ULL(8, 7) 420 #define NPC_PARSE_NIBBLE_LA_LTYPE BIT_ULL(9) 421 #define NPC_PARSE_NIBBLE_LB_FLAGS GENMASK_ULL(11, 10) 422 #define NPC_PARSE_NIBBLE_LB_LTYPE BIT_ULL(12) 423 #define NPC_PARSE_NIBBLE_LC_FLAGS GENMASK_ULL(14, 13) 424 #define NPC_PARSE_NIBBLE_LC_LTYPE BIT_ULL(15) 425 #define NPC_PARSE_NIBBLE_LD_FLAGS GENMASK_ULL(17, 16) 426 #define NPC_PARSE_NIBBLE_LD_LTYPE BIT_ULL(18) 427 #define NPC_PARSE_NIBBLE_LE_FLAGS GENMASK_ULL(20, 19) 428 #define NPC_PARSE_NIBBLE_LE_LTYPE BIT_ULL(21) 429 #define NPC_PARSE_NIBBLE_LF_FLAGS GENMASK_ULL(23, 22) 430 #define NPC_PARSE_NIBBLE_LF_LTYPE BIT_ULL(24) 431 #define NPC_PARSE_NIBBLE_LG_FLAGS GENMASK_ULL(26, 25) 432 #define NPC_PARSE_NIBBLE_LG_LTYPE BIT_ULL(27) 433 #define NPC_PARSE_NIBBLE_LH_FLAGS GENMASK_ULL(29, 28) 434 #define NPC_PARSE_NIBBLE_LH_LTYPE BIT_ULL(30) 435 436 struct nix_tx_action { 437 #if defined(__BIG_ENDIAN_BITFIELD) 438 u64 rsvd_63_48 :16; 439 u64 match_id :16; 440 u64 index :20; 441 u64 rsvd_11_8 :8; 442 u64 op :4; 443 #else 444 u64 op :4; 445 u64 rsvd_11_8 :8; 446 u64 index :20; 447 u64 match_id :16; 448 u64 rsvd_63_48 :16; 449 #endif 450 }; 451 452 /* NIX Receive Vtag Action Structure */ 453 #define RX_VTAG0_VALID_BIT BIT_ULL(15) 454 #define RX_VTAG0_TYPE_MASK GENMASK_ULL(14, 12) 455 #define RX_VTAG0_LID_MASK GENMASK_ULL(10, 8) 456 #define RX_VTAG0_RELPTR_MASK GENMASK_ULL(7, 0) 457 #define RX_VTAG1_VALID_BIT BIT_ULL(47) 458 #define RX_VTAG1_TYPE_MASK GENMASK_ULL(46, 44) 459 #define RX_VTAG1_LID_MASK GENMASK_ULL(42, 40) 460 #define RX_VTAG1_RELPTR_MASK GENMASK_ULL(39, 32) 461 462 /* NIX Transmit Vtag Action Structure */ 463 #define TX_VTAG0_DEF_MASK GENMASK_ULL(25, 16) 464 #define TX_VTAG0_OP_MASK GENMASK_ULL(13, 12) 465 #define TX_VTAG0_LID_MASK GENMASK_ULL(10, 8) 466 #define TX_VTAG0_RELPTR_MASK GENMASK_ULL(7, 0) 467 #define TX_VTAG1_DEF_MASK GENMASK_ULL(57, 48) 468 #define TX_VTAG1_OP_MASK GENMASK_ULL(45, 44) 469 #define TX_VTAG1_LID_MASK GENMASK_ULL(42, 40) 470 #define TX_VTAG1_RELPTR_MASK GENMASK_ULL(39, 32) 471 472 /* NPC MCAM reserved entry index per nixlf */ 473 #define NIXLF_UCAST_ENTRY 0 474 #define NIXLF_BCAST_ENTRY 1 475 #define NIXLF_ALLMULTI_ENTRY 2 476 #define NIXLF_PROMISC_ENTRY 3 477 478 struct npc_coalesced_kpu_prfl { 479 #define NPC_SIGN 0x00666f727063706e 480 #define NPC_PRFL_NAME "npc_prfls_array" 481 #define NPC_NAME_LEN 32 482 __le64 signature; /* "npcprof\0" (8 bytes/ASCII characters) */ 483 u8 name[NPC_NAME_LEN]; /* KPU Profile name */ 484 u64 version; /* KPU firmware/profile version */ 485 u8 num_prfl; /* No of NPC profiles. */ 486 u16 prfl_sz[]; 487 }; 488 489 struct npc_mcam_kex { 490 /* MKEX Profle Header */ 491 u64 mkex_sign; /* "mcam-kex-profile" (8 bytes/ASCII characters) */ 492 u8 name[MKEX_NAME_LEN]; /* MKEX Profile name */ 493 u64 cpu_model; /* Format as profiled by CPU hardware */ 494 u64 kpu_version; /* KPU firmware/profile version */ 495 u64 reserved; /* Reserved for extension */ 496 497 /* MKEX Profle Data */ 498 u64 keyx_cfg[NPC_MAX_INTF]; /* NPC_AF_INTF(0..1)_KEX_CFG */ 499 /* NPC_AF_KEX_LDATA(0..1)_FLAGS_CFG */ 500 u64 kex_ld_flags[NPC_MAX_LD]; 501 /* NPC_AF_INTF(0..1)_LID(0..7)_LT(0..15)_LD(0..1)_CFG */ 502 u64 intf_lid_lt_ld[NPC_MAX_INTF][NPC_MAX_LID][NPC_MAX_LT][NPC_MAX_LD]; 503 /* NPC_AF_INTF(0..1)_LDATA(0..1)_FLAGS(0..15)_CFG */ 504 u64 intf_ld_flags[NPC_MAX_INTF][NPC_MAX_LD][NPC_MAX_LFL]; 505 } __packed; 506 507 struct npc_kpu_fwdata { 508 int entries; 509 /* What follows is: 510 * struct npc_kpu_profile_cam[entries]; 511 * struct npc_kpu_profile_action[entries]; 512 */ 513 u8 data[]; 514 } __packed; 515 516 struct npc_lt_def { 517 u8 ltype_mask; 518 u8 ltype_match; 519 u8 lid; 520 }; 521 522 struct npc_lt_def_ipsec { 523 u8 ltype_mask; 524 u8 ltype_match; 525 u8 lid; 526 u8 spi_offset; 527 u8 spi_nz; 528 }; 529 530 struct npc_lt_def_apad { 531 u8 ltype_mask; 532 u8 ltype_match; 533 u8 lid; 534 u8 valid; 535 } __packed; 536 537 struct npc_lt_def_color { 538 u8 ltype_mask; 539 u8 ltype_match; 540 u8 lid; 541 u8 noffset; 542 u8 offset; 543 } __packed; 544 545 struct npc_lt_def_et { 546 u8 ltype_mask; 547 u8 ltype_match; 548 u8 lid; 549 u8 valid; 550 u8 offset; 551 } __packed; 552 553 struct npc_lt_def_cfg { 554 struct npc_lt_def rx_ol2; 555 struct npc_lt_def rx_oip4; 556 struct npc_lt_def rx_iip4; 557 struct npc_lt_def rx_oip6; 558 struct npc_lt_def rx_iip6; 559 struct npc_lt_def rx_otcp; 560 struct npc_lt_def rx_itcp; 561 struct npc_lt_def rx_oudp; 562 struct npc_lt_def rx_iudp; 563 struct npc_lt_def rx_osctp; 564 struct npc_lt_def rx_isctp; 565 struct npc_lt_def_ipsec rx_ipsec[2]; 566 struct npc_lt_def pck_ol2; 567 struct npc_lt_def pck_oip4; 568 struct npc_lt_def pck_oip6; 569 struct npc_lt_def pck_iip4; 570 struct npc_lt_def_apad rx_apad0; 571 struct npc_lt_def_apad rx_apad1; 572 struct npc_lt_def_color ovlan; 573 struct npc_lt_def_color ivlan; 574 struct npc_lt_def_color rx_gen0_color; 575 struct npc_lt_def_color rx_gen1_color; 576 struct npc_lt_def_et rx_et[2]; 577 } __packed; 578 579 /* Loadable KPU profile firmware data */ 580 struct npc_kpu_profile_fwdata { 581 #define KPU_SIGN 0x00666f727075706b 582 #define KPU_NAME_LEN 32 583 /** Maximum number of custom KPU entries supported by the built-in profile. */ 584 #define KPU_MAX_CST_ENT 6 585 /* KPU Profle Header */ 586 __le64 signature; /* "kpuprof\0" (8 bytes/ASCII characters) */ 587 u8 name[KPU_NAME_LEN]; /* KPU Profile name */ 588 __le64 version; /* KPU profile version */ 589 u8 kpus; 590 u8 reserved[7]; 591 592 /* Default MKEX profile to be used with this KPU profile. May be 593 * overridden with mkex_profile module parameter. Format is same as for 594 * the MKEX profile to streamline processing. 595 */ 596 struct npc_mcam_kex mkex; 597 /* LTYPE values for specific HW offloaded protocols. */ 598 struct npc_lt_def_cfg lt_def; 599 /* Dynamically sized data: 600 * Custom KPU CAM and ACTION configuration entries. 601 * struct npc_kpu_fwdata kpu[kpus]; 602 */ 603 u8 data[]; 604 } __packed; 605 606 struct rvu_npc_mcam_rule { 607 struct flow_msg packet; 608 struct flow_msg mask; 609 u8 intf; 610 union { 611 struct nix_tx_action tx_action; 612 struct nix_rx_action rx_action; 613 }; 614 u64 vtag_action; 615 struct list_head list; 616 u64 features; 617 u16 owner; 618 u16 entry; 619 u16 cntr; 620 bool has_cntr; 621 u8 default_rule; 622 bool enable; 623 bool vfvlan_cfg; 624 u16 chan; 625 u16 chan_mask; 626 u8 lxmb; 627 }; 628 629 #endif /* NPC_H */ 630