1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*  Marvell OcteonTx2 RVU Admin Function driver
3  *
4  * Copyright (C) 2018 Marvell International Ltd.
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License version 2 as
8  * published by the Free Software Foundation.
9  */
10 
11 #ifndef NPC_H
12 #define NPC_H
13 
14 enum NPC_LID_E {
15 	NPC_LID_LA = 0,
16 	NPC_LID_LB,
17 	NPC_LID_LC,
18 	NPC_LID_LD,
19 	NPC_LID_LE,
20 	NPC_LID_LF,
21 	NPC_LID_LG,
22 	NPC_LID_LH,
23 };
24 
25 #define NPC_LT_NA 0
26 
27 enum npc_kpu_la_ltype {
28 	NPC_LT_LA_8023 = 1,
29 	NPC_LT_LA_ETHER,
30 	NPC_LT_LA_IH_NIX_ETHER,
31 	NPC_LT_LA_IH_8_ETHER,
32 	NPC_LT_LA_IH_4_ETHER,
33 	NPC_LT_LA_IH_2_ETHER,
34 	NPC_LT_LA_HIGIG2_ETHER,
35 	NPC_LT_LA_IH_NIX_HIGIG2_ETHER,
36 	NPC_LT_LA_CUSTOM0 = 0xE,
37 	NPC_LT_LA_CUSTOM1 = 0xF,
38 };
39 
40 enum npc_kpu_lb_ltype {
41 	NPC_LT_LB_ETAG = 1,
42 	NPC_LT_LB_CTAG,
43 	NPC_LT_LB_STAG_QINQ,
44 	NPC_LT_LB_BTAG,
45 	NPC_LT_LB_ITAG,
46 	NPC_LT_LB_DSA,
47 	NPC_LT_LB_DSA_VLAN,
48 	NPC_LT_LB_EDSA,
49 	NPC_LT_LB_EDSA_VLAN,
50 	NPC_LT_LB_EXDSA,
51 	NPC_LT_LB_EXDSA_VLAN,
52 	NPC_LT_LB_FDSA,
53 	NPC_LT_LB_CUSTOM0 = 0xE,
54 	NPC_LT_LB_CUSTOM1 = 0xF,
55 };
56 
57 enum npc_kpu_lc_ltype {
58 	NPC_LT_LC_IP = 1,
59 	NPC_LT_LC_IP_OPT,
60 	NPC_LT_LC_IP6,
61 	NPC_LT_LC_IP6_EXT,
62 	NPC_LT_LC_ARP,
63 	NPC_LT_LC_RARP,
64 	NPC_LT_LC_MPLS,
65 	NPC_LT_LC_NSH,
66 	NPC_LT_LC_PTP,
67 	NPC_LT_LC_FCOE,
68 	NPC_LT_LC_CUSTOM0 = 0xE,
69 	NPC_LT_LC_CUSTOM1 = 0xF,
70 };
71 
72 /* Don't modify Ltypes upto SCTP, otherwise it will
73  * effect flow tag calculation and thus RSS.
74  */
75 enum npc_kpu_ld_ltype {
76 	NPC_LT_LD_TCP = 1,
77 	NPC_LT_LD_UDP,
78 	NPC_LT_LD_ICMP,
79 	NPC_LT_LD_SCTP,
80 	NPC_LT_LD_ICMP6,
81 	NPC_LT_LD_CUSTOM0,
82 	NPC_LT_LD_CUSTOM1,
83 	NPC_LT_LD_IGMP = 8,
84 	NPC_LT_LD_AH,
85 	NPC_LT_LD_GRE,
86 	NPC_LT_LD_NVGRE,
87 	NPC_LT_LD_NSH,
88 	NPC_LT_LD_TU_MPLS_IN_NSH,
89 	NPC_LT_LD_TU_MPLS_IN_IP,
90 };
91 
92 enum npc_kpu_le_ltype {
93 	NPC_LT_LE_VXLAN = 1,
94 	NPC_LT_LE_GENEVE,
95 	NPC_LT_LE_ESP,
96 	NPC_LT_LE_GTPU = 4,
97 	NPC_LT_LE_VXLANGPE,
98 	NPC_LT_LE_GTPC,
99 	NPC_LT_LE_NSH,
100 	NPC_LT_LE_TU_MPLS_IN_GRE,
101 	NPC_LT_LE_TU_NSH_IN_GRE,
102 	NPC_LT_LE_TU_MPLS_IN_UDP,
103 	NPC_LT_LE_CUSTOM0 = 0xE,
104 	NPC_LT_LE_CUSTOM1 = 0xF,
105 };
106 
107 enum npc_kpu_lf_ltype {
108 	NPC_LT_LF_TU_ETHER = 1,
109 	NPC_LT_LF_TU_PPP,
110 	NPC_LT_LF_TU_MPLS_IN_VXLANGPE,
111 	NPC_LT_LF_TU_NSH_IN_VXLANGPE,
112 	NPC_LT_LF_TU_MPLS_IN_NSH,
113 	NPC_LT_LF_TU_3RD_NSH,
114 	NPC_LT_LF_CUSTOM0 = 0xE,
115 	NPC_LT_LF_CUSTOM1 = 0xF,
116 };
117 
118 enum npc_kpu_lg_ltype {
119 	NPC_LT_LG_TU_IP = 1,
120 	NPC_LT_LG_TU_IP6,
121 	NPC_LT_LG_TU_ARP,
122 	NPC_LT_LG_TU_ETHER_IN_NSH,
123 	NPC_LT_LG_CUSTOM0 = 0xE,
124 	NPC_LT_LG_CUSTOM1 = 0xF,
125 };
126 
127 /* Don't modify Ltypes upto SCTP, otherwise it will
128  * effect flow tag calculation and thus RSS.
129  */
130 enum npc_kpu_lh_ltype {
131 	NPC_LT_LH_TU_TCP = 1,
132 	NPC_LT_LH_TU_UDP,
133 	NPC_LT_LH_TU_ICMP,
134 	NPC_LT_LH_TU_SCTP,
135 	NPC_LT_LH_TU_ICMP6,
136 	NPC_LT_LH_TU_IGMP = 8,
137 	NPC_LT_LH_TU_ESP,
138 	NPC_LT_LH_TU_AH,
139 	NPC_LT_LH_CUSTOM0 = 0xE,
140 	NPC_LT_LH_CUSTOM1 = 0xF,
141 };
142 
143 /* NPC port kind defines how the incoming or outgoing packets
144  * are processed. NPC accepts packets from up to 64 pkinds.
145  * Software assigns pkind for each incoming port such as CGX
146  * Ethernet interfaces, LBK interfaces, etc.
147  */
148 enum npc_pkind_type {
149 	NPC_TX_DEF_PKIND = 63ULL,	/* NIX-TX PKIND */
150 };
151 
152 /* list of known and supported fields in packet header and
153  * fields present in key structure.
154  */
155 enum key_fields {
156 	NPC_DMAC,
157 	NPC_SMAC,
158 	NPC_ETYPE,
159 	NPC_OUTER_VID,
160 	NPC_TOS,
161 	NPC_SIP_IPV4,
162 	NPC_DIP_IPV4,
163 	NPC_SIP_IPV6,
164 	NPC_DIP_IPV6,
165 	NPC_IPPROTO_TCP,
166 	NPC_IPPROTO_UDP,
167 	NPC_IPPROTO_SCTP,
168 	NPC_IPPROTO_AH,
169 	NPC_IPPROTO_ESP,
170 	NPC_IPPROTO_ICMP,
171 	NPC_IPPROTO_ICMP6,
172 	NPC_SPORT_TCP,
173 	NPC_DPORT_TCP,
174 	NPC_SPORT_UDP,
175 	NPC_DPORT_UDP,
176 	NPC_SPORT_SCTP,
177 	NPC_DPORT_SCTP,
178 	NPC_HEADER_FIELDS_MAX,
179 	NPC_CHAN = NPC_HEADER_FIELDS_MAX, /* Valid when Rx */
180 	NPC_PF_FUNC, /* Valid when Tx */
181 	NPC_ERRLEV,
182 	NPC_ERRCODE,
183 	NPC_LXMB,
184 	NPC_LA,
185 	NPC_LB,
186 	NPC_LC,
187 	NPC_LD,
188 	NPC_LE,
189 	NPC_LF,
190 	NPC_LG,
191 	NPC_LH,
192 	/* Ethertype for untagged frame */
193 	NPC_ETYPE_ETHER,
194 	/* Ethertype for single tagged frame */
195 	NPC_ETYPE_TAG1,
196 	/* Ethertype for double tagged frame */
197 	NPC_ETYPE_TAG2,
198 	/* outer vlan tci for single tagged frame */
199 	NPC_VLAN_TAG1,
200 	/* outer vlan tci for double tagged frame */
201 	NPC_VLAN_TAG2,
202 	/* other header fields programmed to extract but not of our interest */
203 	NPC_UNKNOWN,
204 	NPC_KEY_FIELDS_MAX,
205 };
206 
207 struct npc_kpu_profile_cam {
208 	u8 state;
209 	u8 state_mask;
210 	u16 dp0;
211 	u16 dp0_mask;
212 	u16 dp1;
213 	u16 dp1_mask;
214 	u16 dp2;
215 	u16 dp2_mask;
216 };
217 
218 struct npc_kpu_profile_action {
219 	u8 errlev;
220 	u8 errcode;
221 	u8 dp0_offset;
222 	u8 dp1_offset;
223 	u8 dp2_offset;
224 	u8 bypass_count;
225 	u8 parse_done;
226 	u8 next_state;
227 	u8 ptr_advance;
228 	u8 cap_ena;
229 	u8 lid;
230 	u8 ltype;
231 	u8 flags;
232 	u8 offset;
233 	u8 mask;
234 	u8 right;
235 	u8 shift;
236 };
237 
238 struct npc_kpu_profile {
239 	int cam_entries;
240 	int action_entries;
241 	const struct npc_kpu_profile_cam *cam;
242 	const struct npc_kpu_profile_action *action;
243 };
244 
245 /* NPC KPU register formats */
246 struct npc_kpu_cam {
247 #if defined(__BIG_ENDIAN_BITFIELD)
248 	u64 rsvd_63_56     : 8;
249 	u64 state          : 8;
250 	u64 dp2_data       : 16;
251 	u64 dp1_data       : 16;
252 	u64 dp0_data       : 16;
253 #else
254 	u64 dp0_data       : 16;
255 	u64 dp1_data       : 16;
256 	u64 dp2_data       : 16;
257 	u64 state          : 8;
258 	u64 rsvd_63_56     : 8;
259 #endif
260 };
261 
262 struct npc_kpu_action0 {
263 #if defined(__BIG_ENDIAN_BITFIELD)
264 	u64 rsvd_63_57     : 7;
265 	u64 byp_count      : 3;
266 	u64 capture_ena    : 1;
267 	u64 parse_done     : 1;
268 	u64 next_state     : 8;
269 	u64 rsvd_43        : 1;
270 	u64 capture_lid    : 3;
271 	u64 capture_ltype  : 4;
272 	u64 capture_flags  : 8;
273 	u64 ptr_advance    : 8;
274 	u64 var_len_offset : 8;
275 	u64 var_len_mask   : 8;
276 	u64 var_len_right  : 1;
277 	u64 var_len_shift  : 3;
278 #else
279 	u64 var_len_shift  : 3;
280 	u64 var_len_right  : 1;
281 	u64 var_len_mask   : 8;
282 	u64 var_len_offset : 8;
283 	u64 ptr_advance    : 8;
284 	u64 capture_flags  : 8;
285 	u64 capture_ltype  : 4;
286 	u64 capture_lid    : 3;
287 	u64 rsvd_43        : 1;
288 	u64 next_state     : 8;
289 	u64 parse_done     : 1;
290 	u64 capture_ena    : 1;
291 	u64 byp_count      : 3;
292 	u64 rsvd_63_57     : 7;
293 #endif
294 };
295 
296 struct npc_kpu_action1 {
297 #if defined(__BIG_ENDIAN_BITFIELD)
298 	u64 rsvd_63_36     : 28;
299 	u64 errlev         : 4;
300 	u64 errcode        : 8;
301 	u64 dp2_offset     : 8;
302 	u64 dp1_offset     : 8;
303 	u64 dp0_offset     : 8;
304 #else
305 	u64 dp0_offset     : 8;
306 	u64 dp1_offset     : 8;
307 	u64 dp2_offset     : 8;
308 	u64 errcode        : 8;
309 	u64 errlev         : 4;
310 	u64 rsvd_63_36     : 28;
311 #endif
312 };
313 
314 struct npc_kpu_pkind_cpi_def {
315 #if defined(__BIG_ENDIAN_BITFIELD)
316 	u64 ena            : 1;
317 	u64 rsvd_62_59     : 4;
318 	u64 lid            : 3;
319 	u64 ltype_match    : 4;
320 	u64 ltype_mask     : 4;
321 	u64 flags_match    : 8;
322 	u64 flags_mask     : 8;
323 	u64 add_offset     : 8;
324 	u64 add_mask       : 8;
325 	u64 rsvd_15        : 1;
326 	u64 add_shift      : 3;
327 	u64 rsvd_11_10     : 2;
328 	u64 cpi_base       : 10;
329 #else
330 	u64 cpi_base       : 10;
331 	u64 rsvd_11_10     : 2;
332 	u64 add_shift      : 3;
333 	u64 rsvd_15        : 1;
334 	u64 add_mask       : 8;
335 	u64 add_offset     : 8;
336 	u64 flags_mask     : 8;
337 	u64 flags_match    : 8;
338 	u64 ltype_mask     : 4;
339 	u64 ltype_match    : 4;
340 	u64 lid            : 3;
341 	u64 rsvd_62_59     : 4;
342 	u64 ena            : 1;
343 #endif
344 };
345 
346 struct nix_rx_action {
347 #if defined(__BIG_ENDIAN_BITFIELD)
348 	u64	rsvd_63_61	:3;
349 	u64	flow_key_alg	:5;
350 	u64	match_id	:16;
351 	u64	index		:20;
352 	u64	pf_func		:16;
353 	u64	op		:4;
354 #else
355 	u64	op		:4;
356 	u64	pf_func		:16;
357 	u64	index		:20;
358 	u64	match_id	:16;
359 	u64	flow_key_alg	:5;
360 	u64	rsvd_63_61	:3;
361 #endif
362 };
363 
364 /* NPC_AF_INTFX_KEX_CFG field masks */
365 #define NPC_PARSE_NIBBLE		GENMASK_ULL(30, 0)
366 
367 /* NPC_PARSE_KEX_S nibble definitions for each field */
368 #define NPC_PARSE_NIBBLE_CHAN		GENMASK_ULL(2, 0)
369 #define NPC_PARSE_NIBBLE_ERRLEV		BIT_ULL(3)
370 #define NPC_PARSE_NIBBLE_ERRCODE	GENMASK_ULL(5, 4)
371 #define NPC_PARSE_NIBBLE_L2L3_BCAST	BIT_ULL(6)
372 #define NPC_PARSE_NIBBLE_LA_FLAGS	GENMASK_ULL(8, 7)
373 #define NPC_PARSE_NIBBLE_LA_LTYPE	BIT_ULL(9)
374 #define NPC_PARSE_NIBBLE_LB_FLAGS	GENMASK_ULL(11, 10)
375 #define NPC_PARSE_NIBBLE_LB_LTYPE	BIT_ULL(12)
376 #define NPC_PARSE_NIBBLE_LC_FLAGS	GENMASK_ULL(14, 13)
377 #define NPC_PARSE_NIBBLE_LC_LTYPE	BIT_ULL(15)
378 #define NPC_PARSE_NIBBLE_LD_FLAGS	GENMASK_ULL(17, 16)
379 #define NPC_PARSE_NIBBLE_LD_LTYPE	BIT_ULL(18)
380 #define NPC_PARSE_NIBBLE_LE_FLAGS	GENMASK_ULL(20, 19)
381 #define NPC_PARSE_NIBBLE_LE_LTYPE	BIT_ULL(21)
382 #define NPC_PARSE_NIBBLE_LF_FLAGS	GENMASK_ULL(23, 22)
383 #define NPC_PARSE_NIBBLE_LF_LTYPE	BIT_ULL(24)
384 #define NPC_PARSE_NIBBLE_LG_FLAGS	GENMASK_ULL(26, 25)
385 #define NPC_PARSE_NIBBLE_LG_LTYPE	BIT_ULL(27)
386 #define NPC_PARSE_NIBBLE_LH_FLAGS	GENMASK_ULL(29, 28)
387 #define NPC_PARSE_NIBBLE_LH_LTYPE	BIT_ULL(30)
388 
389 struct nix_tx_action {
390 #if defined(__BIG_ENDIAN_BITFIELD)
391 	u64	rsvd_63_48	:16;
392 	u64	match_id	:16;
393 	u64	index		:20;
394 	u64	rsvd_11_8	:8;
395 	u64	op		:4;
396 #else
397 	u64	op		:4;
398 	u64	rsvd_11_8	:8;
399 	u64	index		:20;
400 	u64	match_id	:16;
401 	u64	rsvd_63_48	:16;
402 #endif
403 };
404 
405 /* NIX Receive Vtag Action Structure */
406 #define RX_VTAG0_VALID_BIT		BIT_ULL(15)
407 #define RX_VTAG0_TYPE_MASK		GENMASK_ULL(14, 12)
408 #define RX_VTAG0_LID_MASK		GENMASK_ULL(10, 8)
409 #define RX_VTAG0_RELPTR_MASK		GENMASK_ULL(7, 0)
410 #define RX_VTAG1_VALID_BIT		BIT_ULL(47)
411 #define RX_VTAG1_TYPE_MASK		GENMASK_ULL(46, 44)
412 #define RX_VTAG1_LID_MASK		GENMASK_ULL(42, 40)
413 #define RX_VTAG1_RELPTR_MASK		GENMASK_ULL(39, 32)
414 
415 /* NIX Transmit Vtag Action Structure */
416 #define TX_VTAG0_DEF_MASK		GENMASK_ULL(25, 16)
417 #define TX_VTAG0_OP_MASK		GENMASK_ULL(13, 12)
418 #define TX_VTAG0_LID_MASK		GENMASK_ULL(10, 8)
419 #define TX_VTAG0_RELPTR_MASK		GENMASK_ULL(7, 0)
420 #define TX_VTAG1_DEF_MASK		GENMASK_ULL(57, 48)
421 #define TX_VTAG1_OP_MASK		GENMASK_ULL(45, 44)
422 #define TX_VTAG1_LID_MASK		GENMASK_ULL(42, 40)
423 #define TX_VTAG1_RELPTR_MASK		GENMASK_ULL(39, 32)
424 
425 /* NPC MCAM reserved entry index per nixlf */
426 #define NIXLF_UCAST_ENTRY	0
427 #define NIXLF_BCAST_ENTRY	1
428 #define NIXLF_PROMISC_ENTRY	2
429 
430 struct npc_mcam_kex {
431 	/* MKEX Profle Header */
432 	u64 mkex_sign; /* "mcam-kex-profile" (8 bytes/ASCII characters) */
433 	u8 name[MKEX_NAME_LEN];   /* MKEX Profile name */
434 	u64 cpu_model;   /* Format as profiled by CPU hardware */
435 	u64 kpu_version; /* KPU firmware/profile version */
436 	u64 reserved; /* Reserved for extension */
437 
438 	/* MKEX Profle Data */
439 	u64 keyx_cfg[NPC_MAX_INTF]; /* NPC_AF_INTF(0..1)_KEX_CFG */
440 	/* NPC_AF_KEX_LDATA(0..1)_FLAGS_CFG */
441 	u64 kex_ld_flags[NPC_MAX_LD];
442 	/* NPC_AF_INTF(0..1)_LID(0..7)_LT(0..15)_LD(0..1)_CFG */
443 	u64 intf_lid_lt_ld[NPC_MAX_INTF][NPC_MAX_LID][NPC_MAX_LT][NPC_MAX_LD];
444 	/* NPC_AF_INTF(0..1)_LDATA(0..1)_FLAGS(0..15)_CFG */
445 	u64 intf_ld_flags[NPC_MAX_INTF][NPC_MAX_LD][NPC_MAX_LFL];
446 } __packed;
447 
448 struct npc_lt_def {
449 	u8	ltype_mask;
450 	u8	ltype_match;
451 	u8	lid;
452 };
453 
454 struct npc_lt_def_ipsec {
455 	u8	ltype_mask;
456 	u8	ltype_match;
457 	u8	lid;
458 	u8	spi_offset;
459 	u8	spi_nz;
460 };
461 
462 struct npc_lt_def_cfg {
463 	struct npc_lt_def	rx_ol2;
464 	struct npc_lt_def	rx_oip4;
465 	struct npc_lt_def	rx_iip4;
466 	struct npc_lt_def	rx_oip6;
467 	struct npc_lt_def	rx_iip6;
468 	struct npc_lt_def	rx_otcp;
469 	struct npc_lt_def	rx_itcp;
470 	struct npc_lt_def	rx_oudp;
471 	struct npc_lt_def	rx_iudp;
472 	struct npc_lt_def	rx_osctp;
473 	struct npc_lt_def	rx_isctp;
474 	struct npc_lt_def_ipsec	rx_ipsec[2];
475 	struct npc_lt_def	pck_ol2;
476 	struct npc_lt_def	pck_oip4;
477 	struct npc_lt_def	pck_oip6;
478 	struct npc_lt_def	pck_iip4;
479 };
480 
481 struct rvu_npc_mcam_rule {
482 	struct flow_msg packet;
483 	struct flow_msg mask;
484 	u8 intf;
485 	union {
486 		struct nix_tx_action tx_action;
487 		struct nix_rx_action rx_action;
488 	};
489 	u64 vtag_action;
490 	struct list_head list;
491 	u64 features;
492 	u16 owner;
493 	u16 entry;
494 	u16 cntr;
495 	bool has_cntr;
496 	u8 default_rule;
497 	bool enable;
498 	bool vfvlan_cfg;
499 };
500 
501 #endif /* NPC_H */
502