1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*  Marvell OcteonTx2 RVU Admin Function driver
3  *
4  * Copyright (C) 2018 Marvell International Ltd.
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License version 2 as
8  * published by the Free Software Foundation.
9  */
10 
11 #ifndef NPC_H
12 #define NPC_H
13 
14 enum NPC_LID_E {
15 	NPC_LID_LA = 0,
16 	NPC_LID_LB,
17 	NPC_LID_LC,
18 	NPC_LID_LD,
19 	NPC_LID_LE,
20 	NPC_LID_LF,
21 	NPC_LID_LG,
22 	NPC_LID_LH,
23 };
24 
25 #define NPC_LT_NA 0
26 
27 enum npc_kpu_la_ltype {
28 	NPC_LT_LA_8023 = 1,
29 	NPC_LT_LA_ETHER,
30 	NPC_LT_LA_IH_NIX_ETHER,
31 	NPC_LT_LA_IH_8_ETHER,
32 	NPC_LT_LA_IH_4_ETHER,
33 	NPC_LT_LA_IH_2_ETHER,
34 	NPC_LT_LA_HIGIG2_ETHER,
35 	NPC_LT_LA_IH_NIX_HIGIG2_ETHER,
36 	NPC_LT_LA_CUSTOM0 = 0xE,
37 	NPC_LT_LA_CUSTOM1 = 0xF,
38 };
39 
40 enum npc_kpu_lb_ltype {
41 	NPC_LT_LB_ETAG = 1,
42 	NPC_LT_LB_CTAG,
43 	NPC_LT_LB_STAG_QINQ,
44 	NPC_LT_LB_BTAG,
45 	NPC_LT_LB_ITAG,
46 	NPC_LT_LB_DSA,
47 	NPC_LT_LB_DSA_VLAN,
48 	NPC_LT_LB_EDSA,
49 	NPC_LT_LB_EDSA_VLAN,
50 	NPC_LT_LB_EXDSA,
51 	NPC_LT_LB_EXDSA_VLAN,
52 	NPC_LT_LB_FDSA,
53 	NPC_LT_LB_CUSTOM0 = 0xE,
54 	NPC_LT_LB_CUSTOM1 = 0xF,
55 };
56 
57 enum npc_kpu_lc_ltype {
58 	NPC_LT_LC_IP = 1,
59 	NPC_LT_LC_IP_OPT,
60 	NPC_LT_LC_IP6,
61 	NPC_LT_LC_IP6_EXT,
62 	NPC_LT_LC_ARP,
63 	NPC_LT_LC_RARP,
64 	NPC_LT_LC_MPLS,
65 	NPC_LT_LC_NSH,
66 	NPC_LT_LC_PTP,
67 	NPC_LT_LC_FCOE,
68 	NPC_LT_LC_CUSTOM0 = 0xE,
69 	NPC_LT_LC_CUSTOM1 = 0xF,
70 };
71 
72 /* Don't modify Ltypes upto SCTP, otherwise it will
73  * effect flow tag calculation and thus RSS.
74  */
75 enum npc_kpu_ld_ltype {
76 	NPC_LT_LD_TCP = 1,
77 	NPC_LT_LD_UDP,
78 	NPC_LT_LD_ICMP,
79 	NPC_LT_LD_SCTP,
80 	NPC_LT_LD_ICMP6,
81 	NPC_LT_LD_CUSTOM0,
82 	NPC_LT_LD_CUSTOM1,
83 	NPC_LT_LD_IGMP = 8,
84 	NPC_LT_LD_AH,
85 	NPC_LT_LD_GRE,
86 	NPC_LT_LD_NVGRE,
87 	NPC_LT_LD_NSH,
88 	NPC_LT_LD_TU_MPLS_IN_NSH,
89 	NPC_LT_LD_TU_MPLS_IN_IP,
90 };
91 
92 enum npc_kpu_le_ltype {
93 	NPC_LT_LE_VXLAN = 1,
94 	NPC_LT_LE_GENEVE,
95 	NPC_LT_LE_ESP,
96 	NPC_LT_LE_GTPU = 4,
97 	NPC_LT_LE_VXLANGPE,
98 	NPC_LT_LE_GTPC,
99 	NPC_LT_LE_NSH,
100 	NPC_LT_LE_TU_MPLS_IN_GRE,
101 	NPC_LT_LE_TU_NSH_IN_GRE,
102 	NPC_LT_LE_TU_MPLS_IN_UDP,
103 	NPC_LT_LE_CUSTOM0 = 0xE,
104 	NPC_LT_LE_CUSTOM1 = 0xF,
105 };
106 
107 enum npc_kpu_lf_ltype {
108 	NPC_LT_LF_TU_ETHER = 1,
109 	NPC_LT_LF_TU_PPP,
110 	NPC_LT_LF_TU_MPLS_IN_VXLANGPE,
111 	NPC_LT_LF_TU_NSH_IN_VXLANGPE,
112 	NPC_LT_LF_TU_MPLS_IN_NSH,
113 	NPC_LT_LF_TU_3RD_NSH,
114 	NPC_LT_LF_CUSTOM0 = 0xE,
115 	NPC_LT_LF_CUSTOM1 = 0xF,
116 };
117 
118 enum npc_kpu_lg_ltype {
119 	NPC_LT_LG_TU_IP = 1,
120 	NPC_LT_LG_TU_IP6,
121 	NPC_LT_LG_TU_ARP,
122 	NPC_LT_LG_TU_ETHER_IN_NSH,
123 	NPC_LT_LG_CUSTOM0 = 0xE,
124 	NPC_LT_LG_CUSTOM1 = 0xF,
125 };
126 
127 /* Don't modify Ltypes upto SCTP, otherwise it will
128  * effect flow tag calculation and thus RSS.
129  */
130 enum npc_kpu_lh_ltype {
131 	NPC_LT_LH_TU_TCP = 1,
132 	NPC_LT_LH_TU_UDP,
133 	NPC_LT_LH_TU_ICMP,
134 	NPC_LT_LH_TU_SCTP,
135 	NPC_LT_LH_TU_ICMP6,
136 	NPC_LT_LH_TU_IGMP = 8,
137 	NPC_LT_LH_TU_ESP,
138 	NPC_LT_LH_TU_AH,
139 	NPC_LT_LH_CUSTOM0 = 0xE,
140 	NPC_LT_LH_CUSTOM1 = 0xF,
141 };
142 
143 struct npc_kpu_profile_cam {
144 	u8 state;
145 	u8 state_mask;
146 	u16 dp0;
147 	u16 dp0_mask;
148 	u16 dp1;
149 	u16 dp1_mask;
150 	u16 dp2;
151 	u16 dp2_mask;
152 };
153 
154 struct npc_kpu_profile_action {
155 	u8 errlev;
156 	u8 errcode;
157 	u8 dp0_offset;
158 	u8 dp1_offset;
159 	u8 dp2_offset;
160 	u8 bypass_count;
161 	u8 parse_done;
162 	u8 next_state;
163 	u8 ptr_advance;
164 	u8 cap_ena;
165 	u8 lid;
166 	u8 ltype;
167 	u8 flags;
168 	u8 offset;
169 	u8 mask;
170 	u8 right;
171 	u8 shift;
172 };
173 
174 struct npc_kpu_profile {
175 	int cam_entries;
176 	int action_entries;
177 	const struct npc_kpu_profile_cam *cam;
178 	const struct npc_kpu_profile_action *action;
179 };
180 
181 /* NPC KPU register formats */
182 struct npc_kpu_cam {
183 #if defined(__BIG_ENDIAN_BITFIELD)
184 	u64 rsvd_63_56     : 8;
185 	u64 state          : 8;
186 	u64 dp2_data       : 16;
187 	u64 dp1_data       : 16;
188 	u64 dp0_data       : 16;
189 #else
190 	u64 dp0_data       : 16;
191 	u64 dp1_data       : 16;
192 	u64 dp2_data       : 16;
193 	u64 state          : 8;
194 	u64 rsvd_63_56     : 8;
195 #endif
196 };
197 
198 struct npc_kpu_action0 {
199 #if defined(__BIG_ENDIAN_BITFIELD)
200 	u64 rsvd_63_57     : 7;
201 	u64 byp_count      : 3;
202 	u64 capture_ena    : 1;
203 	u64 parse_done     : 1;
204 	u64 next_state     : 8;
205 	u64 rsvd_43        : 1;
206 	u64 capture_lid    : 3;
207 	u64 capture_ltype  : 4;
208 	u64 capture_flags  : 8;
209 	u64 ptr_advance    : 8;
210 	u64 var_len_offset : 8;
211 	u64 var_len_mask   : 8;
212 	u64 var_len_right  : 1;
213 	u64 var_len_shift  : 3;
214 #else
215 	u64 var_len_shift  : 3;
216 	u64 var_len_right  : 1;
217 	u64 var_len_mask   : 8;
218 	u64 var_len_offset : 8;
219 	u64 ptr_advance    : 8;
220 	u64 capture_flags  : 8;
221 	u64 capture_ltype  : 4;
222 	u64 capture_lid    : 3;
223 	u64 rsvd_43        : 1;
224 	u64 next_state     : 8;
225 	u64 parse_done     : 1;
226 	u64 capture_ena    : 1;
227 	u64 byp_count      : 3;
228 	u64 rsvd_63_57     : 7;
229 #endif
230 };
231 
232 struct npc_kpu_action1 {
233 #if defined(__BIG_ENDIAN_BITFIELD)
234 	u64 rsvd_63_36     : 28;
235 	u64 errlev         : 4;
236 	u64 errcode        : 8;
237 	u64 dp2_offset     : 8;
238 	u64 dp1_offset     : 8;
239 	u64 dp0_offset     : 8;
240 #else
241 	u64 dp0_offset     : 8;
242 	u64 dp1_offset     : 8;
243 	u64 dp2_offset     : 8;
244 	u64 errcode        : 8;
245 	u64 errlev         : 4;
246 	u64 rsvd_63_36     : 28;
247 #endif
248 };
249 
250 struct npc_kpu_pkind_cpi_def {
251 #if defined(__BIG_ENDIAN_BITFIELD)
252 	u64 ena            : 1;
253 	u64 rsvd_62_59     : 4;
254 	u64 lid            : 3;
255 	u64 ltype_match    : 4;
256 	u64 ltype_mask     : 4;
257 	u64 flags_match    : 8;
258 	u64 flags_mask     : 8;
259 	u64 add_offset     : 8;
260 	u64 add_mask       : 8;
261 	u64 rsvd_15        : 1;
262 	u64 add_shift      : 3;
263 	u64 rsvd_11_10     : 2;
264 	u64 cpi_base       : 10;
265 #else
266 	u64 cpi_base       : 10;
267 	u64 rsvd_11_10     : 2;
268 	u64 add_shift      : 3;
269 	u64 rsvd_15        : 1;
270 	u64 add_mask       : 8;
271 	u64 add_offset     : 8;
272 	u64 flags_mask     : 8;
273 	u64 flags_match    : 8;
274 	u64 ltype_mask     : 4;
275 	u64 ltype_match    : 4;
276 	u64 lid            : 3;
277 	u64 rsvd_62_59     : 4;
278 	u64 ena            : 1;
279 #endif
280 };
281 
282 struct nix_rx_action {
283 #if defined(__BIG_ENDIAN_BITFIELD)
284 	u64	rsvd_63_61	:3;
285 	u64	flow_key_alg	:5;
286 	u64	match_id	:16;
287 	u64	index		:20;
288 	u64	pf_func		:16;
289 	u64	op		:4;
290 #else
291 	u64	op		:4;
292 	u64	pf_func		:16;
293 	u64	index		:20;
294 	u64	match_id	:16;
295 	u64	flow_key_alg	:5;
296 	u64	rsvd_63_61	:3;
297 #endif
298 };
299 
300 /* NPC_AF_INTFX_KEX_CFG field masks */
301 #define NPC_PARSE_NIBBLE		GENMASK_ULL(30, 0)
302 
303 /* NIX Receive Vtag Action Structure */
304 #define VTAG0_VALID_BIT		BIT_ULL(15)
305 #define VTAG0_TYPE_MASK		GENMASK_ULL(14, 12)
306 #define VTAG0_LID_MASK		GENMASK_ULL(10, 8)
307 #define VTAG0_RELPTR_MASK	GENMASK_ULL(7, 0)
308 
309 struct npc_mcam_kex {
310 	/* MKEX Profle Header */
311 	u64 mkex_sign; /* "mcam-kex-profile" (8 bytes/ASCII characters) */
312 	u8 name[MKEX_NAME_LEN];   /* MKEX Profile name */
313 	u64 cpu_model;   /* Format as profiled by CPU hardware */
314 	u64 kpu_version; /* KPU firmware/profile version */
315 	u64 reserved; /* Reserved for extension */
316 
317 	/* MKEX Profle Data */
318 	u64 keyx_cfg[NPC_MAX_INTF]; /* NPC_AF_INTF(0..1)_KEX_CFG */
319 	/* NPC_AF_KEX_LDATA(0..1)_FLAGS_CFG */
320 	u64 kex_ld_flags[NPC_MAX_LD];
321 	/* NPC_AF_INTF(0..1)_LID(0..7)_LT(0..15)_LD(0..1)_CFG */
322 	u64 intf_lid_lt_ld[NPC_MAX_INTF][NPC_MAX_LID][NPC_MAX_LT][NPC_MAX_LD];
323 	/* NPC_AF_INTF(0..1)_LDATA(0..1)_FLAGS(0..15)_CFG */
324 	u64 intf_ld_flags[NPC_MAX_INTF][NPC_MAX_LD][NPC_MAX_LFL];
325 } __packed;
326 
327 struct npc_lt_def {
328 	u8	ltype_mask;
329 	u8	ltype_match;
330 	u8	lid;
331 };
332 
333 struct npc_lt_def_ipsec {
334 	u8	ltype_mask;
335 	u8	ltype_match;
336 	u8	lid;
337 	u8	spi_offset;
338 	u8	spi_nz;
339 };
340 
341 struct npc_lt_def_cfg {
342 	struct npc_lt_def	rx_ol2;
343 	struct npc_lt_def	rx_oip4;
344 	struct npc_lt_def	rx_iip4;
345 	struct npc_lt_def	rx_oip6;
346 	struct npc_lt_def	rx_iip6;
347 	struct npc_lt_def	rx_otcp;
348 	struct npc_lt_def	rx_itcp;
349 	struct npc_lt_def	rx_oudp;
350 	struct npc_lt_def	rx_iudp;
351 	struct npc_lt_def	rx_osctp;
352 	struct npc_lt_def	rx_isctp;
353 	struct npc_lt_def_ipsec	rx_ipsec[2];
354 	struct npc_lt_def	pck_ol2;
355 	struct npc_lt_def	pck_oip4;
356 	struct npc_lt_def	pck_oip6;
357 	struct npc_lt_def	pck_iip4;
358 };
359 
360 #endif /* NPC_H */
361