1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Marvell OcteonTx2 RVU Admin Function driver 3 * 4 * Copyright (C) 2018 Marvell International Ltd. 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 */ 10 11 #ifndef NPC_H 12 #define NPC_H 13 14 enum NPC_LID_E { 15 NPC_LID_LA = 0, 16 NPC_LID_LB, 17 NPC_LID_LC, 18 NPC_LID_LD, 19 NPC_LID_LE, 20 NPC_LID_LF, 21 NPC_LID_LG, 22 NPC_LID_LH, 23 }; 24 25 #define NPC_LT_NA 0 26 27 enum npc_kpu_la_ltype { 28 NPC_LT_LA_8023 = 1, 29 NPC_LT_LA_ETHER, 30 NPC_LT_LA_IH_NIX_ETHER, 31 NPC_LT_LA_IH_8_ETHER, 32 NPC_LT_LA_IH_4_ETHER, 33 NPC_LT_LA_IH_2_ETHER, 34 NPC_LT_LA_HIGIG2_ETHER, 35 NPC_LT_LA_IH_NIX_HIGIG2_ETHER, 36 NPC_LT_LA_CUSTOM0 = 0xE, 37 NPC_LT_LA_CUSTOM1 = 0xF, 38 }; 39 40 enum npc_kpu_lb_ltype { 41 NPC_LT_LB_ETAG = 1, 42 NPC_LT_LB_CTAG, 43 NPC_LT_LB_STAG_QINQ, 44 NPC_LT_LB_BTAG, 45 NPC_LT_LB_ITAG, 46 NPC_LT_LB_DSA, 47 NPC_LT_LB_DSA_VLAN, 48 NPC_LT_LB_EDSA, 49 NPC_LT_LB_EDSA_VLAN, 50 NPC_LT_LB_EXDSA, 51 NPC_LT_LB_EXDSA_VLAN, 52 NPC_LT_LB_FDSA, 53 NPC_LT_LB_CUSTOM0 = 0xE, 54 NPC_LT_LB_CUSTOM1 = 0xF, 55 }; 56 57 enum npc_kpu_lc_ltype { 58 NPC_LT_LC_IP = 1, 59 NPC_LT_LC_IP_OPT, 60 NPC_LT_LC_IP6, 61 NPC_LT_LC_IP6_EXT, 62 NPC_LT_LC_ARP, 63 NPC_LT_LC_RARP, 64 NPC_LT_LC_MPLS, 65 NPC_LT_LC_NSH, 66 NPC_LT_LC_PTP, 67 NPC_LT_LC_FCOE, 68 NPC_LT_LC_CUSTOM0 = 0xE, 69 NPC_LT_LC_CUSTOM1 = 0xF, 70 }; 71 72 /* Don't modify Ltypes upto SCTP, otherwise it will 73 * effect flow tag calculation and thus RSS. 74 */ 75 enum npc_kpu_ld_ltype { 76 NPC_LT_LD_TCP = 1, 77 NPC_LT_LD_UDP, 78 NPC_LT_LD_ICMP, 79 NPC_LT_LD_SCTP, 80 NPC_LT_LD_ICMP6, 81 NPC_LT_LD_CUSTOM0, 82 NPC_LT_LD_CUSTOM1, 83 NPC_LT_LD_IGMP = 8, 84 NPC_LT_LD_AH, 85 NPC_LT_LD_GRE, 86 NPC_LT_LD_NVGRE, 87 NPC_LT_LD_NSH, 88 NPC_LT_LD_TU_MPLS_IN_NSH, 89 NPC_LT_LD_TU_MPLS_IN_IP, 90 }; 91 92 enum npc_kpu_le_ltype { 93 NPC_LT_LE_VXLAN = 1, 94 NPC_LT_LE_GENEVE, 95 NPC_LT_LE_ESP, 96 NPC_LT_LE_GTPU = 4, 97 NPC_LT_LE_VXLANGPE, 98 NPC_LT_LE_GTPC, 99 NPC_LT_LE_NSH, 100 NPC_LT_LE_TU_MPLS_IN_GRE, 101 NPC_LT_LE_TU_NSH_IN_GRE, 102 NPC_LT_LE_TU_MPLS_IN_UDP, 103 NPC_LT_LE_CUSTOM0 = 0xE, 104 NPC_LT_LE_CUSTOM1 = 0xF, 105 }; 106 107 enum npc_kpu_lf_ltype { 108 NPC_LT_LF_TU_ETHER = 1, 109 NPC_LT_LF_TU_PPP, 110 NPC_LT_LF_TU_MPLS_IN_VXLANGPE, 111 NPC_LT_LF_TU_NSH_IN_VXLANGPE, 112 NPC_LT_LF_TU_MPLS_IN_NSH, 113 NPC_LT_LF_TU_3RD_NSH, 114 NPC_LT_LF_CUSTOM0 = 0xE, 115 NPC_LT_LF_CUSTOM1 = 0xF, 116 }; 117 118 enum npc_kpu_lg_ltype { 119 NPC_LT_LG_TU_IP = 1, 120 NPC_LT_LG_TU_IP6, 121 NPC_LT_LG_TU_ARP, 122 NPC_LT_LG_TU_ETHER_IN_NSH, 123 NPC_LT_LG_CUSTOM0 = 0xE, 124 NPC_LT_LG_CUSTOM1 = 0xF, 125 }; 126 127 /* Don't modify Ltypes upto SCTP, otherwise it will 128 * effect flow tag calculation and thus RSS. 129 */ 130 enum npc_kpu_lh_ltype { 131 NPC_LT_LH_TU_TCP = 1, 132 NPC_LT_LH_TU_UDP, 133 NPC_LT_LH_TU_ICMP, 134 NPC_LT_LH_TU_SCTP, 135 NPC_LT_LH_TU_ICMP6, 136 NPC_LT_LH_TU_IGMP = 8, 137 NPC_LT_LH_TU_ESP, 138 NPC_LT_LH_TU_AH, 139 NPC_LT_LH_CUSTOM0 = 0xE, 140 NPC_LT_LH_CUSTOM1 = 0xF, 141 }; 142 143 /* NPC port kind defines how the incoming or outgoing packets 144 * are processed. NPC accepts packets from up to 64 pkinds. 145 * Software assigns pkind for each incoming port such as CGX 146 * Ethernet interfaces, LBK interfaces, etc. 147 */ 148 enum npc_pkind_type { 149 NPC_TX_DEF_PKIND = 63ULL, /* NIX-TX PKIND */ 150 }; 151 152 /* list of known and supported fields in packet header and 153 * fields present in key structure. 154 */ 155 enum key_fields { 156 NPC_DMAC, 157 NPC_SMAC, 158 NPC_ETYPE, 159 NPC_OUTER_VID, 160 NPC_TOS, 161 NPC_SIP_IPV4, 162 NPC_DIP_IPV4, 163 NPC_SIP_IPV6, 164 NPC_DIP_IPV6, 165 NPC_SPORT_TCP, 166 NPC_DPORT_TCP, 167 NPC_SPORT_UDP, 168 NPC_DPORT_UDP, 169 NPC_SPORT_SCTP, 170 NPC_DPORT_SCTP, 171 NPC_HEADER_FIELDS_MAX, 172 NPC_CHAN = NPC_HEADER_FIELDS_MAX, /* Valid when Rx */ 173 NPC_PF_FUNC, /* Valid when Tx */ 174 NPC_ERRLEV, 175 NPC_ERRCODE, 176 NPC_LXMB, 177 NPC_LA, 178 NPC_LB, 179 NPC_LC, 180 NPC_LD, 181 NPC_LE, 182 NPC_LF, 183 NPC_LG, 184 NPC_LH, 185 /* Ethertype for untagged frame */ 186 NPC_ETYPE_ETHER, 187 /* Ethertype for single tagged frame */ 188 NPC_ETYPE_TAG1, 189 /* Ethertype for double tagged frame */ 190 NPC_ETYPE_TAG2, 191 /* outer vlan tci for single tagged frame */ 192 NPC_VLAN_TAG1, 193 /* outer vlan tci for double tagged frame */ 194 NPC_VLAN_TAG2, 195 /* other header fields programmed to extract but not of our interest */ 196 NPC_UNKNOWN, 197 NPC_KEY_FIELDS_MAX, 198 }; 199 200 struct npc_kpu_profile_cam { 201 u8 state; 202 u8 state_mask; 203 u16 dp0; 204 u16 dp0_mask; 205 u16 dp1; 206 u16 dp1_mask; 207 u16 dp2; 208 u16 dp2_mask; 209 }; 210 211 struct npc_kpu_profile_action { 212 u8 errlev; 213 u8 errcode; 214 u8 dp0_offset; 215 u8 dp1_offset; 216 u8 dp2_offset; 217 u8 bypass_count; 218 u8 parse_done; 219 u8 next_state; 220 u8 ptr_advance; 221 u8 cap_ena; 222 u8 lid; 223 u8 ltype; 224 u8 flags; 225 u8 offset; 226 u8 mask; 227 u8 right; 228 u8 shift; 229 }; 230 231 struct npc_kpu_profile { 232 int cam_entries; 233 int action_entries; 234 const struct npc_kpu_profile_cam *cam; 235 const struct npc_kpu_profile_action *action; 236 }; 237 238 /* NPC KPU register formats */ 239 struct npc_kpu_cam { 240 #if defined(__BIG_ENDIAN_BITFIELD) 241 u64 rsvd_63_56 : 8; 242 u64 state : 8; 243 u64 dp2_data : 16; 244 u64 dp1_data : 16; 245 u64 dp0_data : 16; 246 #else 247 u64 dp0_data : 16; 248 u64 dp1_data : 16; 249 u64 dp2_data : 16; 250 u64 state : 8; 251 u64 rsvd_63_56 : 8; 252 #endif 253 }; 254 255 struct npc_kpu_action0 { 256 #if defined(__BIG_ENDIAN_BITFIELD) 257 u64 rsvd_63_57 : 7; 258 u64 byp_count : 3; 259 u64 capture_ena : 1; 260 u64 parse_done : 1; 261 u64 next_state : 8; 262 u64 rsvd_43 : 1; 263 u64 capture_lid : 3; 264 u64 capture_ltype : 4; 265 u64 capture_flags : 8; 266 u64 ptr_advance : 8; 267 u64 var_len_offset : 8; 268 u64 var_len_mask : 8; 269 u64 var_len_right : 1; 270 u64 var_len_shift : 3; 271 #else 272 u64 var_len_shift : 3; 273 u64 var_len_right : 1; 274 u64 var_len_mask : 8; 275 u64 var_len_offset : 8; 276 u64 ptr_advance : 8; 277 u64 capture_flags : 8; 278 u64 capture_ltype : 4; 279 u64 capture_lid : 3; 280 u64 rsvd_43 : 1; 281 u64 next_state : 8; 282 u64 parse_done : 1; 283 u64 capture_ena : 1; 284 u64 byp_count : 3; 285 u64 rsvd_63_57 : 7; 286 #endif 287 }; 288 289 struct npc_kpu_action1 { 290 #if defined(__BIG_ENDIAN_BITFIELD) 291 u64 rsvd_63_36 : 28; 292 u64 errlev : 4; 293 u64 errcode : 8; 294 u64 dp2_offset : 8; 295 u64 dp1_offset : 8; 296 u64 dp0_offset : 8; 297 #else 298 u64 dp0_offset : 8; 299 u64 dp1_offset : 8; 300 u64 dp2_offset : 8; 301 u64 errcode : 8; 302 u64 errlev : 4; 303 u64 rsvd_63_36 : 28; 304 #endif 305 }; 306 307 struct npc_kpu_pkind_cpi_def { 308 #if defined(__BIG_ENDIAN_BITFIELD) 309 u64 ena : 1; 310 u64 rsvd_62_59 : 4; 311 u64 lid : 3; 312 u64 ltype_match : 4; 313 u64 ltype_mask : 4; 314 u64 flags_match : 8; 315 u64 flags_mask : 8; 316 u64 add_offset : 8; 317 u64 add_mask : 8; 318 u64 rsvd_15 : 1; 319 u64 add_shift : 3; 320 u64 rsvd_11_10 : 2; 321 u64 cpi_base : 10; 322 #else 323 u64 cpi_base : 10; 324 u64 rsvd_11_10 : 2; 325 u64 add_shift : 3; 326 u64 rsvd_15 : 1; 327 u64 add_mask : 8; 328 u64 add_offset : 8; 329 u64 flags_mask : 8; 330 u64 flags_match : 8; 331 u64 ltype_mask : 4; 332 u64 ltype_match : 4; 333 u64 lid : 3; 334 u64 rsvd_62_59 : 4; 335 u64 ena : 1; 336 #endif 337 }; 338 339 struct nix_rx_action { 340 #if defined(__BIG_ENDIAN_BITFIELD) 341 u64 rsvd_63_61 :3; 342 u64 flow_key_alg :5; 343 u64 match_id :16; 344 u64 index :20; 345 u64 pf_func :16; 346 u64 op :4; 347 #else 348 u64 op :4; 349 u64 pf_func :16; 350 u64 index :20; 351 u64 match_id :16; 352 u64 flow_key_alg :5; 353 u64 rsvd_63_61 :3; 354 #endif 355 }; 356 357 /* NPC_AF_INTFX_KEX_CFG field masks */ 358 #define NPC_PARSE_NIBBLE GENMASK_ULL(30, 0) 359 360 /* NPC_PARSE_KEX_S nibble definitions for each field */ 361 #define NPC_PARSE_NIBBLE_CHAN GENMASK_ULL(2, 0) 362 #define NPC_PARSE_NIBBLE_ERRLEV BIT_ULL(3) 363 #define NPC_PARSE_NIBBLE_ERRCODE GENMASK_ULL(5, 4) 364 #define NPC_PARSE_NIBBLE_L2L3_BCAST BIT_ULL(6) 365 #define NPC_PARSE_NIBBLE_LA_FLAGS GENMASK_ULL(8, 7) 366 #define NPC_PARSE_NIBBLE_LA_LTYPE BIT_ULL(9) 367 #define NPC_PARSE_NIBBLE_LB_FLAGS GENMASK_ULL(11, 10) 368 #define NPC_PARSE_NIBBLE_LB_LTYPE BIT_ULL(12) 369 #define NPC_PARSE_NIBBLE_LC_FLAGS GENMASK_ULL(14, 13) 370 #define NPC_PARSE_NIBBLE_LC_LTYPE BIT_ULL(15) 371 #define NPC_PARSE_NIBBLE_LD_FLAGS GENMASK_ULL(17, 16) 372 #define NPC_PARSE_NIBBLE_LD_LTYPE BIT_ULL(18) 373 #define NPC_PARSE_NIBBLE_LE_FLAGS GENMASK_ULL(20, 19) 374 #define NPC_PARSE_NIBBLE_LE_LTYPE BIT_ULL(21) 375 #define NPC_PARSE_NIBBLE_LF_FLAGS GENMASK_ULL(23, 22) 376 #define NPC_PARSE_NIBBLE_LF_LTYPE BIT_ULL(24) 377 #define NPC_PARSE_NIBBLE_LG_FLAGS GENMASK_ULL(26, 25) 378 #define NPC_PARSE_NIBBLE_LG_LTYPE BIT_ULL(27) 379 #define NPC_PARSE_NIBBLE_LH_FLAGS GENMASK_ULL(29, 28) 380 #define NPC_PARSE_NIBBLE_LH_LTYPE BIT_ULL(30) 381 382 struct nix_tx_action { 383 #if defined(__BIG_ENDIAN_BITFIELD) 384 u64 rsvd_63_48 :16; 385 u64 match_id :16; 386 u64 index :20; 387 u64 rsvd_11_8 :8; 388 u64 op :4; 389 #else 390 u64 op :4; 391 u64 rsvd_11_8 :8; 392 u64 index :20; 393 u64 match_id :16; 394 u64 rsvd_63_48 :16; 395 #endif 396 }; 397 398 /* NIX Receive Vtag Action Structure */ 399 #define RX_VTAG0_VALID_BIT BIT_ULL(15) 400 #define RX_VTAG0_TYPE_MASK GENMASK_ULL(14, 12) 401 #define RX_VTAG0_LID_MASK GENMASK_ULL(10, 8) 402 #define RX_VTAG0_RELPTR_MASK GENMASK_ULL(7, 0) 403 #define RX_VTAG1_VALID_BIT BIT_ULL(47) 404 #define RX_VTAG1_TYPE_MASK GENMASK_ULL(46, 44) 405 #define RX_VTAG1_LID_MASK GENMASK_ULL(42, 40) 406 #define RX_VTAG1_RELPTR_MASK GENMASK_ULL(39, 32) 407 408 /* NIX Transmit Vtag Action Structure */ 409 #define TX_VTAG0_DEF_MASK GENMASK_ULL(25, 16) 410 #define TX_VTAG0_OP_MASK GENMASK_ULL(13, 12) 411 #define TX_VTAG0_LID_MASK GENMASK_ULL(10, 8) 412 #define TX_VTAG0_RELPTR_MASK GENMASK_ULL(7, 0) 413 #define TX_VTAG1_DEF_MASK GENMASK_ULL(57, 48) 414 #define TX_VTAG1_OP_MASK GENMASK_ULL(45, 44) 415 #define TX_VTAG1_LID_MASK GENMASK_ULL(42, 40) 416 #define TX_VTAG1_RELPTR_MASK GENMASK_ULL(39, 32) 417 418 struct npc_mcam_kex { 419 /* MKEX Profle Header */ 420 u64 mkex_sign; /* "mcam-kex-profile" (8 bytes/ASCII characters) */ 421 u8 name[MKEX_NAME_LEN]; /* MKEX Profile name */ 422 u64 cpu_model; /* Format as profiled by CPU hardware */ 423 u64 kpu_version; /* KPU firmware/profile version */ 424 u64 reserved; /* Reserved for extension */ 425 426 /* MKEX Profle Data */ 427 u64 keyx_cfg[NPC_MAX_INTF]; /* NPC_AF_INTF(0..1)_KEX_CFG */ 428 /* NPC_AF_KEX_LDATA(0..1)_FLAGS_CFG */ 429 u64 kex_ld_flags[NPC_MAX_LD]; 430 /* NPC_AF_INTF(0..1)_LID(0..7)_LT(0..15)_LD(0..1)_CFG */ 431 u64 intf_lid_lt_ld[NPC_MAX_INTF][NPC_MAX_LID][NPC_MAX_LT][NPC_MAX_LD]; 432 /* NPC_AF_INTF(0..1)_LDATA(0..1)_FLAGS(0..15)_CFG */ 433 u64 intf_ld_flags[NPC_MAX_INTF][NPC_MAX_LD][NPC_MAX_LFL]; 434 } __packed; 435 436 struct npc_lt_def { 437 u8 ltype_mask; 438 u8 ltype_match; 439 u8 lid; 440 }; 441 442 struct npc_lt_def_ipsec { 443 u8 ltype_mask; 444 u8 ltype_match; 445 u8 lid; 446 u8 spi_offset; 447 u8 spi_nz; 448 }; 449 450 struct npc_lt_def_cfg { 451 struct npc_lt_def rx_ol2; 452 struct npc_lt_def rx_oip4; 453 struct npc_lt_def rx_iip4; 454 struct npc_lt_def rx_oip6; 455 struct npc_lt_def rx_iip6; 456 struct npc_lt_def rx_otcp; 457 struct npc_lt_def rx_itcp; 458 struct npc_lt_def rx_oudp; 459 struct npc_lt_def rx_iudp; 460 struct npc_lt_def rx_osctp; 461 struct npc_lt_def rx_isctp; 462 struct npc_lt_def_ipsec rx_ipsec[2]; 463 struct npc_lt_def pck_ol2; 464 struct npc_lt_def pck_oip4; 465 struct npc_lt_def pck_oip6; 466 struct npc_lt_def pck_iip4; 467 }; 468 469 struct rvu_npc_mcam_rule { 470 struct flow_msg packet; 471 struct flow_msg mask; 472 u8 intf; 473 union { 474 struct nix_tx_action tx_action; 475 struct nix_rx_action rx_action; 476 }; 477 u64 vtag_action; 478 struct list_head list; 479 u64 features; 480 u16 owner; 481 u16 entry; 482 u16 cntr; 483 bool has_cntr; 484 u8 default_rule; 485 bool enable; 486 bool vfvlan_cfg; 487 }; 488 489 #endif /* NPC_H */ 490