1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Marvell OcteonTx2 RVU Admin Function driver 3 * 4 * Copyright (C) 2018 Marvell International Ltd. 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 */ 10 11 #ifndef MBOX_H 12 #define MBOX_H 13 14 #include <linux/etherdevice.h> 15 #include <linux/sizes.h> 16 17 #include "rvu_struct.h" 18 #include "common.h" 19 20 #define MBOX_SIZE SZ_64K 21 22 /* AF/PF: PF initiated, PF/VF VF initiated */ 23 #define MBOX_DOWN_RX_START 0 24 #define MBOX_DOWN_RX_SIZE (46 * SZ_1K) 25 #define MBOX_DOWN_TX_START (MBOX_DOWN_RX_START + MBOX_DOWN_RX_SIZE) 26 #define MBOX_DOWN_TX_SIZE (16 * SZ_1K) 27 /* AF/PF: AF initiated, PF/VF PF initiated */ 28 #define MBOX_UP_RX_START (MBOX_DOWN_TX_START + MBOX_DOWN_TX_SIZE) 29 #define MBOX_UP_RX_SIZE SZ_1K 30 #define MBOX_UP_TX_START (MBOX_UP_RX_START + MBOX_UP_RX_SIZE) 31 #define MBOX_UP_TX_SIZE SZ_1K 32 33 #if MBOX_UP_TX_SIZE + MBOX_UP_TX_START != MBOX_SIZE 34 # error "incorrect mailbox area sizes" 35 #endif 36 37 #define INTR_MASK(pfvfs) ((pfvfs < 64) ? (BIT_ULL(pfvfs) - 1) : (~0ull)) 38 39 #define MBOX_RSP_TIMEOUT 3000 /* Time(ms) to wait for mbox response */ 40 41 #define MBOX_MSG_ALIGN 16 /* Align mbox msg start to 16bytes */ 42 43 /* Mailbox directions */ 44 #define MBOX_DIR_AFPF 0 /* AF replies to PF */ 45 #define MBOX_DIR_PFAF 1 /* PF sends messages to AF */ 46 #define MBOX_DIR_PFVF 2 /* PF replies to VF */ 47 #define MBOX_DIR_VFPF 3 /* VF sends messages to PF */ 48 #define MBOX_DIR_AFPF_UP 4 /* AF sends messages to PF */ 49 #define MBOX_DIR_PFAF_UP 5 /* PF replies to AF */ 50 #define MBOX_DIR_PFVF_UP 6 /* PF sends messages to VF */ 51 #define MBOX_DIR_VFPF_UP 7 /* VF replies to PF */ 52 53 struct otx2_mbox_dev { 54 void *mbase; /* This dev's mbox region */ 55 void *hwbase; 56 spinlock_t mbox_lock; 57 u16 msg_size; /* Total msg size to be sent */ 58 u16 rsp_size; /* Total rsp size to be sure the reply is ok */ 59 u16 num_msgs; /* No of msgs sent or waiting for response */ 60 u16 msgs_acked; /* No of msgs for which response is received */ 61 }; 62 63 struct otx2_mbox { 64 struct pci_dev *pdev; 65 void *hwbase; /* Mbox region advertised by HW */ 66 void *reg_base;/* CSR base for this dev */ 67 u64 trigger; /* Trigger mbox notification */ 68 u16 tr_shift; /* Mbox trigger shift */ 69 u64 rx_start; /* Offset of Rx region in mbox memory */ 70 u64 tx_start; /* Offset of Tx region in mbox memory */ 71 u16 rx_size; /* Size of Rx region */ 72 u16 tx_size; /* Size of Tx region */ 73 u16 ndevs; /* The number of peers */ 74 struct otx2_mbox_dev *dev; 75 }; 76 77 /* Header which precedes all mbox messages */ 78 struct mbox_hdr { 79 u64 msg_size; /* Total msgs size embedded */ 80 u16 num_msgs; /* No of msgs embedded */ 81 }; 82 83 /* Header which precedes every msg and is also part of it */ 84 struct mbox_msghdr { 85 u16 pcifunc; /* Who's sending this msg */ 86 u16 id; /* Mbox message ID */ 87 #define OTX2_MBOX_REQ_SIG (0xdead) 88 #define OTX2_MBOX_RSP_SIG (0xbeef) 89 u16 sig; /* Signature, for validating corrupted msgs */ 90 #define OTX2_MBOX_VERSION (0x0007) 91 u16 ver; /* Version of msg's structure for this ID */ 92 u16 next_msgoff; /* Offset of next msg within mailbox region */ 93 int rc; /* Msg process'ed response code */ 94 }; 95 96 void otx2_mbox_reset(struct otx2_mbox *mbox, int devid); 97 void __otx2_mbox_reset(struct otx2_mbox *mbox, int devid); 98 void otx2_mbox_destroy(struct otx2_mbox *mbox); 99 int otx2_mbox_init(struct otx2_mbox *mbox, void __force *hwbase, 100 struct pci_dev *pdev, void __force *reg_base, 101 int direction, int ndevs); 102 int otx2_mbox_regions_init(struct otx2_mbox *mbox, void __force **hwbase, 103 struct pci_dev *pdev, void __force *reg_base, 104 int direction, int ndevs); 105 void otx2_mbox_msg_send(struct otx2_mbox *mbox, int devid); 106 int otx2_mbox_wait_for_rsp(struct otx2_mbox *mbox, int devid); 107 int otx2_mbox_busy_poll_for_rsp(struct otx2_mbox *mbox, int devid); 108 struct mbox_msghdr *otx2_mbox_alloc_msg_rsp(struct otx2_mbox *mbox, int devid, 109 int size, int size_rsp); 110 struct mbox_msghdr *otx2_mbox_get_rsp(struct otx2_mbox *mbox, int devid, 111 struct mbox_msghdr *msg); 112 int otx2_mbox_check_rsp_msgs(struct otx2_mbox *mbox, int devid); 113 int otx2_reply_invalid_msg(struct otx2_mbox *mbox, int devid, 114 u16 pcifunc, u16 id); 115 bool otx2_mbox_nonempty(struct otx2_mbox *mbox, int devid); 116 const char *otx2_mbox_id2name(u16 id); 117 static inline struct mbox_msghdr *otx2_mbox_alloc_msg(struct otx2_mbox *mbox, 118 int devid, int size) 119 { 120 return otx2_mbox_alloc_msg_rsp(mbox, devid, size, 0); 121 } 122 123 /* Mailbox message types */ 124 #define MBOX_MSG_MASK 0xFFFF 125 #define MBOX_MSG_INVALID 0xFFFE 126 #define MBOX_MSG_MAX 0xFFFF 127 128 #define MBOX_MESSAGES \ 129 /* Generic mbox IDs (range 0x000 - 0x1FF) */ \ 130 M(READY, 0x001, ready, msg_req, ready_msg_rsp) \ 131 M(ATTACH_RESOURCES, 0x002, attach_resources, rsrc_attach, msg_rsp) \ 132 M(DETACH_RESOURCES, 0x003, detach_resources, rsrc_detach, msg_rsp) \ 133 M(MSIX_OFFSET, 0x005, msix_offset, msg_req, msix_offset_rsp) \ 134 M(VF_FLR, 0x006, vf_flr, msg_req, msg_rsp) \ 135 M(PTP_OP, 0x007, ptp_op, ptp_req, ptp_rsp) \ 136 M(GET_HW_CAP, 0x008, get_hw_cap, msg_req, get_hw_cap_rsp) \ 137 M(SET_VF_PERM, 0x00b, set_vf_perm, set_vf_perm, msg_rsp) \ 138 /* CGX mbox IDs (range 0x200 - 0x3FF) */ \ 139 M(CGX_START_RXTX, 0x200, cgx_start_rxtx, msg_req, msg_rsp) \ 140 M(CGX_STOP_RXTX, 0x201, cgx_stop_rxtx, msg_req, msg_rsp) \ 141 M(CGX_STATS, 0x202, cgx_stats, msg_req, cgx_stats_rsp) \ 142 M(CGX_MAC_ADDR_SET, 0x203, cgx_mac_addr_set, cgx_mac_addr_set_or_get, \ 143 cgx_mac_addr_set_or_get) \ 144 M(CGX_MAC_ADDR_GET, 0x204, cgx_mac_addr_get, cgx_mac_addr_set_or_get, \ 145 cgx_mac_addr_set_or_get) \ 146 M(CGX_PROMISC_ENABLE, 0x205, cgx_promisc_enable, msg_req, msg_rsp) \ 147 M(CGX_PROMISC_DISABLE, 0x206, cgx_promisc_disable, msg_req, msg_rsp) \ 148 M(CGX_START_LINKEVENTS, 0x207, cgx_start_linkevents, msg_req, msg_rsp) \ 149 M(CGX_STOP_LINKEVENTS, 0x208, cgx_stop_linkevents, msg_req, msg_rsp) \ 150 M(CGX_GET_LINKINFO, 0x209, cgx_get_linkinfo, msg_req, cgx_link_info_msg) \ 151 M(CGX_INTLBK_ENABLE, 0x20A, cgx_intlbk_enable, msg_req, msg_rsp) \ 152 M(CGX_INTLBK_DISABLE, 0x20B, cgx_intlbk_disable, msg_req, msg_rsp) \ 153 M(CGX_PTP_RX_ENABLE, 0x20C, cgx_ptp_rx_enable, msg_req, msg_rsp) \ 154 M(CGX_PTP_RX_DISABLE, 0x20D, cgx_ptp_rx_disable, msg_req, msg_rsp) \ 155 M(CGX_CFG_PAUSE_FRM, 0x20E, cgx_cfg_pause_frm, cgx_pause_frm_cfg, \ 156 cgx_pause_frm_cfg) \ 157 M(CGX_FEC_SET, 0x210, cgx_set_fec_param, fec_mode, fec_mode) \ 158 M(CGX_FEC_STATS, 0x211, cgx_fec_stats, msg_req, cgx_fec_stats_rsp) \ 159 M(CGX_GET_PHY_FEC_STATS, 0x212, cgx_get_phy_fec_stats, msg_req, msg_rsp) \ 160 M(CGX_FW_DATA_GET, 0x213, cgx_get_aux_link_info, msg_req, cgx_fw_data) \ 161 M(CGX_SET_LINK_MODE, 0x214, cgx_set_link_mode, cgx_set_link_mode_req,\ 162 cgx_set_link_mode_rsp) \ 163 M(CGX_FEATURES_GET, 0x215, cgx_features_get, msg_req, \ 164 cgx_features_info_msg) \ 165 M(RPM_STATS, 0x216, rpm_stats, msg_req, rpm_stats_rsp) \ 166 /* NPA mbox IDs (range 0x400 - 0x5FF) */ \ 167 /* NPA mbox IDs (range 0x400 - 0x5FF) */ \ 168 M(NPA_LF_ALLOC, 0x400, npa_lf_alloc, \ 169 npa_lf_alloc_req, npa_lf_alloc_rsp) \ 170 M(NPA_LF_FREE, 0x401, npa_lf_free, msg_req, msg_rsp) \ 171 M(NPA_AQ_ENQ, 0x402, npa_aq_enq, npa_aq_enq_req, npa_aq_enq_rsp) \ 172 M(NPA_HWCTX_DISABLE, 0x403, npa_hwctx_disable, hwctx_disable_req, msg_rsp)\ 173 /* SSO/SSOW mbox IDs (range 0x600 - 0x7FF) */ \ 174 /* TIM mbox IDs (range 0x800 - 0x9FF) */ \ 175 /* CPT mbox IDs (range 0xA00 - 0xBFF) */ \ 176 M(CPT_LF_ALLOC, 0xA00, cpt_lf_alloc, cpt_lf_alloc_req_msg, \ 177 msg_rsp) \ 178 M(CPT_LF_FREE, 0xA01, cpt_lf_free, msg_req, msg_rsp) \ 179 M(CPT_RD_WR_REGISTER, 0xA02, cpt_rd_wr_register, cpt_rd_wr_reg_msg, \ 180 cpt_rd_wr_reg_msg) \ 181 M(CPT_STATS, 0xA05, cpt_sts, cpt_sts_req, cpt_sts_rsp) \ 182 M(CPT_RXC_TIME_CFG, 0xA06, cpt_rxc_time_cfg, cpt_rxc_time_cfg_req, \ 183 msg_rsp) \ 184 /* NPC mbox IDs (range 0x6000 - 0x7FFF) */ \ 185 M(NPC_MCAM_ALLOC_ENTRY, 0x6000, npc_mcam_alloc_entry, npc_mcam_alloc_entry_req,\ 186 npc_mcam_alloc_entry_rsp) \ 187 M(NPC_MCAM_FREE_ENTRY, 0x6001, npc_mcam_free_entry, \ 188 npc_mcam_free_entry_req, msg_rsp) \ 189 M(NPC_MCAM_WRITE_ENTRY, 0x6002, npc_mcam_write_entry, \ 190 npc_mcam_write_entry_req, msg_rsp) \ 191 M(NPC_MCAM_ENA_ENTRY, 0x6003, npc_mcam_ena_entry, \ 192 npc_mcam_ena_dis_entry_req, msg_rsp) \ 193 M(NPC_MCAM_DIS_ENTRY, 0x6004, npc_mcam_dis_entry, \ 194 npc_mcam_ena_dis_entry_req, msg_rsp) \ 195 M(NPC_MCAM_SHIFT_ENTRY, 0x6005, npc_mcam_shift_entry, npc_mcam_shift_entry_req,\ 196 npc_mcam_shift_entry_rsp) \ 197 M(NPC_MCAM_ALLOC_COUNTER, 0x6006, npc_mcam_alloc_counter, \ 198 npc_mcam_alloc_counter_req, \ 199 npc_mcam_alloc_counter_rsp) \ 200 M(NPC_MCAM_FREE_COUNTER, 0x6007, npc_mcam_free_counter, \ 201 npc_mcam_oper_counter_req, msg_rsp) \ 202 M(NPC_MCAM_UNMAP_COUNTER, 0x6008, npc_mcam_unmap_counter, \ 203 npc_mcam_unmap_counter_req, msg_rsp) \ 204 M(NPC_MCAM_CLEAR_COUNTER, 0x6009, npc_mcam_clear_counter, \ 205 npc_mcam_oper_counter_req, msg_rsp) \ 206 M(NPC_MCAM_COUNTER_STATS, 0x600a, npc_mcam_counter_stats, \ 207 npc_mcam_oper_counter_req, \ 208 npc_mcam_oper_counter_rsp) \ 209 M(NPC_MCAM_ALLOC_AND_WRITE_ENTRY, 0x600b, npc_mcam_alloc_and_write_entry, \ 210 npc_mcam_alloc_and_write_entry_req, \ 211 npc_mcam_alloc_and_write_entry_rsp) \ 212 M(NPC_GET_KEX_CFG, 0x600c, npc_get_kex_cfg, \ 213 msg_req, npc_get_kex_cfg_rsp) \ 214 M(NPC_INSTALL_FLOW, 0x600d, npc_install_flow, \ 215 npc_install_flow_req, npc_install_flow_rsp) \ 216 M(NPC_DELETE_FLOW, 0x600e, npc_delete_flow, \ 217 npc_delete_flow_req, msg_rsp) \ 218 M(NPC_MCAM_READ_ENTRY, 0x600f, npc_mcam_read_entry, \ 219 npc_mcam_read_entry_req, \ 220 npc_mcam_read_entry_rsp) \ 221 M(NPC_MCAM_READ_BASE_RULE, 0x6011, npc_read_base_steer_rule, \ 222 msg_req, npc_mcam_read_base_rule_rsp) \ 223 M(NPC_MCAM_GET_STATS, 0x6012, npc_mcam_entry_stats, \ 224 npc_mcam_get_stats_req, \ 225 npc_mcam_get_stats_rsp) \ 226 /* NIX mbox IDs (range 0x8000 - 0xFFFF) */ \ 227 M(NIX_LF_ALLOC, 0x8000, nix_lf_alloc, \ 228 nix_lf_alloc_req, nix_lf_alloc_rsp) \ 229 M(NIX_LF_FREE, 0x8001, nix_lf_free, nix_lf_free_req, msg_rsp) \ 230 M(NIX_AQ_ENQ, 0x8002, nix_aq_enq, nix_aq_enq_req, nix_aq_enq_rsp) \ 231 M(NIX_HWCTX_DISABLE, 0x8003, nix_hwctx_disable, \ 232 hwctx_disable_req, msg_rsp) \ 233 M(NIX_TXSCH_ALLOC, 0x8004, nix_txsch_alloc, \ 234 nix_txsch_alloc_req, nix_txsch_alloc_rsp) \ 235 M(NIX_TXSCH_FREE, 0x8005, nix_txsch_free, nix_txsch_free_req, msg_rsp) \ 236 M(NIX_TXSCHQ_CFG, 0x8006, nix_txschq_cfg, nix_txschq_config, msg_rsp) \ 237 M(NIX_STATS_RST, 0x8007, nix_stats_rst, msg_req, msg_rsp) \ 238 M(NIX_VTAG_CFG, 0x8008, nix_vtag_cfg, nix_vtag_config, \ 239 nix_vtag_config_rsp) \ 240 M(NIX_RSS_FLOWKEY_CFG, 0x8009, nix_rss_flowkey_cfg, \ 241 nix_rss_flowkey_cfg, \ 242 nix_rss_flowkey_cfg_rsp) \ 243 M(NIX_SET_MAC_ADDR, 0x800a, nix_set_mac_addr, nix_set_mac_addr, msg_rsp) \ 244 M(NIX_SET_RX_MODE, 0x800b, nix_set_rx_mode, nix_rx_mode, msg_rsp) \ 245 M(NIX_SET_HW_FRS, 0x800c, nix_set_hw_frs, nix_frs_cfg, msg_rsp) \ 246 M(NIX_LF_START_RX, 0x800d, nix_lf_start_rx, msg_req, msg_rsp) \ 247 M(NIX_LF_STOP_RX, 0x800e, nix_lf_stop_rx, msg_req, msg_rsp) \ 248 M(NIX_MARK_FORMAT_CFG, 0x800f, nix_mark_format_cfg, \ 249 nix_mark_format_cfg, \ 250 nix_mark_format_cfg_rsp) \ 251 M(NIX_SET_RX_CFG, 0x8010, nix_set_rx_cfg, nix_rx_cfg, msg_rsp) \ 252 M(NIX_LSO_FORMAT_CFG, 0x8011, nix_lso_format_cfg, \ 253 nix_lso_format_cfg, \ 254 nix_lso_format_cfg_rsp) \ 255 M(NIX_LF_PTP_TX_ENABLE, 0x8013, nix_lf_ptp_tx_enable, msg_req, msg_rsp) \ 256 M(NIX_LF_PTP_TX_DISABLE, 0x8014, nix_lf_ptp_tx_disable, msg_req, msg_rsp) \ 257 M(NIX_BP_ENABLE, 0x8016, nix_bp_enable, nix_bp_cfg_req, \ 258 nix_bp_cfg_rsp) \ 259 M(NIX_BP_DISABLE, 0x8017, nix_bp_disable, nix_bp_cfg_req, msg_rsp) \ 260 M(NIX_GET_MAC_ADDR, 0x8018, nix_get_mac_addr, msg_req, nix_get_mac_addr_rsp) \ 261 M(NIX_CN10K_AQ_ENQ, 0x8019, nix_cn10k_aq_enq, nix_cn10k_aq_enq_req, \ 262 nix_cn10k_aq_enq_rsp) \ 263 M(NIX_GET_HW_INFO, 0x801a, nix_get_hw_info, msg_req, nix_hw_info) 264 265 /* Messages initiated by AF (range 0xC00 - 0xDFF) */ 266 #define MBOX_UP_CGX_MESSAGES \ 267 M(CGX_LINK_EVENT, 0xC00, cgx_link_event, cgx_link_info_msg, msg_rsp) 268 269 enum { 270 #define M(_name, _id, _1, _2, _3) MBOX_MSG_ ## _name = _id, 271 MBOX_MESSAGES 272 MBOX_UP_CGX_MESSAGES 273 #undef M 274 }; 275 276 /* Mailbox message formats */ 277 278 #define RVU_DEFAULT_PF_FUNC 0xFFFF 279 280 /* Generic request msg used for those mbox messages which 281 * don't send any data in the request. 282 */ 283 struct msg_req { 284 struct mbox_msghdr hdr; 285 }; 286 287 /* Generic response msg used an ack or response for those mbox 288 * messages which don't have a specific rsp msg format. 289 */ 290 struct msg_rsp { 291 struct mbox_msghdr hdr; 292 }; 293 294 /* RVU mailbox error codes 295 * Range 256 - 300. 296 */ 297 enum rvu_af_status { 298 RVU_INVALID_VF_ID = -256, 299 }; 300 301 struct ready_msg_rsp { 302 struct mbox_msghdr hdr; 303 u16 sclk_freq; /* SCLK frequency (in MHz) */ 304 u16 rclk_freq; /* RCLK frequency (in MHz) */ 305 }; 306 307 /* Structure for requesting resource provisioning. 308 * 'modify' flag to be used when either requesting more 309 * or to detach partial of a certain resource type. 310 * Rest of the fields specify how many of what type to 311 * be attached. 312 * To request LFs from two blocks of same type this mailbox 313 * can be sent twice as below: 314 * struct rsrc_attach *attach; 315 * .. Allocate memory for message .. 316 * attach->cptlfs = 3; <3 LFs from CPT0> 317 * .. Send message .. 318 * .. Allocate memory for message .. 319 * attach->modify = 1; 320 * attach->cpt_blkaddr = BLKADDR_CPT1; 321 * attach->cptlfs = 2; <2 LFs from CPT1> 322 * .. Send message .. 323 */ 324 struct rsrc_attach { 325 struct mbox_msghdr hdr; 326 u8 modify:1; 327 u8 npalf:1; 328 u8 nixlf:1; 329 u16 sso; 330 u16 ssow; 331 u16 timlfs; 332 u16 cptlfs; 333 int cpt_blkaddr; /* BLKADDR_CPT0/BLKADDR_CPT1 or 0 for BLKADDR_CPT0 */ 334 }; 335 336 /* Structure for relinquishing resources. 337 * 'partial' flag to be used when relinquishing all resources 338 * but only of a certain type. If not set, all resources of all 339 * types provisioned to the RVU function will be detached. 340 */ 341 struct rsrc_detach { 342 struct mbox_msghdr hdr; 343 u8 partial:1; 344 u8 npalf:1; 345 u8 nixlf:1; 346 u8 sso:1; 347 u8 ssow:1; 348 u8 timlfs:1; 349 u8 cptlfs:1; 350 }; 351 352 #define MSIX_VECTOR_INVALID 0xFFFF 353 #define MAX_RVU_BLKLF_CNT 256 354 355 struct msix_offset_rsp { 356 struct mbox_msghdr hdr; 357 u16 npa_msixoff; 358 u16 nix_msixoff; 359 u8 sso; 360 u8 ssow; 361 u8 timlfs; 362 u8 cptlfs; 363 u16 sso_msixoff[MAX_RVU_BLKLF_CNT]; 364 u16 ssow_msixoff[MAX_RVU_BLKLF_CNT]; 365 u16 timlf_msixoff[MAX_RVU_BLKLF_CNT]; 366 u16 cptlf_msixoff[MAX_RVU_BLKLF_CNT]; 367 u8 cpt1_lfs; 368 u16 cpt1_lf_msixoff[MAX_RVU_BLKLF_CNT]; 369 }; 370 371 struct get_hw_cap_rsp { 372 struct mbox_msghdr hdr; 373 u8 nix_fixed_txschq_mapping; /* Schq mapping fixed or flexible */ 374 u8 nix_shaping; /* Is shaping and coloring supported */ 375 }; 376 377 /* CGX mbox message formats */ 378 379 struct cgx_stats_rsp { 380 struct mbox_msghdr hdr; 381 #define CGX_RX_STATS_COUNT 9 382 #define CGX_TX_STATS_COUNT 18 383 u64 rx_stats[CGX_RX_STATS_COUNT]; 384 u64 tx_stats[CGX_TX_STATS_COUNT]; 385 }; 386 387 struct cgx_fec_stats_rsp { 388 struct mbox_msghdr hdr; 389 u64 fec_corr_blks; 390 u64 fec_uncorr_blks; 391 }; 392 /* Structure for requesting the operation for 393 * setting/getting mac address in the CGX interface 394 */ 395 struct cgx_mac_addr_set_or_get { 396 struct mbox_msghdr hdr; 397 u8 mac_addr[ETH_ALEN]; 398 }; 399 400 struct cgx_link_user_info { 401 uint64_t link_up:1; 402 uint64_t full_duplex:1; 403 uint64_t lmac_type_id:4; 404 uint64_t speed:20; /* speed in Mbps */ 405 uint64_t an:1; /* AN supported or not */ 406 uint64_t fec:2; /* FEC type if enabled else 0 */ 407 #define LMACTYPE_STR_LEN 16 408 char lmac_type[LMACTYPE_STR_LEN]; 409 }; 410 411 struct cgx_link_info_msg { 412 struct mbox_msghdr hdr; 413 struct cgx_link_user_info link_info; 414 }; 415 416 struct cgx_pause_frm_cfg { 417 struct mbox_msghdr hdr; 418 u8 set; 419 /* set = 1 if the request is to config pause frames */ 420 /* set = 0 if the request is to fetch pause frames config */ 421 u8 rx_pause; 422 u8 tx_pause; 423 }; 424 425 enum fec_type { 426 OTX2_FEC_NONE, 427 OTX2_FEC_BASER, 428 OTX2_FEC_RS, 429 OTX2_FEC_STATS_CNT = 2, 430 OTX2_FEC_OFF, 431 }; 432 433 struct fec_mode { 434 struct mbox_msghdr hdr; 435 int fec; 436 }; 437 438 struct sfp_eeprom_s { 439 #define SFP_EEPROM_SIZE 256 440 u16 sff_id; 441 u8 buf[SFP_EEPROM_SIZE]; 442 u64 reserved; 443 }; 444 445 struct phy_s { 446 struct { 447 u64 can_change_mod_type:1; 448 u64 mod_type:1; 449 u64 has_fec_stats:1; 450 } misc; 451 struct fec_stats_s { 452 u32 rsfec_corr_cws; 453 u32 rsfec_uncorr_cws; 454 u32 brfec_corr_blks; 455 u32 brfec_uncorr_blks; 456 } fec_stats; 457 }; 458 459 struct cgx_lmac_fwdata_s { 460 u16 rw_valid; 461 u64 supported_fec; 462 u64 supported_an; 463 u64 supported_link_modes; 464 /* only applicable if AN is supported */ 465 u64 advertised_fec; 466 u64 advertised_link_modes; 467 /* Only applicable if SFP/QSFP slot is present */ 468 struct sfp_eeprom_s sfp_eeprom; 469 struct phy_s phy; 470 #define LMAC_FWDATA_RESERVED_MEM 1021 471 u64 reserved[LMAC_FWDATA_RESERVED_MEM]; 472 }; 473 474 struct cgx_fw_data { 475 struct mbox_msghdr hdr; 476 struct cgx_lmac_fwdata_s fwdata; 477 }; 478 479 struct cgx_set_link_mode_args { 480 u32 speed; 481 u8 duplex; 482 u8 an; 483 u8 ports; 484 u64 mode; 485 }; 486 487 struct cgx_set_link_mode_req { 488 #define AUTONEG_UNKNOWN 0xff 489 struct mbox_msghdr hdr; 490 struct cgx_set_link_mode_args args; 491 }; 492 493 struct cgx_set_link_mode_rsp { 494 struct mbox_msghdr hdr; 495 int status; 496 }; 497 498 #define RVU_LMAC_FEAT_FC BIT_ULL(0) /* pause frames */ 499 #define RVU_LMAC_FEAT_PTP BIT_ULL(1) /* precision time protocol */ 500 #define RVU_MAC_VERSION BIT_ULL(2) 501 #define RVU_MAC_CGX BIT_ULL(3) 502 #define RVU_MAC_RPM BIT_ULL(4) 503 504 struct cgx_features_info_msg { 505 struct mbox_msghdr hdr; 506 u64 lmac_features; 507 }; 508 509 struct rpm_stats_rsp { 510 struct mbox_msghdr hdr; 511 #define RPM_RX_STATS_COUNT 43 512 #define RPM_TX_STATS_COUNT 34 513 u64 rx_stats[RPM_RX_STATS_COUNT]; 514 u64 tx_stats[RPM_TX_STATS_COUNT]; 515 }; 516 517 /* NPA mbox message formats */ 518 519 /* NPA mailbox error codes 520 * Range 301 - 400. 521 */ 522 enum npa_af_status { 523 NPA_AF_ERR_PARAM = -301, 524 NPA_AF_ERR_AQ_FULL = -302, 525 NPA_AF_ERR_AQ_ENQUEUE = -303, 526 NPA_AF_ERR_AF_LF_INVALID = -304, 527 NPA_AF_ERR_AF_LF_ALLOC = -305, 528 NPA_AF_ERR_LF_RESET = -306, 529 }; 530 531 /* For NPA LF context alloc and init */ 532 struct npa_lf_alloc_req { 533 struct mbox_msghdr hdr; 534 int node; 535 int aura_sz; /* No of auras */ 536 u32 nr_pools; /* No of pools */ 537 u64 way_mask; 538 }; 539 540 struct npa_lf_alloc_rsp { 541 struct mbox_msghdr hdr; 542 u32 stack_pg_ptrs; /* No of ptrs per stack page */ 543 u32 stack_pg_bytes; /* Size of stack page */ 544 u16 qints; /* NPA_AF_CONST::QINTS */ 545 }; 546 547 /* NPA AQ enqueue msg */ 548 struct npa_aq_enq_req { 549 struct mbox_msghdr hdr; 550 u32 aura_id; 551 u8 ctype; 552 u8 op; 553 union { 554 /* Valid when op == WRITE/INIT and ctype == AURA. 555 * LF fills the pool_id in aura.pool_addr. AF will translate 556 * the pool_id to pool context pointer. 557 */ 558 struct npa_aura_s aura; 559 /* Valid when op == WRITE/INIT and ctype == POOL */ 560 struct npa_pool_s pool; 561 }; 562 /* Mask data when op == WRITE (1=write, 0=don't write) */ 563 union { 564 /* Valid when op == WRITE and ctype == AURA */ 565 struct npa_aura_s aura_mask; 566 /* Valid when op == WRITE and ctype == POOL */ 567 struct npa_pool_s pool_mask; 568 }; 569 }; 570 571 struct npa_aq_enq_rsp { 572 struct mbox_msghdr hdr; 573 union { 574 /* Valid when op == READ and ctype == AURA */ 575 struct npa_aura_s aura; 576 /* Valid when op == READ and ctype == POOL */ 577 struct npa_pool_s pool; 578 }; 579 }; 580 581 /* Disable all contexts of type 'ctype' */ 582 struct hwctx_disable_req { 583 struct mbox_msghdr hdr; 584 u8 ctype; 585 }; 586 587 /* NIX mbox message formats */ 588 589 /* NIX mailbox error codes 590 * Range 401 - 500. 591 */ 592 enum nix_af_status { 593 NIX_AF_ERR_PARAM = -401, 594 NIX_AF_ERR_AQ_FULL = -402, 595 NIX_AF_ERR_AQ_ENQUEUE = -403, 596 NIX_AF_ERR_AF_LF_INVALID = -404, 597 NIX_AF_ERR_AF_LF_ALLOC = -405, 598 NIX_AF_ERR_TLX_ALLOC_FAIL = -406, 599 NIX_AF_ERR_TLX_INVALID = -407, 600 NIX_AF_ERR_RSS_SIZE_INVALID = -408, 601 NIX_AF_ERR_RSS_GRPS_INVALID = -409, 602 NIX_AF_ERR_FRS_INVALID = -410, 603 NIX_AF_ERR_RX_LINK_INVALID = -411, 604 NIX_AF_INVAL_TXSCHQ_CFG = -412, 605 NIX_AF_SMQ_FLUSH_FAILED = -413, 606 NIX_AF_ERR_LF_RESET = -414, 607 NIX_AF_ERR_RSS_NOSPC_FIELD = -415, 608 NIX_AF_ERR_RSS_NOSPC_ALGO = -416, 609 NIX_AF_ERR_MARK_CFG_FAIL = -417, 610 NIX_AF_ERR_LSO_CFG_FAIL = -418, 611 NIX_AF_INVAL_NPA_PF_FUNC = -419, 612 NIX_AF_INVAL_SSO_PF_FUNC = -420, 613 NIX_AF_ERR_TX_VTAG_NOSPC = -421, 614 NIX_AF_ERR_RX_VTAG_INUSE = -422, 615 NIX_AF_ERR_PTP_CONFIG_FAIL = -423, 616 NIX_AF_ERR_NPC_KEY_NOT_SUPP = -424, 617 NIX_AF_ERR_INVALID_NIXBLK = -425, 618 }; 619 620 /* For NIX RX vtag action */ 621 enum nix_rx_vtag0_type { 622 NIX_AF_LFX_RX_VTAG_TYPE0, /* reserved for rx vlan offload */ 623 NIX_AF_LFX_RX_VTAG_TYPE1, 624 NIX_AF_LFX_RX_VTAG_TYPE2, 625 NIX_AF_LFX_RX_VTAG_TYPE3, 626 NIX_AF_LFX_RX_VTAG_TYPE4, 627 NIX_AF_LFX_RX_VTAG_TYPE5, 628 NIX_AF_LFX_RX_VTAG_TYPE6, 629 NIX_AF_LFX_RX_VTAG_TYPE7, 630 }; 631 632 /* For NIX LF context alloc and init */ 633 struct nix_lf_alloc_req { 634 struct mbox_msghdr hdr; 635 int node; 636 u32 rq_cnt; /* No of receive queues */ 637 u32 sq_cnt; /* No of send queues */ 638 u32 cq_cnt; /* No of completion queues */ 639 u8 xqe_sz; 640 u16 rss_sz; 641 u8 rss_grps; 642 u16 npa_func; 643 u16 sso_func; 644 u64 rx_cfg; /* See NIX_AF_LF(0..127)_RX_CFG */ 645 u64 way_mask; 646 }; 647 648 struct nix_lf_alloc_rsp { 649 struct mbox_msghdr hdr; 650 u16 sqb_size; 651 u16 rx_chan_base; 652 u16 tx_chan_base; 653 u8 rx_chan_cnt; /* total number of RX channels */ 654 u8 tx_chan_cnt; /* total number of TX channels */ 655 u8 lso_tsov4_idx; 656 u8 lso_tsov6_idx; 657 u8 mac_addr[ETH_ALEN]; 658 u8 lf_rx_stats; /* NIX_AF_CONST1::LF_RX_STATS */ 659 u8 lf_tx_stats; /* NIX_AF_CONST1::LF_TX_STATS */ 660 u16 cints; /* NIX_AF_CONST2::CINTS */ 661 u16 qints; /* NIX_AF_CONST2::QINTS */ 662 u8 cgx_links; /* No. of CGX links present in HW */ 663 u8 lbk_links; /* No. of LBK links present in HW */ 664 u8 sdp_links; /* No. of SDP links present in HW */ 665 }; 666 667 struct nix_lf_free_req { 668 struct mbox_msghdr hdr; 669 #define NIX_LF_DISABLE_FLOWS BIT_ULL(0) 670 #define NIX_LF_DONT_FREE_TX_VTAG BIT_ULL(1) 671 u64 flags; 672 }; 673 674 /* CN10K NIX AQ enqueue msg */ 675 struct nix_cn10k_aq_enq_req { 676 struct mbox_msghdr hdr; 677 u32 qidx; 678 u8 ctype; 679 u8 op; 680 union { 681 struct nix_cn10k_rq_ctx_s rq; 682 struct nix_cn10k_sq_ctx_s sq; 683 struct nix_cq_ctx_s cq; 684 struct nix_rsse_s rss; 685 struct nix_rx_mce_s mce; 686 }; 687 union { 688 struct nix_cn10k_rq_ctx_s rq_mask; 689 struct nix_cn10k_sq_ctx_s sq_mask; 690 struct nix_cq_ctx_s cq_mask; 691 struct nix_rsse_s rss_mask; 692 struct nix_rx_mce_s mce_mask; 693 }; 694 }; 695 696 struct nix_cn10k_aq_enq_rsp { 697 struct mbox_msghdr hdr; 698 union { 699 struct nix_cn10k_rq_ctx_s rq; 700 struct nix_cn10k_sq_ctx_s sq; 701 struct nix_cq_ctx_s cq; 702 struct nix_rsse_s rss; 703 struct nix_rx_mce_s mce; 704 }; 705 }; 706 707 /* NIX AQ enqueue msg */ 708 struct nix_aq_enq_req { 709 struct mbox_msghdr hdr; 710 u32 qidx; 711 u8 ctype; 712 u8 op; 713 union { 714 struct nix_rq_ctx_s rq; 715 struct nix_sq_ctx_s sq; 716 struct nix_cq_ctx_s cq; 717 struct nix_rsse_s rss; 718 struct nix_rx_mce_s mce; 719 }; 720 union { 721 struct nix_rq_ctx_s rq_mask; 722 struct nix_sq_ctx_s sq_mask; 723 struct nix_cq_ctx_s cq_mask; 724 struct nix_rsse_s rss_mask; 725 struct nix_rx_mce_s mce_mask; 726 }; 727 }; 728 729 struct nix_aq_enq_rsp { 730 struct mbox_msghdr hdr; 731 union { 732 struct nix_rq_ctx_s rq; 733 struct nix_sq_ctx_s sq; 734 struct nix_cq_ctx_s cq; 735 struct nix_rsse_s rss; 736 struct nix_rx_mce_s mce; 737 }; 738 }; 739 740 /* Tx scheduler/shaper mailbox messages */ 741 742 #define MAX_TXSCHQ_PER_FUNC 128 743 744 struct nix_txsch_alloc_req { 745 struct mbox_msghdr hdr; 746 /* Scheduler queue count request at each level */ 747 u16 schq_contig[NIX_TXSCH_LVL_CNT]; /* No of contiguous queues */ 748 u16 schq[NIX_TXSCH_LVL_CNT]; /* No of non-contiguous queues */ 749 }; 750 751 struct nix_txsch_alloc_rsp { 752 struct mbox_msghdr hdr; 753 /* Scheduler queue count allocated at each level */ 754 u16 schq_contig[NIX_TXSCH_LVL_CNT]; 755 u16 schq[NIX_TXSCH_LVL_CNT]; 756 /* Scheduler queue list allocated at each level */ 757 u16 schq_contig_list[NIX_TXSCH_LVL_CNT][MAX_TXSCHQ_PER_FUNC]; 758 u16 schq_list[NIX_TXSCH_LVL_CNT][MAX_TXSCHQ_PER_FUNC]; 759 u8 aggr_level; /* Traffic aggregation scheduler level */ 760 u8 aggr_lvl_rr_prio; /* Aggregation lvl's RR_PRIO config */ 761 u8 link_cfg_lvl; /* LINKX_CFG CSRs mapped to TL3 or TL2's index ? */ 762 }; 763 764 struct nix_txsch_free_req { 765 struct mbox_msghdr hdr; 766 #define TXSCHQ_FREE_ALL BIT_ULL(0) 767 u16 flags; 768 /* Scheduler queue level to be freed */ 769 u16 schq_lvl; 770 /* List of scheduler queues to be freed */ 771 u16 schq; 772 }; 773 774 struct nix_txschq_config { 775 struct mbox_msghdr hdr; 776 u8 lvl; /* SMQ/MDQ/TL4/TL3/TL2/TL1 */ 777 #define TXSCHQ_IDX_SHIFT 16 778 #define TXSCHQ_IDX_MASK (BIT_ULL(10) - 1) 779 #define TXSCHQ_IDX(reg, shift) (((reg) >> (shift)) & TXSCHQ_IDX_MASK) 780 u8 num_regs; 781 #define MAX_REGS_PER_MBOX_MSG 20 782 u64 reg[MAX_REGS_PER_MBOX_MSG]; 783 u64 regval[MAX_REGS_PER_MBOX_MSG]; 784 }; 785 786 struct nix_vtag_config { 787 struct mbox_msghdr hdr; 788 /* '0' for 4 octet VTAG, '1' for 8 octet VTAG */ 789 u8 vtag_size; 790 /* cfg_type is '0' for tx vlan cfg 791 * cfg_type is '1' for rx vlan cfg 792 */ 793 u8 cfg_type; 794 union { 795 /* valid when cfg_type is '0' */ 796 struct { 797 u64 vtag0; 798 u64 vtag1; 799 800 /* cfg_vtag0 & cfg_vtag1 fields are valid 801 * when free_vtag0 & free_vtag1 are '0's. 802 */ 803 /* cfg_vtag0 = 1 to configure vtag0 */ 804 u8 cfg_vtag0 :1; 805 /* cfg_vtag1 = 1 to configure vtag1 */ 806 u8 cfg_vtag1 :1; 807 808 /* vtag0_idx & vtag1_idx are only valid when 809 * both cfg_vtag0 & cfg_vtag1 are '0's, 810 * these fields are used along with free_vtag0 811 * & free_vtag1 to free the nix lf's tx_vlan 812 * configuration. 813 * 814 * Denotes the indices of tx_vtag def registers 815 * that needs to be cleared and freed. 816 */ 817 int vtag0_idx; 818 int vtag1_idx; 819 820 /* free_vtag0 & free_vtag1 fields are valid 821 * when cfg_vtag0 & cfg_vtag1 are '0's. 822 */ 823 /* free_vtag0 = 1 clears vtag0 configuration 824 * vtag0_idx denotes the index to be cleared. 825 */ 826 u8 free_vtag0 :1; 827 /* free_vtag1 = 1 clears vtag1 configuration 828 * vtag1_idx denotes the index to be cleared. 829 */ 830 u8 free_vtag1 :1; 831 } tx; 832 833 /* valid when cfg_type is '1' */ 834 struct { 835 /* rx vtag type index, valid values are in 0..7 range */ 836 u8 vtag_type; 837 /* rx vtag strip */ 838 u8 strip_vtag :1; 839 /* rx vtag capture */ 840 u8 capture_vtag :1; 841 } rx; 842 }; 843 }; 844 845 struct nix_vtag_config_rsp { 846 struct mbox_msghdr hdr; 847 int vtag0_idx; 848 int vtag1_idx; 849 /* Indices of tx_vtag def registers used to configure 850 * tx vtag0 & vtag1 headers, these indices are valid 851 * when nix_vtag_config mbox requested for vtag0 and/ 852 * or vtag1 configuration. 853 */ 854 }; 855 856 struct nix_rss_flowkey_cfg { 857 struct mbox_msghdr hdr; 858 int mcam_index; /* MCAM entry index to modify */ 859 #define NIX_FLOW_KEY_TYPE_PORT BIT(0) 860 #define NIX_FLOW_KEY_TYPE_IPV4 BIT(1) 861 #define NIX_FLOW_KEY_TYPE_IPV6 BIT(2) 862 #define NIX_FLOW_KEY_TYPE_TCP BIT(3) 863 #define NIX_FLOW_KEY_TYPE_UDP BIT(4) 864 #define NIX_FLOW_KEY_TYPE_SCTP BIT(5) 865 #define NIX_FLOW_KEY_TYPE_NVGRE BIT(6) 866 #define NIX_FLOW_KEY_TYPE_VXLAN BIT(7) 867 #define NIX_FLOW_KEY_TYPE_GENEVE BIT(8) 868 #define NIX_FLOW_KEY_TYPE_ETH_DMAC BIT(9) 869 #define NIX_FLOW_KEY_TYPE_IPV6_EXT BIT(10) 870 #define NIX_FLOW_KEY_TYPE_GTPU BIT(11) 871 #define NIX_FLOW_KEY_TYPE_INNR_IPV4 BIT(12) 872 #define NIX_FLOW_KEY_TYPE_INNR_IPV6 BIT(13) 873 #define NIX_FLOW_KEY_TYPE_INNR_TCP BIT(14) 874 #define NIX_FLOW_KEY_TYPE_INNR_UDP BIT(15) 875 #define NIX_FLOW_KEY_TYPE_INNR_SCTP BIT(16) 876 #define NIX_FLOW_KEY_TYPE_INNR_ETH_DMAC BIT(17) 877 #define NIX_FLOW_KEY_TYPE_VLAN BIT(20) 878 #define NIX_FLOW_KEY_TYPE_IPV4_PROTO BIT(21) 879 #define NIX_FLOW_KEY_TYPE_AH BIT(22) 880 #define NIX_FLOW_KEY_TYPE_ESP BIT(23) 881 u32 flowkey_cfg; /* Flowkey types selected */ 882 u8 group; /* RSS context or group */ 883 }; 884 885 struct nix_rss_flowkey_cfg_rsp { 886 struct mbox_msghdr hdr; 887 u8 alg_idx; /* Selected algo index */ 888 }; 889 890 struct nix_set_mac_addr { 891 struct mbox_msghdr hdr; 892 u8 mac_addr[ETH_ALEN]; /* MAC address to be set for this pcifunc */ 893 }; 894 895 struct nix_get_mac_addr_rsp { 896 struct mbox_msghdr hdr; 897 u8 mac_addr[ETH_ALEN]; 898 }; 899 900 struct nix_mark_format_cfg { 901 struct mbox_msghdr hdr; 902 u8 offset; 903 u8 y_mask; 904 u8 y_val; 905 u8 r_mask; 906 u8 r_val; 907 }; 908 909 struct nix_mark_format_cfg_rsp { 910 struct mbox_msghdr hdr; 911 u8 mark_format_idx; 912 }; 913 914 struct nix_rx_mode { 915 struct mbox_msghdr hdr; 916 #define NIX_RX_MODE_UCAST BIT(0) 917 #define NIX_RX_MODE_PROMISC BIT(1) 918 #define NIX_RX_MODE_ALLMULTI BIT(2) 919 #define NIX_RX_MODE_USE_MCE BIT(3) 920 u16 mode; 921 }; 922 923 struct nix_rx_cfg { 924 struct mbox_msghdr hdr; 925 #define NIX_RX_OL3_VERIFY BIT(0) 926 #define NIX_RX_OL4_VERIFY BIT(1) 927 u8 len_verify; /* Outer L3/L4 len check */ 928 #define NIX_RX_CSUM_OL4_VERIFY BIT(0) 929 u8 csum_verify; /* Outer L4 checksum verification */ 930 }; 931 932 struct nix_frs_cfg { 933 struct mbox_msghdr hdr; 934 u8 update_smq; /* Update SMQ's min/max lens */ 935 u8 update_minlen; /* Set minlen also */ 936 u8 sdp_link; /* Set SDP RX link */ 937 u16 maxlen; 938 u16 minlen; 939 }; 940 941 struct nix_lso_format_cfg { 942 struct mbox_msghdr hdr; 943 u64 field_mask; 944 #define NIX_LSO_FIELD_MAX 8 945 u64 fields[NIX_LSO_FIELD_MAX]; 946 }; 947 948 struct nix_lso_format_cfg_rsp { 949 struct mbox_msghdr hdr; 950 u8 lso_format_idx; 951 }; 952 953 struct nix_bp_cfg_req { 954 struct mbox_msghdr hdr; 955 u16 chan_base; /* Starting channel number */ 956 u8 chan_cnt; /* Number of channels */ 957 u8 bpid_per_chan; 958 /* bpid_per_chan = 0 assigns single bp id for range of channels */ 959 /* bpid_per_chan = 1 assigns separate bp id for each channel */ 960 }; 961 962 /* PF can be mapped to either CGX or LBK interface, 963 * so maximum 64 channels are possible. 964 */ 965 #define NIX_MAX_BPID_CHAN 64 966 struct nix_bp_cfg_rsp { 967 struct mbox_msghdr hdr; 968 u16 chan_bpid[NIX_MAX_BPID_CHAN]; /* Channel and bpid mapping */ 969 u8 chan_cnt; /* Number of channel for which bpids are assigned */ 970 }; 971 972 struct nix_hw_info { 973 struct mbox_msghdr hdr; 974 u16 max_mtu; 975 u16 min_mtu; 976 }; 977 978 /* NPC mbox message structs */ 979 980 #define NPC_MCAM_ENTRY_INVALID 0xFFFF 981 #define NPC_MCAM_INVALID_MAP 0xFFFF 982 983 /* NPC mailbox error codes 984 * Range 701 - 800. 985 */ 986 enum npc_af_status { 987 NPC_MCAM_INVALID_REQ = -701, 988 NPC_MCAM_ALLOC_DENIED = -702, 989 NPC_MCAM_ALLOC_FAILED = -703, 990 NPC_MCAM_PERM_DENIED = -704, 991 }; 992 993 struct npc_mcam_alloc_entry_req { 994 struct mbox_msghdr hdr; 995 #define NPC_MAX_NONCONTIG_ENTRIES 256 996 u8 contig; /* Contiguous entries ? */ 997 #define NPC_MCAM_ANY_PRIO 0 998 #define NPC_MCAM_LOWER_PRIO 1 999 #define NPC_MCAM_HIGHER_PRIO 2 1000 u8 priority; /* Lower or higher w.r.t ref_entry */ 1001 u16 ref_entry; 1002 u16 count; /* Number of entries requested */ 1003 }; 1004 1005 struct npc_mcam_alloc_entry_rsp { 1006 struct mbox_msghdr hdr; 1007 u16 entry; /* Entry allocated or start index if contiguous. 1008 * Invalid incase of non-contiguous. 1009 */ 1010 u16 count; /* Number of entries allocated */ 1011 u16 free_count; /* Number of entries available */ 1012 u16 entry_list[NPC_MAX_NONCONTIG_ENTRIES]; 1013 }; 1014 1015 struct npc_mcam_free_entry_req { 1016 struct mbox_msghdr hdr; 1017 u16 entry; /* Entry index to be freed */ 1018 u8 all; /* If all entries allocated to this PFVF to be freed */ 1019 }; 1020 1021 struct mcam_entry { 1022 #define NPC_MAX_KWS_IN_KEY 7 /* Number of keywords in max keywidth */ 1023 u64 kw[NPC_MAX_KWS_IN_KEY]; 1024 u64 kw_mask[NPC_MAX_KWS_IN_KEY]; 1025 u64 action; 1026 u64 vtag_action; 1027 }; 1028 1029 struct npc_mcam_write_entry_req { 1030 struct mbox_msghdr hdr; 1031 struct mcam_entry entry_data; 1032 u16 entry; /* MCAM entry to write this match key */ 1033 u16 cntr; /* Counter for this MCAM entry */ 1034 u8 intf; /* Rx or Tx interface */ 1035 u8 enable_entry;/* Enable this MCAM entry ? */ 1036 u8 set_cntr; /* Set counter for this entry ? */ 1037 }; 1038 1039 /* Enable/Disable a given entry */ 1040 struct npc_mcam_ena_dis_entry_req { 1041 struct mbox_msghdr hdr; 1042 u16 entry; 1043 }; 1044 1045 struct npc_mcam_shift_entry_req { 1046 struct mbox_msghdr hdr; 1047 #define NPC_MCAM_MAX_SHIFTS 64 1048 u16 curr_entry[NPC_MCAM_MAX_SHIFTS]; 1049 u16 new_entry[NPC_MCAM_MAX_SHIFTS]; 1050 u16 shift_count; /* Number of entries to shift */ 1051 }; 1052 1053 struct npc_mcam_shift_entry_rsp { 1054 struct mbox_msghdr hdr; 1055 u16 failed_entry_idx; /* Index in 'curr_entry', not entry itself */ 1056 }; 1057 1058 struct npc_mcam_alloc_counter_req { 1059 struct mbox_msghdr hdr; 1060 u8 contig; /* Contiguous counters ? */ 1061 #define NPC_MAX_NONCONTIG_COUNTERS 64 1062 u16 count; /* Number of counters requested */ 1063 }; 1064 1065 struct npc_mcam_alloc_counter_rsp { 1066 struct mbox_msghdr hdr; 1067 u16 cntr; /* Counter allocated or start index if contiguous. 1068 * Invalid incase of non-contiguous. 1069 */ 1070 u16 count; /* Number of counters allocated */ 1071 u16 cntr_list[NPC_MAX_NONCONTIG_COUNTERS]; 1072 }; 1073 1074 struct npc_mcam_oper_counter_req { 1075 struct mbox_msghdr hdr; 1076 u16 cntr; /* Free a counter or clear/fetch it's stats */ 1077 }; 1078 1079 struct npc_mcam_oper_counter_rsp { 1080 struct mbox_msghdr hdr; 1081 u64 stat; /* valid only while fetching counter's stats */ 1082 }; 1083 1084 struct npc_mcam_unmap_counter_req { 1085 struct mbox_msghdr hdr; 1086 u16 cntr; 1087 u16 entry; /* Entry and counter to be unmapped */ 1088 u8 all; /* Unmap all entries using this counter ? */ 1089 }; 1090 1091 struct npc_mcam_alloc_and_write_entry_req { 1092 struct mbox_msghdr hdr; 1093 struct mcam_entry entry_data; 1094 u16 ref_entry; 1095 u8 priority; /* Lower or higher w.r.t ref_entry */ 1096 u8 intf; /* Rx or Tx interface */ 1097 u8 enable_entry;/* Enable this MCAM entry ? */ 1098 u8 alloc_cntr; /* Allocate counter and map ? */ 1099 }; 1100 1101 struct npc_mcam_alloc_and_write_entry_rsp { 1102 struct mbox_msghdr hdr; 1103 u16 entry; 1104 u16 cntr; 1105 }; 1106 1107 struct npc_get_kex_cfg_rsp { 1108 struct mbox_msghdr hdr; 1109 u64 rx_keyx_cfg; /* NPC_AF_INTF(0)_KEX_CFG */ 1110 u64 tx_keyx_cfg; /* NPC_AF_INTF(1)_KEX_CFG */ 1111 #define NPC_MAX_INTF 2 1112 #define NPC_MAX_LID 8 1113 #define NPC_MAX_LT 16 1114 #define NPC_MAX_LD 2 1115 #define NPC_MAX_LFL 16 1116 /* NPC_AF_KEX_LDATA(0..1)_FLAGS_CFG */ 1117 u64 kex_ld_flags[NPC_MAX_LD]; 1118 /* NPC_AF_INTF(0..1)_LID(0..7)_LT(0..15)_LD(0..1)_CFG */ 1119 u64 intf_lid_lt_ld[NPC_MAX_INTF][NPC_MAX_LID][NPC_MAX_LT][NPC_MAX_LD]; 1120 /* NPC_AF_INTF(0..1)_LDATA(0..1)_FLAGS(0..15)_CFG */ 1121 u64 intf_ld_flags[NPC_MAX_INTF][NPC_MAX_LD][NPC_MAX_LFL]; 1122 #define MKEX_NAME_LEN 128 1123 u8 mkex_pfl_name[MKEX_NAME_LEN]; 1124 }; 1125 1126 struct flow_msg { 1127 unsigned char dmac[6]; 1128 unsigned char smac[6]; 1129 __be16 etype; 1130 __be16 vlan_etype; 1131 __be16 vlan_tci; 1132 union { 1133 __be32 ip4src; 1134 __be32 ip6src[4]; 1135 }; 1136 union { 1137 __be32 ip4dst; 1138 __be32 ip6dst[4]; 1139 }; 1140 u8 tos; 1141 u8 ip_ver; 1142 u8 ip_proto; 1143 u8 tc; 1144 __be16 sport; 1145 __be16 dport; 1146 }; 1147 1148 struct npc_install_flow_req { 1149 struct mbox_msghdr hdr; 1150 struct flow_msg packet; 1151 struct flow_msg mask; 1152 u64 features; 1153 u16 entry; 1154 u16 channel; 1155 u16 chan_mask; 1156 u8 intf; 1157 u8 set_cntr; /* If counter is available set counter for this entry ? */ 1158 u8 default_rule; 1159 u8 append; /* overwrite(0) or append(1) flow to default rule? */ 1160 u16 vf; 1161 /* action */ 1162 u32 index; 1163 u16 match_id; 1164 u8 flow_key_alg; 1165 u8 op; 1166 /* vtag rx action */ 1167 u8 vtag0_type; 1168 u8 vtag0_valid; 1169 u8 vtag1_type; 1170 u8 vtag1_valid; 1171 /* vtag tx action */ 1172 u16 vtag0_def; 1173 u8 vtag0_op; 1174 u16 vtag1_def; 1175 u8 vtag1_op; 1176 }; 1177 1178 struct npc_install_flow_rsp { 1179 struct mbox_msghdr hdr; 1180 int counter; /* negative if no counter else counter number */ 1181 }; 1182 1183 struct npc_delete_flow_req { 1184 struct mbox_msghdr hdr; 1185 u16 entry; 1186 u16 start;/*Disable range of entries */ 1187 u16 end; 1188 u8 all; /* PF + VFs */ 1189 }; 1190 1191 struct npc_mcam_read_entry_req { 1192 struct mbox_msghdr hdr; 1193 u16 entry; /* MCAM entry to read */ 1194 }; 1195 1196 struct npc_mcam_read_entry_rsp { 1197 struct mbox_msghdr hdr; 1198 struct mcam_entry entry_data; 1199 u8 intf; 1200 u8 enable; 1201 }; 1202 1203 struct npc_mcam_read_base_rule_rsp { 1204 struct mbox_msghdr hdr; 1205 struct mcam_entry entry; 1206 }; 1207 1208 struct npc_mcam_get_stats_req { 1209 struct mbox_msghdr hdr; 1210 u16 entry; /* mcam entry */ 1211 }; 1212 1213 struct npc_mcam_get_stats_rsp { 1214 struct mbox_msghdr hdr; 1215 u64 stat; /* counter stats */ 1216 u8 stat_ena; /* enabled */ 1217 }; 1218 1219 enum ptp_op { 1220 PTP_OP_ADJFINE = 0, 1221 PTP_OP_GET_CLOCK = 1, 1222 }; 1223 1224 struct ptp_req { 1225 struct mbox_msghdr hdr; 1226 u8 op; 1227 s64 scaled_ppm; 1228 }; 1229 1230 struct ptp_rsp { 1231 struct mbox_msghdr hdr; 1232 u64 clk; 1233 }; 1234 1235 struct set_vf_perm { 1236 struct mbox_msghdr hdr; 1237 u16 vf; 1238 #define RESET_VF_PERM BIT_ULL(0) 1239 #define VF_TRUSTED BIT_ULL(1) 1240 u64 flags; 1241 }; 1242 1243 /* CPT mailbox error codes 1244 * Range 901 - 1000. 1245 */ 1246 enum cpt_af_status { 1247 CPT_AF_ERR_PARAM = -901, 1248 CPT_AF_ERR_GRP_INVALID = -902, 1249 CPT_AF_ERR_LF_INVALID = -903, 1250 CPT_AF_ERR_ACCESS_DENIED = -904, 1251 CPT_AF_ERR_SSO_PF_FUNC_INVALID = -905, 1252 CPT_AF_ERR_NIX_PF_FUNC_INVALID = -906 1253 }; 1254 1255 /* CPT mbox message formats */ 1256 struct cpt_rd_wr_reg_msg { 1257 struct mbox_msghdr hdr; 1258 u64 reg_offset; 1259 u64 *ret_val; 1260 u64 val; 1261 u8 is_write; 1262 int blkaddr; 1263 }; 1264 1265 struct cpt_lf_alloc_req_msg { 1266 struct mbox_msghdr hdr; 1267 u16 nix_pf_func; 1268 u16 sso_pf_func; 1269 u16 eng_grpmsk; 1270 int blkaddr; 1271 }; 1272 1273 /* Mailbox message request and response format for CPT stats. */ 1274 struct cpt_sts_req { 1275 struct mbox_msghdr hdr; 1276 u8 blkaddr; 1277 }; 1278 1279 struct cpt_sts_rsp { 1280 struct mbox_msghdr hdr; 1281 u64 inst_req_pc; 1282 u64 inst_lat_pc; 1283 u64 rd_req_pc; 1284 u64 rd_lat_pc; 1285 u64 rd_uc_pc; 1286 u64 active_cycles_pc; 1287 u64 ctx_mis_pc; 1288 u64 ctx_hit_pc; 1289 u64 ctx_aop_pc; 1290 u64 ctx_aop_lat_pc; 1291 u64 ctx_ifetch_pc; 1292 u64 ctx_ifetch_lat_pc; 1293 u64 ctx_ffetch_pc; 1294 u64 ctx_ffetch_lat_pc; 1295 u64 ctx_wback_pc; 1296 u64 ctx_wback_lat_pc; 1297 u64 ctx_psh_pc; 1298 u64 ctx_psh_lat_pc; 1299 u64 ctx_err; 1300 u64 ctx_enc_id; 1301 u64 ctx_flush_timer; 1302 u64 rxc_time; 1303 u64 rxc_time_cfg; 1304 u64 rxc_active_sts; 1305 u64 rxc_zombie_sts; 1306 u64 busy_sts_ae; 1307 u64 free_sts_ae; 1308 u64 busy_sts_se; 1309 u64 free_sts_se; 1310 u64 busy_sts_ie; 1311 u64 free_sts_ie; 1312 u64 exe_err_info; 1313 u64 cptclk_cnt; 1314 u64 diag; 1315 u64 rxc_dfrg; 1316 u64 x2p_link_cfg0; 1317 u64 x2p_link_cfg1; 1318 }; 1319 1320 /* Mailbox message request format to configure reassembly timeout. */ 1321 struct cpt_rxc_time_cfg_req { 1322 struct mbox_msghdr hdr; 1323 int blkaddr; 1324 u32 step; 1325 u16 zombie_thres; 1326 u16 zombie_limit; 1327 u16 active_thres; 1328 u16 active_limit; 1329 }; 1330 1331 #endif /* MBOX_H */ 1332