1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Marvell OcteonTx2 RVU Admin Function driver 3 * 4 * Copyright (C) 2018 Marvell International Ltd. 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 */ 10 11 #ifndef MBOX_H 12 #define MBOX_H 13 14 #include <linux/etherdevice.h> 15 #include <linux/sizes.h> 16 17 #include "rvu_struct.h" 18 #include "common.h" 19 20 #define MBOX_SIZE SZ_64K 21 22 /* AF/PF: PF initiated, PF/VF VF initiated */ 23 #define MBOX_DOWN_RX_START 0 24 #define MBOX_DOWN_RX_SIZE (46 * SZ_1K) 25 #define MBOX_DOWN_TX_START (MBOX_DOWN_RX_START + MBOX_DOWN_RX_SIZE) 26 #define MBOX_DOWN_TX_SIZE (16 * SZ_1K) 27 /* AF/PF: AF initiated, PF/VF PF initiated */ 28 #define MBOX_UP_RX_START (MBOX_DOWN_TX_START + MBOX_DOWN_TX_SIZE) 29 #define MBOX_UP_RX_SIZE SZ_1K 30 #define MBOX_UP_TX_START (MBOX_UP_RX_START + MBOX_UP_RX_SIZE) 31 #define MBOX_UP_TX_SIZE SZ_1K 32 33 #if MBOX_UP_TX_SIZE + MBOX_UP_TX_START != MBOX_SIZE 34 # error "incorrect mailbox area sizes" 35 #endif 36 37 #define INTR_MASK(pfvfs) ((pfvfs < 64) ? (BIT_ULL(pfvfs) - 1) : (~0ull)) 38 39 #define MBOX_RSP_TIMEOUT 3000 /* Time(ms) to wait for mbox response */ 40 41 #define MBOX_MSG_ALIGN 16 /* Align mbox msg start to 16bytes */ 42 43 /* Mailbox directions */ 44 #define MBOX_DIR_AFPF 0 /* AF replies to PF */ 45 #define MBOX_DIR_PFAF 1 /* PF sends messages to AF */ 46 #define MBOX_DIR_PFVF 2 /* PF replies to VF */ 47 #define MBOX_DIR_VFPF 3 /* VF sends messages to PF */ 48 #define MBOX_DIR_AFPF_UP 4 /* AF sends messages to PF */ 49 #define MBOX_DIR_PFAF_UP 5 /* PF replies to AF */ 50 #define MBOX_DIR_PFVF_UP 6 /* PF sends messages to VF */ 51 #define MBOX_DIR_VFPF_UP 7 /* VF replies to PF */ 52 53 struct otx2_mbox_dev { 54 void *mbase; /* This dev's mbox region */ 55 void *hwbase; 56 spinlock_t mbox_lock; 57 u16 msg_size; /* Total msg size to be sent */ 58 u16 rsp_size; /* Total rsp size to be sure the reply is ok */ 59 u16 num_msgs; /* No of msgs sent or waiting for response */ 60 u16 msgs_acked; /* No of msgs for which response is received */ 61 }; 62 63 struct otx2_mbox { 64 struct pci_dev *pdev; 65 void *hwbase; /* Mbox region advertised by HW */ 66 void *reg_base;/* CSR base for this dev */ 67 u64 trigger; /* Trigger mbox notification */ 68 u16 tr_shift; /* Mbox trigger shift */ 69 u64 rx_start; /* Offset of Rx region in mbox memory */ 70 u64 tx_start; /* Offset of Tx region in mbox memory */ 71 u16 rx_size; /* Size of Rx region */ 72 u16 tx_size; /* Size of Tx region */ 73 u16 ndevs; /* The number of peers */ 74 struct otx2_mbox_dev *dev; 75 }; 76 77 /* Header which precedes all mbox messages */ 78 struct mbox_hdr { 79 u64 msg_size; /* Total msgs size embedded */ 80 u16 num_msgs; /* No of msgs embedded */ 81 }; 82 83 /* Header which precedes every msg and is also part of it */ 84 struct mbox_msghdr { 85 u16 pcifunc; /* Who's sending this msg */ 86 u16 id; /* Mbox message ID */ 87 #define OTX2_MBOX_REQ_SIG (0xdead) 88 #define OTX2_MBOX_RSP_SIG (0xbeef) 89 u16 sig; /* Signature, for validating corrupted msgs */ 90 #define OTX2_MBOX_VERSION (0x0009) 91 u16 ver; /* Version of msg's structure for this ID */ 92 u16 next_msgoff; /* Offset of next msg within mailbox region */ 93 int rc; /* Msg process'ed response code */ 94 }; 95 96 void otx2_mbox_reset(struct otx2_mbox *mbox, int devid); 97 void __otx2_mbox_reset(struct otx2_mbox *mbox, int devid); 98 void otx2_mbox_destroy(struct otx2_mbox *mbox); 99 int otx2_mbox_init(struct otx2_mbox *mbox, void __force *hwbase, 100 struct pci_dev *pdev, void __force *reg_base, 101 int direction, int ndevs); 102 int otx2_mbox_regions_init(struct otx2_mbox *mbox, void __force **hwbase, 103 struct pci_dev *pdev, void __force *reg_base, 104 int direction, int ndevs); 105 void otx2_mbox_msg_send(struct otx2_mbox *mbox, int devid); 106 int otx2_mbox_wait_for_rsp(struct otx2_mbox *mbox, int devid); 107 int otx2_mbox_busy_poll_for_rsp(struct otx2_mbox *mbox, int devid); 108 struct mbox_msghdr *otx2_mbox_alloc_msg_rsp(struct otx2_mbox *mbox, int devid, 109 int size, int size_rsp); 110 struct mbox_msghdr *otx2_mbox_get_rsp(struct otx2_mbox *mbox, int devid, 111 struct mbox_msghdr *msg); 112 int otx2_mbox_check_rsp_msgs(struct otx2_mbox *mbox, int devid); 113 int otx2_reply_invalid_msg(struct otx2_mbox *mbox, int devid, 114 u16 pcifunc, u16 id); 115 bool otx2_mbox_nonempty(struct otx2_mbox *mbox, int devid); 116 const char *otx2_mbox_id2name(u16 id); 117 static inline struct mbox_msghdr *otx2_mbox_alloc_msg(struct otx2_mbox *mbox, 118 int devid, int size) 119 { 120 return otx2_mbox_alloc_msg_rsp(mbox, devid, size, 0); 121 } 122 123 /* Mailbox message types */ 124 #define MBOX_MSG_MASK 0xFFFF 125 #define MBOX_MSG_INVALID 0xFFFE 126 #define MBOX_MSG_MAX 0xFFFF 127 128 #define MBOX_MESSAGES \ 129 /* Generic mbox IDs (range 0x000 - 0x1FF) */ \ 130 M(READY, 0x001, ready, msg_req, ready_msg_rsp) \ 131 M(ATTACH_RESOURCES, 0x002, attach_resources, rsrc_attach, msg_rsp) \ 132 M(DETACH_RESOURCES, 0x003, detach_resources, rsrc_detach, msg_rsp) \ 133 M(FREE_RSRC_CNT, 0x004, free_rsrc_cnt, msg_req, free_rsrcs_rsp) \ 134 M(MSIX_OFFSET, 0x005, msix_offset, msg_req, msix_offset_rsp) \ 135 M(VF_FLR, 0x006, vf_flr, msg_req, msg_rsp) \ 136 M(PTP_OP, 0x007, ptp_op, ptp_req, ptp_rsp) \ 137 M(GET_HW_CAP, 0x008, get_hw_cap, msg_req, get_hw_cap_rsp) \ 138 M(LMTST_TBL_SETUP, 0x00a, lmtst_tbl_setup, lmtst_tbl_setup_req, \ 139 msg_rsp) \ 140 M(SET_VF_PERM, 0x00b, set_vf_perm, set_vf_perm, msg_rsp) \ 141 /* CGX mbox IDs (range 0x200 - 0x3FF) */ \ 142 M(CGX_START_RXTX, 0x200, cgx_start_rxtx, msg_req, msg_rsp) \ 143 M(CGX_STOP_RXTX, 0x201, cgx_stop_rxtx, msg_req, msg_rsp) \ 144 M(CGX_STATS, 0x202, cgx_stats, msg_req, cgx_stats_rsp) \ 145 M(CGX_MAC_ADDR_SET, 0x203, cgx_mac_addr_set, cgx_mac_addr_set_or_get, \ 146 cgx_mac_addr_set_or_get) \ 147 M(CGX_MAC_ADDR_GET, 0x204, cgx_mac_addr_get, cgx_mac_addr_set_or_get, \ 148 cgx_mac_addr_set_or_get) \ 149 M(CGX_PROMISC_ENABLE, 0x205, cgx_promisc_enable, msg_req, msg_rsp) \ 150 M(CGX_PROMISC_DISABLE, 0x206, cgx_promisc_disable, msg_req, msg_rsp) \ 151 M(CGX_START_LINKEVENTS, 0x207, cgx_start_linkevents, msg_req, msg_rsp) \ 152 M(CGX_STOP_LINKEVENTS, 0x208, cgx_stop_linkevents, msg_req, msg_rsp) \ 153 M(CGX_GET_LINKINFO, 0x209, cgx_get_linkinfo, msg_req, cgx_link_info_msg) \ 154 M(CGX_INTLBK_ENABLE, 0x20A, cgx_intlbk_enable, msg_req, msg_rsp) \ 155 M(CGX_INTLBK_DISABLE, 0x20B, cgx_intlbk_disable, msg_req, msg_rsp) \ 156 M(CGX_PTP_RX_ENABLE, 0x20C, cgx_ptp_rx_enable, msg_req, msg_rsp) \ 157 M(CGX_PTP_RX_DISABLE, 0x20D, cgx_ptp_rx_disable, msg_req, msg_rsp) \ 158 M(CGX_CFG_PAUSE_FRM, 0x20E, cgx_cfg_pause_frm, cgx_pause_frm_cfg, \ 159 cgx_pause_frm_cfg) \ 160 M(CGX_FEC_SET, 0x210, cgx_set_fec_param, fec_mode, fec_mode) \ 161 M(CGX_FEC_STATS, 0x211, cgx_fec_stats, msg_req, cgx_fec_stats_rsp) \ 162 M(CGX_GET_PHY_FEC_STATS, 0x212, cgx_get_phy_fec_stats, msg_req, msg_rsp) \ 163 M(CGX_FW_DATA_GET, 0x213, cgx_get_aux_link_info, msg_req, cgx_fw_data) \ 164 M(CGX_SET_LINK_MODE, 0x214, cgx_set_link_mode, cgx_set_link_mode_req,\ 165 cgx_set_link_mode_rsp) \ 166 M(CGX_FEATURES_GET, 0x215, cgx_features_get, msg_req, \ 167 cgx_features_info_msg) \ 168 M(RPM_STATS, 0x216, rpm_stats, msg_req, rpm_stats_rsp) \ 169 M(CGX_MAC_ADDR_ADD, 0x217, cgx_mac_addr_add, cgx_mac_addr_add_req, \ 170 cgx_mac_addr_add_rsp) \ 171 M(CGX_MAC_ADDR_DEL, 0x218, cgx_mac_addr_del, cgx_mac_addr_del_req, \ 172 msg_rsp) \ 173 M(CGX_MAC_MAX_ENTRIES_GET, 0x219, cgx_mac_max_entries_get, msg_req, \ 174 cgx_max_dmac_entries_get_rsp) \ 175 M(CGX_MAC_ADDR_RESET, 0x21A, cgx_mac_addr_reset, msg_req, msg_rsp) \ 176 M(CGX_MAC_ADDR_UPDATE, 0x21B, cgx_mac_addr_update, cgx_mac_addr_update_req, \ 177 msg_rsp) \ 178 /* NPA mbox IDs (range 0x400 - 0x5FF) */ \ 179 M(NPA_LF_ALLOC, 0x400, npa_lf_alloc, \ 180 npa_lf_alloc_req, npa_lf_alloc_rsp) \ 181 M(NPA_LF_FREE, 0x401, npa_lf_free, msg_req, msg_rsp) \ 182 M(NPA_AQ_ENQ, 0x402, npa_aq_enq, npa_aq_enq_req, npa_aq_enq_rsp) \ 183 M(NPA_HWCTX_DISABLE, 0x403, npa_hwctx_disable, hwctx_disable_req, msg_rsp)\ 184 /* SSO/SSOW mbox IDs (range 0x600 - 0x7FF) */ \ 185 /* TIM mbox IDs (range 0x800 - 0x9FF) */ \ 186 /* CPT mbox IDs (range 0xA00 - 0xBFF) */ \ 187 M(CPT_LF_ALLOC, 0xA00, cpt_lf_alloc, cpt_lf_alloc_req_msg, \ 188 msg_rsp) \ 189 M(CPT_LF_FREE, 0xA01, cpt_lf_free, msg_req, msg_rsp) \ 190 M(CPT_RD_WR_REGISTER, 0xA02, cpt_rd_wr_register, cpt_rd_wr_reg_msg, \ 191 cpt_rd_wr_reg_msg) \ 192 M(CPT_STATS, 0xA05, cpt_sts, cpt_sts_req, cpt_sts_rsp) \ 193 M(CPT_RXC_TIME_CFG, 0xA06, cpt_rxc_time_cfg, cpt_rxc_time_cfg_req, \ 194 msg_rsp) \ 195 /* SDP mbox IDs (range 0x1000 - 0x11FF) */ \ 196 M(SET_SDP_CHAN_INFO, 0x1000, set_sdp_chan_info, sdp_chan_info_msg, msg_rsp) \ 197 M(GET_SDP_CHAN_INFO, 0x1001, get_sdp_chan_info, msg_req, sdp_get_chan_info_msg) \ 198 /* NPC mbox IDs (range 0x6000 - 0x7FFF) */ \ 199 M(NPC_MCAM_ALLOC_ENTRY, 0x6000, npc_mcam_alloc_entry, npc_mcam_alloc_entry_req,\ 200 npc_mcam_alloc_entry_rsp) \ 201 M(NPC_MCAM_FREE_ENTRY, 0x6001, npc_mcam_free_entry, \ 202 npc_mcam_free_entry_req, msg_rsp) \ 203 M(NPC_MCAM_WRITE_ENTRY, 0x6002, npc_mcam_write_entry, \ 204 npc_mcam_write_entry_req, msg_rsp) \ 205 M(NPC_MCAM_ENA_ENTRY, 0x6003, npc_mcam_ena_entry, \ 206 npc_mcam_ena_dis_entry_req, msg_rsp) \ 207 M(NPC_MCAM_DIS_ENTRY, 0x6004, npc_mcam_dis_entry, \ 208 npc_mcam_ena_dis_entry_req, msg_rsp) \ 209 M(NPC_MCAM_SHIFT_ENTRY, 0x6005, npc_mcam_shift_entry, npc_mcam_shift_entry_req,\ 210 npc_mcam_shift_entry_rsp) \ 211 M(NPC_MCAM_ALLOC_COUNTER, 0x6006, npc_mcam_alloc_counter, \ 212 npc_mcam_alloc_counter_req, \ 213 npc_mcam_alloc_counter_rsp) \ 214 M(NPC_MCAM_FREE_COUNTER, 0x6007, npc_mcam_free_counter, \ 215 npc_mcam_oper_counter_req, msg_rsp) \ 216 M(NPC_MCAM_UNMAP_COUNTER, 0x6008, npc_mcam_unmap_counter, \ 217 npc_mcam_unmap_counter_req, msg_rsp) \ 218 M(NPC_MCAM_CLEAR_COUNTER, 0x6009, npc_mcam_clear_counter, \ 219 npc_mcam_oper_counter_req, msg_rsp) \ 220 M(NPC_MCAM_COUNTER_STATS, 0x600a, npc_mcam_counter_stats, \ 221 npc_mcam_oper_counter_req, \ 222 npc_mcam_oper_counter_rsp) \ 223 M(NPC_MCAM_ALLOC_AND_WRITE_ENTRY, 0x600b, npc_mcam_alloc_and_write_entry, \ 224 npc_mcam_alloc_and_write_entry_req, \ 225 npc_mcam_alloc_and_write_entry_rsp) \ 226 M(NPC_GET_KEX_CFG, 0x600c, npc_get_kex_cfg, \ 227 msg_req, npc_get_kex_cfg_rsp) \ 228 M(NPC_INSTALL_FLOW, 0x600d, npc_install_flow, \ 229 npc_install_flow_req, npc_install_flow_rsp) \ 230 M(NPC_DELETE_FLOW, 0x600e, npc_delete_flow, \ 231 npc_delete_flow_req, msg_rsp) \ 232 M(NPC_MCAM_READ_ENTRY, 0x600f, npc_mcam_read_entry, \ 233 npc_mcam_read_entry_req, \ 234 npc_mcam_read_entry_rsp) \ 235 M(NPC_MCAM_READ_BASE_RULE, 0x6011, npc_read_base_steer_rule, \ 236 msg_req, npc_mcam_read_base_rule_rsp) \ 237 M(NPC_MCAM_GET_STATS, 0x6012, npc_mcam_entry_stats, \ 238 npc_mcam_get_stats_req, \ 239 npc_mcam_get_stats_rsp) \ 240 /* NIX mbox IDs (range 0x8000 - 0xFFFF) */ \ 241 M(NIX_LF_ALLOC, 0x8000, nix_lf_alloc, \ 242 nix_lf_alloc_req, nix_lf_alloc_rsp) \ 243 M(NIX_LF_FREE, 0x8001, nix_lf_free, nix_lf_free_req, msg_rsp) \ 244 M(NIX_AQ_ENQ, 0x8002, nix_aq_enq, nix_aq_enq_req, nix_aq_enq_rsp) \ 245 M(NIX_HWCTX_DISABLE, 0x8003, nix_hwctx_disable, \ 246 hwctx_disable_req, msg_rsp) \ 247 M(NIX_TXSCH_ALLOC, 0x8004, nix_txsch_alloc, \ 248 nix_txsch_alloc_req, nix_txsch_alloc_rsp) \ 249 M(NIX_TXSCH_FREE, 0x8005, nix_txsch_free, nix_txsch_free_req, msg_rsp) \ 250 M(NIX_TXSCHQ_CFG, 0x8006, nix_txschq_cfg, nix_txschq_config, \ 251 nix_txschq_config) \ 252 M(NIX_STATS_RST, 0x8007, nix_stats_rst, msg_req, msg_rsp) \ 253 M(NIX_VTAG_CFG, 0x8008, nix_vtag_cfg, nix_vtag_config, \ 254 nix_vtag_config_rsp) \ 255 M(NIX_RSS_FLOWKEY_CFG, 0x8009, nix_rss_flowkey_cfg, \ 256 nix_rss_flowkey_cfg, \ 257 nix_rss_flowkey_cfg_rsp) \ 258 M(NIX_SET_MAC_ADDR, 0x800a, nix_set_mac_addr, nix_set_mac_addr, msg_rsp) \ 259 M(NIX_SET_RX_MODE, 0x800b, nix_set_rx_mode, nix_rx_mode, msg_rsp) \ 260 M(NIX_SET_HW_FRS, 0x800c, nix_set_hw_frs, nix_frs_cfg, msg_rsp) \ 261 M(NIX_LF_START_RX, 0x800d, nix_lf_start_rx, msg_req, msg_rsp) \ 262 M(NIX_LF_STOP_RX, 0x800e, nix_lf_stop_rx, msg_req, msg_rsp) \ 263 M(NIX_MARK_FORMAT_CFG, 0x800f, nix_mark_format_cfg, \ 264 nix_mark_format_cfg, \ 265 nix_mark_format_cfg_rsp) \ 266 M(NIX_SET_RX_CFG, 0x8010, nix_set_rx_cfg, nix_rx_cfg, msg_rsp) \ 267 M(NIX_LSO_FORMAT_CFG, 0x8011, nix_lso_format_cfg, \ 268 nix_lso_format_cfg, \ 269 nix_lso_format_cfg_rsp) \ 270 M(NIX_LF_PTP_TX_ENABLE, 0x8013, nix_lf_ptp_tx_enable, msg_req, msg_rsp) \ 271 M(NIX_LF_PTP_TX_DISABLE, 0x8014, nix_lf_ptp_tx_disable, msg_req, msg_rsp) \ 272 M(NIX_BP_ENABLE, 0x8016, nix_bp_enable, nix_bp_cfg_req, \ 273 nix_bp_cfg_rsp) \ 274 M(NIX_BP_DISABLE, 0x8017, nix_bp_disable, nix_bp_cfg_req, msg_rsp) \ 275 M(NIX_GET_MAC_ADDR, 0x8018, nix_get_mac_addr, msg_req, nix_get_mac_addr_rsp) \ 276 M(NIX_CN10K_AQ_ENQ, 0x8019, nix_cn10k_aq_enq, nix_cn10k_aq_enq_req, \ 277 nix_cn10k_aq_enq_rsp) \ 278 M(NIX_GET_HW_INFO, 0x801c, nix_get_hw_info, msg_req, nix_hw_info) \ 279 M(NIX_BANDPROF_ALLOC, 0x801d, nix_bandprof_alloc, nix_bandprof_alloc_req, \ 280 nix_bandprof_alloc_rsp) \ 281 M(NIX_BANDPROF_FREE, 0x801e, nix_bandprof_free, nix_bandprof_free_req, \ 282 msg_rsp) \ 283 M(NIX_BANDPROF_GET_HWINFO, 0x801f, nix_bandprof_get_hwinfo, msg_req, \ 284 nix_bandprof_get_hwinfo_rsp) 285 286 /* Messages initiated by AF (range 0xC00 - 0xDFF) */ 287 #define MBOX_UP_CGX_MESSAGES \ 288 M(CGX_LINK_EVENT, 0xC00, cgx_link_event, cgx_link_info_msg, msg_rsp) 289 290 enum { 291 #define M(_name, _id, _1, _2, _3) MBOX_MSG_ ## _name = _id, 292 MBOX_MESSAGES 293 MBOX_UP_CGX_MESSAGES 294 #undef M 295 }; 296 297 /* Mailbox message formats */ 298 299 #define RVU_DEFAULT_PF_FUNC 0xFFFF 300 301 /* Generic request msg used for those mbox messages which 302 * don't send any data in the request. 303 */ 304 struct msg_req { 305 struct mbox_msghdr hdr; 306 }; 307 308 /* Generic response msg used an ack or response for those mbox 309 * messages which don't have a specific rsp msg format. 310 */ 311 struct msg_rsp { 312 struct mbox_msghdr hdr; 313 }; 314 315 /* RVU mailbox error codes 316 * Range 256 - 300. 317 */ 318 enum rvu_af_status { 319 RVU_INVALID_VF_ID = -256, 320 }; 321 322 struct ready_msg_rsp { 323 struct mbox_msghdr hdr; 324 u16 sclk_freq; /* SCLK frequency (in MHz) */ 325 u16 rclk_freq; /* RCLK frequency (in MHz) */ 326 }; 327 328 /* Structure for requesting resource provisioning. 329 * 'modify' flag to be used when either requesting more 330 * or to detach partial of a certain resource type. 331 * Rest of the fields specify how many of what type to 332 * be attached. 333 * To request LFs from two blocks of same type this mailbox 334 * can be sent twice as below: 335 * struct rsrc_attach *attach; 336 * .. Allocate memory for message .. 337 * attach->cptlfs = 3; <3 LFs from CPT0> 338 * .. Send message .. 339 * .. Allocate memory for message .. 340 * attach->modify = 1; 341 * attach->cpt_blkaddr = BLKADDR_CPT1; 342 * attach->cptlfs = 2; <2 LFs from CPT1> 343 * .. Send message .. 344 */ 345 struct rsrc_attach { 346 struct mbox_msghdr hdr; 347 u8 modify:1; 348 u8 npalf:1; 349 u8 nixlf:1; 350 u16 sso; 351 u16 ssow; 352 u16 timlfs; 353 u16 cptlfs; 354 int cpt_blkaddr; /* BLKADDR_CPT0/BLKADDR_CPT1 or 0 for BLKADDR_CPT0 */ 355 }; 356 357 /* Structure for relinquishing resources. 358 * 'partial' flag to be used when relinquishing all resources 359 * but only of a certain type. If not set, all resources of all 360 * types provisioned to the RVU function will be detached. 361 */ 362 struct rsrc_detach { 363 struct mbox_msghdr hdr; 364 u8 partial:1; 365 u8 npalf:1; 366 u8 nixlf:1; 367 u8 sso:1; 368 u8 ssow:1; 369 u8 timlfs:1; 370 u8 cptlfs:1; 371 }; 372 373 /* Number of resources available to the caller. 374 * In reply to MBOX_MSG_FREE_RSRC_CNT. 375 */ 376 struct free_rsrcs_rsp { 377 struct mbox_msghdr hdr; 378 u16 schq[NIX_TXSCH_LVL_CNT]; 379 u16 sso; 380 u16 tim; 381 u16 ssow; 382 u16 cpt; 383 u8 npa; 384 u8 nix; 385 u16 schq_nix1[NIX_TXSCH_LVL_CNT]; 386 u8 nix1; 387 u8 cpt1; 388 u8 ree0; 389 u8 ree1; 390 }; 391 392 #define MSIX_VECTOR_INVALID 0xFFFF 393 #define MAX_RVU_BLKLF_CNT 256 394 395 struct msix_offset_rsp { 396 struct mbox_msghdr hdr; 397 u16 npa_msixoff; 398 u16 nix_msixoff; 399 u16 sso; 400 u16 ssow; 401 u16 timlfs; 402 u16 cptlfs; 403 u16 sso_msixoff[MAX_RVU_BLKLF_CNT]; 404 u16 ssow_msixoff[MAX_RVU_BLKLF_CNT]; 405 u16 timlf_msixoff[MAX_RVU_BLKLF_CNT]; 406 u16 cptlf_msixoff[MAX_RVU_BLKLF_CNT]; 407 u16 cpt1_lfs; 408 u16 ree0_lfs; 409 u16 ree1_lfs; 410 u16 cpt1_lf_msixoff[MAX_RVU_BLKLF_CNT]; 411 u16 ree0_lf_msixoff[MAX_RVU_BLKLF_CNT]; 412 u16 ree1_lf_msixoff[MAX_RVU_BLKLF_CNT]; 413 }; 414 415 struct get_hw_cap_rsp { 416 struct mbox_msghdr hdr; 417 u8 nix_fixed_txschq_mapping; /* Schq mapping fixed or flexible */ 418 u8 nix_shaping; /* Is shaping and coloring supported */ 419 }; 420 421 /* CGX mbox message formats */ 422 423 struct cgx_stats_rsp { 424 struct mbox_msghdr hdr; 425 #define CGX_RX_STATS_COUNT 9 426 #define CGX_TX_STATS_COUNT 18 427 u64 rx_stats[CGX_RX_STATS_COUNT]; 428 u64 tx_stats[CGX_TX_STATS_COUNT]; 429 }; 430 431 struct cgx_fec_stats_rsp { 432 struct mbox_msghdr hdr; 433 u64 fec_corr_blks; 434 u64 fec_uncorr_blks; 435 }; 436 /* Structure for requesting the operation for 437 * setting/getting mac address in the CGX interface 438 */ 439 struct cgx_mac_addr_set_or_get { 440 struct mbox_msghdr hdr; 441 u8 mac_addr[ETH_ALEN]; 442 }; 443 444 /* Structure for requesting the operation to 445 * add DMAC filter entry into CGX interface 446 */ 447 struct cgx_mac_addr_add_req { 448 struct mbox_msghdr hdr; 449 u8 mac_addr[ETH_ALEN]; 450 }; 451 452 /* Structure for response against the operation to 453 * add DMAC filter entry into CGX interface 454 */ 455 struct cgx_mac_addr_add_rsp { 456 struct mbox_msghdr hdr; 457 u8 index; 458 }; 459 460 /* Structure for requesting the operation to 461 * delete DMAC filter entry from CGX interface 462 */ 463 struct cgx_mac_addr_del_req { 464 struct mbox_msghdr hdr; 465 u8 index; 466 }; 467 468 /* Structure for response against the operation to 469 * get maximum supported DMAC filter entries 470 */ 471 struct cgx_max_dmac_entries_get_rsp { 472 struct mbox_msghdr hdr; 473 u8 max_dmac_filters; 474 }; 475 476 struct cgx_link_user_info { 477 uint64_t link_up:1; 478 uint64_t full_duplex:1; 479 uint64_t lmac_type_id:4; 480 uint64_t speed:20; /* speed in Mbps */ 481 uint64_t an:1; /* AN supported or not */ 482 uint64_t fec:2; /* FEC type if enabled else 0 */ 483 #define LMACTYPE_STR_LEN 16 484 char lmac_type[LMACTYPE_STR_LEN]; 485 }; 486 487 struct cgx_link_info_msg { 488 struct mbox_msghdr hdr; 489 struct cgx_link_user_info link_info; 490 }; 491 492 struct cgx_pause_frm_cfg { 493 struct mbox_msghdr hdr; 494 u8 set; 495 /* set = 1 if the request is to config pause frames */ 496 /* set = 0 if the request is to fetch pause frames config */ 497 u8 rx_pause; 498 u8 tx_pause; 499 }; 500 501 enum fec_type { 502 OTX2_FEC_NONE, 503 OTX2_FEC_BASER, 504 OTX2_FEC_RS, 505 OTX2_FEC_STATS_CNT = 2, 506 OTX2_FEC_OFF, 507 }; 508 509 struct fec_mode { 510 struct mbox_msghdr hdr; 511 int fec; 512 }; 513 514 struct sfp_eeprom_s { 515 #define SFP_EEPROM_SIZE 256 516 u16 sff_id; 517 u8 buf[SFP_EEPROM_SIZE]; 518 u64 reserved; 519 }; 520 521 struct phy_s { 522 struct { 523 u64 can_change_mod_type:1; 524 u64 mod_type:1; 525 u64 has_fec_stats:1; 526 } misc; 527 struct fec_stats_s { 528 u32 rsfec_corr_cws; 529 u32 rsfec_uncorr_cws; 530 u32 brfec_corr_blks; 531 u32 brfec_uncorr_blks; 532 } fec_stats; 533 }; 534 535 struct cgx_lmac_fwdata_s { 536 u16 rw_valid; 537 u64 supported_fec; 538 u64 supported_an; 539 u64 supported_link_modes; 540 /* only applicable if AN is supported */ 541 u64 advertised_fec; 542 u64 advertised_link_modes; 543 /* Only applicable if SFP/QSFP slot is present */ 544 struct sfp_eeprom_s sfp_eeprom; 545 struct phy_s phy; 546 #define LMAC_FWDATA_RESERVED_MEM 1021 547 u64 reserved[LMAC_FWDATA_RESERVED_MEM]; 548 }; 549 550 struct cgx_fw_data { 551 struct mbox_msghdr hdr; 552 struct cgx_lmac_fwdata_s fwdata; 553 }; 554 555 struct cgx_set_link_mode_args { 556 u32 speed; 557 u8 duplex; 558 u8 an; 559 u8 ports; 560 u64 mode; 561 }; 562 563 struct cgx_set_link_mode_req { 564 #define AUTONEG_UNKNOWN 0xff 565 struct mbox_msghdr hdr; 566 struct cgx_set_link_mode_args args; 567 }; 568 569 struct cgx_set_link_mode_rsp { 570 struct mbox_msghdr hdr; 571 int status; 572 }; 573 574 struct cgx_mac_addr_update_req { 575 struct mbox_msghdr hdr; 576 u8 mac_addr[ETH_ALEN]; 577 u8 index; 578 }; 579 580 #define RVU_LMAC_FEAT_FC BIT_ULL(0) /* pause frames */ 581 #define RVU_LMAC_FEAT_PTP BIT_ULL(1) /* precision time protocol */ 582 #define RVU_MAC_VERSION BIT_ULL(2) 583 #define RVU_MAC_CGX BIT_ULL(3) 584 #define RVU_MAC_RPM BIT_ULL(4) 585 586 struct cgx_features_info_msg { 587 struct mbox_msghdr hdr; 588 u64 lmac_features; 589 }; 590 591 struct rpm_stats_rsp { 592 struct mbox_msghdr hdr; 593 #define RPM_RX_STATS_COUNT 43 594 #define RPM_TX_STATS_COUNT 34 595 u64 rx_stats[RPM_RX_STATS_COUNT]; 596 u64 tx_stats[RPM_TX_STATS_COUNT]; 597 }; 598 599 /* NPA mbox message formats */ 600 601 /* NPA mailbox error codes 602 * Range 301 - 400. 603 */ 604 enum npa_af_status { 605 NPA_AF_ERR_PARAM = -301, 606 NPA_AF_ERR_AQ_FULL = -302, 607 NPA_AF_ERR_AQ_ENQUEUE = -303, 608 NPA_AF_ERR_AF_LF_INVALID = -304, 609 NPA_AF_ERR_AF_LF_ALLOC = -305, 610 NPA_AF_ERR_LF_RESET = -306, 611 }; 612 613 /* For NPA LF context alloc and init */ 614 struct npa_lf_alloc_req { 615 struct mbox_msghdr hdr; 616 int node; 617 int aura_sz; /* No of auras */ 618 u32 nr_pools; /* No of pools */ 619 u64 way_mask; 620 }; 621 622 struct npa_lf_alloc_rsp { 623 struct mbox_msghdr hdr; 624 u32 stack_pg_ptrs; /* No of ptrs per stack page */ 625 u32 stack_pg_bytes; /* Size of stack page */ 626 u16 qints; /* NPA_AF_CONST::QINTS */ 627 u8 cache_lines; /*BATCH ALLOC DMA */ 628 }; 629 630 /* NPA AQ enqueue msg */ 631 struct npa_aq_enq_req { 632 struct mbox_msghdr hdr; 633 u32 aura_id; 634 u8 ctype; 635 u8 op; 636 union { 637 /* Valid when op == WRITE/INIT and ctype == AURA. 638 * LF fills the pool_id in aura.pool_addr. AF will translate 639 * the pool_id to pool context pointer. 640 */ 641 struct npa_aura_s aura; 642 /* Valid when op == WRITE/INIT and ctype == POOL */ 643 struct npa_pool_s pool; 644 }; 645 /* Mask data when op == WRITE (1=write, 0=don't write) */ 646 union { 647 /* Valid when op == WRITE and ctype == AURA */ 648 struct npa_aura_s aura_mask; 649 /* Valid when op == WRITE and ctype == POOL */ 650 struct npa_pool_s pool_mask; 651 }; 652 }; 653 654 struct npa_aq_enq_rsp { 655 struct mbox_msghdr hdr; 656 union { 657 /* Valid when op == READ and ctype == AURA */ 658 struct npa_aura_s aura; 659 /* Valid when op == READ and ctype == POOL */ 660 struct npa_pool_s pool; 661 }; 662 }; 663 664 /* Disable all contexts of type 'ctype' */ 665 struct hwctx_disable_req { 666 struct mbox_msghdr hdr; 667 u8 ctype; 668 }; 669 670 /* NIX mbox message formats */ 671 672 /* NIX mailbox error codes 673 * Range 401 - 500. 674 */ 675 enum nix_af_status { 676 NIX_AF_ERR_PARAM = -401, 677 NIX_AF_ERR_AQ_FULL = -402, 678 NIX_AF_ERR_AQ_ENQUEUE = -403, 679 NIX_AF_ERR_AF_LF_INVALID = -404, 680 NIX_AF_ERR_AF_LF_ALLOC = -405, 681 NIX_AF_ERR_TLX_ALLOC_FAIL = -406, 682 NIX_AF_ERR_TLX_INVALID = -407, 683 NIX_AF_ERR_RSS_SIZE_INVALID = -408, 684 NIX_AF_ERR_RSS_GRPS_INVALID = -409, 685 NIX_AF_ERR_FRS_INVALID = -410, 686 NIX_AF_ERR_RX_LINK_INVALID = -411, 687 NIX_AF_INVAL_TXSCHQ_CFG = -412, 688 NIX_AF_SMQ_FLUSH_FAILED = -413, 689 NIX_AF_ERR_LF_RESET = -414, 690 NIX_AF_ERR_RSS_NOSPC_FIELD = -415, 691 NIX_AF_ERR_RSS_NOSPC_ALGO = -416, 692 NIX_AF_ERR_MARK_CFG_FAIL = -417, 693 NIX_AF_ERR_LSO_CFG_FAIL = -418, 694 NIX_AF_INVAL_NPA_PF_FUNC = -419, 695 NIX_AF_INVAL_SSO_PF_FUNC = -420, 696 NIX_AF_ERR_TX_VTAG_NOSPC = -421, 697 NIX_AF_ERR_RX_VTAG_INUSE = -422, 698 NIX_AF_ERR_PTP_CONFIG_FAIL = -423, 699 NIX_AF_ERR_NPC_KEY_NOT_SUPP = -424, 700 NIX_AF_ERR_INVALID_NIXBLK = -425, 701 NIX_AF_ERR_INVALID_BANDPROF = -426, 702 NIX_AF_ERR_IPOLICER_NOTSUPP = -427, 703 NIX_AF_ERR_BANDPROF_INVAL_REQ = -428, 704 }; 705 706 /* For NIX RX vtag action */ 707 enum nix_rx_vtag0_type { 708 NIX_AF_LFX_RX_VTAG_TYPE0, /* reserved for rx vlan offload */ 709 NIX_AF_LFX_RX_VTAG_TYPE1, 710 NIX_AF_LFX_RX_VTAG_TYPE2, 711 NIX_AF_LFX_RX_VTAG_TYPE3, 712 NIX_AF_LFX_RX_VTAG_TYPE4, 713 NIX_AF_LFX_RX_VTAG_TYPE5, 714 NIX_AF_LFX_RX_VTAG_TYPE6, 715 NIX_AF_LFX_RX_VTAG_TYPE7, 716 }; 717 718 /* For NIX LF context alloc and init */ 719 struct nix_lf_alloc_req { 720 struct mbox_msghdr hdr; 721 int node; 722 u32 rq_cnt; /* No of receive queues */ 723 u32 sq_cnt; /* No of send queues */ 724 u32 cq_cnt; /* No of completion queues */ 725 u8 xqe_sz; 726 u16 rss_sz; 727 u8 rss_grps; 728 u16 npa_func; 729 u16 sso_func; 730 u64 rx_cfg; /* See NIX_AF_LF(0..127)_RX_CFG */ 731 u64 way_mask; 732 #define NIX_LF_RSS_TAG_LSB_AS_ADDER BIT_ULL(0) 733 #define NIX_LF_LBK_BLK_SEL BIT_ULL(1) 734 u64 flags; 735 }; 736 737 struct nix_lf_alloc_rsp { 738 struct mbox_msghdr hdr; 739 u16 sqb_size; 740 u16 rx_chan_base; 741 u16 tx_chan_base; 742 u8 rx_chan_cnt; /* total number of RX channels */ 743 u8 tx_chan_cnt; /* total number of TX channels */ 744 u8 lso_tsov4_idx; 745 u8 lso_tsov6_idx; 746 u8 mac_addr[ETH_ALEN]; 747 u8 lf_rx_stats; /* NIX_AF_CONST1::LF_RX_STATS */ 748 u8 lf_tx_stats; /* NIX_AF_CONST1::LF_TX_STATS */ 749 u16 cints; /* NIX_AF_CONST2::CINTS */ 750 u16 qints; /* NIX_AF_CONST2::QINTS */ 751 u8 cgx_links; /* No. of CGX links present in HW */ 752 u8 lbk_links; /* No. of LBK links present in HW */ 753 u8 sdp_links; /* No. of SDP links present in HW */ 754 u8 tx_link; /* Transmit channel link number */ 755 }; 756 757 struct nix_lf_free_req { 758 struct mbox_msghdr hdr; 759 #define NIX_LF_DISABLE_FLOWS BIT_ULL(0) 760 #define NIX_LF_DONT_FREE_TX_VTAG BIT_ULL(1) 761 u64 flags; 762 }; 763 764 /* CN10K NIX AQ enqueue msg */ 765 struct nix_cn10k_aq_enq_req { 766 struct mbox_msghdr hdr; 767 u32 qidx; 768 u8 ctype; 769 u8 op; 770 union { 771 struct nix_cn10k_rq_ctx_s rq; 772 struct nix_cn10k_sq_ctx_s sq; 773 struct nix_cq_ctx_s cq; 774 struct nix_rsse_s rss; 775 struct nix_rx_mce_s mce; 776 struct nix_bandprof_s prof; 777 }; 778 union { 779 struct nix_cn10k_rq_ctx_s rq_mask; 780 struct nix_cn10k_sq_ctx_s sq_mask; 781 struct nix_cq_ctx_s cq_mask; 782 struct nix_rsse_s rss_mask; 783 struct nix_rx_mce_s mce_mask; 784 struct nix_bandprof_s prof_mask; 785 }; 786 }; 787 788 struct nix_cn10k_aq_enq_rsp { 789 struct mbox_msghdr hdr; 790 union { 791 struct nix_cn10k_rq_ctx_s rq; 792 struct nix_cn10k_sq_ctx_s sq; 793 struct nix_cq_ctx_s cq; 794 struct nix_rsse_s rss; 795 struct nix_rx_mce_s mce; 796 struct nix_bandprof_s prof; 797 }; 798 }; 799 800 /* NIX AQ enqueue msg */ 801 struct nix_aq_enq_req { 802 struct mbox_msghdr hdr; 803 u32 qidx; 804 u8 ctype; 805 u8 op; 806 union { 807 struct nix_rq_ctx_s rq; 808 struct nix_sq_ctx_s sq; 809 struct nix_cq_ctx_s cq; 810 struct nix_rsse_s rss; 811 struct nix_rx_mce_s mce; 812 u64 prof; 813 }; 814 union { 815 struct nix_rq_ctx_s rq_mask; 816 struct nix_sq_ctx_s sq_mask; 817 struct nix_cq_ctx_s cq_mask; 818 struct nix_rsse_s rss_mask; 819 struct nix_rx_mce_s mce_mask; 820 u64 prof_mask; 821 }; 822 }; 823 824 struct nix_aq_enq_rsp { 825 struct mbox_msghdr hdr; 826 union { 827 struct nix_rq_ctx_s rq; 828 struct nix_sq_ctx_s sq; 829 struct nix_cq_ctx_s cq; 830 struct nix_rsse_s rss; 831 struct nix_rx_mce_s mce; 832 struct nix_bandprof_s prof; 833 }; 834 }; 835 836 /* Tx scheduler/shaper mailbox messages */ 837 838 #define MAX_TXSCHQ_PER_FUNC 128 839 840 struct nix_txsch_alloc_req { 841 struct mbox_msghdr hdr; 842 /* Scheduler queue count request at each level */ 843 u16 schq_contig[NIX_TXSCH_LVL_CNT]; /* No of contiguous queues */ 844 u16 schq[NIX_TXSCH_LVL_CNT]; /* No of non-contiguous queues */ 845 }; 846 847 struct nix_txsch_alloc_rsp { 848 struct mbox_msghdr hdr; 849 /* Scheduler queue count allocated at each level */ 850 u16 schq_contig[NIX_TXSCH_LVL_CNT]; 851 u16 schq[NIX_TXSCH_LVL_CNT]; 852 /* Scheduler queue list allocated at each level */ 853 u16 schq_contig_list[NIX_TXSCH_LVL_CNT][MAX_TXSCHQ_PER_FUNC]; 854 u16 schq_list[NIX_TXSCH_LVL_CNT][MAX_TXSCHQ_PER_FUNC]; 855 u8 aggr_level; /* Traffic aggregation scheduler level */ 856 u8 aggr_lvl_rr_prio; /* Aggregation lvl's RR_PRIO config */ 857 u8 link_cfg_lvl; /* LINKX_CFG CSRs mapped to TL3 or TL2's index ? */ 858 }; 859 860 struct nix_txsch_free_req { 861 struct mbox_msghdr hdr; 862 #define TXSCHQ_FREE_ALL BIT_ULL(0) 863 u16 flags; 864 /* Scheduler queue level to be freed */ 865 u16 schq_lvl; 866 /* List of scheduler queues to be freed */ 867 u16 schq; 868 }; 869 870 struct nix_txschq_config { 871 struct mbox_msghdr hdr; 872 u8 lvl; /* SMQ/MDQ/TL4/TL3/TL2/TL1 */ 873 u8 read; 874 #define TXSCHQ_IDX_SHIFT 16 875 #define TXSCHQ_IDX_MASK (BIT_ULL(10) - 1) 876 #define TXSCHQ_IDX(reg, shift) (((reg) >> (shift)) & TXSCHQ_IDX_MASK) 877 u8 num_regs; 878 #define MAX_REGS_PER_MBOX_MSG 20 879 u64 reg[MAX_REGS_PER_MBOX_MSG]; 880 u64 regval[MAX_REGS_PER_MBOX_MSG]; 881 /* All 0's => overwrite with new value */ 882 u64 regval_mask[MAX_REGS_PER_MBOX_MSG]; 883 }; 884 885 struct nix_vtag_config { 886 struct mbox_msghdr hdr; 887 /* '0' for 4 octet VTAG, '1' for 8 octet VTAG */ 888 u8 vtag_size; 889 /* cfg_type is '0' for tx vlan cfg 890 * cfg_type is '1' for rx vlan cfg 891 */ 892 u8 cfg_type; 893 union { 894 /* valid when cfg_type is '0' */ 895 struct { 896 u64 vtag0; 897 u64 vtag1; 898 899 /* cfg_vtag0 & cfg_vtag1 fields are valid 900 * when free_vtag0 & free_vtag1 are '0's. 901 */ 902 /* cfg_vtag0 = 1 to configure vtag0 */ 903 u8 cfg_vtag0 :1; 904 /* cfg_vtag1 = 1 to configure vtag1 */ 905 u8 cfg_vtag1 :1; 906 907 /* vtag0_idx & vtag1_idx are only valid when 908 * both cfg_vtag0 & cfg_vtag1 are '0's, 909 * these fields are used along with free_vtag0 910 * & free_vtag1 to free the nix lf's tx_vlan 911 * configuration. 912 * 913 * Denotes the indices of tx_vtag def registers 914 * that needs to be cleared and freed. 915 */ 916 int vtag0_idx; 917 int vtag1_idx; 918 919 /* free_vtag0 & free_vtag1 fields are valid 920 * when cfg_vtag0 & cfg_vtag1 are '0's. 921 */ 922 /* free_vtag0 = 1 clears vtag0 configuration 923 * vtag0_idx denotes the index to be cleared. 924 */ 925 u8 free_vtag0 :1; 926 /* free_vtag1 = 1 clears vtag1 configuration 927 * vtag1_idx denotes the index to be cleared. 928 */ 929 u8 free_vtag1 :1; 930 } tx; 931 932 /* valid when cfg_type is '1' */ 933 struct { 934 /* rx vtag type index, valid values are in 0..7 range */ 935 u8 vtag_type; 936 /* rx vtag strip */ 937 u8 strip_vtag :1; 938 /* rx vtag capture */ 939 u8 capture_vtag :1; 940 } rx; 941 }; 942 }; 943 944 struct nix_vtag_config_rsp { 945 struct mbox_msghdr hdr; 946 int vtag0_idx; 947 int vtag1_idx; 948 /* Indices of tx_vtag def registers used to configure 949 * tx vtag0 & vtag1 headers, these indices are valid 950 * when nix_vtag_config mbox requested for vtag0 and/ 951 * or vtag1 configuration. 952 */ 953 }; 954 955 struct nix_rss_flowkey_cfg { 956 struct mbox_msghdr hdr; 957 int mcam_index; /* MCAM entry index to modify */ 958 #define NIX_FLOW_KEY_TYPE_PORT BIT(0) 959 #define NIX_FLOW_KEY_TYPE_IPV4 BIT(1) 960 #define NIX_FLOW_KEY_TYPE_IPV6 BIT(2) 961 #define NIX_FLOW_KEY_TYPE_TCP BIT(3) 962 #define NIX_FLOW_KEY_TYPE_UDP BIT(4) 963 #define NIX_FLOW_KEY_TYPE_SCTP BIT(5) 964 #define NIX_FLOW_KEY_TYPE_NVGRE BIT(6) 965 #define NIX_FLOW_KEY_TYPE_VXLAN BIT(7) 966 #define NIX_FLOW_KEY_TYPE_GENEVE BIT(8) 967 #define NIX_FLOW_KEY_TYPE_ETH_DMAC BIT(9) 968 #define NIX_FLOW_KEY_TYPE_IPV6_EXT BIT(10) 969 #define NIX_FLOW_KEY_TYPE_GTPU BIT(11) 970 #define NIX_FLOW_KEY_TYPE_INNR_IPV4 BIT(12) 971 #define NIX_FLOW_KEY_TYPE_INNR_IPV6 BIT(13) 972 #define NIX_FLOW_KEY_TYPE_INNR_TCP BIT(14) 973 #define NIX_FLOW_KEY_TYPE_INNR_UDP BIT(15) 974 #define NIX_FLOW_KEY_TYPE_INNR_SCTP BIT(16) 975 #define NIX_FLOW_KEY_TYPE_INNR_ETH_DMAC BIT(17) 976 #define NIX_FLOW_KEY_TYPE_VLAN BIT(20) 977 #define NIX_FLOW_KEY_TYPE_IPV4_PROTO BIT(21) 978 #define NIX_FLOW_KEY_TYPE_AH BIT(22) 979 #define NIX_FLOW_KEY_TYPE_ESP BIT(23) 980 u32 flowkey_cfg; /* Flowkey types selected */ 981 u8 group; /* RSS context or group */ 982 }; 983 984 struct nix_rss_flowkey_cfg_rsp { 985 struct mbox_msghdr hdr; 986 u8 alg_idx; /* Selected algo index */ 987 }; 988 989 struct nix_set_mac_addr { 990 struct mbox_msghdr hdr; 991 u8 mac_addr[ETH_ALEN]; /* MAC address to be set for this pcifunc */ 992 }; 993 994 struct nix_get_mac_addr_rsp { 995 struct mbox_msghdr hdr; 996 u8 mac_addr[ETH_ALEN]; 997 }; 998 999 struct nix_mark_format_cfg { 1000 struct mbox_msghdr hdr; 1001 u8 offset; 1002 u8 y_mask; 1003 u8 y_val; 1004 u8 r_mask; 1005 u8 r_val; 1006 }; 1007 1008 struct nix_mark_format_cfg_rsp { 1009 struct mbox_msghdr hdr; 1010 u8 mark_format_idx; 1011 }; 1012 1013 struct nix_rx_mode { 1014 struct mbox_msghdr hdr; 1015 #define NIX_RX_MODE_UCAST BIT(0) 1016 #define NIX_RX_MODE_PROMISC BIT(1) 1017 #define NIX_RX_MODE_ALLMULTI BIT(2) 1018 #define NIX_RX_MODE_USE_MCE BIT(3) 1019 u16 mode; 1020 }; 1021 1022 struct nix_rx_cfg { 1023 struct mbox_msghdr hdr; 1024 #define NIX_RX_OL3_VERIFY BIT(0) 1025 #define NIX_RX_OL4_VERIFY BIT(1) 1026 u8 len_verify; /* Outer L3/L4 len check */ 1027 #define NIX_RX_CSUM_OL4_VERIFY BIT(0) 1028 u8 csum_verify; /* Outer L4 checksum verification */ 1029 }; 1030 1031 struct nix_frs_cfg { 1032 struct mbox_msghdr hdr; 1033 u8 update_smq; /* Update SMQ's min/max lens */ 1034 u8 update_minlen; /* Set minlen also */ 1035 u8 sdp_link; /* Set SDP RX link */ 1036 u16 maxlen; 1037 u16 minlen; 1038 }; 1039 1040 struct nix_lso_format_cfg { 1041 struct mbox_msghdr hdr; 1042 u64 field_mask; 1043 #define NIX_LSO_FIELD_MAX 8 1044 u64 fields[NIX_LSO_FIELD_MAX]; 1045 }; 1046 1047 struct nix_lso_format_cfg_rsp { 1048 struct mbox_msghdr hdr; 1049 u8 lso_format_idx; 1050 }; 1051 1052 struct nix_bp_cfg_req { 1053 struct mbox_msghdr hdr; 1054 u16 chan_base; /* Starting channel number */ 1055 u8 chan_cnt; /* Number of channels */ 1056 u8 bpid_per_chan; 1057 /* bpid_per_chan = 0 assigns single bp id for range of channels */ 1058 /* bpid_per_chan = 1 assigns separate bp id for each channel */ 1059 }; 1060 1061 /* PF can be mapped to either CGX or LBK interface, 1062 * so maximum 64 channels are possible. 1063 */ 1064 #define NIX_MAX_BPID_CHAN 64 1065 struct nix_bp_cfg_rsp { 1066 struct mbox_msghdr hdr; 1067 u16 chan_bpid[NIX_MAX_BPID_CHAN]; /* Channel and bpid mapping */ 1068 u8 chan_cnt; /* Number of channel for which bpids are assigned */ 1069 }; 1070 1071 struct nix_hw_info { 1072 struct mbox_msghdr hdr; 1073 u16 rsvs16; 1074 u16 max_mtu; 1075 u16 min_mtu; 1076 u32 rpm_dwrr_mtu; 1077 u32 sdp_dwrr_mtu; 1078 u64 rsvd[16]; /* Add reserved fields for future expansion */ 1079 }; 1080 1081 struct nix_bandprof_alloc_req { 1082 struct mbox_msghdr hdr; 1083 /* Count of profiles needed per layer */ 1084 u16 prof_count[BAND_PROF_NUM_LAYERS]; 1085 }; 1086 1087 struct nix_bandprof_alloc_rsp { 1088 struct mbox_msghdr hdr; 1089 u16 prof_count[BAND_PROF_NUM_LAYERS]; 1090 1091 /* There is no need to allocate morethan 1 bandwidth profile 1092 * per RQ of a PF_FUNC's NIXLF. So limit the maximum 1093 * profiles to 64 per PF_FUNC. 1094 */ 1095 #define MAX_BANDPROF_PER_PFFUNC 64 1096 u16 prof_idx[BAND_PROF_NUM_LAYERS][MAX_BANDPROF_PER_PFFUNC]; 1097 }; 1098 1099 struct nix_bandprof_free_req { 1100 struct mbox_msghdr hdr; 1101 u8 free_all; 1102 u16 prof_count[BAND_PROF_NUM_LAYERS]; 1103 u16 prof_idx[BAND_PROF_NUM_LAYERS][MAX_BANDPROF_PER_PFFUNC]; 1104 }; 1105 1106 struct nix_bandprof_get_hwinfo_rsp { 1107 struct mbox_msghdr hdr; 1108 u16 prof_count[BAND_PROF_NUM_LAYERS]; 1109 u32 policer_timeunit; 1110 }; 1111 1112 /* NPC mbox message structs */ 1113 1114 #define NPC_MCAM_ENTRY_INVALID 0xFFFF 1115 #define NPC_MCAM_INVALID_MAP 0xFFFF 1116 1117 /* NPC mailbox error codes 1118 * Range 701 - 800. 1119 */ 1120 enum npc_af_status { 1121 NPC_MCAM_INVALID_REQ = -701, 1122 NPC_MCAM_ALLOC_DENIED = -702, 1123 NPC_MCAM_ALLOC_FAILED = -703, 1124 NPC_MCAM_PERM_DENIED = -704, 1125 NPC_FLOW_INTF_INVALID = -707, 1126 NPC_FLOW_CHAN_INVALID = -708, 1127 NPC_FLOW_NO_NIXLF = -709, 1128 NPC_FLOW_NOT_SUPPORTED = -710, 1129 NPC_FLOW_VF_PERM_DENIED = -711, 1130 NPC_FLOW_VF_NOT_INIT = -712, 1131 NPC_FLOW_VF_OVERLAP = -713, 1132 }; 1133 1134 struct npc_mcam_alloc_entry_req { 1135 struct mbox_msghdr hdr; 1136 #define NPC_MAX_NONCONTIG_ENTRIES 256 1137 u8 contig; /* Contiguous entries ? */ 1138 #define NPC_MCAM_ANY_PRIO 0 1139 #define NPC_MCAM_LOWER_PRIO 1 1140 #define NPC_MCAM_HIGHER_PRIO 2 1141 u8 priority; /* Lower or higher w.r.t ref_entry */ 1142 u16 ref_entry; 1143 u16 count; /* Number of entries requested */ 1144 }; 1145 1146 struct npc_mcam_alloc_entry_rsp { 1147 struct mbox_msghdr hdr; 1148 u16 entry; /* Entry allocated or start index if contiguous. 1149 * Invalid incase of non-contiguous. 1150 */ 1151 u16 count; /* Number of entries allocated */ 1152 u16 free_count; /* Number of entries available */ 1153 u16 entry_list[NPC_MAX_NONCONTIG_ENTRIES]; 1154 }; 1155 1156 struct npc_mcam_free_entry_req { 1157 struct mbox_msghdr hdr; 1158 u16 entry; /* Entry index to be freed */ 1159 u8 all; /* If all entries allocated to this PFVF to be freed */ 1160 }; 1161 1162 struct mcam_entry { 1163 #define NPC_MAX_KWS_IN_KEY 7 /* Number of keywords in max keywidth */ 1164 u64 kw[NPC_MAX_KWS_IN_KEY]; 1165 u64 kw_mask[NPC_MAX_KWS_IN_KEY]; 1166 u64 action; 1167 u64 vtag_action; 1168 }; 1169 1170 struct npc_mcam_write_entry_req { 1171 struct mbox_msghdr hdr; 1172 struct mcam_entry entry_data; 1173 u16 entry; /* MCAM entry to write this match key */ 1174 u16 cntr; /* Counter for this MCAM entry */ 1175 u8 intf; /* Rx or Tx interface */ 1176 u8 enable_entry;/* Enable this MCAM entry ? */ 1177 u8 set_cntr; /* Set counter for this entry ? */ 1178 }; 1179 1180 /* Enable/Disable a given entry */ 1181 struct npc_mcam_ena_dis_entry_req { 1182 struct mbox_msghdr hdr; 1183 u16 entry; 1184 }; 1185 1186 struct npc_mcam_shift_entry_req { 1187 struct mbox_msghdr hdr; 1188 #define NPC_MCAM_MAX_SHIFTS 64 1189 u16 curr_entry[NPC_MCAM_MAX_SHIFTS]; 1190 u16 new_entry[NPC_MCAM_MAX_SHIFTS]; 1191 u16 shift_count; /* Number of entries to shift */ 1192 }; 1193 1194 struct npc_mcam_shift_entry_rsp { 1195 struct mbox_msghdr hdr; 1196 u16 failed_entry_idx; /* Index in 'curr_entry', not entry itself */ 1197 }; 1198 1199 struct npc_mcam_alloc_counter_req { 1200 struct mbox_msghdr hdr; 1201 u8 contig; /* Contiguous counters ? */ 1202 #define NPC_MAX_NONCONTIG_COUNTERS 64 1203 u16 count; /* Number of counters requested */ 1204 }; 1205 1206 struct npc_mcam_alloc_counter_rsp { 1207 struct mbox_msghdr hdr; 1208 u16 cntr; /* Counter allocated or start index if contiguous. 1209 * Invalid incase of non-contiguous. 1210 */ 1211 u16 count; /* Number of counters allocated */ 1212 u16 cntr_list[NPC_MAX_NONCONTIG_COUNTERS]; 1213 }; 1214 1215 struct npc_mcam_oper_counter_req { 1216 struct mbox_msghdr hdr; 1217 u16 cntr; /* Free a counter or clear/fetch it's stats */ 1218 }; 1219 1220 struct npc_mcam_oper_counter_rsp { 1221 struct mbox_msghdr hdr; 1222 u64 stat; /* valid only while fetching counter's stats */ 1223 }; 1224 1225 struct npc_mcam_unmap_counter_req { 1226 struct mbox_msghdr hdr; 1227 u16 cntr; 1228 u16 entry; /* Entry and counter to be unmapped */ 1229 u8 all; /* Unmap all entries using this counter ? */ 1230 }; 1231 1232 struct npc_mcam_alloc_and_write_entry_req { 1233 struct mbox_msghdr hdr; 1234 struct mcam_entry entry_data; 1235 u16 ref_entry; 1236 u8 priority; /* Lower or higher w.r.t ref_entry */ 1237 u8 intf; /* Rx or Tx interface */ 1238 u8 enable_entry;/* Enable this MCAM entry ? */ 1239 u8 alloc_cntr; /* Allocate counter and map ? */ 1240 }; 1241 1242 struct npc_mcam_alloc_and_write_entry_rsp { 1243 struct mbox_msghdr hdr; 1244 u16 entry; 1245 u16 cntr; 1246 }; 1247 1248 struct npc_get_kex_cfg_rsp { 1249 struct mbox_msghdr hdr; 1250 u64 rx_keyx_cfg; /* NPC_AF_INTF(0)_KEX_CFG */ 1251 u64 tx_keyx_cfg; /* NPC_AF_INTF(1)_KEX_CFG */ 1252 #define NPC_MAX_INTF 2 1253 #define NPC_MAX_LID 8 1254 #define NPC_MAX_LT 16 1255 #define NPC_MAX_LD 2 1256 #define NPC_MAX_LFL 16 1257 /* NPC_AF_KEX_LDATA(0..1)_FLAGS_CFG */ 1258 u64 kex_ld_flags[NPC_MAX_LD]; 1259 /* NPC_AF_INTF(0..1)_LID(0..7)_LT(0..15)_LD(0..1)_CFG */ 1260 u64 intf_lid_lt_ld[NPC_MAX_INTF][NPC_MAX_LID][NPC_MAX_LT][NPC_MAX_LD]; 1261 /* NPC_AF_INTF(0..1)_LDATA(0..1)_FLAGS(0..15)_CFG */ 1262 u64 intf_ld_flags[NPC_MAX_INTF][NPC_MAX_LD][NPC_MAX_LFL]; 1263 #define MKEX_NAME_LEN 128 1264 u8 mkex_pfl_name[MKEX_NAME_LEN]; 1265 }; 1266 1267 struct flow_msg { 1268 unsigned char dmac[6]; 1269 unsigned char smac[6]; 1270 __be16 etype; 1271 __be16 vlan_etype; 1272 __be16 vlan_tci; 1273 union { 1274 __be32 ip4src; 1275 __be32 ip6src[4]; 1276 }; 1277 union { 1278 __be32 ip4dst; 1279 __be32 ip6dst[4]; 1280 }; 1281 u8 tos; 1282 u8 ip_ver; 1283 u8 ip_proto; 1284 u8 tc; 1285 __be16 sport; 1286 __be16 dport; 1287 }; 1288 1289 struct npc_install_flow_req { 1290 struct mbox_msghdr hdr; 1291 struct flow_msg packet; 1292 struct flow_msg mask; 1293 u64 features; 1294 u16 entry; 1295 u16 channel; 1296 u16 chan_mask; 1297 u8 intf; 1298 u8 set_cntr; /* If counter is available set counter for this entry ? */ 1299 u8 default_rule; 1300 u8 append; /* overwrite(0) or append(1) flow to default rule? */ 1301 u16 vf; 1302 /* action */ 1303 u32 index; 1304 u16 match_id; 1305 u8 flow_key_alg; 1306 u8 op; 1307 /* vtag rx action */ 1308 u8 vtag0_type; 1309 u8 vtag0_valid; 1310 u8 vtag1_type; 1311 u8 vtag1_valid; 1312 /* vtag tx action */ 1313 u16 vtag0_def; 1314 u8 vtag0_op; 1315 u16 vtag1_def; 1316 u8 vtag1_op; 1317 }; 1318 1319 struct npc_install_flow_rsp { 1320 struct mbox_msghdr hdr; 1321 int counter; /* negative if no counter else counter number */ 1322 }; 1323 1324 struct npc_delete_flow_req { 1325 struct mbox_msghdr hdr; 1326 u16 entry; 1327 u16 start;/*Disable range of entries */ 1328 u16 end; 1329 u8 all; /* PF + VFs */ 1330 }; 1331 1332 struct npc_mcam_read_entry_req { 1333 struct mbox_msghdr hdr; 1334 u16 entry; /* MCAM entry to read */ 1335 }; 1336 1337 struct npc_mcam_read_entry_rsp { 1338 struct mbox_msghdr hdr; 1339 struct mcam_entry entry_data; 1340 u8 intf; 1341 u8 enable; 1342 }; 1343 1344 struct npc_mcam_read_base_rule_rsp { 1345 struct mbox_msghdr hdr; 1346 struct mcam_entry entry; 1347 }; 1348 1349 struct npc_mcam_get_stats_req { 1350 struct mbox_msghdr hdr; 1351 u16 entry; /* mcam entry */ 1352 }; 1353 1354 struct npc_mcam_get_stats_rsp { 1355 struct mbox_msghdr hdr; 1356 u64 stat; /* counter stats */ 1357 u8 stat_ena; /* enabled */ 1358 }; 1359 1360 enum ptp_op { 1361 PTP_OP_ADJFINE = 0, 1362 PTP_OP_GET_CLOCK = 1, 1363 }; 1364 1365 struct ptp_req { 1366 struct mbox_msghdr hdr; 1367 u8 op; 1368 s64 scaled_ppm; 1369 }; 1370 1371 struct ptp_rsp { 1372 struct mbox_msghdr hdr; 1373 u64 clk; 1374 }; 1375 1376 struct set_vf_perm { 1377 struct mbox_msghdr hdr; 1378 u16 vf; 1379 #define RESET_VF_PERM BIT_ULL(0) 1380 #define VF_TRUSTED BIT_ULL(1) 1381 u64 flags; 1382 }; 1383 1384 struct lmtst_tbl_setup_req { 1385 struct mbox_msghdr hdr; 1386 u16 base_pcifunc; 1387 u8 use_local_lmt_region; 1388 u64 lmt_iova; 1389 u64 rsvd[4]; 1390 }; 1391 1392 /* CPT mailbox error codes 1393 * Range 901 - 1000. 1394 */ 1395 enum cpt_af_status { 1396 CPT_AF_ERR_PARAM = -901, 1397 CPT_AF_ERR_GRP_INVALID = -902, 1398 CPT_AF_ERR_LF_INVALID = -903, 1399 CPT_AF_ERR_ACCESS_DENIED = -904, 1400 CPT_AF_ERR_SSO_PF_FUNC_INVALID = -905, 1401 CPT_AF_ERR_NIX_PF_FUNC_INVALID = -906 1402 }; 1403 1404 /* CPT mbox message formats */ 1405 struct cpt_rd_wr_reg_msg { 1406 struct mbox_msghdr hdr; 1407 u64 reg_offset; 1408 u64 *ret_val; 1409 u64 val; 1410 u8 is_write; 1411 int blkaddr; 1412 }; 1413 1414 struct cpt_lf_alloc_req_msg { 1415 struct mbox_msghdr hdr; 1416 u16 nix_pf_func; 1417 u16 sso_pf_func; 1418 u16 eng_grpmsk; 1419 int blkaddr; 1420 }; 1421 1422 /* Mailbox message request and response format for CPT stats. */ 1423 struct cpt_sts_req { 1424 struct mbox_msghdr hdr; 1425 u8 blkaddr; 1426 }; 1427 1428 struct cpt_sts_rsp { 1429 struct mbox_msghdr hdr; 1430 u64 inst_req_pc; 1431 u64 inst_lat_pc; 1432 u64 rd_req_pc; 1433 u64 rd_lat_pc; 1434 u64 rd_uc_pc; 1435 u64 active_cycles_pc; 1436 u64 ctx_mis_pc; 1437 u64 ctx_hit_pc; 1438 u64 ctx_aop_pc; 1439 u64 ctx_aop_lat_pc; 1440 u64 ctx_ifetch_pc; 1441 u64 ctx_ifetch_lat_pc; 1442 u64 ctx_ffetch_pc; 1443 u64 ctx_ffetch_lat_pc; 1444 u64 ctx_wback_pc; 1445 u64 ctx_wback_lat_pc; 1446 u64 ctx_psh_pc; 1447 u64 ctx_psh_lat_pc; 1448 u64 ctx_err; 1449 u64 ctx_enc_id; 1450 u64 ctx_flush_timer; 1451 u64 rxc_time; 1452 u64 rxc_time_cfg; 1453 u64 rxc_active_sts; 1454 u64 rxc_zombie_sts; 1455 u64 busy_sts_ae; 1456 u64 free_sts_ae; 1457 u64 busy_sts_se; 1458 u64 free_sts_se; 1459 u64 busy_sts_ie; 1460 u64 free_sts_ie; 1461 u64 exe_err_info; 1462 u64 cptclk_cnt; 1463 u64 diag; 1464 u64 rxc_dfrg; 1465 u64 x2p_link_cfg0; 1466 u64 x2p_link_cfg1; 1467 }; 1468 1469 /* Mailbox message request format to configure reassembly timeout. */ 1470 struct cpt_rxc_time_cfg_req { 1471 struct mbox_msghdr hdr; 1472 int blkaddr; 1473 u32 step; 1474 u16 zombie_thres; 1475 u16 zombie_limit; 1476 u16 active_thres; 1477 u16 active_limit; 1478 }; 1479 1480 struct sdp_node_info { 1481 /* Node to which this PF belons to */ 1482 u8 node_id; 1483 u8 max_vfs; 1484 u8 num_pf_rings; 1485 u8 pf_srn; 1486 #define SDP_MAX_VFS 128 1487 u8 vf_rings[SDP_MAX_VFS]; 1488 }; 1489 1490 struct sdp_chan_info_msg { 1491 struct mbox_msghdr hdr; 1492 struct sdp_node_info info; 1493 }; 1494 1495 struct sdp_get_chan_info_msg { 1496 struct mbox_msghdr hdr; 1497 u16 chan_base; 1498 u16 num_chan; 1499 }; 1500 1501 /* CGX mailbox error codes 1502 * Range 1101 - 1200. 1503 */ 1504 enum cgx_af_status { 1505 LMAC_AF_ERR_INVALID_PARAM = -1101, 1506 LMAC_AF_ERR_PF_NOT_MAPPED = -1102, 1507 LMAC_AF_ERR_PERM_DENIED = -1103, 1508 }; 1509 1510 #endif /* MBOX_H */ 1511