1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Marvell RVU Admin Function driver 3 * 4 * Copyright (C) 2018 Marvell. 5 * 6 */ 7 8 #ifndef MBOX_H 9 #define MBOX_H 10 11 #include <linux/etherdevice.h> 12 #include <linux/sizes.h> 13 14 #include "rvu_struct.h" 15 #include "common.h" 16 17 #define MBOX_SIZE SZ_64K 18 19 #define MBOX_DOWN_MSG 1 20 #define MBOX_UP_MSG 2 21 22 /* AF/PF: PF initiated, PF/VF VF initiated */ 23 #define MBOX_DOWN_RX_START 0 24 #define MBOX_DOWN_RX_SIZE (46 * SZ_1K) 25 #define MBOX_DOWN_TX_START (MBOX_DOWN_RX_START + MBOX_DOWN_RX_SIZE) 26 #define MBOX_DOWN_TX_SIZE (16 * SZ_1K) 27 /* AF/PF: AF initiated, PF/VF PF initiated */ 28 #define MBOX_UP_RX_START (MBOX_DOWN_TX_START + MBOX_DOWN_TX_SIZE) 29 #define MBOX_UP_RX_SIZE SZ_1K 30 #define MBOX_UP_TX_START (MBOX_UP_RX_START + MBOX_UP_RX_SIZE) 31 #define MBOX_UP_TX_SIZE SZ_1K 32 33 #if MBOX_UP_TX_SIZE + MBOX_UP_TX_START != MBOX_SIZE 34 # error "incorrect mailbox area sizes" 35 #endif 36 37 #define INTR_MASK(pfvfs) ((pfvfs < 64) ? (BIT_ULL(pfvfs) - 1) : (~0ull)) 38 39 #define MBOX_RSP_TIMEOUT 6000 /* Time(ms) to wait for mbox response */ 40 41 #define MBOX_MSG_ALIGN 16 /* Align mbox msg start to 16bytes */ 42 43 /* Mailbox directions */ 44 #define MBOX_DIR_AFPF 0 /* AF replies to PF */ 45 #define MBOX_DIR_PFAF 1 /* PF sends messages to AF */ 46 #define MBOX_DIR_PFVF 2 /* PF replies to VF */ 47 #define MBOX_DIR_VFPF 3 /* VF sends messages to PF */ 48 #define MBOX_DIR_AFPF_UP 4 /* AF sends messages to PF */ 49 #define MBOX_DIR_PFAF_UP 5 /* PF replies to AF */ 50 #define MBOX_DIR_PFVF_UP 6 /* PF sends messages to VF */ 51 #define MBOX_DIR_VFPF_UP 7 /* VF replies to PF */ 52 53 struct otx2_mbox_dev { 54 void *mbase; /* This dev's mbox region */ 55 void *hwbase; 56 spinlock_t mbox_lock; 57 u16 msg_size; /* Total msg size to be sent */ 58 u16 rsp_size; /* Total rsp size to be sure the reply is ok */ 59 u16 num_msgs; /* No of msgs sent or waiting for response */ 60 u16 msgs_acked; /* No of msgs for which response is received */ 61 }; 62 63 struct otx2_mbox { 64 struct pci_dev *pdev; 65 void *hwbase; /* Mbox region advertised by HW */ 66 void *reg_base;/* CSR base for this dev */ 67 u64 trigger; /* Trigger mbox notification */ 68 u16 tr_shift; /* Mbox trigger shift */ 69 u64 rx_start; /* Offset of Rx region in mbox memory */ 70 u64 tx_start; /* Offset of Tx region in mbox memory */ 71 u16 rx_size; /* Size of Rx region */ 72 u16 tx_size; /* Size of Tx region */ 73 u16 ndevs; /* The number of peers */ 74 struct otx2_mbox_dev *dev; 75 }; 76 77 /* Header which precedes all mbox messages */ 78 struct mbox_hdr { 79 u64 msg_size; /* Total msgs size embedded */ 80 u16 num_msgs; /* No of msgs embedded */ 81 }; 82 83 /* Header which precedes every msg and is also part of it */ 84 struct mbox_msghdr { 85 u16 pcifunc; /* Who's sending this msg */ 86 u16 id; /* Mbox message ID */ 87 #define OTX2_MBOX_REQ_SIG (0xdead) 88 #define OTX2_MBOX_RSP_SIG (0xbeef) 89 u16 sig; /* Signature, for validating corrupted msgs */ 90 #define OTX2_MBOX_VERSION (0x000a) 91 u16 ver; /* Version of msg's structure for this ID */ 92 u16 next_msgoff; /* Offset of next msg within mailbox region */ 93 int rc; /* Msg process'ed response code */ 94 }; 95 96 void otx2_mbox_reset(struct otx2_mbox *mbox, int devid); 97 void __otx2_mbox_reset(struct otx2_mbox *mbox, int devid); 98 void otx2_mbox_destroy(struct otx2_mbox *mbox); 99 int otx2_mbox_init(struct otx2_mbox *mbox, void __force *hwbase, 100 struct pci_dev *pdev, void __force *reg_base, 101 int direction, int ndevs); 102 103 int otx2_mbox_regions_init(struct otx2_mbox *mbox, void __force **hwbase, 104 struct pci_dev *pdev, void __force *reg_base, 105 int direction, int ndevs, unsigned long *bmap); 106 void otx2_mbox_msg_send(struct otx2_mbox *mbox, int devid); 107 void otx2_mbox_msg_send_up(struct otx2_mbox *mbox, int devid); 108 int otx2_mbox_wait_for_rsp(struct otx2_mbox *mbox, int devid); 109 int otx2_mbox_busy_poll_for_rsp(struct otx2_mbox *mbox, int devid); 110 struct mbox_msghdr *otx2_mbox_alloc_msg_rsp(struct otx2_mbox *mbox, int devid, 111 int size, int size_rsp); 112 struct mbox_msghdr *otx2_mbox_get_rsp(struct otx2_mbox *mbox, int devid, 113 struct mbox_msghdr *msg); 114 int otx2_mbox_check_rsp_msgs(struct otx2_mbox *mbox, int devid); 115 int otx2_reply_invalid_msg(struct otx2_mbox *mbox, int devid, 116 u16 pcifunc, u16 id); 117 bool otx2_mbox_nonempty(struct otx2_mbox *mbox, int devid); 118 const char *otx2_mbox_id2name(u16 id); 119 static inline struct mbox_msghdr *otx2_mbox_alloc_msg(struct otx2_mbox *mbox, 120 int devid, int size) 121 { 122 return otx2_mbox_alloc_msg_rsp(mbox, devid, size, 0); 123 } 124 125 bool otx2_mbox_wait_for_zero(struct otx2_mbox *mbox, int devid); 126 127 /* Mailbox message types */ 128 #define MBOX_MSG_MASK 0xFFFF 129 #define MBOX_MSG_INVALID 0xFFFE 130 #define MBOX_MSG_MAX 0xFFFF 131 132 #define MBOX_MESSAGES \ 133 /* Generic mbox IDs (range 0x000 - 0x1FF) */ \ 134 M(READY, 0x001, ready, msg_req, ready_msg_rsp) \ 135 M(ATTACH_RESOURCES, 0x002, attach_resources, rsrc_attach, msg_rsp) \ 136 M(DETACH_RESOURCES, 0x003, detach_resources, rsrc_detach, msg_rsp) \ 137 M(FREE_RSRC_CNT, 0x004, free_rsrc_cnt, msg_req, free_rsrcs_rsp) \ 138 M(MSIX_OFFSET, 0x005, msix_offset, msg_req, msix_offset_rsp) \ 139 M(VF_FLR, 0x006, vf_flr, msg_req, msg_rsp) \ 140 M(PTP_OP, 0x007, ptp_op, ptp_req, ptp_rsp) \ 141 M(GET_HW_CAP, 0x008, get_hw_cap, msg_req, get_hw_cap_rsp) \ 142 M(LMTST_TBL_SETUP, 0x00a, lmtst_tbl_setup, lmtst_tbl_setup_req, \ 143 msg_rsp) \ 144 M(SET_VF_PERM, 0x00b, set_vf_perm, set_vf_perm, msg_rsp) \ 145 M(PTP_GET_CAP, 0x00c, ptp_get_cap, msg_req, ptp_get_cap_rsp) \ 146 /* CGX mbox IDs (range 0x200 - 0x3FF) */ \ 147 M(CGX_START_RXTX, 0x200, cgx_start_rxtx, msg_req, msg_rsp) \ 148 M(CGX_STOP_RXTX, 0x201, cgx_stop_rxtx, msg_req, msg_rsp) \ 149 M(CGX_STATS, 0x202, cgx_stats, msg_req, cgx_stats_rsp) \ 150 M(CGX_MAC_ADDR_SET, 0x203, cgx_mac_addr_set, cgx_mac_addr_set_or_get, \ 151 cgx_mac_addr_set_or_get) \ 152 M(CGX_MAC_ADDR_GET, 0x204, cgx_mac_addr_get, cgx_mac_addr_set_or_get, \ 153 cgx_mac_addr_set_or_get) \ 154 M(CGX_PROMISC_ENABLE, 0x205, cgx_promisc_enable, msg_req, msg_rsp) \ 155 M(CGX_PROMISC_DISABLE, 0x206, cgx_promisc_disable, msg_req, msg_rsp) \ 156 M(CGX_START_LINKEVENTS, 0x207, cgx_start_linkevents, msg_req, msg_rsp) \ 157 M(CGX_STOP_LINKEVENTS, 0x208, cgx_stop_linkevents, msg_req, msg_rsp) \ 158 M(CGX_GET_LINKINFO, 0x209, cgx_get_linkinfo, msg_req, cgx_link_info_msg) \ 159 M(CGX_INTLBK_ENABLE, 0x20A, cgx_intlbk_enable, msg_req, msg_rsp) \ 160 M(CGX_INTLBK_DISABLE, 0x20B, cgx_intlbk_disable, msg_req, msg_rsp) \ 161 M(CGX_PTP_RX_ENABLE, 0x20C, cgx_ptp_rx_enable, msg_req, msg_rsp) \ 162 M(CGX_PTP_RX_DISABLE, 0x20D, cgx_ptp_rx_disable, msg_req, msg_rsp) \ 163 M(CGX_CFG_PAUSE_FRM, 0x20E, cgx_cfg_pause_frm, cgx_pause_frm_cfg, \ 164 cgx_pause_frm_cfg) \ 165 M(CGX_FW_DATA_GET, 0x20F, cgx_get_aux_link_info, msg_req, cgx_fw_data) \ 166 M(CGX_FEC_SET, 0x210, cgx_set_fec_param, fec_mode, fec_mode) \ 167 M(CGX_MAC_ADDR_ADD, 0x211, cgx_mac_addr_add, cgx_mac_addr_add_req, \ 168 cgx_mac_addr_add_rsp) \ 169 M(CGX_MAC_ADDR_DEL, 0x212, cgx_mac_addr_del, cgx_mac_addr_del_req, \ 170 msg_rsp) \ 171 M(CGX_MAC_MAX_ENTRIES_GET, 0x213, cgx_mac_max_entries_get, msg_req, \ 172 cgx_max_dmac_entries_get_rsp) \ 173 M(CGX_FEC_STATS, 0x217, cgx_fec_stats, msg_req, cgx_fec_stats_rsp) \ 174 M(CGX_SET_LINK_MODE, 0x218, cgx_set_link_mode, cgx_set_link_mode_req,\ 175 cgx_set_link_mode_rsp) \ 176 M(CGX_GET_PHY_FEC_STATS, 0x219, cgx_get_phy_fec_stats, msg_req, msg_rsp) \ 177 M(CGX_STATS_RST, 0x21A, cgx_stats_rst, msg_req, msg_rsp) \ 178 M(CGX_FEATURES_GET, 0x21B, cgx_features_get, msg_req, \ 179 cgx_features_info_msg) \ 180 M(RPM_STATS, 0x21C, rpm_stats, msg_req, rpm_stats_rsp) \ 181 M(CGX_MAC_ADDR_RESET, 0x21D, cgx_mac_addr_reset, cgx_mac_addr_reset_req, \ 182 msg_rsp) \ 183 M(CGX_MAC_ADDR_UPDATE, 0x21E, cgx_mac_addr_update, cgx_mac_addr_update_req, \ 184 cgx_mac_addr_update_rsp) \ 185 M(CGX_PRIO_FLOW_CTRL_CFG, 0x21F, cgx_prio_flow_ctrl_cfg, cgx_pfc_cfg, \ 186 cgx_pfc_rsp) \ 187 /* NPA mbox IDs (range 0x400 - 0x5FF) */ \ 188 M(NPA_LF_ALLOC, 0x400, npa_lf_alloc, \ 189 npa_lf_alloc_req, npa_lf_alloc_rsp) \ 190 M(NPA_LF_FREE, 0x401, npa_lf_free, msg_req, msg_rsp) \ 191 M(NPA_AQ_ENQ, 0x402, npa_aq_enq, npa_aq_enq_req, npa_aq_enq_rsp) \ 192 M(NPA_HWCTX_DISABLE, 0x403, npa_hwctx_disable, hwctx_disable_req, msg_rsp)\ 193 /* SSO/SSOW mbox IDs (range 0x600 - 0x7FF) */ \ 194 /* TIM mbox IDs (range 0x800 - 0x9FF) */ \ 195 /* CPT mbox IDs (range 0xA00 - 0xBFF) */ \ 196 M(CPT_LF_ALLOC, 0xA00, cpt_lf_alloc, cpt_lf_alloc_req_msg, \ 197 msg_rsp) \ 198 M(CPT_LF_FREE, 0xA01, cpt_lf_free, msg_req, msg_rsp) \ 199 M(CPT_RD_WR_REGISTER, 0xA02, cpt_rd_wr_register, cpt_rd_wr_reg_msg, \ 200 cpt_rd_wr_reg_msg) \ 201 M(CPT_INLINE_IPSEC_CFG, 0xA04, cpt_inline_ipsec_cfg, \ 202 cpt_inline_ipsec_cfg_msg, msg_rsp) \ 203 M(CPT_STATS, 0xA05, cpt_sts, cpt_sts_req, cpt_sts_rsp) \ 204 M(CPT_RXC_TIME_CFG, 0xA06, cpt_rxc_time_cfg, cpt_rxc_time_cfg_req, \ 205 msg_rsp) \ 206 M(CPT_CTX_CACHE_SYNC, 0xA07, cpt_ctx_cache_sync, msg_req, msg_rsp) \ 207 M(CPT_LF_RESET, 0xA08, cpt_lf_reset, cpt_lf_rst_req, msg_rsp) \ 208 M(CPT_FLT_ENG_INFO, 0xA09, cpt_flt_eng_info, cpt_flt_eng_info_req, \ 209 cpt_flt_eng_info_rsp) \ 210 /* SDP mbox IDs (range 0x1000 - 0x11FF) */ \ 211 M(SET_SDP_CHAN_INFO, 0x1000, set_sdp_chan_info, sdp_chan_info_msg, msg_rsp) \ 212 M(GET_SDP_CHAN_INFO, 0x1001, get_sdp_chan_info, msg_req, sdp_get_chan_info_msg) \ 213 /* NPC mbox IDs (range 0x6000 - 0x7FFF) */ \ 214 M(NPC_MCAM_ALLOC_ENTRY, 0x6000, npc_mcam_alloc_entry, npc_mcam_alloc_entry_req,\ 215 npc_mcam_alloc_entry_rsp) \ 216 M(NPC_MCAM_FREE_ENTRY, 0x6001, npc_mcam_free_entry, \ 217 npc_mcam_free_entry_req, msg_rsp) \ 218 M(NPC_MCAM_WRITE_ENTRY, 0x6002, npc_mcam_write_entry, \ 219 npc_mcam_write_entry_req, msg_rsp) \ 220 M(NPC_MCAM_ENA_ENTRY, 0x6003, npc_mcam_ena_entry, \ 221 npc_mcam_ena_dis_entry_req, msg_rsp) \ 222 M(NPC_MCAM_DIS_ENTRY, 0x6004, npc_mcam_dis_entry, \ 223 npc_mcam_ena_dis_entry_req, msg_rsp) \ 224 M(NPC_MCAM_SHIFT_ENTRY, 0x6005, npc_mcam_shift_entry, npc_mcam_shift_entry_req,\ 225 npc_mcam_shift_entry_rsp) \ 226 M(NPC_MCAM_ALLOC_COUNTER, 0x6006, npc_mcam_alloc_counter, \ 227 npc_mcam_alloc_counter_req, \ 228 npc_mcam_alloc_counter_rsp) \ 229 M(NPC_MCAM_FREE_COUNTER, 0x6007, npc_mcam_free_counter, \ 230 npc_mcam_oper_counter_req, msg_rsp) \ 231 M(NPC_MCAM_UNMAP_COUNTER, 0x6008, npc_mcam_unmap_counter, \ 232 npc_mcam_unmap_counter_req, msg_rsp) \ 233 M(NPC_MCAM_CLEAR_COUNTER, 0x6009, npc_mcam_clear_counter, \ 234 npc_mcam_oper_counter_req, msg_rsp) \ 235 M(NPC_MCAM_COUNTER_STATS, 0x600a, npc_mcam_counter_stats, \ 236 npc_mcam_oper_counter_req, \ 237 npc_mcam_oper_counter_rsp) \ 238 M(NPC_MCAM_ALLOC_AND_WRITE_ENTRY, 0x600b, npc_mcam_alloc_and_write_entry, \ 239 npc_mcam_alloc_and_write_entry_req, \ 240 npc_mcam_alloc_and_write_entry_rsp) \ 241 M(NPC_GET_KEX_CFG, 0x600c, npc_get_kex_cfg, \ 242 msg_req, npc_get_kex_cfg_rsp) \ 243 M(NPC_INSTALL_FLOW, 0x600d, npc_install_flow, \ 244 npc_install_flow_req, npc_install_flow_rsp) \ 245 M(NPC_DELETE_FLOW, 0x600e, npc_delete_flow, \ 246 npc_delete_flow_req, npc_delete_flow_rsp) \ 247 M(NPC_MCAM_READ_ENTRY, 0x600f, npc_mcam_read_entry, \ 248 npc_mcam_read_entry_req, \ 249 npc_mcam_read_entry_rsp) \ 250 M(NPC_SET_PKIND, 0x6010, npc_set_pkind, \ 251 npc_set_pkind, msg_rsp) \ 252 M(NPC_MCAM_READ_BASE_RULE, 0x6011, npc_read_base_steer_rule, \ 253 msg_req, npc_mcam_read_base_rule_rsp) \ 254 M(NPC_MCAM_GET_STATS, 0x6012, npc_mcam_entry_stats, \ 255 npc_mcam_get_stats_req, \ 256 npc_mcam_get_stats_rsp) \ 257 M(NPC_GET_FIELD_HASH_INFO, 0x6013, npc_get_field_hash_info, \ 258 npc_get_field_hash_info_req, \ 259 npc_get_field_hash_info_rsp) \ 260 M(NPC_GET_FIELD_STATUS, 0x6014, npc_get_field_status, \ 261 npc_get_field_status_req, \ 262 npc_get_field_status_rsp) \ 263 /* NIX mbox IDs (range 0x8000 - 0xFFFF) */ \ 264 M(NIX_LF_ALLOC, 0x8000, nix_lf_alloc, \ 265 nix_lf_alloc_req, nix_lf_alloc_rsp) \ 266 M(NIX_LF_FREE, 0x8001, nix_lf_free, nix_lf_free_req, msg_rsp) \ 267 M(NIX_AQ_ENQ, 0x8002, nix_aq_enq, nix_aq_enq_req, nix_aq_enq_rsp) \ 268 M(NIX_HWCTX_DISABLE, 0x8003, nix_hwctx_disable, \ 269 hwctx_disable_req, msg_rsp) \ 270 M(NIX_TXSCH_ALLOC, 0x8004, nix_txsch_alloc, \ 271 nix_txsch_alloc_req, nix_txsch_alloc_rsp) \ 272 M(NIX_TXSCH_FREE, 0x8005, nix_txsch_free, nix_txsch_free_req, msg_rsp) \ 273 M(NIX_TXSCHQ_CFG, 0x8006, nix_txschq_cfg, nix_txschq_config, \ 274 nix_txschq_config) \ 275 M(NIX_STATS_RST, 0x8007, nix_stats_rst, msg_req, msg_rsp) \ 276 M(NIX_VTAG_CFG, 0x8008, nix_vtag_cfg, nix_vtag_config, \ 277 nix_vtag_config_rsp) \ 278 M(NIX_RSS_FLOWKEY_CFG, 0x8009, nix_rss_flowkey_cfg, \ 279 nix_rss_flowkey_cfg, \ 280 nix_rss_flowkey_cfg_rsp) \ 281 M(NIX_SET_MAC_ADDR, 0x800a, nix_set_mac_addr, nix_set_mac_addr, msg_rsp) \ 282 M(NIX_SET_RX_MODE, 0x800b, nix_set_rx_mode, nix_rx_mode, msg_rsp) \ 283 M(NIX_SET_HW_FRS, 0x800c, nix_set_hw_frs, nix_frs_cfg, msg_rsp) \ 284 M(NIX_LF_START_RX, 0x800d, nix_lf_start_rx, msg_req, msg_rsp) \ 285 M(NIX_LF_STOP_RX, 0x800e, nix_lf_stop_rx, msg_req, msg_rsp) \ 286 M(NIX_MARK_FORMAT_CFG, 0x800f, nix_mark_format_cfg, \ 287 nix_mark_format_cfg, \ 288 nix_mark_format_cfg_rsp) \ 289 M(NIX_SET_RX_CFG, 0x8010, nix_set_rx_cfg, nix_rx_cfg, msg_rsp) \ 290 M(NIX_LSO_FORMAT_CFG, 0x8011, nix_lso_format_cfg, \ 291 nix_lso_format_cfg, \ 292 nix_lso_format_cfg_rsp) \ 293 M(NIX_LF_PTP_TX_ENABLE, 0x8013, nix_lf_ptp_tx_enable, msg_req, msg_rsp) \ 294 M(NIX_LF_PTP_TX_DISABLE, 0x8014, nix_lf_ptp_tx_disable, msg_req, msg_rsp) \ 295 M(NIX_BP_ENABLE, 0x8016, nix_bp_enable, nix_bp_cfg_req, \ 296 nix_bp_cfg_rsp) \ 297 M(NIX_BP_DISABLE, 0x8017, nix_bp_disable, nix_bp_cfg_req, msg_rsp) \ 298 M(NIX_GET_MAC_ADDR, 0x8018, nix_get_mac_addr, msg_req, nix_get_mac_addr_rsp) \ 299 M(NIX_INLINE_IPSEC_CFG, 0x8019, nix_inline_ipsec_cfg, \ 300 nix_inline_ipsec_cfg, msg_rsp) \ 301 M(NIX_INLINE_IPSEC_LF_CFG, 0x801a, nix_inline_ipsec_lf_cfg, \ 302 nix_inline_ipsec_lf_cfg, msg_rsp) \ 303 M(NIX_CN10K_AQ_ENQ, 0x801b, nix_cn10k_aq_enq, nix_cn10k_aq_enq_req, \ 304 nix_cn10k_aq_enq_rsp) \ 305 M(NIX_GET_HW_INFO, 0x801c, nix_get_hw_info, msg_req, nix_hw_info) \ 306 M(NIX_BANDPROF_ALLOC, 0x801d, nix_bandprof_alloc, nix_bandprof_alloc_req, \ 307 nix_bandprof_alloc_rsp) \ 308 M(NIX_BANDPROF_FREE, 0x801e, nix_bandprof_free, nix_bandprof_free_req, \ 309 msg_rsp) \ 310 M(NIX_BANDPROF_GET_HWINFO, 0x801f, nix_bandprof_get_hwinfo, msg_req, \ 311 nix_bandprof_get_hwinfo_rsp) \ 312 M(NIX_READ_INLINE_IPSEC_CFG, 0x8023, nix_read_inline_ipsec_cfg, \ 313 msg_req, nix_inline_ipsec_cfg) \ 314 /* MCS mbox IDs (range 0xA000 - 0xBFFF) */ \ 315 M(MCS_ALLOC_RESOURCES, 0xa000, mcs_alloc_resources, mcs_alloc_rsrc_req, \ 316 mcs_alloc_rsrc_rsp) \ 317 M(MCS_FREE_RESOURCES, 0xa001, mcs_free_resources, mcs_free_rsrc_req, msg_rsp) \ 318 M(MCS_FLOWID_ENTRY_WRITE, 0xa002, mcs_flowid_entry_write, mcs_flowid_entry_write_req, \ 319 msg_rsp) \ 320 M(MCS_SECY_PLCY_WRITE, 0xa003, mcs_secy_plcy_write, mcs_secy_plcy_write_req, \ 321 msg_rsp) \ 322 M(MCS_RX_SC_CAM_WRITE, 0xa004, mcs_rx_sc_cam_write, mcs_rx_sc_cam_write_req, \ 323 msg_rsp) \ 324 M(MCS_SA_PLCY_WRITE, 0xa005, mcs_sa_plcy_write, mcs_sa_plcy_write_req, \ 325 msg_rsp) \ 326 M(MCS_TX_SC_SA_MAP_WRITE, 0xa006, mcs_tx_sc_sa_map_write, mcs_tx_sc_sa_map, \ 327 msg_rsp) \ 328 M(MCS_RX_SC_SA_MAP_WRITE, 0xa007, mcs_rx_sc_sa_map_write, mcs_rx_sc_sa_map, \ 329 msg_rsp) \ 330 M(MCS_FLOWID_ENA_ENTRY, 0xa008, mcs_flowid_ena_entry, mcs_flowid_ena_dis_entry, \ 331 msg_rsp) \ 332 M(MCS_PN_TABLE_WRITE, 0xa009, mcs_pn_table_write, mcs_pn_table_write_req, \ 333 msg_rsp) \ 334 M(MCS_SET_ACTIVE_LMAC, 0xa00a, mcs_set_active_lmac, mcs_set_active_lmac, \ 335 msg_rsp) \ 336 M(MCS_GET_HW_INFO, 0xa00b, mcs_get_hw_info, msg_req, mcs_hw_info) \ 337 M(MCS_GET_FLOWID_STATS, 0xa00c, mcs_get_flowid_stats, mcs_stats_req, \ 338 mcs_flowid_stats) \ 339 M(MCS_GET_SECY_STATS, 0xa00d, mcs_get_secy_stats, mcs_stats_req, \ 340 mcs_secy_stats) \ 341 M(MCS_GET_SC_STATS, 0xa00e, mcs_get_sc_stats, mcs_stats_req, mcs_sc_stats) \ 342 M(MCS_GET_SA_STATS, 0xa00f, mcs_get_sa_stats, mcs_stats_req, mcs_sa_stats) \ 343 M(MCS_GET_PORT_STATS, 0xa010, mcs_get_port_stats, mcs_stats_req, \ 344 mcs_port_stats) \ 345 M(MCS_CLEAR_STATS, 0xa011, mcs_clear_stats, mcs_clear_stats, msg_rsp) \ 346 M(MCS_INTR_CFG, 0xa012, mcs_intr_cfg, mcs_intr_cfg, msg_rsp) \ 347 M(MCS_SET_LMAC_MODE, 0xa013, mcs_set_lmac_mode, mcs_set_lmac_mode, msg_rsp) \ 348 M(MCS_SET_PN_THRESHOLD, 0xa014, mcs_set_pn_threshold, mcs_set_pn_threshold, \ 349 msg_rsp) \ 350 M(MCS_ALLOC_CTRL_PKT_RULE, 0xa015, mcs_alloc_ctrl_pkt_rule, \ 351 mcs_alloc_ctrl_pkt_rule_req, \ 352 mcs_alloc_ctrl_pkt_rule_rsp) \ 353 M(MCS_FREE_CTRL_PKT_RULE, 0xa016, mcs_free_ctrl_pkt_rule, \ 354 mcs_free_ctrl_pkt_rule_req, msg_rsp) \ 355 M(MCS_CTRL_PKT_RULE_WRITE, 0xa017, mcs_ctrl_pkt_rule_write, \ 356 mcs_ctrl_pkt_rule_write_req, msg_rsp) \ 357 M(MCS_PORT_RESET, 0xa018, mcs_port_reset, mcs_port_reset_req, msg_rsp) \ 358 M(MCS_PORT_CFG_SET, 0xa019, mcs_port_cfg_set, mcs_port_cfg_set_req, msg_rsp)\ 359 M(MCS_PORT_CFG_GET, 0xa020, mcs_port_cfg_get, mcs_port_cfg_get_req, \ 360 mcs_port_cfg_get_rsp) \ 361 M(MCS_CUSTOM_TAG_CFG_GET, 0xa021, mcs_custom_tag_cfg_get, \ 362 mcs_custom_tag_cfg_get_req, \ 363 mcs_custom_tag_cfg_get_rsp) 364 365 /* Messages initiated by AF (range 0xC00 - 0xEFF) */ 366 #define MBOX_UP_CGX_MESSAGES \ 367 M(CGX_LINK_EVENT, 0xC00, cgx_link_event, cgx_link_info_msg, msg_rsp) 368 369 #define MBOX_UP_CPT_MESSAGES \ 370 M(CPT_INST_LMTST, 0xD00, cpt_inst_lmtst, cpt_inst_lmtst_req, msg_rsp) 371 372 #define MBOX_UP_MCS_MESSAGES \ 373 M(MCS_INTR_NOTIFY, 0xE00, mcs_intr_notify, mcs_intr_info, msg_rsp) 374 375 enum { 376 #define M(_name, _id, _1, _2, _3) MBOX_MSG_ ## _name = _id, 377 MBOX_MESSAGES 378 MBOX_UP_CGX_MESSAGES 379 MBOX_UP_CPT_MESSAGES 380 MBOX_UP_MCS_MESSAGES 381 #undef M 382 }; 383 384 /* Mailbox message formats */ 385 386 #define RVU_DEFAULT_PF_FUNC 0xFFFF 387 388 /* Generic request msg used for those mbox messages which 389 * don't send any data in the request. 390 */ 391 struct msg_req { 392 struct mbox_msghdr hdr; 393 }; 394 395 /* Generic response msg used an ack or response for those mbox 396 * messages which don't have a specific rsp msg format. 397 */ 398 struct msg_rsp { 399 struct mbox_msghdr hdr; 400 }; 401 402 /* RVU mailbox error codes 403 * Range 256 - 300. 404 */ 405 enum rvu_af_status { 406 RVU_INVALID_VF_ID = -256, 407 }; 408 409 struct ready_msg_rsp { 410 struct mbox_msghdr hdr; 411 u16 sclk_freq; /* SCLK frequency (in MHz) */ 412 u16 rclk_freq; /* RCLK frequency (in MHz) */ 413 }; 414 415 /* Structure for requesting resource provisioning. 416 * 'modify' flag to be used when either requesting more 417 * or to detach partial of a certain resource type. 418 * Rest of the fields specify how many of what type to 419 * be attached. 420 * To request LFs from two blocks of same type this mailbox 421 * can be sent twice as below: 422 * struct rsrc_attach *attach; 423 * .. Allocate memory for message .. 424 * attach->cptlfs = 3; <3 LFs from CPT0> 425 * .. Send message .. 426 * .. Allocate memory for message .. 427 * attach->modify = 1; 428 * attach->cpt_blkaddr = BLKADDR_CPT1; 429 * attach->cptlfs = 2; <2 LFs from CPT1> 430 * .. Send message .. 431 */ 432 struct rsrc_attach { 433 struct mbox_msghdr hdr; 434 u8 modify:1; 435 u8 npalf:1; 436 u8 nixlf:1; 437 u16 sso; 438 u16 ssow; 439 u16 timlfs; 440 u16 cptlfs; 441 int cpt_blkaddr; /* BLKADDR_CPT0/BLKADDR_CPT1 or 0 for BLKADDR_CPT0 */ 442 }; 443 444 /* Structure for relinquishing resources. 445 * 'partial' flag to be used when relinquishing all resources 446 * but only of a certain type. If not set, all resources of all 447 * types provisioned to the RVU function will be detached. 448 */ 449 struct rsrc_detach { 450 struct mbox_msghdr hdr; 451 u8 partial:1; 452 u8 npalf:1; 453 u8 nixlf:1; 454 u8 sso:1; 455 u8 ssow:1; 456 u8 timlfs:1; 457 u8 cptlfs:1; 458 }; 459 460 /* Number of resources available to the caller. 461 * In reply to MBOX_MSG_FREE_RSRC_CNT. 462 */ 463 struct free_rsrcs_rsp { 464 struct mbox_msghdr hdr; 465 u16 schq[NIX_TXSCH_LVL_CNT]; 466 u16 sso; 467 u16 tim; 468 u16 ssow; 469 u16 cpt; 470 u8 npa; 471 u8 nix; 472 u16 schq_nix1[NIX_TXSCH_LVL_CNT]; 473 u8 nix1; 474 u8 cpt1; 475 u8 ree0; 476 u8 ree1; 477 }; 478 479 #define MSIX_VECTOR_INVALID 0xFFFF 480 #define MAX_RVU_BLKLF_CNT 256 481 482 struct msix_offset_rsp { 483 struct mbox_msghdr hdr; 484 u16 npa_msixoff; 485 u16 nix_msixoff; 486 u16 sso; 487 u16 ssow; 488 u16 timlfs; 489 u16 cptlfs; 490 u16 sso_msixoff[MAX_RVU_BLKLF_CNT]; 491 u16 ssow_msixoff[MAX_RVU_BLKLF_CNT]; 492 u16 timlf_msixoff[MAX_RVU_BLKLF_CNT]; 493 u16 cptlf_msixoff[MAX_RVU_BLKLF_CNT]; 494 u16 cpt1_lfs; 495 u16 ree0_lfs; 496 u16 ree1_lfs; 497 u16 cpt1_lf_msixoff[MAX_RVU_BLKLF_CNT]; 498 u16 ree0_lf_msixoff[MAX_RVU_BLKLF_CNT]; 499 u16 ree1_lf_msixoff[MAX_RVU_BLKLF_CNT]; 500 }; 501 502 struct get_hw_cap_rsp { 503 struct mbox_msghdr hdr; 504 u8 nix_fixed_txschq_mapping; /* Schq mapping fixed or flexible */ 505 u8 nix_shaping; /* Is shaping and coloring supported */ 506 u8 npc_hash_extract; /* Is hash extract supported */ 507 }; 508 509 /* CGX mbox message formats */ 510 511 struct cgx_stats_rsp { 512 struct mbox_msghdr hdr; 513 #define CGX_RX_STATS_COUNT 9 514 #define CGX_TX_STATS_COUNT 18 515 u64 rx_stats[CGX_RX_STATS_COUNT]; 516 u64 tx_stats[CGX_TX_STATS_COUNT]; 517 }; 518 519 struct cgx_fec_stats_rsp { 520 struct mbox_msghdr hdr; 521 u64 fec_corr_blks; 522 u64 fec_uncorr_blks; 523 }; 524 /* Structure for requesting the operation for 525 * setting/getting mac address in the CGX interface 526 */ 527 struct cgx_mac_addr_set_or_get { 528 struct mbox_msghdr hdr; 529 u8 mac_addr[ETH_ALEN]; 530 u32 index; 531 }; 532 533 /* Structure for requesting the operation to 534 * add DMAC filter entry into CGX interface 535 */ 536 struct cgx_mac_addr_add_req { 537 struct mbox_msghdr hdr; 538 u8 mac_addr[ETH_ALEN]; 539 }; 540 541 /* Structure for response against the operation to 542 * add DMAC filter entry into CGX interface 543 */ 544 struct cgx_mac_addr_add_rsp { 545 struct mbox_msghdr hdr; 546 u32 index; 547 }; 548 549 /* Structure for requesting the operation to 550 * delete DMAC filter entry from CGX interface 551 */ 552 struct cgx_mac_addr_del_req { 553 struct mbox_msghdr hdr; 554 u32 index; 555 }; 556 557 /* Structure for response against the operation to 558 * get maximum supported DMAC filter entries 559 */ 560 struct cgx_max_dmac_entries_get_rsp { 561 struct mbox_msghdr hdr; 562 u32 max_dmac_filters; 563 }; 564 565 struct cgx_link_user_info { 566 uint64_t link_up:1; 567 uint64_t full_duplex:1; 568 uint64_t lmac_type_id:4; 569 uint64_t speed:20; /* speed in Mbps */ 570 uint64_t an:1; /* AN supported or not */ 571 uint64_t fec:2; /* FEC type if enabled else 0 */ 572 #define LMACTYPE_STR_LEN 16 573 char lmac_type[LMACTYPE_STR_LEN]; 574 }; 575 576 struct cgx_link_info_msg { 577 struct mbox_msghdr hdr; 578 struct cgx_link_user_info link_info; 579 }; 580 581 struct cgx_pause_frm_cfg { 582 struct mbox_msghdr hdr; 583 u8 set; 584 /* set = 1 if the request is to config pause frames */ 585 /* set = 0 if the request is to fetch pause frames config */ 586 u8 rx_pause; 587 u8 tx_pause; 588 }; 589 590 enum fec_type { 591 OTX2_FEC_NONE, 592 OTX2_FEC_BASER, 593 OTX2_FEC_RS, 594 OTX2_FEC_STATS_CNT = 2, 595 OTX2_FEC_OFF, 596 }; 597 598 struct fec_mode { 599 struct mbox_msghdr hdr; 600 int fec; 601 }; 602 603 struct sfp_eeprom_s { 604 #define SFP_EEPROM_SIZE 256 605 u16 sff_id; 606 u8 buf[SFP_EEPROM_SIZE]; 607 u64 reserved; 608 }; 609 610 struct phy_s { 611 struct { 612 u64 can_change_mod_type:1; 613 u64 mod_type:1; 614 u64 has_fec_stats:1; 615 } misc; 616 struct fec_stats_s { 617 u32 rsfec_corr_cws; 618 u32 rsfec_uncorr_cws; 619 u32 brfec_corr_blks; 620 u32 brfec_uncorr_blks; 621 } fec_stats; 622 }; 623 624 struct cgx_lmac_fwdata_s { 625 u16 rw_valid; 626 u64 supported_fec; 627 u64 supported_an; 628 u64 supported_link_modes; 629 /* only applicable if AN is supported */ 630 u64 advertised_fec; 631 u64 advertised_link_modes; 632 /* Only applicable if SFP/QSFP slot is present */ 633 struct sfp_eeprom_s sfp_eeprom; 634 struct phy_s phy; 635 #define LMAC_FWDATA_RESERVED_MEM 1021 636 u64 reserved[LMAC_FWDATA_RESERVED_MEM]; 637 }; 638 639 struct cgx_fw_data { 640 struct mbox_msghdr hdr; 641 struct cgx_lmac_fwdata_s fwdata; 642 }; 643 644 struct cgx_set_link_mode_args { 645 u32 speed; 646 u8 duplex; 647 u8 an; 648 u8 ports; 649 u64 mode; 650 }; 651 652 struct cgx_set_link_mode_req { 653 #define AUTONEG_UNKNOWN 0xff 654 struct mbox_msghdr hdr; 655 struct cgx_set_link_mode_args args; 656 }; 657 658 struct cgx_set_link_mode_rsp { 659 struct mbox_msghdr hdr; 660 int status; 661 }; 662 663 struct cgx_mac_addr_reset_req { 664 struct mbox_msghdr hdr; 665 u32 index; 666 }; 667 668 struct cgx_mac_addr_update_req { 669 struct mbox_msghdr hdr; 670 u8 mac_addr[ETH_ALEN]; 671 u32 index; 672 }; 673 674 struct cgx_mac_addr_update_rsp { 675 struct mbox_msghdr hdr; 676 u32 index; 677 }; 678 679 #define RVU_LMAC_FEAT_FC BIT_ULL(0) /* pause frames */ 680 #define RVU_LMAC_FEAT_HIGIG2 BIT_ULL(1) 681 /* flow control from physical link higig2 messages */ 682 #define RVU_LMAC_FEAT_PTP BIT_ULL(2) /* precison time protocol */ 683 #define RVU_LMAC_FEAT_DMACF BIT_ULL(3) /* DMAC FILTER */ 684 #define RVU_MAC_VERSION BIT_ULL(4) 685 #define RVU_MAC_CGX BIT_ULL(5) 686 #define RVU_MAC_RPM BIT_ULL(6) 687 688 struct cgx_features_info_msg { 689 struct mbox_msghdr hdr; 690 u64 lmac_features; 691 }; 692 693 struct rpm_stats_rsp { 694 struct mbox_msghdr hdr; 695 #define RPM_RX_STATS_COUNT 43 696 #define RPM_TX_STATS_COUNT 34 697 u64 rx_stats[RPM_RX_STATS_COUNT]; 698 u64 tx_stats[RPM_TX_STATS_COUNT]; 699 }; 700 701 struct cgx_pfc_cfg { 702 struct mbox_msghdr hdr; 703 u8 rx_pause; 704 u8 tx_pause; 705 u16 pfc_en; /* bitmap indicating pfc enabled traffic classes */ 706 }; 707 708 struct cgx_pfc_rsp { 709 struct mbox_msghdr hdr; 710 u8 rx_pause; 711 u8 tx_pause; 712 }; 713 714 /* NPA mbox message formats */ 715 716 struct npc_set_pkind { 717 struct mbox_msghdr hdr; 718 #define OTX2_PRIV_FLAGS_DEFAULT BIT_ULL(0) 719 #define OTX2_PRIV_FLAGS_CUSTOM BIT_ULL(63) 720 u64 mode; 721 #define PKIND_TX BIT_ULL(0) 722 #define PKIND_RX BIT_ULL(1) 723 u8 dir; 724 u8 pkind; /* valid only in case custom flag */ 725 u8 var_len_off; /* Offset of custom header length field. 726 * Valid only for pkind NPC_RX_CUSTOM_PRE_L2_PKIND 727 */ 728 u8 var_len_off_mask; /* Mask for length with in offset */ 729 u8 shift_dir; /* shift direction to get length of the header at var_len_off */ 730 }; 731 732 /* NPA mbox message formats */ 733 734 /* NPA mailbox error codes 735 * Range 301 - 400. 736 */ 737 enum npa_af_status { 738 NPA_AF_ERR_PARAM = -301, 739 NPA_AF_ERR_AQ_FULL = -302, 740 NPA_AF_ERR_AQ_ENQUEUE = -303, 741 NPA_AF_ERR_AF_LF_INVALID = -304, 742 NPA_AF_ERR_AF_LF_ALLOC = -305, 743 NPA_AF_ERR_LF_RESET = -306, 744 }; 745 746 /* For NPA LF context alloc and init */ 747 struct npa_lf_alloc_req { 748 struct mbox_msghdr hdr; 749 int node; 750 int aura_sz; /* No of auras */ 751 u32 nr_pools; /* No of pools */ 752 u64 way_mask; 753 }; 754 755 struct npa_lf_alloc_rsp { 756 struct mbox_msghdr hdr; 757 u32 stack_pg_ptrs; /* No of ptrs per stack page */ 758 u32 stack_pg_bytes; /* Size of stack page */ 759 u16 qints; /* NPA_AF_CONST::QINTS */ 760 u8 cache_lines; /*BATCH ALLOC DMA */ 761 }; 762 763 /* NPA AQ enqueue msg */ 764 struct npa_aq_enq_req { 765 struct mbox_msghdr hdr; 766 u32 aura_id; 767 u8 ctype; 768 u8 op; 769 union { 770 /* Valid when op == WRITE/INIT and ctype == AURA. 771 * LF fills the pool_id in aura.pool_addr. AF will translate 772 * the pool_id to pool context pointer. 773 */ 774 struct npa_aura_s aura; 775 /* Valid when op == WRITE/INIT and ctype == POOL */ 776 struct npa_pool_s pool; 777 }; 778 /* Mask data when op == WRITE (1=write, 0=don't write) */ 779 union { 780 /* Valid when op == WRITE and ctype == AURA */ 781 struct npa_aura_s aura_mask; 782 /* Valid when op == WRITE and ctype == POOL */ 783 struct npa_pool_s pool_mask; 784 }; 785 }; 786 787 struct npa_aq_enq_rsp { 788 struct mbox_msghdr hdr; 789 union { 790 /* Valid when op == READ and ctype == AURA */ 791 struct npa_aura_s aura; 792 /* Valid when op == READ and ctype == POOL */ 793 struct npa_pool_s pool; 794 }; 795 }; 796 797 /* Disable all contexts of type 'ctype' */ 798 struct hwctx_disable_req { 799 struct mbox_msghdr hdr; 800 u8 ctype; 801 }; 802 803 /* NIX mbox message formats */ 804 805 /* NIX mailbox error codes 806 * Range 401 - 500. 807 */ 808 enum nix_af_status { 809 NIX_AF_ERR_PARAM = -401, 810 NIX_AF_ERR_AQ_FULL = -402, 811 NIX_AF_ERR_AQ_ENQUEUE = -403, 812 NIX_AF_ERR_AF_LF_INVALID = -404, 813 NIX_AF_ERR_AF_LF_ALLOC = -405, 814 NIX_AF_ERR_TLX_ALLOC_FAIL = -406, 815 NIX_AF_ERR_TLX_INVALID = -407, 816 NIX_AF_ERR_RSS_SIZE_INVALID = -408, 817 NIX_AF_ERR_RSS_GRPS_INVALID = -409, 818 NIX_AF_ERR_FRS_INVALID = -410, 819 NIX_AF_ERR_RX_LINK_INVALID = -411, 820 NIX_AF_INVAL_TXSCHQ_CFG = -412, 821 NIX_AF_SMQ_FLUSH_FAILED = -413, 822 NIX_AF_ERR_LF_RESET = -414, 823 NIX_AF_ERR_RSS_NOSPC_FIELD = -415, 824 NIX_AF_ERR_RSS_NOSPC_ALGO = -416, 825 NIX_AF_ERR_MARK_CFG_FAIL = -417, 826 NIX_AF_ERR_LSO_CFG_FAIL = -418, 827 NIX_AF_INVAL_NPA_PF_FUNC = -419, 828 NIX_AF_INVAL_SSO_PF_FUNC = -420, 829 NIX_AF_ERR_TX_VTAG_NOSPC = -421, 830 NIX_AF_ERR_RX_VTAG_INUSE = -422, 831 NIX_AF_ERR_PTP_CONFIG_FAIL = -423, 832 NIX_AF_ERR_NPC_KEY_NOT_SUPP = -424, 833 NIX_AF_ERR_INVALID_NIXBLK = -425, 834 NIX_AF_ERR_INVALID_BANDPROF = -426, 835 NIX_AF_ERR_IPOLICER_NOTSUPP = -427, 836 NIX_AF_ERR_BANDPROF_INVAL_REQ = -428, 837 NIX_AF_ERR_CQ_CTX_WRITE_ERR = -429, 838 NIX_AF_ERR_AQ_CTX_RETRY_WRITE = -430, 839 NIX_AF_ERR_LINK_CREDITS = -431, 840 }; 841 842 /* For NIX RX vtag action */ 843 enum nix_rx_vtag0_type { 844 NIX_AF_LFX_RX_VTAG_TYPE0, /* reserved for rx vlan offload */ 845 NIX_AF_LFX_RX_VTAG_TYPE1, 846 NIX_AF_LFX_RX_VTAG_TYPE2, 847 NIX_AF_LFX_RX_VTAG_TYPE3, 848 NIX_AF_LFX_RX_VTAG_TYPE4, 849 NIX_AF_LFX_RX_VTAG_TYPE5, 850 NIX_AF_LFX_RX_VTAG_TYPE6, 851 NIX_AF_LFX_RX_VTAG_TYPE7, 852 }; 853 854 /* For NIX LF context alloc and init */ 855 struct nix_lf_alloc_req { 856 struct mbox_msghdr hdr; 857 int node; 858 u32 rq_cnt; /* No of receive queues */ 859 u32 sq_cnt; /* No of send queues */ 860 u32 cq_cnt; /* No of completion queues */ 861 u8 xqe_sz; 862 u16 rss_sz; 863 u8 rss_grps; 864 u16 npa_func; 865 u16 sso_func; 866 u64 rx_cfg; /* See NIX_AF_LF(0..127)_RX_CFG */ 867 u64 way_mask; 868 #define NIX_LF_RSS_TAG_LSB_AS_ADDER BIT_ULL(0) 869 #define NIX_LF_LBK_BLK_SEL BIT_ULL(1) 870 u64 flags; 871 }; 872 873 struct nix_lf_alloc_rsp { 874 struct mbox_msghdr hdr; 875 u16 sqb_size; 876 u16 rx_chan_base; 877 u16 tx_chan_base; 878 u8 rx_chan_cnt; /* total number of RX channels */ 879 u8 tx_chan_cnt; /* total number of TX channels */ 880 u8 lso_tsov4_idx; 881 u8 lso_tsov6_idx; 882 u8 mac_addr[ETH_ALEN]; 883 u8 lf_rx_stats; /* NIX_AF_CONST1::LF_RX_STATS */ 884 u8 lf_tx_stats; /* NIX_AF_CONST1::LF_TX_STATS */ 885 u16 cints; /* NIX_AF_CONST2::CINTS */ 886 u16 qints; /* NIX_AF_CONST2::QINTS */ 887 u8 cgx_links; /* No. of CGX links present in HW */ 888 u8 lbk_links; /* No. of LBK links present in HW */ 889 u8 sdp_links; /* No. of SDP links present in HW */ 890 u8 tx_link; /* Transmit channel link number */ 891 }; 892 893 struct nix_lf_free_req { 894 struct mbox_msghdr hdr; 895 #define NIX_LF_DISABLE_FLOWS BIT_ULL(0) 896 #define NIX_LF_DONT_FREE_TX_VTAG BIT_ULL(1) 897 u64 flags; 898 }; 899 900 /* CN10K NIX AQ enqueue msg */ 901 struct nix_cn10k_aq_enq_req { 902 struct mbox_msghdr hdr; 903 u32 qidx; 904 u8 ctype; 905 u8 op; 906 union { 907 struct nix_cn10k_rq_ctx_s rq; 908 struct nix_cn10k_sq_ctx_s sq; 909 struct nix_cq_ctx_s cq; 910 struct nix_rsse_s rss; 911 struct nix_rx_mce_s mce; 912 struct nix_bandprof_s prof; 913 }; 914 union { 915 struct nix_cn10k_rq_ctx_s rq_mask; 916 struct nix_cn10k_sq_ctx_s sq_mask; 917 struct nix_cq_ctx_s cq_mask; 918 struct nix_rsse_s rss_mask; 919 struct nix_rx_mce_s mce_mask; 920 struct nix_bandprof_s prof_mask; 921 }; 922 }; 923 924 struct nix_cn10k_aq_enq_rsp { 925 struct mbox_msghdr hdr; 926 union { 927 struct nix_cn10k_rq_ctx_s rq; 928 struct nix_cn10k_sq_ctx_s sq; 929 struct nix_cq_ctx_s cq; 930 struct nix_rsse_s rss; 931 struct nix_rx_mce_s mce; 932 struct nix_bandprof_s prof; 933 }; 934 }; 935 936 /* NIX AQ enqueue msg */ 937 struct nix_aq_enq_req { 938 struct mbox_msghdr hdr; 939 u32 qidx; 940 u8 ctype; 941 u8 op; 942 union { 943 struct nix_rq_ctx_s rq; 944 struct nix_sq_ctx_s sq; 945 struct nix_cq_ctx_s cq; 946 struct nix_rsse_s rss; 947 struct nix_rx_mce_s mce; 948 struct nix_bandprof_s prof; 949 }; 950 union { 951 struct nix_rq_ctx_s rq_mask; 952 struct nix_sq_ctx_s sq_mask; 953 struct nix_cq_ctx_s cq_mask; 954 struct nix_rsse_s rss_mask; 955 struct nix_rx_mce_s mce_mask; 956 struct nix_bandprof_s prof_mask; 957 }; 958 }; 959 960 struct nix_aq_enq_rsp { 961 struct mbox_msghdr hdr; 962 union { 963 struct nix_rq_ctx_s rq; 964 struct nix_sq_ctx_s sq; 965 struct nix_cq_ctx_s cq; 966 struct nix_rsse_s rss; 967 struct nix_rx_mce_s mce; 968 struct nix_bandprof_s prof; 969 }; 970 }; 971 972 /* Tx scheduler/shaper mailbox messages */ 973 974 #define MAX_TXSCHQ_PER_FUNC 128 975 976 struct nix_txsch_alloc_req { 977 struct mbox_msghdr hdr; 978 /* Scheduler queue count request at each level */ 979 u16 schq_contig[NIX_TXSCH_LVL_CNT]; /* No of contiguous queues */ 980 u16 schq[NIX_TXSCH_LVL_CNT]; /* No of non-contiguous queues */ 981 }; 982 983 struct nix_txsch_alloc_rsp { 984 struct mbox_msghdr hdr; 985 /* Scheduler queue count allocated at each level */ 986 u16 schq_contig[NIX_TXSCH_LVL_CNT]; 987 u16 schq[NIX_TXSCH_LVL_CNT]; 988 /* Scheduler queue list allocated at each level */ 989 u16 schq_contig_list[NIX_TXSCH_LVL_CNT][MAX_TXSCHQ_PER_FUNC]; 990 u16 schq_list[NIX_TXSCH_LVL_CNT][MAX_TXSCHQ_PER_FUNC]; 991 u8 aggr_level; /* Traffic aggregation scheduler level */ 992 u8 aggr_lvl_rr_prio; /* Aggregation lvl's RR_PRIO config */ 993 u8 link_cfg_lvl; /* LINKX_CFG CSRs mapped to TL3 or TL2's index ? */ 994 }; 995 996 struct nix_txsch_free_req { 997 struct mbox_msghdr hdr; 998 #define TXSCHQ_FREE_ALL BIT_ULL(0) 999 u16 flags; 1000 /* Scheduler queue level to be freed */ 1001 u16 schq_lvl; 1002 /* List of scheduler queues to be freed */ 1003 u16 schq; 1004 }; 1005 1006 struct nix_txschq_config { 1007 struct mbox_msghdr hdr; 1008 u8 lvl; /* SMQ/MDQ/TL4/TL3/TL2/TL1 */ 1009 u8 read; 1010 #define TXSCHQ_IDX_SHIFT 16 1011 #define TXSCHQ_IDX_MASK (BIT_ULL(10) - 1) 1012 #define TXSCHQ_IDX(reg, shift) (((reg) >> (shift)) & TXSCHQ_IDX_MASK) 1013 u8 num_regs; 1014 #define MAX_REGS_PER_MBOX_MSG 20 1015 u64 reg[MAX_REGS_PER_MBOX_MSG]; 1016 u64 regval[MAX_REGS_PER_MBOX_MSG]; 1017 /* All 0's => overwrite with new value */ 1018 u64 regval_mask[MAX_REGS_PER_MBOX_MSG]; 1019 }; 1020 1021 struct nix_vtag_config { 1022 struct mbox_msghdr hdr; 1023 /* '0' for 4 octet VTAG, '1' for 8 octet VTAG */ 1024 u8 vtag_size; 1025 /* cfg_type is '0' for tx vlan cfg 1026 * cfg_type is '1' for rx vlan cfg 1027 */ 1028 u8 cfg_type; 1029 union { 1030 /* valid when cfg_type is '0' */ 1031 struct { 1032 u64 vtag0; 1033 u64 vtag1; 1034 1035 /* cfg_vtag0 & cfg_vtag1 fields are valid 1036 * when free_vtag0 & free_vtag1 are '0's. 1037 */ 1038 /* cfg_vtag0 = 1 to configure vtag0 */ 1039 u8 cfg_vtag0 :1; 1040 /* cfg_vtag1 = 1 to configure vtag1 */ 1041 u8 cfg_vtag1 :1; 1042 1043 /* vtag0_idx & vtag1_idx are only valid when 1044 * both cfg_vtag0 & cfg_vtag1 are '0's, 1045 * these fields are used along with free_vtag0 1046 * & free_vtag1 to free the nix lf's tx_vlan 1047 * configuration. 1048 * 1049 * Denotes the indices of tx_vtag def registers 1050 * that needs to be cleared and freed. 1051 */ 1052 int vtag0_idx; 1053 int vtag1_idx; 1054 1055 /* free_vtag0 & free_vtag1 fields are valid 1056 * when cfg_vtag0 & cfg_vtag1 are '0's. 1057 */ 1058 /* free_vtag0 = 1 clears vtag0 configuration 1059 * vtag0_idx denotes the index to be cleared. 1060 */ 1061 u8 free_vtag0 :1; 1062 /* free_vtag1 = 1 clears vtag1 configuration 1063 * vtag1_idx denotes the index to be cleared. 1064 */ 1065 u8 free_vtag1 :1; 1066 } tx; 1067 1068 /* valid when cfg_type is '1' */ 1069 struct { 1070 /* rx vtag type index, valid values are in 0..7 range */ 1071 u8 vtag_type; 1072 /* rx vtag strip */ 1073 u8 strip_vtag :1; 1074 /* rx vtag capture */ 1075 u8 capture_vtag :1; 1076 } rx; 1077 }; 1078 }; 1079 1080 struct nix_vtag_config_rsp { 1081 struct mbox_msghdr hdr; 1082 int vtag0_idx; 1083 int vtag1_idx; 1084 /* Indices of tx_vtag def registers used to configure 1085 * tx vtag0 & vtag1 headers, these indices are valid 1086 * when nix_vtag_config mbox requested for vtag0 and/ 1087 * or vtag1 configuration. 1088 */ 1089 }; 1090 1091 #define NIX_FLOW_KEY_TYPE_L3_L4_MASK (~(0xf << 28)) 1092 1093 struct nix_rss_flowkey_cfg { 1094 struct mbox_msghdr hdr; 1095 int mcam_index; /* MCAM entry index to modify */ 1096 #define NIX_FLOW_KEY_TYPE_PORT BIT(0) 1097 #define NIX_FLOW_KEY_TYPE_IPV4 BIT(1) 1098 #define NIX_FLOW_KEY_TYPE_IPV6 BIT(2) 1099 #define NIX_FLOW_KEY_TYPE_TCP BIT(3) 1100 #define NIX_FLOW_KEY_TYPE_UDP BIT(4) 1101 #define NIX_FLOW_KEY_TYPE_SCTP BIT(5) 1102 #define NIX_FLOW_KEY_TYPE_NVGRE BIT(6) 1103 #define NIX_FLOW_KEY_TYPE_VXLAN BIT(7) 1104 #define NIX_FLOW_KEY_TYPE_GENEVE BIT(8) 1105 #define NIX_FLOW_KEY_TYPE_ETH_DMAC BIT(9) 1106 #define NIX_FLOW_KEY_TYPE_IPV6_EXT BIT(10) 1107 #define NIX_FLOW_KEY_TYPE_GTPU BIT(11) 1108 #define NIX_FLOW_KEY_TYPE_INNR_IPV4 BIT(12) 1109 #define NIX_FLOW_KEY_TYPE_INNR_IPV6 BIT(13) 1110 #define NIX_FLOW_KEY_TYPE_INNR_TCP BIT(14) 1111 #define NIX_FLOW_KEY_TYPE_INNR_UDP BIT(15) 1112 #define NIX_FLOW_KEY_TYPE_INNR_SCTP BIT(16) 1113 #define NIX_FLOW_KEY_TYPE_INNR_ETH_DMAC BIT(17) 1114 #define NIX_FLOW_KEY_TYPE_VLAN BIT(20) 1115 #define NIX_FLOW_KEY_TYPE_IPV4_PROTO BIT(21) 1116 #define NIX_FLOW_KEY_TYPE_AH BIT(22) 1117 #define NIX_FLOW_KEY_TYPE_ESP BIT(23) 1118 #define NIX_FLOW_KEY_TYPE_L4_DST_ONLY BIT(28) 1119 #define NIX_FLOW_KEY_TYPE_L4_SRC_ONLY BIT(29) 1120 #define NIX_FLOW_KEY_TYPE_L3_DST_ONLY BIT(30) 1121 #define NIX_FLOW_KEY_TYPE_L3_SRC_ONLY BIT(31) 1122 u32 flowkey_cfg; /* Flowkey types selected */ 1123 u8 group; /* RSS context or group */ 1124 }; 1125 1126 struct nix_rss_flowkey_cfg_rsp { 1127 struct mbox_msghdr hdr; 1128 u8 alg_idx; /* Selected algo index */ 1129 }; 1130 1131 struct nix_set_mac_addr { 1132 struct mbox_msghdr hdr; 1133 u8 mac_addr[ETH_ALEN]; /* MAC address to be set for this pcifunc */ 1134 }; 1135 1136 struct nix_get_mac_addr_rsp { 1137 struct mbox_msghdr hdr; 1138 u8 mac_addr[ETH_ALEN]; 1139 }; 1140 1141 struct nix_mark_format_cfg { 1142 struct mbox_msghdr hdr; 1143 u8 offset; 1144 u8 y_mask; 1145 u8 y_val; 1146 u8 r_mask; 1147 u8 r_val; 1148 }; 1149 1150 struct nix_mark_format_cfg_rsp { 1151 struct mbox_msghdr hdr; 1152 u8 mark_format_idx; 1153 }; 1154 1155 struct nix_rx_mode { 1156 struct mbox_msghdr hdr; 1157 #define NIX_RX_MODE_UCAST BIT(0) 1158 #define NIX_RX_MODE_PROMISC BIT(1) 1159 #define NIX_RX_MODE_ALLMULTI BIT(2) 1160 #define NIX_RX_MODE_USE_MCE BIT(3) 1161 u16 mode; 1162 }; 1163 1164 struct nix_rx_cfg { 1165 struct mbox_msghdr hdr; 1166 #define NIX_RX_OL3_VERIFY BIT(0) 1167 #define NIX_RX_OL4_VERIFY BIT(1) 1168 #define NIX_RX_DROP_RE BIT(2) 1169 u8 len_verify; /* Outer L3/L4 len check */ 1170 #define NIX_RX_CSUM_OL4_VERIFY BIT(0) 1171 u8 csum_verify; /* Outer L4 checksum verification */ 1172 }; 1173 1174 struct nix_frs_cfg { 1175 struct mbox_msghdr hdr; 1176 u8 update_smq; /* Update SMQ's min/max lens */ 1177 u8 update_minlen; /* Set minlen also */ 1178 u8 sdp_link; /* Set SDP RX link */ 1179 u16 maxlen; 1180 u16 minlen; 1181 }; 1182 1183 struct nix_lso_format_cfg { 1184 struct mbox_msghdr hdr; 1185 u64 field_mask; 1186 #define NIX_LSO_FIELD_MAX 8 1187 u64 fields[NIX_LSO_FIELD_MAX]; 1188 }; 1189 1190 struct nix_lso_format_cfg_rsp { 1191 struct mbox_msghdr hdr; 1192 u8 lso_format_idx; 1193 }; 1194 1195 struct nix_bp_cfg_req { 1196 struct mbox_msghdr hdr; 1197 u16 chan_base; /* Starting channel number */ 1198 u8 chan_cnt; /* Number of channels */ 1199 u8 bpid_per_chan; 1200 /* bpid_per_chan = 0 assigns single bp id for range of channels */ 1201 /* bpid_per_chan = 1 assigns separate bp id for each channel */ 1202 }; 1203 1204 /* PF can be mapped to either CGX or LBK interface, 1205 * so maximum 64 channels are possible. 1206 */ 1207 #define NIX_MAX_BPID_CHAN 64 1208 struct nix_bp_cfg_rsp { 1209 struct mbox_msghdr hdr; 1210 u16 chan_bpid[NIX_MAX_BPID_CHAN]; /* Channel and bpid mapping */ 1211 u8 chan_cnt; /* Number of channel for which bpids are assigned */ 1212 }; 1213 1214 /* Global NIX inline IPSec configuration */ 1215 struct nix_inline_ipsec_cfg { 1216 struct mbox_msghdr hdr; 1217 u32 cpt_credit; 1218 struct { 1219 u8 egrp; 1220 u16 opcode; 1221 u16 param1; 1222 u16 param2; 1223 } gen_cfg; 1224 struct { 1225 u16 cpt_pf_func; 1226 u8 cpt_slot; 1227 } inst_qsel; 1228 u8 enable; 1229 u16 bpid; 1230 u32 credit_th; 1231 }; 1232 1233 /* Per NIX LF inline IPSec configuration */ 1234 struct nix_inline_ipsec_lf_cfg { 1235 struct mbox_msghdr hdr; 1236 u64 sa_base_addr; 1237 struct { 1238 u32 tag_const; 1239 u16 lenm1_max; 1240 u8 sa_pow2_size; 1241 u8 tt; 1242 } ipsec_cfg0; 1243 struct { 1244 u32 sa_idx_max; 1245 u8 sa_idx_w; 1246 } ipsec_cfg1; 1247 u8 enable; 1248 }; 1249 1250 struct nix_hw_info { 1251 struct mbox_msghdr hdr; 1252 u16 rsvs16; 1253 u16 max_mtu; 1254 u16 min_mtu; 1255 u32 rpm_dwrr_mtu; 1256 u32 sdp_dwrr_mtu; 1257 u32 lbk_dwrr_mtu; 1258 u32 rsvd32[1]; 1259 u64 rsvd[15]; /* Add reserved fields for future expansion */ 1260 }; 1261 1262 struct nix_bandprof_alloc_req { 1263 struct mbox_msghdr hdr; 1264 /* Count of profiles needed per layer */ 1265 u16 prof_count[BAND_PROF_NUM_LAYERS]; 1266 }; 1267 1268 struct nix_bandprof_alloc_rsp { 1269 struct mbox_msghdr hdr; 1270 u16 prof_count[BAND_PROF_NUM_LAYERS]; 1271 1272 /* There is no need to allocate morethan 1 bandwidth profile 1273 * per RQ of a PF_FUNC's NIXLF. So limit the maximum 1274 * profiles to 64 per PF_FUNC. 1275 */ 1276 #define MAX_BANDPROF_PER_PFFUNC 64 1277 u16 prof_idx[BAND_PROF_NUM_LAYERS][MAX_BANDPROF_PER_PFFUNC]; 1278 }; 1279 1280 struct nix_bandprof_free_req { 1281 struct mbox_msghdr hdr; 1282 u8 free_all; 1283 u16 prof_count[BAND_PROF_NUM_LAYERS]; 1284 u16 prof_idx[BAND_PROF_NUM_LAYERS][MAX_BANDPROF_PER_PFFUNC]; 1285 }; 1286 1287 struct nix_bandprof_get_hwinfo_rsp { 1288 struct mbox_msghdr hdr; 1289 u16 prof_count[BAND_PROF_NUM_LAYERS]; 1290 u32 policer_timeunit; 1291 }; 1292 1293 /* NPC mbox message structs */ 1294 1295 #define NPC_MCAM_ENTRY_INVALID 0xFFFF 1296 #define NPC_MCAM_INVALID_MAP 0xFFFF 1297 1298 /* NPC mailbox error codes 1299 * Range 701 - 800. 1300 */ 1301 enum npc_af_status { 1302 NPC_MCAM_INVALID_REQ = -701, 1303 NPC_MCAM_ALLOC_DENIED = -702, 1304 NPC_MCAM_ALLOC_FAILED = -703, 1305 NPC_MCAM_PERM_DENIED = -704, 1306 NPC_FLOW_INTF_INVALID = -707, 1307 NPC_FLOW_CHAN_INVALID = -708, 1308 NPC_FLOW_NO_NIXLF = -709, 1309 NPC_FLOW_NOT_SUPPORTED = -710, 1310 NPC_FLOW_VF_PERM_DENIED = -711, 1311 NPC_FLOW_VF_NOT_INIT = -712, 1312 NPC_FLOW_VF_OVERLAP = -713, 1313 }; 1314 1315 struct npc_mcam_alloc_entry_req { 1316 struct mbox_msghdr hdr; 1317 #define NPC_MAX_NONCONTIG_ENTRIES 256 1318 u8 contig; /* Contiguous entries ? */ 1319 #define NPC_MCAM_ANY_PRIO 0 1320 #define NPC_MCAM_LOWER_PRIO 1 1321 #define NPC_MCAM_HIGHER_PRIO 2 1322 u8 priority; /* Lower or higher w.r.t ref_entry */ 1323 u16 ref_entry; 1324 u16 count; /* Number of entries requested */ 1325 }; 1326 1327 struct npc_mcam_alloc_entry_rsp { 1328 struct mbox_msghdr hdr; 1329 u16 entry; /* Entry allocated or start index if contiguous. 1330 * Invalid incase of non-contiguous. 1331 */ 1332 u16 count; /* Number of entries allocated */ 1333 u16 free_count; /* Number of entries available */ 1334 u16 entry_list[NPC_MAX_NONCONTIG_ENTRIES]; 1335 }; 1336 1337 struct npc_mcam_free_entry_req { 1338 struct mbox_msghdr hdr; 1339 u16 entry; /* Entry index to be freed */ 1340 u8 all; /* If all entries allocated to this PFVF to be freed */ 1341 }; 1342 1343 struct mcam_entry { 1344 #define NPC_MAX_KWS_IN_KEY 7 /* Number of keywords in max keywidth */ 1345 u64 kw[NPC_MAX_KWS_IN_KEY]; 1346 u64 kw_mask[NPC_MAX_KWS_IN_KEY]; 1347 u64 action; 1348 u64 vtag_action; 1349 }; 1350 1351 struct npc_mcam_write_entry_req { 1352 struct mbox_msghdr hdr; 1353 struct mcam_entry entry_data; 1354 u16 entry; /* MCAM entry to write this match key */ 1355 u16 cntr; /* Counter for this MCAM entry */ 1356 u8 intf; /* Rx or Tx interface */ 1357 u8 enable_entry;/* Enable this MCAM entry ? */ 1358 u8 set_cntr; /* Set counter for this entry ? */ 1359 }; 1360 1361 /* Enable/Disable a given entry */ 1362 struct npc_mcam_ena_dis_entry_req { 1363 struct mbox_msghdr hdr; 1364 u16 entry; 1365 }; 1366 1367 struct npc_mcam_shift_entry_req { 1368 struct mbox_msghdr hdr; 1369 #define NPC_MCAM_MAX_SHIFTS 64 1370 u16 curr_entry[NPC_MCAM_MAX_SHIFTS]; 1371 u16 new_entry[NPC_MCAM_MAX_SHIFTS]; 1372 u16 shift_count; /* Number of entries to shift */ 1373 }; 1374 1375 struct npc_mcam_shift_entry_rsp { 1376 struct mbox_msghdr hdr; 1377 u16 failed_entry_idx; /* Index in 'curr_entry', not entry itself */ 1378 }; 1379 1380 struct npc_mcam_alloc_counter_req { 1381 struct mbox_msghdr hdr; 1382 u8 contig; /* Contiguous counters ? */ 1383 #define NPC_MAX_NONCONTIG_COUNTERS 64 1384 u16 count; /* Number of counters requested */ 1385 }; 1386 1387 struct npc_mcam_alloc_counter_rsp { 1388 struct mbox_msghdr hdr; 1389 u16 cntr; /* Counter allocated or start index if contiguous. 1390 * Invalid incase of non-contiguous. 1391 */ 1392 u16 count; /* Number of counters allocated */ 1393 u16 cntr_list[NPC_MAX_NONCONTIG_COUNTERS]; 1394 }; 1395 1396 struct npc_mcam_oper_counter_req { 1397 struct mbox_msghdr hdr; 1398 u16 cntr; /* Free a counter or clear/fetch it's stats */ 1399 }; 1400 1401 struct npc_mcam_oper_counter_rsp { 1402 struct mbox_msghdr hdr; 1403 u64 stat; /* valid only while fetching counter's stats */ 1404 }; 1405 1406 struct npc_mcam_unmap_counter_req { 1407 struct mbox_msghdr hdr; 1408 u16 cntr; 1409 u16 entry; /* Entry and counter to be unmapped */ 1410 u8 all; /* Unmap all entries using this counter ? */ 1411 }; 1412 1413 struct npc_mcam_alloc_and_write_entry_req { 1414 struct mbox_msghdr hdr; 1415 struct mcam_entry entry_data; 1416 u16 ref_entry; 1417 u8 priority; /* Lower or higher w.r.t ref_entry */ 1418 u8 intf; /* Rx or Tx interface */ 1419 u8 enable_entry;/* Enable this MCAM entry ? */ 1420 u8 alloc_cntr; /* Allocate counter and map ? */ 1421 }; 1422 1423 struct npc_mcam_alloc_and_write_entry_rsp { 1424 struct mbox_msghdr hdr; 1425 u16 entry; 1426 u16 cntr; 1427 }; 1428 1429 struct npc_get_kex_cfg_rsp { 1430 struct mbox_msghdr hdr; 1431 u64 rx_keyx_cfg; /* NPC_AF_INTF(0)_KEX_CFG */ 1432 u64 tx_keyx_cfg; /* NPC_AF_INTF(1)_KEX_CFG */ 1433 #define NPC_MAX_INTF 2 1434 #define NPC_MAX_LID 8 1435 #define NPC_MAX_LT 16 1436 #define NPC_MAX_LD 2 1437 #define NPC_MAX_LFL 16 1438 /* NPC_AF_KEX_LDATA(0..1)_FLAGS_CFG */ 1439 u64 kex_ld_flags[NPC_MAX_LD]; 1440 /* NPC_AF_INTF(0..1)_LID(0..7)_LT(0..15)_LD(0..1)_CFG */ 1441 u64 intf_lid_lt_ld[NPC_MAX_INTF][NPC_MAX_LID][NPC_MAX_LT][NPC_MAX_LD]; 1442 /* NPC_AF_INTF(0..1)_LDATA(0..1)_FLAGS(0..15)_CFG */ 1443 u64 intf_ld_flags[NPC_MAX_INTF][NPC_MAX_LD][NPC_MAX_LFL]; 1444 #define MKEX_NAME_LEN 128 1445 u8 mkex_pfl_name[MKEX_NAME_LEN]; 1446 }; 1447 1448 struct ptp_get_cap_rsp { 1449 struct mbox_msghdr hdr; 1450 #define PTP_CAP_HW_ATOMIC_UPDATE BIT_ULL(0) 1451 u64 cap; 1452 }; 1453 1454 struct flow_msg { 1455 unsigned char dmac[6]; 1456 unsigned char smac[6]; 1457 __be16 etype; 1458 __be16 vlan_etype; 1459 __be16 vlan_tci; 1460 union { 1461 __be32 ip4src; 1462 __be32 ip6src[4]; 1463 }; 1464 union { 1465 __be32 ip4dst; 1466 __be32 ip6dst[4]; 1467 }; 1468 union { 1469 __be32 spi; 1470 }; 1471 1472 u8 tos; 1473 u8 ip_ver; 1474 u8 ip_proto; 1475 u8 tc; 1476 __be16 sport; 1477 __be16 dport; 1478 union { 1479 u8 ip_flag; 1480 u8 next_header; 1481 }; 1482 __be16 vlan_itci; 1483 }; 1484 1485 struct npc_install_flow_req { 1486 struct mbox_msghdr hdr; 1487 struct flow_msg packet; 1488 struct flow_msg mask; 1489 u64 features; 1490 u16 entry; 1491 u16 channel; 1492 u16 chan_mask; 1493 u8 intf; 1494 u8 set_cntr; /* If counter is available set counter for this entry ? */ 1495 u8 default_rule; 1496 u8 append; /* overwrite(0) or append(1) flow to default rule? */ 1497 u16 vf; 1498 /* action */ 1499 u32 index; 1500 u16 match_id; 1501 u8 flow_key_alg; 1502 u8 op; 1503 /* vtag rx action */ 1504 u8 vtag0_type; 1505 u8 vtag0_valid; 1506 u8 vtag1_type; 1507 u8 vtag1_valid; 1508 /* vtag tx action */ 1509 u16 vtag0_def; 1510 u8 vtag0_op; 1511 u16 vtag1_def; 1512 u8 vtag1_op; 1513 /* old counter value */ 1514 u16 cntr_val; 1515 }; 1516 1517 struct npc_install_flow_rsp { 1518 struct mbox_msghdr hdr; 1519 int counter; /* negative if no counter else counter number */ 1520 }; 1521 1522 struct npc_delete_flow_req { 1523 struct mbox_msghdr hdr; 1524 u16 entry; 1525 u16 start;/*Disable range of entries */ 1526 u16 end; 1527 u8 all; /* PF + VFs */ 1528 }; 1529 1530 struct npc_delete_flow_rsp { 1531 struct mbox_msghdr hdr; 1532 u16 cntr_val; 1533 }; 1534 1535 struct npc_mcam_read_entry_req { 1536 struct mbox_msghdr hdr; 1537 u16 entry; /* MCAM entry to read */ 1538 }; 1539 1540 struct npc_mcam_read_entry_rsp { 1541 struct mbox_msghdr hdr; 1542 struct mcam_entry entry_data; 1543 u8 intf; 1544 u8 enable; 1545 }; 1546 1547 struct npc_mcam_read_base_rule_rsp { 1548 struct mbox_msghdr hdr; 1549 struct mcam_entry entry; 1550 }; 1551 1552 struct npc_mcam_get_stats_req { 1553 struct mbox_msghdr hdr; 1554 u16 entry; /* mcam entry */ 1555 }; 1556 1557 struct npc_mcam_get_stats_rsp { 1558 struct mbox_msghdr hdr; 1559 u64 stat; /* counter stats */ 1560 u8 stat_ena; /* enabled */ 1561 }; 1562 1563 struct npc_get_field_hash_info_req { 1564 struct mbox_msghdr hdr; 1565 u8 intf; 1566 }; 1567 1568 struct npc_get_field_hash_info_rsp { 1569 struct mbox_msghdr hdr; 1570 u64 secret_key[3]; 1571 #define NPC_MAX_HASH 2 1572 #define NPC_MAX_HASH_MASK 2 1573 /* NPC_AF_INTF(0..1)_HASH(0..1)_MASK(0..1) */ 1574 u64 hash_mask[NPC_MAX_INTF][NPC_MAX_HASH][NPC_MAX_HASH_MASK]; 1575 /* NPC_AF_INTF(0..1)_HASH(0..1)_RESULT_CTRL */ 1576 u64 hash_ctrl[NPC_MAX_INTF][NPC_MAX_HASH]; 1577 }; 1578 1579 enum ptp_op { 1580 PTP_OP_ADJFINE = 0, 1581 PTP_OP_GET_CLOCK = 1, 1582 PTP_OP_GET_TSTMP = 2, 1583 PTP_OP_SET_THRESH = 3, 1584 PTP_OP_EXTTS_ON = 4, 1585 PTP_OP_ADJTIME = 5, 1586 PTP_OP_SET_CLOCK = 6, 1587 }; 1588 1589 struct ptp_req { 1590 struct mbox_msghdr hdr; 1591 u8 op; 1592 s64 scaled_ppm; 1593 u64 thresh; 1594 int extts_on; 1595 s64 delta; 1596 u64 clk; 1597 }; 1598 1599 struct ptp_rsp { 1600 struct mbox_msghdr hdr; 1601 u64 clk; 1602 u64 tsc; 1603 }; 1604 1605 struct npc_get_field_status_req { 1606 struct mbox_msghdr hdr; 1607 u8 intf; 1608 u8 field; 1609 }; 1610 1611 struct npc_get_field_status_rsp { 1612 struct mbox_msghdr hdr; 1613 u8 enable; 1614 }; 1615 1616 struct set_vf_perm { 1617 struct mbox_msghdr hdr; 1618 u16 vf; 1619 #define RESET_VF_PERM BIT_ULL(0) 1620 #define VF_TRUSTED BIT_ULL(1) 1621 u64 flags; 1622 }; 1623 1624 struct lmtst_tbl_setup_req { 1625 struct mbox_msghdr hdr; 1626 u64 dis_sched_early_comp :1; 1627 u64 sch_ena :1; 1628 u64 dis_line_pref :1; 1629 u64 ssow_pf_func :13; 1630 u16 base_pcifunc; 1631 u8 use_local_lmt_region; 1632 u64 lmt_iova; 1633 u64 rsvd[4]; 1634 }; 1635 1636 /* CPT mailbox error codes 1637 * Range 901 - 1000. 1638 */ 1639 enum cpt_af_status { 1640 CPT_AF_ERR_PARAM = -901, 1641 CPT_AF_ERR_GRP_INVALID = -902, 1642 CPT_AF_ERR_LF_INVALID = -903, 1643 CPT_AF_ERR_ACCESS_DENIED = -904, 1644 CPT_AF_ERR_SSO_PF_FUNC_INVALID = -905, 1645 CPT_AF_ERR_NIX_PF_FUNC_INVALID = -906, 1646 CPT_AF_ERR_INLINE_IPSEC_INB_ENA = -907, 1647 CPT_AF_ERR_INLINE_IPSEC_OUT_ENA = -908 1648 }; 1649 1650 /* CPT mbox message formats */ 1651 struct cpt_rd_wr_reg_msg { 1652 struct mbox_msghdr hdr; 1653 u64 reg_offset; 1654 u64 *ret_val; 1655 u64 val; 1656 u8 is_write; 1657 int blkaddr; 1658 }; 1659 1660 struct cpt_lf_alloc_req_msg { 1661 struct mbox_msghdr hdr; 1662 u16 nix_pf_func; 1663 u16 sso_pf_func; 1664 u16 eng_grpmsk; 1665 u8 blkaddr; 1666 u8 ctx_ilen_valid : 1; 1667 u8 ctx_ilen : 7; 1668 }; 1669 1670 #define CPT_INLINE_INBOUND 0 1671 #define CPT_INLINE_OUTBOUND 1 1672 1673 /* Mailbox message request format for CPT IPsec 1674 * inline inbound and outbound configuration. 1675 */ 1676 struct cpt_inline_ipsec_cfg_msg { 1677 struct mbox_msghdr hdr; 1678 u8 enable; 1679 u8 slot; 1680 u8 dir; 1681 u8 sso_pf_func_ovrd; 1682 u16 sso_pf_func; /* inbound path SSO_PF_FUNC */ 1683 u16 nix_pf_func; /* outbound path NIX_PF_FUNC */ 1684 }; 1685 1686 /* Mailbox message request and response format for CPT stats. */ 1687 struct cpt_sts_req { 1688 struct mbox_msghdr hdr; 1689 u8 blkaddr; 1690 }; 1691 1692 struct cpt_sts_rsp { 1693 struct mbox_msghdr hdr; 1694 u64 inst_req_pc; 1695 u64 inst_lat_pc; 1696 u64 rd_req_pc; 1697 u64 rd_lat_pc; 1698 u64 rd_uc_pc; 1699 u64 active_cycles_pc; 1700 u64 ctx_mis_pc; 1701 u64 ctx_hit_pc; 1702 u64 ctx_aop_pc; 1703 u64 ctx_aop_lat_pc; 1704 u64 ctx_ifetch_pc; 1705 u64 ctx_ifetch_lat_pc; 1706 u64 ctx_ffetch_pc; 1707 u64 ctx_ffetch_lat_pc; 1708 u64 ctx_wback_pc; 1709 u64 ctx_wback_lat_pc; 1710 u64 ctx_psh_pc; 1711 u64 ctx_psh_lat_pc; 1712 u64 ctx_err; 1713 u64 ctx_enc_id; 1714 u64 ctx_flush_timer; 1715 u64 rxc_time; 1716 u64 rxc_time_cfg; 1717 u64 rxc_active_sts; 1718 u64 rxc_zombie_sts; 1719 u64 busy_sts_ae; 1720 u64 free_sts_ae; 1721 u64 busy_sts_se; 1722 u64 free_sts_se; 1723 u64 busy_sts_ie; 1724 u64 free_sts_ie; 1725 u64 exe_err_info; 1726 u64 cptclk_cnt; 1727 u64 diag; 1728 u64 rxc_dfrg; 1729 u64 x2p_link_cfg0; 1730 u64 x2p_link_cfg1; 1731 }; 1732 1733 /* Mailbox message request format to configure reassembly timeout. */ 1734 struct cpt_rxc_time_cfg_req { 1735 struct mbox_msghdr hdr; 1736 int blkaddr; 1737 u32 step; 1738 u16 zombie_thres; 1739 u16 zombie_limit; 1740 u16 active_thres; 1741 u16 active_limit; 1742 }; 1743 1744 /* Mailbox message request format to request for CPT_INST_S lmtst. */ 1745 struct cpt_inst_lmtst_req { 1746 struct mbox_msghdr hdr; 1747 u64 inst[8]; 1748 u64 rsvd; 1749 }; 1750 1751 /* Mailbox message format to request for CPT LF reset */ 1752 struct cpt_lf_rst_req { 1753 struct mbox_msghdr hdr; 1754 u32 slot; 1755 u32 rsvd; 1756 }; 1757 1758 /* Mailbox message format to request for CPT faulted engines */ 1759 struct cpt_flt_eng_info_req { 1760 struct mbox_msghdr hdr; 1761 int blkaddr; 1762 bool reset; 1763 u32 rsvd; 1764 }; 1765 1766 struct cpt_flt_eng_info_rsp { 1767 struct mbox_msghdr hdr; 1768 u64 flt_eng_map[CPT_10K_AF_INT_VEC_RVU]; 1769 u64 rcvrd_eng_map[CPT_10K_AF_INT_VEC_RVU]; 1770 u64 rsvd; 1771 }; 1772 1773 struct sdp_node_info { 1774 /* Node to which this PF belons to */ 1775 u8 node_id; 1776 u8 max_vfs; 1777 u8 num_pf_rings; 1778 u8 pf_srn; 1779 #define SDP_MAX_VFS 128 1780 u8 vf_rings[SDP_MAX_VFS]; 1781 }; 1782 1783 struct sdp_chan_info_msg { 1784 struct mbox_msghdr hdr; 1785 struct sdp_node_info info; 1786 }; 1787 1788 struct sdp_get_chan_info_msg { 1789 struct mbox_msghdr hdr; 1790 u16 chan_base; 1791 u16 num_chan; 1792 }; 1793 1794 /* CGX mailbox error codes 1795 * Range 1101 - 1200. 1796 */ 1797 enum cgx_af_status { 1798 LMAC_AF_ERR_INVALID_PARAM = -1101, 1799 LMAC_AF_ERR_PF_NOT_MAPPED = -1102, 1800 LMAC_AF_ERR_PERM_DENIED = -1103, 1801 LMAC_AF_ERR_PFC_ENADIS_PERM_DENIED = -1104, 1802 LMAC_AF_ERR_8023PAUSE_ENADIS_PERM_DENIED = -1105, 1803 LMAC_AF_ERR_CMD_TIMEOUT = -1106, 1804 LMAC_AF_ERR_FIRMWARE_DATA_NOT_MAPPED = -1107, 1805 LMAC_AF_ERR_EXACT_MATCH_TBL_ADD_FAILED = -1108, 1806 LMAC_AF_ERR_EXACT_MATCH_TBL_DEL_FAILED = -1109, 1807 LMAC_AF_ERR_EXACT_MATCH_TBL_LOOK_UP_FAILED = -1110, 1808 }; 1809 1810 enum mcs_direction { 1811 MCS_RX, 1812 MCS_TX, 1813 }; 1814 1815 enum mcs_rsrc_type { 1816 MCS_RSRC_TYPE_FLOWID, 1817 MCS_RSRC_TYPE_SECY, 1818 MCS_RSRC_TYPE_SC, 1819 MCS_RSRC_TYPE_SA, 1820 }; 1821 1822 struct mcs_alloc_rsrc_req { 1823 struct mbox_msghdr hdr; 1824 u8 rsrc_type; 1825 u8 rsrc_cnt; /* Resources count */ 1826 u8 mcs_id; /* MCS block ID */ 1827 u8 dir; /* Macsec ingress or egress side */ 1828 u8 all; /* Allocate all resource type one each */ 1829 u64 rsvd; 1830 }; 1831 1832 struct mcs_alloc_rsrc_rsp { 1833 struct mbox_msghdr hdr; 1834 u8 flow_ids[128]; /* Index of reserved entries */ 1835 u8 secy_ids[128]; 1836 u8 sc_ids[128]; 1837 u8 sa_ids[256]; 1838 u8 rsrc_type; 1839 u8 rsrc_cnt; /* No of entries reserved */ 1840 u8 mcs_id; 1841 u8 dir; 1842 u8 all; 1843 u8 rsvd[256]; /* reserved fields for future expansion */ 1844 }; 1845 1846 struct mcs_free_rsrc_req { 1847 struct mbox_msghdr hdr; 1848 u8 rsrc_id; /* Index of the entry to be freed */ 1849 u8 rsrc_type; 1850 u8 mcs_id; 1851 u8 dir; 1852 u8 all; /* Free all the cam resources */ 1853 u64 rsvd; 1854 }; 1855 1856 struct mcs_flowid_entry_write_req { 1857 struct mbox_msghdr hdr; 1858 u64 data[4]; 1859 u64 mask[4]; 1860 u64 sci; /* CNF10K-B for tx_secy_mem_map */ 1861 u8 flow_id; 1862 u8 secy_id; /* secyid for which flowid is mapped */ 1863 u8 sc_id; /* Valid if dir = MCS_TX, SC_CAM id mapped to flowid */ 1864 u8 ena; /* Enable tcam entry */ 1865 u8 ctrl_pkt; 1866 u8 mcs_id; 1867 u8 dir; 1868 u64 rsvd; 1869 }; 1870 1871 struct mcs_secy_plcy_write_req { 1872 struct mbox_msghdr hdr; 1873 u64 plcy; 1874 u8 secy_id; 1875 u8 mcs_id; 1876 u8 dir; 1877 u64 rsvd; 1878 }; 1879 1880 /* RX SC_CAM mapping */ 1881 struct mcs_rx_sc_cam_write_req { 1882 struct mbox_msghdr hdr; 1883 u64 sci; /* SCI */ 1884 u64 secy_id; /* secy index mapped to SC */ 1885 u8 sc_id; /* SC CAM entry index */ 1886 u8 mcs_id; 1887 u64 rsvd; 1888 }; 1889 1890 struct mcs_sa_plcy_write_req { 1891 struct mbox_msghdr hdr; 1892 u64 plcy[2][9]; /* Support 2 SA policy */ 1893 u8 sa_index[2]; 1894 u8 sa_cnt; 1895 u8 mcs_id; 1896 u8 dir; 1897 u64 rsvd; 1898 }; 1899 1900 struct mcs_tx_sc_sa_map { 1901 struct mbox_msghdr hdr; 1902 u8 sa_index0; 1903 u8 sa_index1; 1904 u8 rekey_ena; 1905 u8 sa_index0_vld; 1906 u8 sa_index1_vld; 1907 u8 tx_sa_active; 1908 u64 sectag_sci; 1909 u8 sc_id; /* used as index for SA_MEM_MAP */ 1910 u8 mcs_id; 1911 u64 rsvd; 1912 }; 1913 1914 struct mcs_rx_sc_sa_map { 1915 struct mbox_msghdr hdr; 1916 u8 sa_index; 1917 u8 sa_in_use; 1918 u8 sc_id; 1919 u8 an; /* value range 0-3, sc_id + an used as index SA_MEM_MAP */ 1920 u8 mcs_id; 1921 u64 rsvd; 1922 }; 1923 1924 struct mcs_flowid_ena_dis_entry { 1925 struct mbox_msghdr hdr; 1926 u8 flow_id; 1927 u8 ena; 1928 u8 mcs_id; 1929 u8 dir; 1930 u64 rsvd; 1931 }; 1932 1933 struct mcs_pn_table_write_req { 1934 struct mbox_msghdr hdr; 1935 u64 next_pn; 1936 u8 pn_id; 1937 u8 mcs_id; 1938 u8 dir; 1939 u64 rsvd; 1940 }; 1941 1942 struct mcs_hw_info { 1943 struct mbox_msghdr hdr; 1944 u8 num_mcs_blks; /* Number of MCS blocks */ 1945 u8 tcam_entries; /* RX/TX Tcam entries per mcs block */ 1946 u8 secy_entries; /* RX/TX SECY entries per mcs block */ 1947 u8 sc_entries; /* RX/TX SC CAM entries per mcs block */ 1948 u16 sa_entries; /* PN table entries = SA entries */ 1949 u64 rsvd[16]; 1950 }; 1951 1952 struct mcs_set_active_lmac { 1953 struct mbox_msghdr hdr; 1954 u32 lmac_bmap; /* bitmap of active lmac per mcs block */ 1955 u8 mcs_id; 1956 u16 chan_base; /* MCS channel base */ 1957 u64 rsvd; 1958 }; 1959 1960 struct mcs_set_lmac_mode { 1961 struct mbox_msghdr hdr; 1962 u8 mode; /* 1:Bypass 0:Operational */ 1963 u8 lmac_id; 1964 u8 mcs_id; 1965 u64 rsvd; 1966 }; 1967 1968 struct mcs_port_reset_req { 1969 struct mbox_msghdr hdr; 1970 u8 reset; 1971 u8 mcs_id; 1972 u8 port_id; 1973 u64 rsvd; 1974 }; 1975 1976 struct mcs_port_cfg_set_req { 1977 struct mbox_msghdr hdr; 1978 u8 cstm_tag_rel_mode_sel; 1979 u8 custom_hdr_enb; 1980 u8 fifo_skid; 1981 u8 port_mode; 1982 u8 port_id; 1983 u8 mcs_id; 1984 u64 rsvd; 1985 }; 1986 1987 struct mcs_port_cfg_get_req { 1988 struct mbox_msghdr hdr; 1989 u8 port_id; 1990 u8 mcs_id; 1991 u64 rsvd; 1992 }; 1993 1994 struct mcs_port_cfg_get_rsp { 1995 struct mbox_msghdr hdr; 1996 u8 cstm_tag_rel_mode_sel; 1997 u8 custom_hdr_enb; 1998 u8 fifo_skid; 1999 u8 port_mode; 2000 u8 port_id; 2001 u8 mcs_id; 2002 u64 rsvd; 2003 }; 2004 2005 struct mcs_custom_tag_cfg_get_req { 2006 struct mbox_msghdr hdr; 2007 u8 mcs_id; 2008 u8 dir; 2009 u64 rsvd; 2010 }; 2011 2012 struct mcs_custom_tag_cfg_get_rsp { 2013 struct mbox_msghdr hdr; 2014 u16 cstm_etype[8]; 2015 u8 cstm_indx[8]; 2016 u8 cstm_etype_en; 2017 u8 mcs_id; 2018 u8 dir; 2019 u64 rsvd; 2020 }; 2021 2022 /* MCS mailbox error codes 2023 * Range 1201 - 1300. 2024 */ 2025 enum mcs_af_status { 2026 MCS_AF_ERR_INVALID_MCSID = -1201, 2027 MCS_AF_ERR_NOT_MAPPED = -1202, 2028 }; 2029 2030 struct mcs_set_pn_threshold { 2031 struct mbox_msghdr hdr; 2032 u64 threshold; 2033 u8 xpn; /* '1' for setting xpn threshold */ 2034 u8 mcs_id; 2035 u8 dir; 2036 u64 rsvd; 2037 }; 2038 2039 enum mcs_ctrl_pkt_rulew_type { 2040 MCS_CTRL_PKT_RULE_TYPE_ETH, 2041 MCS_CTRL_PKT_RULE_TYPE_DA, 2042 MCS_CTRL_PKT_RULE_TYPE_RANGE, 2043 MCS_CTRL_PKT_RULE_TYPE_COMBO, 2044 MCS_CTRL_PKT_RULE_TYPE_MAC, 2045 }; 2046 2047 struct mcs_alloc_ctrl_pkt_rule_req { 2048 struct mbox_msghdr hdr; 2049 u8 rule_type; 2050 u8 mcs_id; /* MCS block ID */ 2051 u8 dir; /* Macsec ingress or egress side */ 2052 u64 rsvd; 2053 }; 2054 2055 struct mcs_alloc_ctrl_pkt_rule_rsp { 2056 struct mbox_msghdr hdr; 2057 u8 rule_idx; 2058 u8 rule_type; 2059 u8 mcs_id; 2060 u8 dir; 2061 u64 rsvd; 2062 }; 2063 2064 struct mcs_free_ctrl_pkt_rule_req { 2065 struct mbox_msghdr hdr; 2066 u8 rule_idx; 2067 u8 rule_type; 2068 u8 mcs_id; 2069 u8 dir; 2070 u8 all; 2071 u64 rsvd; 2072 }; 2073 2074 struct mcs_ctrl_pkt_rule_write_req { 2075 struct mbox_msghdr hdr; 2076 u64 data0; 2077 u64 data1; 2078 u64 data2; 2079 u8 rule_idx; 2080 u8 rule_type; 2081 u8 mcs_id; 2082 u8 dir; 2083 u64 rsvd; 2084 }; 2085 2086 struct mcs_stats_req { 2087 struct mbox_msghdr hdr; 2088 u8 id; 2089 u8 mcs_id; 2090 u8 dir; 2091 u64 rsvd; 2092 }; 2093 2094 struct mcs_flowid_stats { 2095 struct mbox_msghdr hdr; 2096 u64 tcam_hit_cnt; 2097 u64 rsvd; 2098 }; 2099 2100 struct mcs_secy_stats { 2101 struct mbox_msghdr hdr; 2102 u64 ctl_pkt_bcast_cnt; 2103 u64 ctl_pkt_mcast_cnt; 2104 u64 ctl_pkt_ucast_cnt; 2105 u64 ctl_octet_cnt; 2106 u64 unctl_pkt_bcast_cnt; 2107 u64 unctl_pkt_mcast_cnt; 2108 u64 unctl_pkt_ucast_cnt; 2109 u64 unctl_octet_cnt; 2110 /* Valid only for RX */ 2111 u64 octet_decrypted_cnt; 2112 u64 octet_validated_cnt; 2113 u64 pkt_port_disabled_cnt; 2114 u64 pkt_badtag_cnt; 2115 u64 pkt_nosa_cnt; 2116 u64 pkt_nosaerror_cnt; 2117 u64 pkt_tagged_ctl_cnt; 2118 u64 pkt_untaged_cnt; 2119 u64 pkt_ctl_cnt; /* CN10K-B */ 2120 u64 pkt_notag_cnt; /* CNF10K-B */ 2121 /* Valid only for TX */ 2122 u64 octet_encrypted_cnt; 2123 u64 octet_protected_cnt; 2124 u64 pkt_noactivesa_cnt; 2125 u64 pkt_toolong_cnt; 2126 u64 pkt_untagged_cnt; 2127 u64 rsvd[4]; 2128 }; 2129 2130 struct mcs_port_stats { 2131 struct mbox_msghdr hdr; 2132 u64 tcam_miss_cnt; 2133 u64 parser_err_cnt; 2134 u64 preempt_err_cnt; /* CNF10K-B */ 2135 u64 sectag_insert_err_cnt; 2136 u64 rsvd[4]; 2137 }; 2138 2139 /* Only for CN10K-B */ 2140 struct mcs_sa_stats { 2141 struct mbox_msghdr hdr; 2142 /* RX */ 2143 u64 pkt_invalid_cnt; 2144 u64 pkt_nosaerror_cnt; 2145 u64 pkt_notvalid_cnt; 2146 u64 pkt_ok_cnt; 2147 u64 pkt_nosa_cnt; 2148 /* TX */ 2149 u64 pkt_encrypt_cnt; 2150 u64 pkt_protected_cnt; 2151 u64 rsvd[4]; 2152 }; 2153 2154 struct mcs_sc_stats { 2155 struct mbox_msghdr hdr; 2156 /* RX */ 2157 u64 hit_cnt; 2158 u64 pkt_invalid_cnt; 2159 u64 pkt_late_cnt; 2160 u64 pkt_notvalid_cnt; 2161 u64 pkt_unchecked_cnt; 2162 u64 pkt_delay_cnt; /* CNF10K-B */ 2163 u64 pkt_ok_cnt; /* CNF10K-B */ 2164 u64 octet_decrypt_cnt; /* CN10K-B */ 2165 u64 octet_validate_cnt; /* CN10K-B */ 2166 /* TX */ 2167 u64 pkt_encrypt_cnt; 2168 u64 pkt_protected_cnt; 2169 u64 octet_encrypt_cnt; /* CN10K-B */ 2170 u64 octet_protected_cnt; /* CN10K-B */ 2171 u64 rsvd[4]; 2172 }; 2173 2174 struct mcs_clear_stats { 2175 struct mbox_msghdr hdr; 2176 #define MCS_FLOWID_STATS 0 2177 #define MCS_SECY_STATS 1 2178 #define MCS_SC_STATS 2 2179 #define MCS_SA_STATS 3 2180 #define MCS_PORT_STATS 4 2181 u8 type; /* FLOWID, SECY, SC, SA, PORT */ 2182 u8 id; /* type = PORT, If id = FF(invalid) port no is derived from pcifunc */ 2183 u8 mcs_id; 2184 u8 dir; 2185 u8 all; /* All resources stats mapped to PF are cleared */ 2186 }; 2187 2188 struct mcs_intr_cfg { 2189 struct mbox_msghdr hdr; 2190 #define MCS_CPM_RX_SECTAG_V_EQ1_INT BIT_ULL(0) 2191 #define MCS_CPM_RX_SECTAG_E_EQ0_C_EQ1_INT BIT_ULL(1) 2192 #define MCS_CPM_RX_SECTAG_SL_GTE48_INT BIT_ULL(2) 2193 #define MCS_CPM_RX_SECTAG_ES_EQ1_SC_EQ1_INT BIT_ULL(3) 2194 #define MCS_CPM_RX_SECTAG_SC_EQ1_SCB_EQ1_INT BIT_ULL(4) 2195 #define MCS_CPM_RX_PACKET_XPN_EQ0_INT BIT_ULL(5) 2196 #define MCS_CPM_RX_PN_THRESH_REACHED_INT BIT_ULL(6) 2197 #define MCS_CPM_TX_PACKET_XPN_EQ0_INT BIT_ULL(7) 2198 #define MCS_CPM_TX_PN_THRESH_REACHED_INT BIT_ULL(8) 2199 #define MCS_CPM_TX_SA_NOT_VALID_INT BIT_ULL(9) 2200 #define MCS_BBE_RX_DFIFO_OVERFLOW_INT BIT_ULL(10) 2201 #define MCS_BBE_RX_PLFIFO_OVERFLOW_INT BIT_ULL(11) 2202 #define MCS_BBE_TX_DFIFO_OVERFLOW_INT BIT_ULL(12) 2203 #define MCS_BBE_TX_PLFIFO_OVERFLOW_INT BIT_ULL(13) 2204 #define MCS_PAB_RX_CHAN_OVERFLOW_INT BIT_ULL(14) 2205 #define MCS_PAB_TX_CHAN_OVERFLOW_INT BIT_ULL(15) 2206 u64 intr_mask; /* Interrupt enable mask */ 2207 u8 mcs_id; 2208 u8 lmac_id; 2209 u64 rsvd; 2210 }; 2211 2212 struct mcs_intr_info { 2213 struct mbox_msghdr hdr; 2214 u64 intr_mask; 2215 int sa_id; 2216 u8 mcs_id; 2217 u8 lmac_id; 2218 u64 rsvd; 2219 }; 2220 2221 #endif /* MBOX_H */ 2222