1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Marvell RVU Admin Function driver 3 * 4 * Copyright (C) 2018 Marvell. 5 * 6 */ 7 8 #ifndef MBOX_H 9 #define MBOX_H 10 11 #include <linux/etherdevice.h> 12 #include <linux/sizes.h> 13 14 #include "rvu_struct.h" 15 #include "common.h" 16 17 #define MBOX_SIZE SZ_64K 18 19 /* AF/PF: PF initiated, PF/VF VF initiated */ 20 #define MBOX_DOWN_RX_START 0 21 #define MBOX_DOWN_RX_SIZE (46 * SZ_1K) 22 #define MBOX_DOWN_TX_START (MBOX_DOWN_RX_START + MBOX_DOWN_RX_SIZE) 23 #define MBOX_DOWN_TX_SIZE (16 * SZ_1K) 24 /* AF/PF: AF initiated, PF/VF PF initiated */ 25 #define MBOX_UP_RX_START (MBOX_DOWN_TX_START + MBOX_DOWN_TX_SIZE) 26 #define MBOX_UP_RX_SIZE SZ_1K 27 #define MBOX_UP_TX_START (MBOX_UP_RX_START + MBOX_UP_RX_SIZE) 28 #define MBOX_UP_TX_SIZE SZ_1K 29 30 #if MBOX_UP_TX_SIZE + MBOX_UP_TX_START != MBOX_SIZE 31 # error "incorrect mailbox area sizes" 32 #endif 33 34 #define INTR_MASK(pfvfs) ((pfvfs < 64) ? (BIT_ULL(pfvfs) - 1) : (~0ull)) 35 36 #define MBOX_RSP_TIMEOUT 3000 /* Time(ms) to wait for mbox response */ 37 38 #define MBOX_MSG_ALIGN 16 /* Align mbox msg start to 16bytes */ 39 40 /* Mailbox directions */ 41 #define MBOX_DIR_AFPF 0 /* AF replies to PF */ 42 #define MBOX_DIR_PFAF 1 /* PF sends messages to AF */ 43 #define MBOX_DIR_PFVF 2 /* PF replies to VF */ 44 #define MBOX_DIR_VFPF 3 /* VF sends messages to PF */ 45 #define MBOX_DIR_AFPF_UP 4 /* AF sends messages to PF */ 46 #define MBOX_DIR_PFAF_UP 5 /* PF replies to AF */ 47 #define MBOX_DIR_PFVF_UP 6 /* PF sends messages to VF */ 48 #define MBOX_DIR_VFPF_UP 7 /* VF replies to PF */ 49 50 struct otx2_mbox_dev { 51 void *mbase; /* This dev's mbox region */ 52 void *hwbase; 53 spinlock_t mbox_lock; 54 u16 msg_size; /* Total msg size to be sent */ 55 u16 rsp_size; /* Total rsp size to be sure the reply is ok */ 56 u16 num_msgs; /* No of msgs sent or waiting for response */ 57 u16 msgs_acked; /* No of msgs for which response is received */ 58 }; 59 60 struct otx2_mbox { 61 struct pci_dev *pdev; 62 void *hwbase; /* Mbox region advertised by HW */ 63 void *reg_base;/* CSR base for this dev */ 64 u64 trigger; /* Trigger mbox notification */ 65 u16 tr_shift; /* Mbox trigger shift */ 66 u64 rx_start; /* Offset of Rx region in mbox memory */ 67 u64 tx_start; /* Offset of Tx region in mbox memory */ 68 u16 rx_size; /* Size of Rx region */ 69 u16 tx_size; /* Size of Tx region */ 70 u16 ndevs; /* The number of peers */ 71 struct otx2_mbox_dev *dev; 72 }; 73 74 /* Header which precedes all mbox messages */ 75 struct mbox_hdr { 76 u64 msg_size; /* Total msgs size embedded */ 77 u16 num_msgs; /* No of msgs embedded */ 78 }; 79 80 /* Header which precedes every msg and is also part of it */ 81 struct mbox_msghdr { 82 u16 pcifunc; /* Who's sending this msg */ 83 u16 id; /* Mbox message ID */ 84 #define OTX2_MBOX_REQ_SIG (0xdead) 85 #define OTX2_MBOX_RSP_SIG (0xbeef) 86 u16 sig; /* Signature, for validating corrupted msgs */ 87 #define OTX2_MBOX_VERSION (0x000a) 88 u16 ver; /* Version of msg's structure for this ID */ 89 u16 next_msgoff; /* Offset of next msg within mailbox region */ 90 int rc; /* Msg process'ed response code */ 91 }; 92 93 void otx2_mbox_reset(struct otx2_mbox *mbox, int devid); 94 void __otx2_mbox_reset(struct otx2_mbox *mbox, int devid); 95 void otx2_mbox_destroy(struct otx2_mbox *mbox); 96 int otx2_mbox_init(struct otx2_mbox *mbox, void __force *hwbase, 97 struct pci_dev *pdev, void __force *reg_base, 98 int direction, int ndevs); 99 int otx2_mbox_regions_init(struct otx2_mbox *mbox, void __force **hwbase, 100 struct pci_dev *pdev, void __force *reg_base, 101 int direction, int ndevs); 102 void otx2_mbox_msg_send(struct otx2_mbox *mbox, int devid); 103 int otx2_mbox_wait_for_rsp(struct otx2_mbox *mbox, int devid); 104 int otx2_mbox_busy_poll_for_rsp(struct otx2_mbox *mbox, int devid); 105 struct mbox_msghdr *otx2_mbox_alloc_msg_rsp(struct otx2_mbox *mbox, int devid, 106 int size, int size_rsp); 107 struct mbox_msghdr *otx2_mbox_get_rsp(struct otx2_mbox *mbox, int devid, 108 struct mbox_msghdr *msg); 109 int otx2_mbox_check_rsp_msgs(struct otx2_mbox *mbox, int devid); 110 int otx2_reply_invalid_msg(struct otx2_mbox *mbox, int devid, 111 u16 pcifunc, u16 id); 112 bool otx2_mbox_nonempty(struct otx2_mbox *mbox, int devid); 113 const char *otx2_mbox_id2name(u16 id); 114 static inline struct mbox_msghdr *otx2_mbox_alloc_msg(struct otx2_mbox *mbox, 115 int devid, int size) 116 { 117 return otx2_mbox_alloc_msg_rsp(mbox, devid, size, 0); 118 } 119 120 /* Mailbox message types */ 121 #define MBOX_MSG_MASK 0xFFFF 122 #define MBOX_MSG_INVALID 0xFFFE 123 #define MBOX_MSG_MAX 0xFFFF 124 125 #define MBOX_MESSAGES \ 126 /* Generic mbox IDs (range 0x000 - 0x1FF) */ \ 127 M(READY, 0x001, ready, msg_req, ready_msg_rsp) \ 128 M(ATTACH_RESOURCES, 0x002, attach_resources, rsrc_attach, msg_rsp) \ 129 M(DETACH_RESOURCES, 0x003, detach_resources, rsrc_detach, msg_rsp) \ 130 M(FREE_RSRC_CNT, 0x004, free_rsrc_cnt, msg_req, free_rsrcs_rsp) \ 131 M(MSIX_OFFSET, 0x005, msix_offset, msg_req, msix_offset_rsp) \ 132 M(VF_FLR, 0x006, vf_flr, msg_req, msg_rsp) \ 133 M(PTP_OP, 0x007, ptp_op, ptp_req, ptp_rsp) \ 134 M(GET_HW_CAP, 0x008, get_hw_cap, msg_req, get_hw_cap_rsp) \ 135 M(LMTST_TBL_SETUP, 0x00a, lmtst_tbl_setup, lmtst_tbl_setup_req, \ 136 msg_rsp) \ 137 M(SET_VF_PERM, 0x00b, set_vf_perm, set_vf_perm, msg_rsp) \ 138 /* CGX mbox IDs (range 0x200 - 0x3FF) */ \ 139 M(CGX_START_RXTX, 0x200, cgx_start_rxtx, msg_req, msg_rsp) \ 140 M(CGX_STOP_RXTX, 0x201, cgx_stop_rxtx, msg_req, msg_rsp) \ 141 M(CGX_STATS, 0x202, cgx_stats, msg_req, cgx_stats_rsp) \ 142 M(CGX_MAC_ADDR_SET, 0x203, cgx_mac_addr_set, cgx_mac_addr_set_or_get, \ 143 cgx_mac_addr_set_or_get) \ 144 M(CGX_MAC_ADDR_GET, 0x204, cgx_mac_addr_get, cgx_mac_addr_set_or_get, \ 145 cgx_mac_addr_set_or_get) \ 146 M(CGX_PROMISC_ENABLE, 0x205, cgx_promisc_enable, msg_req, msg_rsp) \ 147 M(CGX_PROMISC_DISABLE, 0x206, cgx_promisc_disable, msg_req, msg_rsp) \ 148 M(CGX_START_LINKEVENTS, 0x207, cgx_start_linkevents, msg_req, msg_rsp) \ 149 M(CGX_STOP_LINKEVENTS, 0x208, cgx_stop_linkevents, msg_req, msg_rsp) \ 150 M(CGX_GET_LINKINFO, 0x209, cgx_get_linkinfo, msg_req, cgx_link_info_msg) \ 151 M(CGX_INTLBK_ENABLE, 0x20A, cgx_intlbk_enable, msg_req, msg_rsp) \ 152 M(CGX_INTLBK_DISABLE, 0x20B, cgx_intlbk_disable, msg_req, msg_rsp) \ 153 M(CGX_PTP_RX_ENABLE, 0x20C, cgx_ptp_rx_enable, msg_req, msg_rsp) \ 154 M(CGX_PTP_RX_DISABLE, 0x20D, cgx_ptp_rx_disable, msg_req, msg_rsp) \ 155 M(CGX_CFG_PAUSE_FRM, 0x20E, cgx_cfg_pause_frm, cgx_pause_frm_cfg, \ 156 cgx_pause_frm_cfg) \ 157 M(CGX_FW_DATA_GET, 0x20F, cgx_get_aux_link_info, msg_req, cgx_fw_data) \ 158 M(CGX_FEC_SET, 0x210, cgx_set_fec_param, fec_mode, fec_mode) \ 159 M(CGX_MAC_ADDR_ADD, 0x211, cgx_mac_addr_add, cgx_mac_addr_add_req, \ 160 cgx_mac_addr_add_rsp) \ 161 M(CGX_MAC_ADDR_DEL, 0x212, cgx_mac_addr_del, cgx_mac_addr_del_req, \ 162 msg_rsp) \ 163 M(CGX_MAC_MAX_ENTRIES_GET, 0x213, cgx_mac_max_entries_get, msg_req, \ 164 cgx_max_dmac_entries_get_rsp) \ 165 M(CGX_FEC_STATS, 0x217, cgx_fec_stats, msg_req, cgx_fec_stats_rsp) \ 166 M(CGX_SET_LINK_MODE, 0x218, cgx_set_link_mode, cgx_set_link_mode_req,\ 167 cgx_set_link_mode_rsp) \ 168 M(CGX_GET_PHY_FEC_STATS, 0x219, cgx_get_phy_fec_stats, msg_req, msg_rsp) \ 169 M(CGX_FEATURES_GET, 0x21B, cgx_features_get, msg_req, \ 170 cgx_features_info_msg) \ 171 M(RPM_STATS, 0x21C, rpm_stats, msg_req, rpm_stats_rsp) \ 172 M(CGX_MAC_ADDR_RESET, 0x21D, cgx_mac_addr_reset, msg_req, msg_rsp) \ 173 M(CGX_MAC_ADDR_UPDATE, 0x21E, cgx_mac_addr_update, cgx_mac_addr_update_req, \ 174 msg_rsp) \ 175 /* NPA mbox IDs (range 0x400 - 0x5FF) */ \ 176 M(NPA_LF_ALLOC, 0x400, npa_lf_alloc, \ 177 npa_lf_alloc_req, npa_lf_alloc_rsp) \ 178 M(NPA_LF_FREE, 0x401, npa_lf_free, msg_req, msg_rsp) \ 179 M(NPA_AQ_ENQ, 0x402, npa_aq_enq, npa_aq_enq_req, npa_aq_enq_rsp) \ 180 M(NPA_HWCTX_DISABLE, 0x403, npa_hwctx_disable, hwctx_disable_req, msg_rsp)\ 181 /* SSO/SSOW mbox IDs (range 0x600 - 0x7FF) */ \ 182 /* TIM mbox IDs (range 0x800 - 0x9FF) */ \ 183 /* CPT mbox IDs (range 0xA00 - 0xBFF) */ \ 184 M(CPT_LF_ALLOC, 0xA00, cpt_lf_alloc, cpt_lf_alloc_req_msg, \ 185 msg_rsp) \ 186 M(CPT_LF_FREE, 0xA01, cpt_lf_free, msg_req, msg_rsp) \ 187 M(CPT_RD_WR_REGISTER, 0xA02, cpt_rd_wr_register, cpt_rd_wr_reg_msg, \ 188 cpt_rd_wr_reg_msg) \ 189 M(CPT_INLINE_IPSEC_CFG, 0xA04, cpt_inline_ipsec_cfg, \ 190 cpt_inline_ipsec_cfg_msg, msg_rsp) \ 191 M(CPT_STATS, 0xA05, cpt_sts, cpt_sts_req, cpt_sts_rsp) \ 192 M(CPT_RXC_TIME_CFG, 0xA06, cpt_rxc_time_cfg, cpt_rxc_time_cfg_req, \ 193 msg_rsp) \ 194 /* SDP mbox IDs (range 0x1000 - 0x11FF) */ \ 195 M(SET_SDP_CHAN_INFO, 0x1000, set_sdp_chan_info, sdp_chan_info_msg, msg_rsp) \ 196 M(GET_SDP_CHAN_INFO, 0x1001, get_sdp_chan_info, msg_req, sdp_get_chan_info_msg) \ 197 /* NPC mbox IDs (range 0x6000 - 0x7FFF) */ \ 198 M(NPC_MCAM_ALLOC_ENTRY, 0x6000, npc_mcam_alloc_entry, npc_mcam_alloc_entry_req,\ 199 npc_mcam_alloc_entry_rsp) \ 200 M(NPC_MCAM_FREE_ENTRY, 0x6001, npc_mcam_free_entry, \ 201 npc_mcam_free_entry_req, msg_rsp) \ 202 M(NPC_MCAM_WRITE_ENTRY, 0x6002, npc_mcam_write_entry, \ 203 npc_mcam_write_entry_req, msg_rsp) \ 204 M(NPC_MCAM_ENA_ENTRY, 0x6003, npc_mcam_ena_entry, \ 205 npc_mcam_ena_dis_entry_req, msg_rsp) \ 206 M(NPC_MCAM_DIS_ENTRY, 0x6004, npc_mcam_dis_entry, \ 207 npc_mcam_ena_dis_entry_req, msg_rsp) \ 208 M(NPC_MCAM_SHIFT_ENTRY, 0x6005, npc_mcam_shift_entry, npc_mcam_shift_entry_req,\ 209 npc_mcam_shift_entry_rsp) \ 210 M(NPC_MCAM_ALLOC_COUNTER, 0x6006, npc_mcam_alloc_counter, \ 211 npc_mcam_alloc_counter_req, \ 212 npc_mcam_alloc_counter_rsp) \ 213 M(NPC_MCAM_FREE_COUNTER, 0x6007, npc_mcam_free_counter, \ 214 npc_mcam_oper_counter_req, msg_rsp) \ 215 M(NPC_MCAM_UNMAP_COUNTER, 0x6008, npc_mcam_unmap_counter, \ 216 npc_mcam_unmap_counter_req, msg_rsp) \ 217 M(NPC_MCAM_CLEAR_COUNTER, 0x6009, npc_mcam_clear_counter, \ 218 npc_mcam_oper_counter_req, msg_rsp) \ 219 M(NPC_MCAM_COUNTER_STATS, 0x600a, npc_mcam_counter_stats, \ 220 npc_mcam_oper_counter_req, \ 221 npc_mcam_oper_counter_rsp) \ 222 M(NPC_MCAM_ALLOC_AND_WRITE_ENTRY, 0x600b, npc_mcam_alloc_and_write_entry, \ 223 npc_mcam_alloc_and_write_entry_req, \ 224 npc_mcam_alloc_and_write_entry_rsp) \ 225 M(NPC_GET_KEX_CFG, 0x600c, npc_get_kex_cfg, \ 226 msg_req, npc_get_kex_cfg_rsp) \ 227 M(NPC_INSTALL_FLOW, 0x600d, npc_install_flow, \ 228 npc_install_flow_req, npc_install_flow_rsp) \ 229 M(NPC_DELETE_FLOW, 0x600e, npc_delete_flow, \ 230 npc_delete_flow_req, msg_rsp) \ 231 M(NPC_MCAM_READ_ENTRY, 0x600f, npc_mcam_read_entry, \ 232 npc_mcam_read_entry_req, \ 233 npc_mcam_read_entry_rsp) \ 234 M(NPC_SET_PKIND, 0x6010, npc_set_pkind, \ 235 npc_set_pkind, msg_rsp) \ 236 M(NPC_MCAM_READ_BASE_RULE, 0x6011, npc_read_base_steer_rule, \ 237 msg_req, npc_mcam_read_base_rule_rsp) \ 238 M(NPC_MCAM_GET_STATS, 0x6012, npc_mcam_entry_stats, \ 239 npc_mcam_get_stats_req, \ 240 npc_mcam_get_stats_rsp) \ 241 /* NIX mbox IDs (range 0x8000 - 0xFFFF) */ \ 242 M(NIX_LF_ALLOC, 0x8000, nix_lf_alloc, \ 243 nix_lf_alloc_req, nix_lf_alloc_rsp) \ 244 M(NIX_LF_FREE, 0x8001, nix_lf_free, nix_lf_free_req, msg_rsp) \ 245 M(NIX_AQ_ENQ, 0x8002, nix_aq_enq, nix_aq_enq_req, nix_aq_enq_rsp) \ 246 M(NIX_HWCTX_DISABLE, 0x8003, nix_hwctx_disable, \ 247 hwctx_disable_req, msg_rsp) \ 248 M(NIX_TXSCH_ALLOC, 0x8004, nix_txsch_alloc, \ 249 nix_txsch_alloc_req, nix_txsch_alloc_rsp) \ 250 M(NIX_TXSCH_FREE, 0x8005, nix_txsch_free, nix_txsch_free_req, msg_rsp) \ 251 M(NIX_TXSCHQ_CFG, 0x8006, nix_txschq_cfg, nix_txschq_config, \ 252 nix_txschq_config) \ 253 M(NIX_STATS_RST, 0x8007, nix_stats_rst, msg_req, msg_rsp) \ 254 M(NIX_VTAG_CFG, 0x8008, nix_vtag_cfg, nix_vtag_config, \ 255 nix_vtag_config_rsp) \ 256 M(NIX_RSS_FLOWKEY_CFG, 0x8009, nix_rss_flowkey_cfg, \ 257 nix_rss_flowkey_cfg, \ 258 nix_rss_flowkey_cfg_rsp) \ 259 M(NIX_SET_MAC_ADDR, 0x800a, nix_set_mac_addr, nix_set_mac_addr, msg_rsp) \ 260 M(NIX_SET_RX_MODE, 0x800b, nix_set_rx_mode, nix_rx_mode, msg_rsp) \ 261 M(NIX_SET_HW_FRS, 0x800c, nix_set_hw_frs, nix_frs_cfg, msg_rsp) \ 262 M(NIX_LF_START_RX, 0x800d, nix_lf_start_rx, msg_req, msg_rsp) \ 263 M(NIX_LF_STOP_RX, 0x800e, nix_lf_stop_rx, msg_req, msg_rsp) \ 264 M(NIX_MARK_FORMAT_CFG, 0x800f, nix_mark_format_cfg, \ 265 nix_mark_format_cfg, \ 266 nix_mark_format_cfg_rsp) \ 267 M(NIX_SET_RX_CFG, 0x8010, nix_set_rx_cfg, nix_rx_cfg, msg_rsp) \ 268 M(NIX_LSO_FORMAT_CFG, 0x8011, nix_lso_format_cfg, \ 269 nix_lso_format_cfg, \ 270 nix_lso_format_cfg_rsp) \ 271 M(NIX_LF_PTP_TX_ENABLE, 0x8013, nix_lf_ptp_tx_enable, msg_req, msg_rsp) \ 272 M(NIX_LF_PTP_TX_DISABLE, 0x8014, nix_lf_ptp_tx_disable, msg_req, msg_rsp) \ 273 M(NIX_BP_ENABLE, 0x8016, nix_bp_enable, nix_bp_cfg_req, \ 274 nix_bp_cfg_rsp) \ 275 M(NIX_BP_DISABLE, 0x8017, nix_bp_disable, nix_bp_cfg_req, msg_rsp) \ 276 M(NIX_GET_MAC_ADDR, 0x8018, nix_get_mac_addr, msg_req, nix_get_mac_addr_rsp) \ 277 M(NIX_INLINE_IPSEC_CFG, 0x8019, nix_inline_ipsec_cfg, \ 278 nix_inline_ipsec_cfg, msg_rsp) \ 279 M(NIX_INLINE_IPSEC_LF_CFG, 0x801a, nix_inline_ipsec_lf_cfg, \ 280 nix_inline_ipsec_lf_cfg, msg_rsp) \ 281 M(NIX_CN10K_AQ_ENQ, 0x801b, nix_cn10k_aq_enq, nix_cn10k_aq_enq_req, \ 282 nix_cn10k_aq_enq_rsp) \ 283 M(NIX_GET_HW_INFO, 0x801c, nix_get_hw_info, msg_req, nix_hw_info) \ 284 M(NIX_BANDPROF_ALLOC, 0x801d, nix_bandprof_alloc, nix_bandprof_alloc_req, \ 285 nix_bandprof_alloc_rsp) \ 286 M(NIX_BANDPROF_FREE, 0x801e, nix_bandprof_free, nix_bandprof_free_req, \ 287 msg_rsp) \ 288 M(NIX_BANDPROF_GET_HWINFO, 0x801f, nix_bandprof_get_hwinfo, msg_req, \ 289 nix_bandprof_get_hwinfo_rsp) 290 291 /* Messages initiated by AF (range 0xC00 - 0xDFF) */ 292 #define MBOX_UP_CGX_MESSAGES \ 293 M(CGX_LINK_EVENT, 0xC00, cgx_link_event, cgx_link_info_msg, msg_rsp) 294 295 enum { 296 #define M(_name, _id, _1, _2, _3) MBOX_MSG_ ## _name = _id, 297 MBOX_MESSAGES 298 MBOX_UP_CGX_MESSAGES 299 #undef M 300 }; 301 302 /* Mailbox message formats */ 303 304 #define RVU_DEFAULT_PF_FUNC 0xFFFF 305 306 /* Generic request msg used for those mbox messages which 307 * don't send any data in the request. 308 */ 309 struct msg_req { 310 struct mbox_msghdr hdr; 311 }; 312 313 /* Generic response msg used an ack or response for those mbox 314 * messages which don't have a specific rsp msg format. 315 */ 316 struct msg_rsp { 317 struct mbox_msghdr hdr; 318 }; 319 320 /* RVU mailbox error codes 321 * Range 256 - 300. 322 */ 323 enum rvu_af_status { 324 RVU_INVALID_VF_ID = -256, 325 }; 326 327 struct ready_msg_rsp { 328 struct mbox_msghdr hdr; 329 u16 sclk_freq; /* SCLK frequency (in MHz) */ 330 u16 rclk_freq; /* RCLK frequency (in MHz) */ 331 }; 332 333 /* Structure for requesting resource provisioning. 334 * 'modify' flag to be used when either requesting more 335 * or to detach partial of a certain resource type. 336 * Rest of the fields specify how many of what type to 337 * be attached. 338 * To request LFs from two blocks of same type this mailbox 339 * can be sent twice as below: 340 * struct rsrc_attach *attach; 341 * .. Allocate memory for message .. 342 * attach->cptlfs = 3; <3 LFs from CPT0> 343 * .. Send message .. 344 * .. Allocate memory for message .. 345 * attach->modify = 1; 346 * attach->cpt_blkaddr = BLKADDR_CPT1; 347 * attach->cptlfs = 2; <2 LFs from CPT1> 348 * .. Send message .. 349 */ 350 struct rsrc_attach { 351 struct mbox_msghdr hdr; 352 u8 modify:1; 353 u8 npalf:1; 354 u8 nixlf:1; 355 u16 sso; 356 u16 ssow; 357 u16 timlfs; 358 u16 cptlfs; 359 int cpt_blkaddr; /* BLKADDR_CPT0/BLKADDR_CPT1 or 0 for BLKADDR_CPT0 */ 360 }; 361 362 /* Structure for relinquishing resources. 363 * 'partial' flag to be used when relinquishing all resources 364 * but only of a certain type. If not set, all resources of all 365 * types provisioned to the RVU function will be detached. 366 */ 367 struct rsrc_detach { 368 struct mbox_msghdr hdr; 369 u8 partial:1; 370 u8 npalf:1; 371 u8 nixlf:1; 372 u8 sso:1; 373 u8 ssow:1; 374 u8 timlfs:1; 375 u8 cptlfs:1; 376 }; 377 378 /* Number of resources available to the caller. 379 * In reply to MBOX_MSG_FREE_RSRC_CNT. 380 */ 381 struct free_rsrcs_rsp { 382 struct mbox_msghdr hdr; 383 u16 schq[NIX_TXSCH_LVL_CNT]; 384 u16 sso; 385 u16 tim; 386 u16 ssow; 387 u16 cpt; 388 u8 npa; 389 u8 nix; 390 u16 schq_nix1[NIX_TXSCH_LVL_CNT]; 391 u8 nix1; 392 u8 cpt1; 393 u8 ree0; 394 u8 ree1; 395 }; 396 397 #define MSIX_VECTOR_INVALID 0xFFFF 398 #define MAX_RVU_BLKLF_CNT 256 399 400 struct msix_offset_rsp { 401 struct mbox_msghdr hdr; 402 u16 npa_msixoff; 403 u16 nix_msixoff; 404 u16 sso; 405 u16 ssow; 406 u16 timlfs; 407 u16 cptlfs; 408 u16 sso_msixoff[MAX_RVU_BLKLF_CNT]; 409 u16 ssow_msixoff[MAX_RVU_BLKLF_CNT]; 410 u16 timlf_msixoff[MAX_RVU_BLKLF_CNT]; 411 u16 cptlf_msixoff[MAX_RVU_BLKLF_CNT]; 412 u16 cpt1_lfs; 413 u16 ree0_lfs; 414 u16 ree1_lfs; 415 u16 cpt1_lf_msixoff[MAX_RVU_BLKLF_CNT]; 416 u16 ree0_lf_msixoff[MAX_RVU_BLKLF_CNT]; 417 u16 ree1_lf_msixoff[MAX_RVU_BLKLF_CNT]; 418 }; 419 420 struct get_hw_cap_rsp { 421 struct mbox_msghdr hdr; 422 u8 nix_fixed_txschq_mapping; /* Schq mapping fixed or flexible */ 423 u8 nix_shaping; /* Is shaping and coloring supported */ 424 }; 425 426 /* CGX mbox message formats */ 427 428 struct cgx_stats_rsp { 429 struct mbox_msghdr hdr; 430 #define CGX_RX_STATS_COUNT 9 431 #define CGX_TX_STATS_COUNT 18 432 u64 rx_stats[CGX_RX_STATS_COUNT]; 433 u64 tx_stats[CGX_TX_STATS_COUNT]; 434 }; 435 436 struct cgx_fec_stats_rsp { 437 struct mbox_msghdr hdr; 438 u64 fec_corr_blks; 439 u64 fec_uncorr_blks; 440 }; 441 /* Structure for requesting the operation for 442 * setting/getting mac address in the CGX interface 443 */ 444 struct cgx_mac_addr_set_or_get { 445 struct mbox_msghdr hdr; 446 u8 mac_addr[ETH_ALEN]; 447 }; 448 449 /* Structure for requesting the operation to 450 * add DMAC filter entry into CGX interface 451 */ 452 struct cgx_mac_addr_add_req { 453 struct mbox_msghdr hdr; 454 u8 mac_addr[ETH_ALEN]; 455 }; 456 457 /* Structure for response against the operation to 458 * add DMAC filter entry into CGX interface 459 */ 460 struct cgx_mac_addr_add_rsp { 461 struct mbox_msghdr hdr; 462 u8 index; 463 }; 464 465 /* Structure for requesting the operation to 466 * delete DMAC filter entry from CGX interface 467 */ 468 struct cgx_mac_addr_del_req { 469 struct mbox_msghdr hdr; 470 u8 index; 471 }; 472 473 /* Structure for response against the operation to 474 * get maximum supported DMAC filter entries 475 */ 476 struct cgx_max_dmac_entries_get_rsp { 477 struct mbox_msghdr hdr; 478 u8 max_dmac_filters; 479 }; 480 481 struct cgx_link_user_info { 482 uint64_t link_up:1; 483 uint64_t full_duplex:1; 484 uint64_t lmac_type_id:4; 485 uint64_t speed:20; /* speed in Mbps */ 486 uint64_t an:1; /* AN supported or not */ 487 uint64_t fec:2; /* FEC type if enabled else 0 */ 488 #define LMACTYPE_STR_LEN 16 489 char lmac_type[LMACTYPE_STR_LEN]; 490 }; 491 492 struct cgx_link_info_msg { 493 struct mbox_msghdr hdr; 494 struct cgx_link_user_info link_info; 495 }; 496 497 struct cgx_pause_frm_cfg { 498 struct mbox_msghdr hdr; 499 u8 set; 500 /* set = 1 if the request is to config pause frames */ 501 /* set = 0 if the request is to fetch pause frames config */ 502 u8 rx_pause; 503 u8 tx_pause; 504 }; 505 506 enum fec_type { 507 OTX2_FEC_NONE, 508 OTX2_FEC_BASER, 509 OTX2_FEC_RS, 510 OTX2_FEC_STATS_CNT = 2, 511 OTX2_FEC_OFF, 512 }; 513 514 struct fec_mode { 515 struct mbox_msghdr hdr; 516 int fec; 517 }; 518 519 struct sfp_eeprom_s { 520 #define SFP_EEPROM_SIZE 256 521 u16 sff_id; 522 u8 buf[SFP_EEPROM_SIZE]; 523 u64 reserved; 524 }; 525 526 struct phy_s { 527 struct { 528 u64 can_change_mod_type:1; 529 u64 mod_type:1; 530 u64 has_fec_stats:1; 531 } misc; 532 struct fec_stats_s { 533 u32 rsfec_corr_cws; 534 u32 rsfec_uncorr_cws; 535 u32 brfec_corr_blks; 536 u32 brfec_uncorr_blks; 537 } fec_stats; 538 }; 539 540 struct cgx_lmac_fwdata_s { 541 u16 rw_valid; 542 u64 supported_fec; 543 u64 supported_an; 544 u64 supported_link_modes; 545 /* only applicable if AN is supported */ 546 u64 advertised_fec; 547 u64 advertised_link_modes; 548 /* Only applicable if SFP/QSFP slot is present */ 549 struct sfp_eeprom_s sfp_eeprom; 550 struct phy_s phy; 551 #define LMAC_FWDATA_RESERVED_MEM 1021 552 u64 reserved[LMAC_FWDATA_RESERVED_MEM]; 553 }; 554 555 struct cgx_fw_data { 556 struct mbox_msghdr hdr; 557 struct cgx_lmac_fwdata_s fwdata; 558 }; 559 560 struct cgx_set_link_mode_args { 561 u32 speed; 562 u8 duplex; 563 u8 an; 564 u8 ports; 565 u64 mode; 566 }; 567 568 struct cgx_set_link_mode_req { 569 #define AUTONEG_UNKNOWN 0xff 570 struct mbox_msghdr hdr; 571 struct cgx_set_link_mode_args args; 572 }; 573 574 struct cgx_set_link_mode_rsp { 575 struct mbox_msghdr hdr; 576 int status; 577 }; 578 579 struct cgx_mac_addr_update_req { 580 struct mbox_msghdr hdr; 581 u8 mac_addr[ETH_ALEN]; 582 u8 index; 583 }; 584 585 #define RVU_LMAC_FEAT_FC BIT_ULL(0) /* pause frames */ 586 #define RVU_LMAC_FEAT_HIGIG2 BIT_ULL(1) 587 /* flow control from physical link higig2 messages */ 588 #define RVU_LMAC_FEAT_PTP BIT_ULL(2) /* precison time protocol */ 589 #define RVU_LMAC_FEAT_DMACF BIT_ULL(3) /* DMAC FILTER */ 590 #define RVU_MAC_VERSION BIT_ULL(4) 591 #define RVU_MAC_CGX BIT_ULL(5) 592 #define RVU_MAC_RPM BIT_ULL(6) 593 594 struct cgx_features_info_msg { 595 struct mbox_msghdr hdr; 596 u64 lmac_features; 597 }; 598 599 struct rpm_stats_rsp { 600 struct mbox_msghdr hdr; 601 #define RPM_RX_STATS_COUNT 43 602 #define RPM_TX_STATS_COUNT 34 603 u64 rx_stats[RPM_RX_STATS_COUNT]; 604 u64 tx_stats[RPM_TX_STATS_COUNT]; 605 }; 606 607 struct npc_set_pkind { 608 struct mbox_msghdr hdr; 609 #define OTX2_PRIV_FLAGS_DEFAULT BIT_ULL(0) 610 #define OTX2_PRIV_FLAGS_CUSTOM BIT_ULL(63) 611 u64 mode; 612 #define PKIND_TX BIT_ULL(0) 613 #define PKIND_RX BIT_ULL(1) 614 u8 dir; 615 u8 pkind; /* valid only in case custom flag */ 616 u8 var_len_off; /* Offset of custom header length field. 617 * Valid only for pkind NPC_RX_CUSTOM_PRE_L2_PKIND 618 */ 619 u8 var_len_off_mask; /* Mask for length with in offset */ 620 u8 shift_dir; /* shift direction to get length of the header at var_len_off */ 621 }; 622 623 /* NPA mbox message formats */ 624 625 /* NPA mailbox error codes 626 * Range 301 - 400. 627 */ 628 enum npa_af_status { 629 NPA_AF_ERR_PARAM = -301, 630 NPA_AF_ERR_AQ_FULL = -302, 631 NPA_AF_ERR_AQ_ENQUEUE = -303, 632 NPA_AF_ERR_AF_LF_INVALID = -304, 633 NPA_AF_ERR_AF_LF_ALLOC = -305, 634 NPA_AF_ERR_LF_RESET = -306, 635 }; 636 637 /* For NPA LF context alloc and init */ 638 struct npa_lf_alloc_req { 639 struct mbox_msghdr hdr; 640 int node; 641 int aura_sz; /* No of auras */ 642 u32 nr_pools; /* No of pools */ 643 u64 way_mask; 644 }; 645 646 struct npa_lf_alloc_rsp { 647 struct mbox_msghdr hdr; 648 u32 stack_pg_ptrs; /* No of ptrs per stack page */ 649 u32 stack_pg_bytes; /* Size of stack page */ 650 u16 qints; /* NPA_AF_CONST::QINTS */ 651 u8 cache_lines; /*BATCH ALLOC DMA */ 652 }; 653 654 /* NPA AQ enqueue msg */ 655 struct npa_aq_enq_req { 656 struct mbox_msghdr hdr; 657 u32 aura_id; 658 u8 ctype; 659 u8 op; 660 union { 661 /* Valid when op == WRITE/INIT and ctype == AURA. 662 * LF fills the pool_id in aura.pool_addr. AF will translate 663 * the pool_id to pool context pointer. 664 */ 665 struct npa_aura_s aura; 666 /* Valid when op == WRITE/INIT and ctype == POOL */ 667 struct npa_pool_s pool; 668 }; 669 /* Mask data when op == WRITE (1=write, 0=don't write) */ 670 union { 671 /* Valid when op == WRITE and ctype == AURA */ 672 struct npa_aura_s aura_mask; 673 /* Valid when op == WRITE and ctype == POOL */ 674 struct npa_pool_s pool_mask; 675 }; 676 }; 677 678 struct npa_aq_enq_rsp { 679 struct mbox_msghdr hdr; 680 union { 681 /* Valid when op == READ and ctype == AURA */ 682 struct npa_aura_s aura; 683 /* Valid when op == READ and ctype == POOL */ 684 struct npa_pool_s pool; 685 }; 686 }; 687 688 /* Disable all contexts of type 'ctype' */ 689 struct hwctx_disable_req { 690 struct mbox_msghdr hdr; 691 u8 ctype; 692 }; 693 694 /* NIX mbox message formats */ 695 696 /* NIX mailbox error codes 697 * Range 401 - 500. 698 */ 699 enum nix_af_status { 700 NIX_AF_ERR_PARAM = -401, 701 NIX_AF_ERR_AQ_FULL = -402, 702 NIX_AF_ERR_AQ_ENQUEUE = -403, 703 NIX_AF_ERR_AF_LF_INVALID = -404, 704 NIX_AF_ERR_AF_LF_ALLOC = -405, 705 NIX_AF_ERR_TLX_ALLOC_FAIL = -406, 706 NIX_AF_ERR_TLX_INVALID = -407, 707 NIX_AF_ERR_RSS_SIZE_INVALID = -408, 708 NIX_AF_ERR_RSS_GRPS_INVALID = -409, 709 NIX_AF_ERR_FRS_INVALID = -410, 710 NIX_AF_ERR_RX_LINK_INVALID = -411, 711 NIX_AF_INVAL_TXSCHQ_CFG = -412, 712 NIX_AF_SMQ_FLUSH_FAILED = -413, 713 NIX_AF_ERR_LF_RESET = -414, 714 NIX_AF_ERR_RSS_NOSPC_FIELD = -415, 715 NIX_AF_ERR_RSS_NOSPC_ALGO = -416, 716 NIX_AF_ERR_MARK_CFG_FAIL = -417, 717 NIX_AF_ERR_LSO_CFG_FAIL = -418, 718 NIX_AF_INVAL_NPA_PF_FUNC = -419, 719 NIX_AF_INVAL_SSO_PF_FUNC = -420, 720 NIX_AF_ERR_TX_VTAG_NOSPC = -421, 721 NIX_AF_ERR_RX_VTAG_INUSE = -422, 722 NIX_AF_ERR_PTP_CONFIG_FAIL = -423, 723 NIX_AF_ERR_NPC_KEY_NOT_SUPP = -424, 724 NIX_AF_ERR_INVALID_NIXBLK = -425, 725 NIX_AF_ERR_INVALID_BANDPROF = -426, 726 NIX_AF_ERR_IPOLICER_NOTSUPP = -427, 727 NIX_AF_ERR_BANDPROF_INVAL_REQ = -428, 728 NIX_AF_ERR_CQ_CTX_WRITE_ERR = -429, 729 NIX_AF_ERR_AQ_CTX_RETRY_WRITE = -430, 730 }; 731 732 /* For NIX RX vtag action */ 733 enum nix_rx_vtag0_type { 734 NIX_AF_LFX_RX_VTAG_TYPE0, /* reserved for rx vlan offload */ 735 NIX_AF_LFX_RX_VTAG_TYPE1, 736 NIX_AF_LFX_RX_VTAG_TYPE2, 737 NIX_AF_LFX_RX_VTAG_TYPE3, 738 NIX_AF_LFX_RX_VTAG_TYPE4, 739 NIX_AF_LFX_RX_VTAG_TYPE5, 740 NIX_AF_LFX_RX_VTAG_TYPE6, 741 NIX_AF_LFX_RX_VTAG_TYPE7, 742 }; 743 744 /* For NIX LF context alloc and init */ 745 struct nix_lf_alloc_req { 746 struct mbox_msghdr hdr; 747 int node; 748 u32 rq_cnt; /* No of receive queues */ 749 u32 sq_cnt; /* No of send queues */ 750 u32 cq_cnt; /* No of completion queues */ 751 u8 xqe_sz; 752 u16 rss_sz; 753 u8 rss_grps; 754 u16 npa_func; 755 u16 sso_func; 756 u64 rx_cfg; /* See NIX_AF_LF(0..127)_RX_CFG */ 757 u64 way_mask; 758 #define NIX_LF_RSS_TAG_LSB_AS_ADDER BIT_ULL(0) 759 #define NIX_LF_LBK_BLK_SEL BIT_ULL(1) 760 u64 flags; 761 }; 762 763 struct nix_lf_alloc_rsp { 764 struct mbox_msghdr hdr; 765 u16 sqb_size; 766 u16 rx_chan_base; 767 u16 tx_chan_base; 768 u8 rx_chan_cnt; /* total number of RX channels */ 769 u8 tx_chan_cnt; /* total number of TX channels */ 770 u8 lso_tsov4_idx; 771 u8 lso_tsov6_idx; 772 u8 mac_addr[ETH_ALEN]; 773 u8 lf_rx_stats; /* NIX_AF_CONST1::LF_RX_STATS */ 774 u8 lf_tx_stats; /* NIX_AF_CONST1::LF_TX_STATS */ 775 u16 cints; /* NIX_AF_CONST2::CINTS */ 776 u16 qints; /* NIX_AF_CONST2::QINTS */ 777 u8 cgx_links; /* No. of CGX links present in HW */ 778 u8 lbk_links; /* No. of LBK links present in HW */ 779 u8 sdp_links; /* No. of SDP links present in HW */ 780 u8 tx_link; /* Transmit channel link number */ 781 }; 782 783 struct nix_lf_free_req { 784 struct mbox_msghdr hdr; 785 #define NIX_LF_DISABLE_FLOWS BIT_ULL(0) 786 #define NIX_LF_DONT_FREE_TX_VTAG BIT_ULL(1) 787 u64 flags; 788 }; 789 790 /* CN10K NIX AQ enqueue msg */ 791 struct nix_cn10k_aq_enq_req { 792 struct mbox_msghdr hdr; 793 u32 qidx; 794 u8 ctype; 795 u8 op; 796 union { 797 struct nix_cn10k_rq_ctx_s rq; 798 struct nix_cn10k_sq_ctx_s sq; 799 struct nix_cq_ctx_s cq; 800 struct nix_rsse_s rss; 801 struct nix_rx_mce_s mce; 802 struct nix_bandprof_s prof; 803 }; 804 union { 805 struct nix_cn10k_rq_ctx_s rq_mask; 806 struct nix_cn10k_sq_ctx_s sq_mask; 807 struct nix_cq_ctx_s cq_mask; 808 struct nix_rsse_s rss_mask; 809 struct nix_rx_mce_s mce_mask; 810 struct nix_bandprof_s prof_mask; 811 }; 812 }; 813 814 struct nix_cn10k_aq_enq_rsp { 815 struct mbox_msghdr hdr; 816 union { 817 struct nix_cn10k_rq_ctx_s rq; 818 struct nix_cn10k_sq_ctx_s sq; 819 struct nix_cq_ctx_s cq; 820 struct nix_rsse_s rss; 821 struct nix_rx_mce_s mce; 822 struct nix_bandprof_s prof; 823 }; 824 }; 825 826 /* NIX AQ enqueue msg */ 827 struct nix_aq_enq_req { 828 struct mbox_msghdr hdr; 829 u32 qidx; 830 u8 ctype; 831 u8 op; 832 union { 833 struct nix_rq_ctx_s rq; 834 struct nix_sq_ctx_s sq; 835 struct nix_cq_ctx_s cq; 836 struct nix_rsse_s rss; 837 struct nix_rx_mce_s mce; 838 u64 prof; 839 }; 840 union { 841 struct nix_rq_ctx_s rq_mask; 842 struct nix_sq_ctx_s sq_mask; 843 struct nix_cq_ctx_s cq_mask; 844 struct nix_rsse_s rss_mask; 845 struct nix_rx_mce_s mce_mask; 846 u64 prof_mask; 847 }; 848 }; 849 850 struct nix_aq_enq_rsp { 851 struct mbox_msghdr hdr; 852 union { 853 struct nix_rq_ctx_s rq; 854 struct nix_sq_ctx_s sq; 855 struct nix_cq_ctx_s cq; 856 struct nix_rsse_s rss; 857 struct nix_rx_mce_s mce; 858 struct nix_bandprof_s prof; 859 }; 860 }; 861 862 /* Tx scheduler/shaper mailbox messages */ 863 864 #define MAX_TXSCHQ_PER_FUNC 128 865 866 struct nix_txsch_alloc_req { 867 struct mbox_msghdr hdr; 868 /* Scheduler queue count request at each level */ 869 u16 schq_contig[NIX_TXSCH_LVL_CNT]; /* No of contiguous queues */ 870 u16 schq[NIX_TXSCH_LVL_CNT]; /* No of non-contiguous queues */ 871 }; 872 873 struct nix_txsch_alloc_rsp { 874 struct mbox_msghdr hdr; 875 /* Scheduler queue count allocated at each level */ 876 u16 schq_contig[NIX_TXSCH_LVL_CNT]; 877 u16 schq[NIX_TXSCH_LVL_CNT]; 878 /* Scheduler queue list allocated at each level */ 879 u16 schq_contig_list[NIX_TXSCH_LVL_CNT][MAX_TXSCHQ_PER_FUNC]; 880 u16 schq_list[NIX_TXSCH_LVL_CNT][MAX_TXSCHQ_PER_FUNC]; 881 u8 aggr_level; /* Traffic aggregation scheduler level */ 882 u8 aggr_lvl_rr_prio; /* Aggregation lvl's RR_PRIO config */ 883 u8 link_cfg_lvl; /* LINKX_CFG CSRs mapped to TL3 or TL2's index ? */ 884 }; 885 886 struct nix_txsch_free_req { 887 struct mbox_msghdr hdr; 888 #define TXSCHQ_FREE_ALL BIT_ULL(0) 889 u16 flags; 890 /* Scheduler queue level to be freed */ 891 u16 schq_lvl; 892 /* List of scheduler queues to be freed */ 893 u16 schq; 894 }; 895 896 struct nix_txschq_config { 897 struct mbox_msghdr hdr; 898 u8 lvl; /* SMQ/MDQ/TL4/TL3/TL2/TL1 */ 899 u8 read; 900 #define TXSCHQ_IDX_SHIFT 16 901 #define TXSCHQ_IDX_MASK (BIT_ULL(10) - 1) 902 #define TXSCHQ_IDX(reg, shift) (((reg) >> (shift)) & TXSCHQ_IDX_MASK) 903 u8 num_regs; 904 #define MAX_REGS_PER_MBOX_MSG 20 905 u64 reg[MAX_REGS_PER_MBOX_MSG]; 906 u64 regval[MAX_REGS_PER_MBOX_MSG]; 907 /* All 0's => overwrite with new value */ 908 u64 regval_mask[MAX_REGS_PER_MBOX_MSG]; 909 }; 910 911 struct nix_vtag_config { 912 struct mbox_msghdr hdr; 913 /* '0' for 4 octet VTAG, '1' for 8 octet VTAG */ 914 u8 vtag_size; 915 /* cfg_type is '0' for tx vlan cfg 916 * cfg_type is '1' for rx vlan cfg 917 */ 918 u8 cfg_type; 919 union { 920 /* valid when cfg_type is '0' */ 921 struct { 922 u64 vtag0; 923 u64 vtag1; 924 925 /* cfg_vtag0 & cfg_vtag1 fields are valid 926 * when free_vtag0 & free_vtag1 are '0's. 927 */ 928 /* cfg_vtag0 = 1 to configure vtag0 */ 929 u8 cfg_vtag0 :1; 930 /* cfg_vtag1 = 1 to configure vtag1 */ 931 u8 cfg_vtag1 :1; 932 933 /* vtag0_idx & vtag1_idx are only valid when 934 * both cfg_vtag0 & cfg_vtag1 are '0's, 935 * these fields are used along with free_vtag0 936 * & free_vtag1 to free the nix lf's tx_vlan 937 * configuration. 938 * 939 * Denotes the indices of tx_vtag def registers 940 * that needs to be cleared and freed. 941 */ 942 int vtag0_idx; 943 int vtag1_idx; 944 945 /* free_vtag0 & free_vtag1 fields are valid 946 * when cfg_vtag0 & cfg_vtag1 are '0's. 947 */ 948 /* free_vtag0 = 1 clears vtag0 configuration 949 * vtag0_idx denotes the index to be cleared. 950 */ 951 u8 free_vtag0 :1; 952 /* free_vtag1 = 1 clears vtag1 configuration 953 * vtag1_idx denotes the index to be cleared. 954 */ 955 u8 free_vtag1 :1; 956 } tx; 957 958 /* valid when cfg_type is '1' */ 959 struct { 960 /* rx vtag type index, valid values are in 0..7 range */ 961 u8 vtag_type; 962 /* rx vtag strip */ 963 u8 strip_vtag :1; 964 /* rx vtag capture */ 965 u8 capture_vtag :1; 966 } rx; 967 }; 968 }; 969 970 struct nix_vtag_config_rsp { 971 struct mbox_msghdr hdr; 972 int vtag0_idx; 973 int vtag1_idx; 974 /* Indices of tx_vtag def registers used to configure 975 * tx vtag0 & vtag1 headers, these indices are valid 976 * when nix_vtag_config mbox requested for vtag0 and/ 977 * or vtag1 configuration. 978 */ 979 }; 980 981 struct nix_rss_flowkey_cfg { 982 struct mbox_msghdr hdr; 983 int mcam_index; /* MCAM entry index to modify */ 984 #define NIX_FLOW_KEY_TYPE_PORT BIT(0) 985 #define NIX_FLOW_KEY_TYPE_IPV4 BIT(1) 986 #define NIX_FLOW_KEY_TYPE_IPV6 BIT(2) 987 #define NIX_FLOW_KEY_TYPE_TCP BIT(3) 988 #define NIX_FLOW_KEY_TYPE_UDP BIT(4) 989 #define NIX_FLOW_KEY_TYPE_SCTP BIT(5) 990 #define NIX_FLOW_KEY_TYPE_NVGRE BIT(6) 991 #define NIX_FLOW_KEY_TYPE_VXLAN BIT(7) 992 #define NIX_FLOW_KEY_TYPE_GENEVE BIT(8) 993 #define NIX_FLOW_KEY_TYPE_ETH_DMAC BIT(9) 994 #define NIX_FLOW_KEY_TYPE_IPV6_EXT BIT(10) 995 #define NIX_FLOW_KEY_TYPE_GTPU BIT(11) 996 #define NIX_FLOW_KEY_TYPE_INNR_IPV4 BIT(12) 997 #define NIX_FLOW_KEY_TYPE_INNR_IPV6 BIT(13) 998 #define NIX_FLOW_KEY_TYPE_INNR_TCP BIT(14) 999 #define NIX_FLOW_KEY_TYPE_INNR_UDP BIT(15) 1000 #define NIX_FLOW_KEY_TYPE_INNR_SCTP BIT(16) 1001 #define NIX_FLOW_KEY_TYPE_INNR_ETH_DMAC BIT(17) 1002 #define NIX_FLOW_KEY_TYPE_VLAN BIT(20) 1003 #define NIX_FLOW_KEY_TYPE_IPV4_PROTO BIT(21) 1004 #define NIX_FLOW_KEY_TYPE_AH BIT(22) 1005 #define NIX_FLOW_KEY_TYPE_ESP BIT(23) 1006 u32 flowkey_cfg; /* Flowkey types selected */ 1007 u8 group; /* RSS context or group */ 1008 }; 1009 1010 struct nix_rss_flowkey_cfg_rsp { 1011 struct mbox_msghdr hdr; 1012 u8 alg_idx; /* Selected algo index */ 1013 }; 1014 1015 struct nix_set_mac_addr { 1016 struct mbox_msghdr hdr; 1017 u8 mac_addr[ETH_ALEN]; /* MAC address to be set for this pcifunc */ 1018 }; 1019 1020 struct nix_get_mac_addr_rsp { 1021 struct mbox_msghdr hdr; 1022 u8 mac_addr[ETH_ALEN]; 1023 }; 1024 1025 struct nix_mark_format_cfg { 1026 struct mbox_msghdr hdr; 1027 u8 offset; 1028 u8 y_mask; 1029 u8 y_val; 1030 u8 r_mask; 1031 u8 r_val; 1032 }; 1033 1034 struct nix_mark_format_cfg_rsp { 1035 struct mbox_msghdr hdr; 1036 u8 mark_format_idx; 1037 }; 1038 1039 struct nix_rx_mode { 1040 struct mbox_msghdr hdr; 1041 #define NIX_RX_MODE_UCAST BIT(0) 1042 #define NIX_RX_MODE_PROMISC BIT(1) 1043 #define NIX_RX_MODE_ALLMULTI BIT(2) 1044 #define NIX_RX_MODE_USE_MCE BIT(3) 1045 u16 mode; 1046 }; 1047 1048 struct nix_rx_cfg { 1049 struct mbox_msghdr hdr; 1050 #define NIX_RX_OL3_VERIFY BIT(0) 1051 #define NIX_RX_OL4_VERIFY BIT(1) 1052 u8 len_verify; /* Outer L3/L4 len check */ 1053 #define NIX_RX_CSUM_OL4_VERIFY BIT(0) 1054 u8 csum_verify; /* Outer L4 checksum verification */ 1055 }; 1056 1057 struct nix_frs_cfg { 1058 struct mbox_msghdr hdr; 1059 u8 update_smq; /* Update SMQ's min/max lens */ 1060 u8 update_minlen; /* Set minlen also */ 1061 u8 sdp_link; /* Set SDP RX link */ 1062 u16 maxlen; 1063 u16 minlen; 1064 }; 1065 1066 struct nix_lso_format_cfg { 1067 struct mbox_msghdr hdr; 1068 u64 field_mask; 1069 #define NIX_LSO_FIELD_MAX 8 1070 u64 fields[NIX_LSO_FIELD_MAX]; 1071 }; 1072 1073 struct nix_lso_format_cfg_rsp { 1074 struct mbox_msghdr hdr; 1075 u8 lso_format_idx; 1076 }; 1077 1078 struct nix_bp_cfg_req { 1079 struct mbox_msghdr hdr; 1080 u16 chan_base; /* Starting channel number */ 1081 u8 chan_cnt; /* Number of channels */ 1082 u8 bpid_per_chan; 1083 /* bpid_per_chan = 0 assigns single bp id for range of channels */ 1084 /* bpid_per_chan = 1 assigns separate bp id for each channel */ 1085 }; 1086 1087 /* PF can be mapped to either CGX or LBK interface, 1088 * so maximum 64 channels are possible. 1089 */ 1090 #define NIX_MAX_BPID_CHAN 64 1091 struct nix_bp_cfg_rsp { 1092 struct mbox_msghdr hdr; 1093 u16 chan_bpid[NIX_MAX_BPID_CHAN]; /* Channel and bpid mapping */ 1094 u8 chan_cnt; /* Number of channel for which bpids are assigned */ 1095 }; 1096 1097 /* Global NIX inline IPSec configuration */ 1098 struct nix_inline_ipsec_cfg { 1099 struct mbox_msghdr hdr; 1100 u32 cpt_credit; 1101 struct { 1102 u8 egrp; 1103 u8 opcode; 1104 u16 param1; 1105 u16 param2; 1106 } gen_cfg; 1107 struct { 1108 u16 cpt_pf_func; 1109 u8 cpt_slot; 1110 } inst_qsel; 1111 u8 enable; 1112 }; 1113 1114 /* Per NIX LF inline IPSec configuration */ 1115 struct nix_inline_ipsec_lf_cfg { 1116 struct mbox_msghdr hdr; 1117 u64 sa_base_addr; 1118 struct { 1119 u32 tag_const; 1120 u16 lenm1_max; 1121 u8 sa_pow2_size; 1122 u8 tt; 1123 } ipsec_cfg0; 1124 struct { 1125 u32 sa_idx_max; 1126 u8 sa_idx_w; 1127 } ipsec_cfg1; 1128 u8 enable; 1129 }; 1130 1131 struct nix_hw_info { 1132 struct mbox_msghdr hdr; 1133 u16 rsvs16; 1134 u16 max_mtu; 1135 u16 min_mtu; 1136 u32 rpm_dwrr_mtu; 1137 u32 sdp_dwrr_mtu; 1138 u64 rsvd[16]; /* Add reserved fields for future expansion */ 1139 }; 1140 1141 struct nix_bandprof_alloc_req { 1142 struct mbox_msghdr hdr; 1143 /* Count of profiles needed per layer */ 1144 u16 prof_count[BAND_PROF_NUM_LAYERS]; 1145 }; 1146 1147 struct nix_bandprof_alloc_rsp { 1148 struct mbox_msghdr hdr; 1149 u16 prof_count[BAND_PROF_NUM_LAYERS]; 1150 1151 /* There is no need to allocate morethan 1 bandwidth profile 1152 * per RQ of a PF_FUNC's NIXLF. So limit the maximum 1153 * profiles to 64 per PF_FUNC. 1154 */ 1155 #define MAX_BANDPROF_PER_PFFUNC 64 1156 u16 prof_idx[BAND_PROF_NUM_LAYERS][MAX_BANDPROF_PER_PFFUNC]; 1157 }; 1158 1159 struct nix_bandprof_free_req { 1160 struct mbox_msghdr hdr; 1161 u8 free_all; 1162 u16 prof_count[BAND_PROF_NUM_LAYERS]; 1163 u16 prof_idx[BAND_PROF_NUM_LAYERS][MAX_BANDPROF_PER_PFFUNC]; 1164 }; 1165 1166 struct nix_bandprof_get_hwinfo_rsp { 1167 struct mbox_msghdr hdr; 1168 u16 prof_count[BAND_PROF_NUM_LAYERS]; 1169 u32 policer_timeunit; 1170 }; 1171 1172 /* NPC mbox message structs */ 1173 1174 #define NPC_MCAM_ENTRY_INVALID 0xFFFF 1175 #define NPC_MCAM_INVALID_MAP 0xFFFF 1176 1177 /* NPC mailbox error codes 1178 * Range 701 - 800. 1179 */ 1180 enum npc_af_status { 1181 NPC_MCAM_INVALID_REQ = -701, 1182 NPC_MCAM_ALLOC_DENIED = -702, 1183 NPC_MCAM_ALLOC_FAILED = -703, 1184 NPC_MCAM_PERM_DENIED = -704, 1185 NPC_FLOW_INTF_INVALID = -707, 1186 NPC_FLOW_CHAN_INVALID = -708, 1187 NPC_FLOW_NO_NIXLF = -709, 1188 NPC_FLOW_NOT_SUPPORTED = -710, 1189 NPC_FLOW_VF_PERM_DENIED = -711, 1190 NPC_FLOW_VF_NOT_INIT = -712, 1191 NPC_FLOW_VF_OVERLAP = -713, 1192 }; 1193 1194 struct npc_mcam_alloc_entry_req { 1195 struct mbox_msghdr hdr; 1196 #define NPC_MAX_NONCONTIG_ENTRIES 256 1197 u8 contig; /* Contiguous entries ? */ 1198 #define NPC_MCAM_ANY_PRIO 0 1199 #define NPC_MCAM_LOWER_PRIO 1 1200 #define NPC_MCAM_HIGHER_PRIO 2 1201 u8 priority; /* Lower or higher w.r.t ref_entry */ 1202 u16 ref_entry; 1203 u16 count; /* Number of entries requested */ 1204 }; 1205 1206 struct npc_mcam_alloc_entry_rsp { 1207 struct mbox_msghdr hdr; 1208 u16 entry; /* Entry allocated or start index if contiguous. 1209 * Invalid incase of non-contiguous. 1210 */ 1211 u16 count; /* Number of entries allocated */ 1212 u16 free_count; /* Number of entries available */ 1213 u16 entry_list[NPC_MAX_NONCONTIG_ENTRIES]; 1214 }; 1215 1216 struct npc_mcam_free_entry_req { 1217 struct mbox_msghdr hdr; 1218 u16 entry; /* Entry index to be freed */ 1219 u8 all; /* If all entries allocated to this PFVF to be freed */ 1220 }; 1221 1222 struct mcam_entry { 1223 #define NPC_MAX_KWS_IN_KEY 7 /* Number of keywords in max keywidth */ 1224 u64 kw[NPC_MAX_KWS_IN_KEY]; 1225 u64 kw_mask[NPC_MAX_KWS_IN_KEY]; 1226 u64 action; 1227 u64 vtag_action; 1228 }; 1229 1230 struct npc_mcam_write_entry_req { 1231 struct mbox_msghdr hdr; 1232 struct mcam_entry entry_data; 1233 u16 entry; /* MCAM entry to write this match key */ 1234 u16 cntr; /* Counter for this MCAM entry */ 1235 u8 intf; /* Rx or Tx interface */ 1236 u8 enable_entry;/* Enable this MCAM entry ? */ 1237 u8 set_cntr; /* Set counter for this entry ? */ 1238 }; 1239 1240 /* Enable/Disable a given entry */ 1241 struct npc_mcam_ena_dis_entry_req { 1242 struct mbox_msghdr hdr; 1243 u16 entry; 1244 }; 1245 1246 struct npc_mcam_shift_entry_req { 1247 struct mbox_msghdr hdr; 1248 #define NPC_MCAM_MAX_SHIFTS 64 1249 u16 curr_entry[NPC_MCAM_MAX_SHIFTS]; 1250 u16 new_entry[NPC_MCAM_MAX_SHIFTS]; 1251 u16 shift_count; /* Number of entries to shift */ 1252 }; 1253 1254 struct npc_mcam_shift_entry_rsp { 1255 struct mbox_msghdr hdr; 1256 u16 failed_entry_idx; /* Index in 'curr_entry', not entry itself */ 1257 }; 1258 1259 struct npc_mcam_alloc_counter_req { 1260 struct mbox_msghdr hdr; 1261 u8 contig; /* Contiguous counters ? */ 1262 #define NPC_MAX_NONCONTIG_COUNTERS 64 1263 u16 count; /* Number of counters requested */ 1264 }; 1265 1266 struct npc_mcam_alloc_counter_rsp { 1267 struct mbox_msghdr hdr; 1268 u16 cntr; /* Counter allocated or start index if contiguous. 1269 * Invalid incase of non-contiguous. 1270 */ 1271 u16 count; /* Number of counters allocated */ 1272 u16 cntr_list[NPC_MAX_NONCONTIG_COUNTERS]; 1273 }; 1274 1275 struct npc_mcam_oper_counter_req { 1276 struct mbox_msghdr hdr; 1277 u16 cntr; /* Free a counter or clear/fetch it's stats */ 1278 }; 1279 1280 struct npc_mcam_oper_counter_rsp { 1281 struct mbox_msghdr hdr; 1282 u64 stat; /* valid only while fetching counter's stats */ 1283 }; 1284 1285 struct npc_mcam_unmap_counter_req { 1286 struct mbox_msghdr hdr; 1287 u16 cntr; 1288 u16 entry; /* Entry and counter to be unmapped */ 1289 u8 all; /* Unmap all entries using this counter ? */ 1290 }; 1291 1292 struct npc_mcam_alloc_and_write_entry_req { 1293 struct mbox_msghdr hdr; 1294 struct mcam_entry entry_data; 1295 u16 ref_entry; 1296 u8 priority; /* Lower or higher w.r.t ref_entry */ 1297 u8 intf; /* Rx or Tx interface */ 1298 u8 enable_entry;/* Enable this MCAM entry ? */ 1299 u8 alloc_cntr; /* Allocate counter and map ? */ 1300 }; 1301 1302 struct npc_mcam_alloc_and_write_entry_rsp { 1303 struct mbox_msghdr hdr; 1304 u16 entry; 1305 u16 cntr; 1306 }; 1307 1308 struct npc_get_kex_cfg_rsp { 1309 struct mbox_msghdr hdr; 1310 u64 rx_keyx_cfg; /* NPC_AF_INTF(0)_KEX_CFG */ 1311 u64 tx_keyx_cfg; /* NPC_AF_INTF(1)_KEX_CFG */ 1312 #define NPC_MAX_INTF 2 1313 #define NPC_MAX_LID 8 1314 #define NPC_MAX_LT 16 1315 #define NPC_MAX_LD 2 1316 #define NPC_MAX_LFL 16 1317 /* NPC_AF_KEX_LDATA(0..1)_FLAGS_CFG */ 1318 u64 kex_ld_flags[NPC_MAX_LD]; 1319 /* NPC_AF_INTF(0..1)_LID(0..7)_LT(0..15)_LD(0..1)_CFG */ 1320 u64 intf_lid_lt_ld[NPC_MAX_INTF][NPC_MAX_LID][NPC_MAX_LT][NPC_MAX_LD]; 1321 /* NPC_AF_INTF(0..1)_LDATA(0..1)_FLAGS(0..15)_CFG */ 1322 u64 intf_ld_flags[NPC_MAX_INTF][NPC_MAX_LD][NPC_MAX_LFL]; 1323 #define MKEX_NAME_LEN 128 1324 u8 mkex_pfl_name[MKEX_NAME_LEN]; 1325 }; 1326 1327 struct flow_msg { 1328 unsigned char dmac[6]; 1329 unsigned char smac[6]; 1330 __be16 etype; 1331 __be16 vlan_etype; 1332 __be16 vlan_tci; 1333 union { 1334 __be32 ip4src; 1335 __be32 ip6src[4]; 1336 }; 1337 union { 1338 __be32 ip4dst; 1339 __be32 ip6dst[4]; 1340 }; 1341 u8 tos; 1342 u8 ip_ver; 1343 u8 ip_proto; 1344 u8 tc; 1345 __be16 sport; 1346 __be16 dport; 1347 }; 1348 1349 struct npc_install_flow_req { 1350 struct mbox_msghdr hdr; 1351 struct flow_msg packet; 1352 struct flow_msg mask; 1353 u64 features; 1354 u16 entry; 1355 u16 channel; 1356 u16 chan_mask; 1357 u8 intf; 1358 u8 set_cntr; /* If counter is available set counter for this entry ? */ 1359 u8 default_rule; 1360 u8 append; /* overwrite(0) or append(1) flow to default rule? */ 1361 u16 vf; 1362 /* action */ 1363 u32 index; 1364 u16 match_id; 1365 u8 flow_key_alg; 1366 u8 op; 1367 /* vtag rx action */ 1368 u8 vtag0_type; 1369 u8 vtag0_valid; 1370 u8 vtag1_type; 1371 u8 vtag1_valid; 1372 /* vtag tx action */ 1373 u16 vtag0_def; 1374 u8 vtag0_op; 1375 u16 vtag1_def; 1376 u8 vtag1_op; 1377 }; 1378 1379 struct npc_install_flow_rsp { 1380 struct mbox_msghdr hdr; 1381 int counter; /* negative if no counter else counter number */ 1382 }; 1383 1384 struct npc_delete_flow_req { 1385 struct mbox_msghdr hdr; 1386 u16 entry; 1387 u16 start;/*Disable range of entries */ 1388 u16 end; 1389 u8 all; /* PF + VFs */ 1390 }; 1391 1392 struct npc_mcam_read_entry_req { 1393 struct mbox_msghdr hdr; 1394 u16 entry; /* MCAM entry to read */ 1395 }; 1396 1397 struct npc_mcam_read_entry_rsp { 1398 struct mbox_msghdr hdr; 1399 struct mcam_entry entry_data; 1400 u8 intf; 1401 u8 enable; 1402 }; 1403 1404 struct npc_mcam_read_base_rule_rsp { 1405 struct mbox_msghdr hdr; 1406 struct mcam_entry entry; 1407 }; 1408 1409 struct npc_mcam_get_stats_req { 1410 struct mbox_msghdr hdr; 1411 u16 entry; /* mcam entry */ 1412 }; 1413 1414 struct npc_mcam_get_stats_rsp { 1415 struct mbox_msghdr hdr; 1416 u64 stat; /* counter stats */ 1417 u8 stat_ena; /* enabled */ 1418 }; 1419 1420 enum ptp_op { 1421 PTP_OP_ADJFINE = 0, 1422 PTP_OP_GET_CLOCK = 1, 1423 PTP_OP_GET_TSTMP = 2, 1424 PTP_OP_SET_THRESH = 3, 1425 }; 1426 1427 struct ptp_req { 1428 struct mbox_msghdr hdr; 1429 u8 op; 1430 s64 scaled_ppm; 1431 u64 thresh; 1432 }; 1433 1434 struct ptp_rsp { 1435 struct mbox_msghdr hdr; 1436 u64 clk; 1437 }; 1438 1439 struct set_vf_perm { 1440 struct mbox_msghdr hdr; 1441 u16 vf; 1442 #define RESET_VF_PERM BIT_ULL(0) 1443 #define VF_TRUSTED BIT_ULL(1) 1444 u64 flags; 1445 }; 1446 1447 struct lmtst_tbl_setup_req { 1448 struct mbox_msghdr hdr; 1449 u64 dis_sched_early_comp :1; 1450 u64 sch_ena :1; 1451 u64 dis_line_pref :1; 1452 u64 ssow_pf_func :13; 1453 u16 base_pcifunc; 1454 u8 use_local_lmt_region; 1455 u64 lmt_iova; 1456 u64 rsvd[4]; 1457 }; 1458 1459 /* CPT mailbox error codes 1460 * Range 901 - 1000. 1461 */ 1462 enum cpt_af_status { 1463 CPT_AF_ERR_PARAM = -901, 1464 CPT_AF_ERR_GRP_INVALID = -902, 1465 CPT_AF_ERR_LF_INVALID = -903, 1466 CPT_AF_ERR_ACCESS_DENIED = -904, 1467 CPT_AF_ERR_SSO_PF_FUNC_INVALID = -905, 1468 CPT_AF_ERR_NIX_PF_FUNC_INVALID = -906, 1469 CPT_AF_ERR_INLINE_IPSEC_INB_ENA = -907, 1470 CPT_AF_ERR_INLINE_IPSEC_OUT_ENA = -908 1471 }; 1472 1473 /* CPT mbox message formats */ 1474 struct cpt_rd_wr_reg_msg { 1475 struct mbox_msghdr hdr; 1476 u64 reg_offset; 1477 u64 *ret_val; 1478 u64 val; 1479 u8 is_write; 1480 int blkaddr; 1481 }; 1482 1483 struct cpt_lf_alloc_req_msg { 1484 struct mbox_msghdr hdr; 1485 u16 nix_pf_func; 1486 u16 sso_pf_func; 1487 u16 eng_grpmsk; 1488 int blkaddr; 1489 }; 1490 1491 #define CPT_INLINE_INBOUND 0 1492 #define CPT_INLINE_OUTBOUND 1 1493 1494 /* Mailbox message request format for CPT IPsec 1495 * inline inbound and outbound configuration. 1496 */ 1497 struct cpt_inline_ipsec_cfg_msg { 1498 struct mbox_msghdr hdr; 1499 u8 enable; 1500 u8 slot; 1501 u8 dir; 1502 u8 sso_pf_func_ovrd; 1503 u16 sso_pf_func; /* inbound path SSO_PF_FUNC */ 1504 u16 nix_pf_func; /* outbound path NIX_PF_FUNC */ 1505 }; 1506 1507 /* Mailbox message request and response format for CPT stats. */ 1508 struct cpt_sts_req { 1509 struct mbox_msghdr hdr; 1510 u8 blkaddr; 1511 }; 1512 1513 struct cpt_sts_rsp { 1514 struct mbox_msghdr hdr; 1515 u64 inst_req_pc; 1516 u64 inst_lat_pc; 1517 u64 rd_req_pc; 1518 u64 rd_lat_pc; 1519 u64 rd_uc_pc; 1520 u64 active_cycles_pc; 1521 u64 ctx_mis_pc; 1522 u64 ctx_hit_pc; 1523 u64 ctx_aop_pc; 1524 u64 ctx_aop_lat_pc; 1525 u64 ctx_ifetch_pc; 1526 u64 ctx_ifetch_lat_pc; 1527 u64 ctx_ffetch_pc; 1528 u64 ctx_ffetch_lat_pc; 1529 u64 ctx_wback_pc; 1530 u64 ctx_wback_lat_pc; 1531 u64 ctx_psh_pc; 1532 u64 ctx_psh_lat_pc; 1533 u64 ctx_err; 1534 u64 ctx_enc_id; 1535 u64 ctx_flush_timer; 1536 u64 rxc_time; 1537 u64 rxc_time_cfg; 1538 u64 rxc_active_sts; 1539 u64 rxc_zombie_sts; 1540 u64 busy_sts_ae; 1541 u64 free_sts_ae; 1542 u64 busy_sts_se; 1543 u64 free_sts_se; 1544 u64 busy_sts_ie; 1545 u64 free_sts_ie; 1546 u64 exe_err_info; 1547 u64 cptclk_cnt; 1548 u64 diag; 1549 u64 rxc_dfrg; 1550 u64 x2p_link_cfg0; 1551 u64 x2p_link_cfg1; 1552 }; 1553 1554 /* Mailbox message request format to configure reassembly timeout. */ 1555 struct cpt_rxc_time_cfg_req { 1556 struct mbox_msghdr hdr; 1557 int blkaddr; 1558 u32 step; 1559 u16 zombie_thres; 1560 u16 zombie_limit; 1561 u16 active_thres; 1562 u16 active_limit; 1563 }; 1564 1565 struct sdp_node_info { 1566 /* Node to which this PF belons to */ 1567 u8 node_id; 1568 u8 max_vfs; 1569 u8 num_pf_rings; 1570 u8 pf_srn; 1571 #define SDP_MAX_VFS 128 1572 u8 vf_rings[SDP_MAX_VFS]; 1573 }; 1574 1575 struct sdp_chan_info_msg { 1576 struct mbox_msghdr hdr; 1577 struct sdp_node_info info; 1578 }; 1579 1580 struct sdp_get_chan_info_msg { 1581 struct mbox_msghdr hdr; 1582 u16 chan_base; 1583 u16 num_chan; 1584 }; 1585 1586 /* CGX mailbox error codes 1587 * Range 1101 - 1200. 1588 */ 1589 enum cgx_af_status { 1590 LMAC_AF_ERR_INVALID_PARAM = -1101, 1591 LMAC_AF_ERR_PF_NOT_MAPPED = -1102, 1592 LMAC_AF_ERR_PERM_DENIED = -1103, 1593 }; 1594 1595 #endif /* MBOX_H */ 1596