1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Marvell RVU Admin Function driver 3 * 4 * Copyright (C) 2018 Marvell. 5 * 6 */ 7 8 #ifndef MBOX_H 9 #define MBOX_H 10 11 #include <linux/etherdevice.h> 12 #include <linux/sizes.h> 13 14 #include "rvu_struct.h" 15 #include "common.h" 16 17 #define MBOX_SIZE SZ_64K 18 19 /* AF/PF: PF initiated, PF/VF VF initiated */ 20 #define MBOX_DOWN_RX_START 0 21 #define MBOX_DOWN_RX_SIZE (46 * SZ_1K) 22 #define MBOX_DOWN_TX_START (MBOX_DOWN_RX_START + MBOX_DOWN_RX_SIZE) 23 #define MBOX_DOWN_TX_SIZE (16 * SZ_1K) 24 /* AF/PF: AF initiated, PF/VF PF initiated */ 25 #define MBOX_UP_RX_START (MBOX_DOWN_TX_START + MBOX_DOWN_TX_SIZE) 26 #define MBOX_UP_RX_SIZE SZ_1K 27 #define MBOX_UP_TX_START (MBOX_UP_RX_START + MBOX_UP_RX_SIZE) 28 #define MBOX_UP_TX_SIZE SZ_1K 29 30 #if MBOX_UP_TX_SIZE + MBOX_UP_TX_START != MBOX_SIZE 31 # error "incorrect mailbox area sizes" 32 #endif 33 34 #define INTR_MASK(pfvfs) ((pfvfs < 64) ? (BIT_ULL(pfvfs) - 1) : (~0ull)) 35 36 #define MBOX_RSP_TIMEOUT 6000 /* Time(ms) to wait for mbox response */ 37 38 #define MBOX_MSG_ALIGN 16 /* Align mbox msg start to 16bytes */ 39 40 /* Mailbox directions */ 41 #define MBOX_DIR_AFPF 0 /* AF replies to PF */ 42 #define MBOX_DIR_PFAF 1 /* PF sends messages to AF */ 43 #define MBOX_DIR_PFVF 2 /* PF replies to VF */ 44 #define MBOX_DIR_VFPF 3 /* VF sends messages to PF */ 45 #define MBOX_DIR_AFPF_UP 4 /* AF sends messages to PF */ 46 #define MBOX_DIR_PFAF_UP 5 /* PF replies to AF */ 47 #define MBOX_DIR_PFVF_UP 6 /* PF sends messages to VF */ 48 #define MBOX_DIR_VFPF_UP 7 /* VF replies to PF */ 49 50 struct otx2_mbox_dev { 51 void *mbase; /* This dev's mbox region */ 52 void *hwbase; 53 spinlock_t mbox_lock; 54 u16 msg_size; /* Total msg size to be sent */ 55 u16 rsp_size; /* Total rsp size to be sure the reply is ok */ 56 u16 num_msgs; /* No of msgs sent or waiting for response */ 57 u16 msgs_acked; /* No of msgs for which response is received */ 58 }; 59 60 struct otx2_mbox { 61 struct pci_dev *pdev; 62 void *hwbase; /* Mbox region advertised by HW */ 63 void *reg_base;/* CSR base for this dev */ 64 u64 trigger; /* Trigger mbox notification */ 65 u16 tr_shift; /* Mbox trigger shift */ 66 u64 rx_start; /* Offset of Rx region in mbox memory */ 67 u64 tx_start; /* Offset of Tx region in mbox memory */ 68 u16 rx_size; /* Size of Rx region */ 69 u16 tx_size; /* Size of Tx region */ 70 u16 ndevs; /* The number of peers */ 71 struct otx2_mbox_dev *dev; 72 }; 73 74 /* Header which precedes all mbox messages */ 75 struct mbox_hdr { 76 u64 msg_size; /* Total msgs size embedded */ 77 u16 num_msgs; /* No of msgs embedded */ 78 }; 79 80 /* Header which precedes every msg and is also part of it */ 81 struct mbox_msghdr { 82 u16 pcifunc; /* Who's sending this msg */ 83 u16 id; /* Mbox message ID */ 84 #define OTX2_MBOX_REQ_SIG (0xdead) 85 #define OTX2_MBOX_RSP_SIG (0xbeef) 86 u16 sig; /* Signature, for validating corrupted msgs */ 87 #define OTX2_MBOX_VERSION (0x000a) 88 u16 ver; /* Version of msg's structure for this ID */ 89 u16 next_msgoff; /* Offset of next msg within mailbox region */ 90 int rc; /* Msg process'ed response code */ 91 }; 92 93 void otx2_mbox_reset(struct otx2_mbox *mbox, int devid); 94 void __otx2_mbox_reset(struct otx2_mbox *mbox, int devid); 95 void otx2_mbox_destroy(struct otx2_mbox *mbox); 96 int otx2_mbox_init(struct otx2_mbox *mbox, void __force *hwbase, 97 struct pci_dev *pdev, void __force *reg_base, 98 int direction, int ndevs); 99 int otx2_mbox_regions_init(struct otx2_mbox *mbox, void __force **hwbase, 100 struct pci_dev *pdev, void __force *reg_base, 101 int direction, int ndevs); 102 void otx2_mbox_msg_send(struct otx2_mbox *mbox, int devid); 103 int otx2_mbox_wait_for_rsp(struct otx2_mbox *mbox, int devid); 104 int otx2_mbox_busy_poll_for_rsp(struct otx2_mbox *mbox, int devid); 105 struct mbox_msghdr *otx2_mbox_alloc_msg_rsp(struct otx2_mbox *mbox, int devid, 106 int size, int size_rsp); 107 struct mbox_msghdr *otx2_mbox_get_rsp(struct otx2_mbox *mbox, int devid, 108 struct mbox_msghdr *msg); 109 int otx2_mbox_check_rsp_msgs(struct otx2_mbox *mbox, int devid); 110 int otx2_reply_invalid_msg(struct otx2_mbox *mbox, int devid, 111 u16 pcifunc, u16 id); 112 bool otx2_mbox_nonempty(struct otx2_mbox *mbox, int devid); 113 const char *otx2_mbox_id2name(u16 id); 114 static inline struct mbox_msghdr *otx2_mbox_alloc_msg(struct otx2_mbox *mbox, 115 int devid, int size) 116 { 117 return otx2_mbox_alloc_msg_rsp(mbox, devid, size, 0); 118 } 119 120 /* Mailbox message types */ 121 #define MBOX_MSG_MASK 0xFFFF 122 #define MBOX_MSG_INVALID 0xFFFE 123 #define MBOX_MSG_MAX 0xFFFF 124 125 #define MBOX_MESSAGES \ 126 /* Generic mbox IDs (range 0x000 - 0x1FF) */ \ 127 M(READY, 0x001, ready, msg_req, ready_msg_rsp) \ 128 M(ATTACH_RESOURCES, 0x002, attach_resources, rsrc_attach, msg_rsp) \ 129 M(DETACH_RESOURCES, 0x003, detach_resources, rsrc_detach, msg_rsp) \ 130 M(FREE_RSRC_CNT, 0x004, free_rsrc_cnt, msg_req, free_rsrcs_rsp) \ 131 M(MSIX_OFFSET, 0x005, msix_offset, msg_req, msix_offset_rsp) \ 132 M(VF_FLR, 0x006, vf_flr, msg_req, msg_rsp) \ 133 M(PTP_OP, 0x007, ptp_op, ptp_req, ptp_rsp) \ 134 M(GET_HW_CAP, 0x008, get_hw_cap, msg_req, get_hw_cap_rsp) \ 135 M(LMTST_TBL_SETUP, 0x00a, lmtst_tbl_setup, lmtst_tbl_setup_req, \ 136 msg_rsp) \ 137 M(SET_VF_PERM, 0x00b, set_vf_perm, set_vf_perm, msg_rsp) \ 138 /* CGX mbox IDs (range 0x200 - 0x3FF) */ \ 139 M(CGX_START_RXTX, 0x200, cgx_start_rxtx, msg_req, msg_rsp) \ 140 M(CGX_STOP_RXTX, 0x201, cgx_stop_rxtx, msg_req, msg_rsp) \ 141 M(CGX_STATS, 0x202, cgx_stats, msg_req, cgx_stats_rsp) \ 142 M(CGX_MAC_ADDR_SET, 0x203, cgx_mac_addr_set, cgx_mac_addr_set_or_get, \ 143 cgx_mac_addr_set_or_get) \ 144 M(CGX_MAC_ADDR_GET, 0x204, cgx_mac_addr_get, cgx_mac_addr_set_or_get, \ 145 cgx_mac_addr_set_or_get) \ 146 M(CGX_PROMISC_ENABLE, 0x205, cgx_promisc_enable, msg_req, msg_rsp) \ 147 M(CGX_PROMISC_DISABLE, 0x206, cgx_promisc_disable, msg_req, msg_rsp) \ 148 M(CGX_START_LINKEVENTS, 0x207, cgx_start_linkevents, msg_req, msg_rsp) \ 149 M(CGX_STOP_LINKEVENTS, 0x208, cgx_stop_linkevents, msg_req, msg_rsp) \ 150 M(CGX_GET_LINKINFO, 0x209, cgx_get_linkinfo, msg_req, cgx_link_info_msg) \ 151 M(CGX_INTLBK_ENABLE, 0x20A, cgx_intlbk_enable, msg_req, msg_rsp) \ 152 M(CGX_INTLBK_DISABLE, 0x20B, cgx_intlbk_disable, msg_req, msg_rsp) \ 153 M(CGX_PTP_RX_ENABLE, 0x20C, cgx_ptp_rx_enable, msg_req, msg_rsp) \ 154 M(CGX_PTP_RX_DISABLE, 0x20D, cgx_ptp_rx_disable, msg_req, msg_rsp) \ 155 M(CGX_CFG_PAUSE_FRM, 0x20E, cgx_cfg_pause_frm, cgx_pause_frm_cfg, \ 156 cgx_pause_frm_cfg) \ 157 M(CGX_FW_DATA_GET, 0x20F, cgx_get_aux_link_info, msg_req, cgx_fw_data) \ 158 M(CGX_FEC_SET, 0x210, cgx_set_fec_param, fec_mode, fec_mode) \ 159 M(CGX_MAC_ADDR_ADD, 0x211, cgx_mac_addr_add, cgx_mac_addr_add_req, \ 160 cgx_mac_addr_add_rsp) \ 161 M(CGX_MAC_ADDR_DEL, 0x212, cgx_mac_addr_del, cgx_mac_addr_del_req, \ 162 msg_rsp) \ 163 M(CGX_MAC_MAX_ENTRIES_GET, 0x213, cgx_mac_max_entries_get, msg_req, \ 164 cgx_max_dmac_entries_get_rsp) \ 165 M(CGX_FEC_STATS, 0x217, cgx_fec_stats, msg_req, cgx_fec_stats_rsp) \ 166 M(CGX_SET_LINK_MODE, 0x218, cgx_set_link_mode, cgx_set_link_mode_req,\ 167 cgx_set_link_mode_rsp) \ 168 M(CGX_GET_PHY_FEC_STATS, 0x219, cgx_get_phy_fec_stats, msg_req, msg_rsp) \ 169 M(CGX_FEATURES_GET, 0x21B, cgx_features_get, msg_req, \ 170 cgx_features_info_msg) \ 171 M(RPM_STATS, 0x21C, rpm_stats, msg_req, rpm_stats_rsp) \ 172 M(CGX_MAC_ADDR_RESET, 0x21D, cgx_mac_addr_reset, cgx_mac_addr_reset_req, \ 173 msg_rsp) \ 174 M(CGX_MAC_ADDR_UPDATE, 0x21E, cgx_mac_addr_update, cgx_mac_addr_update_req, \ 175 cgx_mac_addr_update_rsp) \ 176 M(CGX_PRIO_FLOW_CTRL_CFG, 0x21F, cgx_prio_flow_ctrl_cfg, cgx_pfc_cfg, \ 177 cgx_pfc_rsp) \ 178 /* NPA mbox IDs (range 0x400 - 0x5FF) */ \ 179 M(NPA_LF_ALLOC, 0x400, npa_lf_alloc, \ 180 npa_lf_alloc_req, npa_lf_alloc_rsp) \ 181 M(NPA_LF_FREE, 0x401, npa_lf_free, msg_req, msg_rsp) \ 182 M(NPA_AQ_ENQ, 0x402, npa_aq_enq, npa_aq_enq_req, npa_aq_enq_rsp) \ 183 M(NPA_HWCTX_DISABLE, 0x403, npa_hwctx_disable, hwctx_disable_req, msg_rsp)\ 184 /* SSO/SSOW mbox IDs (range 0x600 - 0x7FF) */ \ 185 /* TIM mbox IDs (range 0x800 - 0x9FF) */ \ 186 /* CPT mbox IDs (range 0xA00 - 0xBFF) */ \ 187 M(CPT_LF_ALLOC, 0xA00, cpt_lf_alloc, cpt_lf_alloc_req_msg, \ 188 msg_rsp) \ 189 M(CPT_LF_FREE, 0xA01, cpt_lf_free, msg_req, msg_rsp) \ 190 M(CPT_RD_WR_REGISTER, 0xA02, cpt_rd_wr_register, cpt_rd_wr_reg_msg, \ 191 cpt_rd_wr_reg_msg) \ 192 M(CPT_INLINE_IPSEC_CFG, 0xA04, cpt_inline_ipsec_cfg, \ 193 cpt_inline_ipsec_cfg_msg, msg_rsp) \ 194 M(CPT_STATS, 0xA05, cpt_sts, cpt_sts_req, cpt_sts_rsp) \ 195 M(CPT_RXC_TIME_CFG, 0xA06, cpt_rxc_time_cfg, cpt_rxc_time_cfg_req, \ 196 msg_rsp) \ 197 M(CPT_CTX_CACHE_SYNC, 0xA07, cpt_ctx_cache_sync, msg_req, msg_rsp) \ 198 /* SDP mbox IDs (range 0x1000 - 0x11FF) */ \ 199 M(SET_SDP_CHAN_INFO, 0x1000, set_sdp_chan_info, sdp_chan_info_msg, msg_rsp) \ 200 M(GET_SDP_CHAN_INFO, 0x1001, get_sdp_chan_info, msg_req, sdp_get_chan_info_msg) \ 201 /* NPC mbox IDs (range 0x6000 - 0x7FFF) */ \ 202 M(NPC_MCAM_ALLOC_ENTRY, 0x6000, npc_mcam_alloc_entry, npc_mcam_alloc_entry_req,\ 203 npc_mcam_alloc_entry_rsp) \ 204 M(NPC_MCAM_FREE_ENTRY, 0x6001, npc_mcam_free_entry, \ 205 npc_mcam_free_entry_req, msg_rsp) \ 206 M(NPC_MCAM_WRITE_ENTRY, 0x6002, npc_mcam_write_entry, \ 207 npc_mcam_write_entry_req, msg_rsp) \ 208 M(NPC_MCAM_ENA_ENTRY, 0x6003, npc_mcam_ena_entry, \ 209 npc_mcam_ena_dis_entry_req, msg_rsp) \ 210 M(NPC_MCAM_DIS_ENTRY, 0x6004, npc_mcam_dis_entry, \ 211 npc_mcam_ena_dis_entry_req, msg_rsp) \ 212 M(NPC_MCAM_SHIFT_ENTRY, 0x6005, npc_mcam_shift_entry, npc_mcam_shift_entry_req,\ 213 npc_mcam_shift_entry_rsp) \ 214 M(NPC_MCAM_ALLOC_COUNTER, 0x6006, npc_mcam_alloc_counter, \ 215 npc_mcam_alloc_counter_req, \ 216 npc_mcam_alloc_counter_rsp) \ 217 M(NPC_MCAM_FREE_COUNTER, 0x6007, npc_mcam_free_counter, \ 218 npc_mcam_oper_counter_req, msg_rsp) \ 219 M(NPC_MCAM_UNMAP_COUNTER, 0x6008, npc_mcam_unmap_counter, \ 220 npc_mcam_unmap_counter_req, msg_rsp) \ 221 M(NPC_MCAM_CLEAR_COUNTER, 0x6009, npc_mcam_clear_counter, \ 222 npc_mcam_oper_counter_req, msg_rsp) \ 223 M(NPC_MCAM_COUNTER_STATS, 0x600a, npc_mcam_counter_stats, \ 224 npc_mcam_oper_counter_req, \ 225 npc_mcam_oper_counter_rsp) \ 226 M(NPC_MCAM_ALLOC_AND_WRITE_ENTRY, 0x600b, npc_mcam_alloc_and_write_entry, \ 227 npc_mcam_alloc_and_write_entry_req, \ 228 npc_mcam_alloc_and_write_entry_rsp) \ 229 M(NPC_GET_KEX_CFG, 0x600c, npc_get_kex_cfg, \ 230 msg_req, npc_get_kex_cfg_rsp) \ 231 M(NPC_INSTALL_FLOW, 0x600d, npc_install_flow, \ 232 npc_install_flow_req, npc_install_flow_rsp) \ 233 M(NPC_DELETE_FLOW, 0x600e, npc_delete_flow, \ 234 npc_delete_flow_req, msg_rsp) \ 235 M(NPC_MCAM_READ_ENTRY, 0x600f, npc_mcam_read_entry, \ 236 npc_mcam_read_entry_req, \ 237 npc_mcam_read_entry_rsp) \ 238 M(NPC_SET_PKIND, 0x6010, npc_set_pkind, \ 239 npc_set_pkind, msg_rsp) \ 240 M(NPC_MCAM_READ_BASE_RULE, 0x6011, npc_read_base_steer_rule, \ 241 msg_req, npc_mcam_read_base_rule_rsp) \ 242 M(NPC_MCAM_GET_STATS, 0x6012, npc_mcam_entry_stats, \ 243 npc_mcam_get_stats_req, \ 244 npc_mcam_get_stats_rsp) \ 245 M(NPC_GET_SECRET_KEY, 0x6013, npc_get_secret_key, \ 246 npc_get_secret_key_req, \ 247 npc_get_secret_key_rsp) \ 248 /* NIX mbox IDs (range 0x8000 - 0xFFFF) */ \ 249 M(NIX_LF_ALLOC, 0x8000, nix_lf_alloc, \ 250 nix_lf_alloc_req, nix_lf_alloc_rsp) \ 251 M(NIX_LF_FREE, 0x8001, nix_lf_free, nix_lf_free_req, msg_rsp) \ 252 M(NIX_AQ_ENQ, 0x8002, nix_aq_enq, nix_aq_enq_req, nix_aq_enq_rsp) \ 253 M(NIX_HWCTX_DISABLE, 0x8003, nix_hwctx_disable, \ 254 hwctx_disable_req, msg_rsp) \ 255 M(NIX_TXSCH_ALLOC, 0x8004, nix_txsch_alloc, \ 256 nix_txsch_alloc_req, nix_txsch_alloc_rsp) \ 257 M(NIX_TXSCH_FREE, 0x8005, nix_txsch_free, nix_txsch_free_req, msg_rsp) \ 258 M(NIX_TXSCHQ_CFG, 0x8006, nix_txschq_cfg, nix_txschq_config, \ 259 nix_txschq_config) \ 260 M(NIX_STATS_RST, 0x8007, nix_stats_rst, msg_req, msg_rsp) \ 261 M(NIX_VTAG_CFG, 0x8008, nix_vtag_cfg, nix_vtag_config, \ 262 nix_vtag_config_rsp) \ 263 M(NIX_RSS_FLOWKEY_CFG, 0x8009, nix_rss_flowkey_cfg, \ 264 nix_rss_flowkey_cfg, \ 265 nix_rss_flowkey_cfg_rsp) \ 266 M(NIX_SET_MAC_ADDR, 0x800a, nix_set_mac_addr, nix_set_mac_addr, msg_rsp) \ 267 M(NIX_SET_RX_MODE, 0x800b, nix_set_rx_mode, nix_rx_mode, msg_rsp) \ 268 M(NIX_SET_HW_FRS, 0x800c, nix_set_hw_frs, nix_frs_cfg, msg_rsp) \ 269 M(NIX_LF_START_RX, 0x800d, nix_lf_start_rx, msg_req, msg_rsp) \ 270 M(NIX_LF_STOP_RX, 0x800e, nix_lf_stop_rx, msg_req, msg_rsp) \ 271 M(NIX_MARK_FORMAT_CFG, 0x800f, nix_mark_format_cfg, \ 272 nix_mark_format_cfg, \ 273 nix_mark_format_cfg_rsp) \ 274 M(NIX_SET_RX_CFG, 0x8010, nix_set_rx_cfg, nix_rx_cfg, msg_rsp) \ 275 M(NIX_LSO_FORMAT_CFG, 0x8011, nix_lso_format_cfg, \ 276 nix_lso_format_cfg, \ 277 nix_lso_format_cfg_rsp) \ 278 M(NIX_LF_PTP_TX_ENABLE, 0x8013, nix_lf_ptp_tx_enable, msg_req, msg_rsp) \ 279 M(NIX_LF_PTP_TX_DISABLE, 0x8014, nix_lf_ptp_tx_disable, msg_req, msg_rsp) \ 280 M(NIX_BP_ENABLE, 0x8016, nix_bp_enable, nix_bp_cfg_req, \ 281 nix_bp_cfg_rsp) \ 282 M(NIX_BP_DISABLE, 0x8017, nix_bp_disable, nix_bp_cfg_req, msg_rsp) \ 283 M(NIX_GET_MAC_ADDR, 0x8018, nix_get_mac_addr, msg_req, nix_get_mac_addr_rsp) \ 284 M(NIX_INLINE_IPSEC_CFG, 0x8019, nix_inline_ipsec_cfg, \ 285 nix_inline_ipsec_cfg, msg_rsp) \ 286 M(NIX_INLINE_IPSEC_LF_CFG, 0x801a, nix_inline_ipsec_lf_cfg, \ 287 nix_inline_ipsec_lf_cfg, msg_rsp) \ 288 M(NIX_CN10K_AQ_ENQ, 0x801b, nix_cn10k_aq_enq, nix_cn10k_aq_enq_req, \ 289 nix_cn10k_aq_enq_rsp) \ 290 M(NIX_GET_HW_INFO, 0x801c, nix_get_hw_info, msg_req, nix_hw_info) \ 291 M(NIX_BANDPROF_ALLOC, 0x801d, nix_bandprof_alloc, nix_bandprof_alloc_req, \ 292 nix_bandprof_alloc_rsp) \ 293 M(NIX_BANDPROF_FREE, 0x801e, nix_bandprof_free, nix_bandprof_free_req, \ 294 msg_rsp) \ 295 M(NIX_BANDPROF_GET_HWINFO, 0x801f, nix_bandprof_get_hwinfo, msg_req, \ 296 nix_bandprof_get_hwinfo_rsp) 297 298 /* Messages initiated by AF (range 0xC00 - 0xDFF) */ 299 #define MBOX_UP_CGX_MESSAGES \ 300 M(CGX_LINK_EVENT, 0xC00, cgx_link_event, cgx_link_info_msg, msg_rsp) 301 302 #define MBOX_UP_CPT_MESSAGES \ 303 M(CPT_INST_LMTST, 0xD00, cpt_inst_lmtst, cpt_inst_lmtst_req, msg_rsp) 304 305 enum { 306 #define M(_name, _id, _1, _2, _3) MBOX_MSG_ ## _name = _id, 307 MBOX_MESSAGES 308 MBOX_UP_CGX_MESSAGES 309 MBOX_UP_CPT_MESSAGES 310 #undef M 311 }; 312 313 /* Mailbox message formats */ 314 315 #define RVU_DEFAULT_PF_FUNC 0xFFFF 316 317 /* Generic request msg used for those mbox messages which 318 * don't send any data in the request. 319 */ 320 struct msg_req { 321 struct mbox_msghdr hdr; 322 }; 323 324 /* Generic response msg used an ack or response for those mbox 325 * messages which don't have a specific rsp msg format. 326 */ 327 struct msg_rsp { 328 struct mbox_msghdr hdr; 329 }; 330 331 /* RVU mailbox error codes 332 * Range 256 - 300. 333 */ 334 enum rvu_af_status { 335 RVU_INVALID_VF_ID = -256, 336 }; 337 338 struct ready_msg_rsp { 339 struct mbox_msghdr hdr; 340 u16 sclk_freq; /* SCLK frequency (in MHz) */ 341 u16 rclk_freq; /* RCLK frequency (in MHz) */ 342 }; 343 344 /* Structure for requesting resource provisioning. 345 * 'modify' flag to be used when either requesting more 346 * or to detach partial of a certain resource type. 347 * Rest of the fields specify how many of what type to 348 * be attached. 349 * To request LFs from two blocks of same type this mailbox 350 * can be sent twice as below: 351 * struct rsrc_attach *attach; 352 * .. Allocate memory for message .. 353 * attach->cptlfs = 3; <3 LFs from CPT0> 354 * .. Send message .. 355 * .. Allocate memory for message .. 356 * attach->modify = 1; 357 * attach->cpt_blkaddr = BLKADDR_CPT1; 358 * attach->cptlfs = 2; <2 LFs from CPT1> 359 * .. Send message .. 360 */ 361 struct rsrc_attach { 362 struct mbox_msghdr hdr; 363 u8 modify:1; 364 u8 npalf:1; 365 u8 nixlf:1; 366 u16 sso; 367 u16 ssow; 368 u16 timlfs; 369 u16 cptlfs; 370 int cpt_blkaddr; /* BLKADDR_CPT0/BLKADDR_CPT1 or 0 for BLKADDR_CPT0 */ 371 }; 372 373 /* Structure for relinquishing resources. 374 * 'partial' flag to be used when relinquishing all resources 375 * but only of a certain type. If not set, all resources of all 376 * types provisioned to the RVU function will be detached. 377 */ 378 struct rsrc_detach { 379 struct mbox_msghdr hdr; 380 u8 partial:1; 381 u8 npalf:1; 382 u8 nixlf:1; 383 u8 sso:1; 384 u8 ssow:1; 385 u8 timlfs:1; 386 u8 cptlfs:1; 387 }; 388 389 /* Number of resources available to the caller. 390 * In reply to MBOX_MSG_FREE_RSRC_CNT. 391 */ 392 struct free_rsrcs_rsp { 393 struct mbox_msghdr hdr; 394 u16 schq[NIX_TXSCH_LVL_CNT]; 395 u16 sso; 396 u16 tim; 397 u16 ssow; 398 u16 cpt; 399 u8 npa; 400 u8 nix; 401 u16 schq_nix1[NIX_TXSCH_LVL_CNT]; 402 u8 nix1; 403 u8 cpt1; 404 u8 ree0; 405 u8 ree1; 406 }; 407 408 #define MSIX_VECTOR_INVALID 0xFFFF 409 #define MAX_RVU_BLKLF_CNT 256 410 411 struct msix_offset_rsp { 412 struct mbox_msghdr hdr; 413 u16 npa_msixoff; 414 u16 nix_msixoff; 415 u16 sso; 416 u16 ssow; 417 u16 timlfs; 418 u16 cptlfs; 419 u16 sso_msixoff[MAX_RVU_BLKLF_CNT]; 420 u16 ssow_msixoff[MAX_RVU_BLKLF_CNT]; 421 u16 timlf_msixoff[MAX_RVU_BLKLF_CNT]; 422 u16 cptlf_msixoff[MAX_RVU_BLKLF_CNT]; 423 u16 cpt1_lfs; 424 u16 ree0_lfs; 425 u16 ree1_lfs; 426 u16 cpt1_lf_msixoff[MAX_RVU_BLKLF_CNT]; 427 u16 ree0_lf_msixoff[MAX_RVU_BLKLF_CNT]; 428 u16 ree1_lf_msixoff[MAX_RVU_BLKLF_CNT]; 429 }; 430 431 struct get_hw_cap_rsp { 432 struct mbox_msghdr hdr; 433 u8 nix_fixed_txschq_mapping; /* Schq mapping fixed or flexible */ 434 u8 nix_shaping; /* Is shaping and coloring supported */ 435 u8 npc_hash_extract; /* Is hash extract supported */ 436 }; 437 438 /* CGX mbox message formats */ 439 440 struct cgx_stats_rsp { 441 struct mbox_msghdr hdr; 442 #define CGX_RX_STATS_COUNT 9 443 #define CGX_TX_STATS_COUNT 18 444 u64 rx_stats[CGX_RX_STATS_COUNT]; 445 u64 tx_stats[CGX_TX_STATS_COUNT]; 446 }; 447 448 struct cgx_fec_stats_rsp { 449 struct mbox_msghdr hdr; 450 u64 fec_corr_blks; 451 u64 fec_uncorr_blks; 452 }; 453 /* Structure for requesting the operation for 454 * setting/getting mac address in the CGX interface 455 */ 456 struct cgx_mac_addr_set_or_get { 457 struct mbox_msghdr hdr; 458 u8 mac_addr[ETH_ALEN]; 459 u32 index; 460 }; 461 462 /* Structure for requesting the operation to 463 * add DMAC filter entry into CGX interface 464 */ 465 struct cgx_mac_addr_add_req { 466 struct mbox_msghdr hdr; 467 u8 mac_addr[ETH_ALEN]; 468 }; 469 470 /* Structure for response against the operation to 471 * add DMAC filter entry into CGX interface 472 */ 473 struct cgx_mac_addr_add_rsp { 474 struct mbox_msghdr hdr; 475 u32 index; 476 }; 477 478 /* Structure for requesting the operation to 479 * delete DMAC filter entry from CGX interface 480 */ 481 struct cgx_mac_addr_del_req { 482 struct mbox_msghdr hdr; 483 u32 index; 484 }; 485 486 /* Structure for response against the operation to 487 * get maximum supported DMAC filter entries 488 */ 489 struct cgx_max_dmac_entries_get_rsp { 490 struct mbox_msghdr hdr; 491 u32 max_dmac_filters; 492 }; 493 494 struct cgx_link_user_info { 495 uint64_t link_up:1; 496 uint64_t full_duplex:1; 497 uint64_t lmac_type_id:4; 498 uint64_t speed:20; /* speed in Mbps */ 499 uint64_t an:1; /* AN supported or not */ 500 uint64_t fec:2; /* FEC type if enabled else 0 */ 501 #define LMACTYPE_STR_LEN 16 502 char lmac_type[LMACTYPE_STR_LEN]; 503 }; 504 505 struct cgx_link_info_msg { 506 struct mbox_msghdr hdr; 507 struct cgx_link_user_info link_info; 508 }; 509 510 struct cgx_pause_frm_cfg { 511 struct mbox_msghdr hdr; 512 u8 set; 513 /* set = 1 if the request is to config pause frames */ 514 /* set = 0 if the request is to fetch pause frames config */ 515 u8 rx_pause; 516 u8 tx_pause; 517 }; 518 519 enum fec_type { 520 OTX2_FEC_NONE, 521 OTX2_FEC_BASER, 522 OTX2_FEC_RS, 523 OTX2_FEC_STATS_CNT = 2, 524 OTX2_FEC_OFF, 525 }; 526 527 struct fec_mode { 528 struct mbox_msghdr hdr; 529 int fec; 530 }; 531 532 struct sfp_eeprom_s { 533 #define SFP_EEPROM_SIZE 256 534 u16 sff_id; 535 u8 buf[SFP_EEPROM_SIZE]; 536 u64 reserved; 537 }; 538 539 struct phy_s { 540 struct { 541 u64 can_change_mod_type:1; 542 u64 mod_type:1; 543 u64 has_fec_stats:1; 544 } misc; 545 struct fec_stats_s { 546 u32 rsfec_corr_cws; 547 u32 rsfec_uncorr_cws; 548 u32 brfec_corr_blks; 549 u32 brfec_uncorr_blks; 550 } fec_stats; 551 }; 552 553 struct cgx_lmac_fwdata_s { 554 u16 rw_valid; 555 u64 supported_fec; 556 u64 supported_an; 557 u64 supported_link_modes; 558 /* only applicable if AN is supported */ 559 u64 advertised_fec; 560 u64 advertised_link_modes; 561 /* Only applicable if SFP/QSFP slot is present */ 562 struct sfp_eeprom_s sfp_eeprom; 563 struct phy_s phy; 564 #define LMAC_FWDATA_RESERVED_MEM 1021 565 u64 reserved[LMAC_FWDATA_RESERVED_MEM]; 566 }; 567 568 struct cgx_fw_data { 569 struct mbox_msghdr hdr; 570 struct cgx_lmac_fwdata_s fwdata; 571 }; 572 573 struct cgx_set_link_mode_args { 574 u32 speed; 575 u8 duplex; 576 u8 an; 577 u8 ports; 578 u64 mode; 579 }; 580 581 struct cgx_set_link_mode_req { 582 #define AUTONEG_UNKNOWN 0xff 583 struct mbox_msghdr hdr; 584 struct cgx_set_link_mode_args args; 585 }; 586 587 struct cgx_set_link_mode_rsp { 588 struct mbox_msghdr hdr; 589 int status; 590 }; 591 592 struct cgx_mac_addr_reset_req { 593 struct mbox_msghdr hdr; 594 u32 index; 595 }; 596 597 struct cgx_mac_addr_update_req { 598 struct mbox_msghdr hdr; 599 u8 mac_addr[ETH_ALEN]; 600 u32 index; 601 }; 602 603 struct cgx_mac_addr_update_rsp { 604 struct mbox_msghdr hdr; 605 u32 index; 606 }; 607 608 #define RVU_LMAC_FEAT_FC BIT_ULL(0) /* pause frames */ 609 #define RVU_LMAC_FEAT_HIGIG2 BIT_ULL(1) 610 /* flow control from physical link higig2 messages */ 611 #define RVU_LMAC_FEAT_PTP BIT_ULL(2) /* precison time protocol */ 612 #define RVU_LMAC_FEAT_DMACF BIT_ULL(3) /* DMAC FILTER */ 613 #define RVU_MAC_VERSION BIT_ULL(4) 614 #define RVU_MAC_CGX BIT_ULL(5) 615 #define RVU_MAC_RPM BIT_ULL(6) 616 617 struct cgx_features_info_msg { 618 struct mbox_msghdr hdr; 619 u64 lmac_features; 620 }; 621 622 struct rpm_stats_rsp { 623 struct mbox_msghdr hdr; 624 #define RPM_RX_STATS_COUNT 43 625 #define RPM_TX_STATS_COUNT 34 626 u64 rx_stats[RPM_RX_STATS_COUNT]; 627 u64 tx_stats[RPM_TX_STATS_COUNT]; 628 }; 629 630 struct cgx_pfc_cfg { 631 struct mbox_msghdr hdr; 632 u8 rx_pause; 633 u8 tx_pause; 634 u16 pfc_en; /* bitmap indicating pfc enabled traffic classes */ 635 }; 636 637 struct cgx_pfc_rsp { 638 struct mbox_msghdr hdr; 639 u8 rx_pause; 640 u8 tx_pause; 641 }; 642 643 /* NPA mbox message formats */ 644 645 struct npc_set_pkind { 646 struct mbox_msghdr hdr; 647 #define OTX2_PRIV_FLAGS_DEFAULT BIT_ULL(0) 648 #define OTX2_PRIV_FLAGS_CUSTOM BIT_ULL(63) 649 u64 mode; 650 #define PKIND_TX BIT_ULL(0) 651 #define PKIND_RX BIT_ULL(1) 652 u8 dir; 653 u8 pkind; /* valid only in case custom flag */ 654 u8 var_len_off; /* Offset of custom header length field. 655 * Valid only for pkind NPC_RX_CUSTOM_PRE_L2_PKIND 656 */ 657 u8 var_len_off_mask; /* Mask for length with in offset */ 658 u8 shift_dir; /* shift direction to get length of the header at var_len_off */ 659 }; 660 661 /* NPA mbox message formats */ 662 663 /* NPA mailbox error codes 664 * Range 301 - 400. 665 */ 666 enum npa_af_status { 667 NPA_AF_ERR_PARAM = -301, 668 NPA_AF_ERR_AQ_FULL = -302, 669 NPA_AF_ERR_AQ_ENQUEUE = -303, 670 NPA_AF_ERR_AF_LF_INVALID = -304, 671 NPA_AF_ERR_AF_LF_ALLOC = -305, 672 NPA_AF_ERR_LF_RESET = -306, 673 }; 674 675 /* For NPA LF context alloc and init */ 676 struct npa_lf_alloc_req { 677 struct mbox_msghdr hdr; 678 int node; 679 int aura_sz; /* No of auras */ 680 u32 nr_pools; /* No of pools */ 681 u64 way_mask; 682 }; 683 684 struct npa_lf_alloc_rsp { 685 struct mbox_msghdr hdr; 686 u32 stack_pg_ptrs; /* No of ptrs per stack page */ 687 u32 stack_pg_bytes; /* Size of stack page */ 688 u16 qints; /* NPA_AF_CONST::QINTS */ 689 u8 cache_lines; /*BATCH ALLOC DMA */ 690 }; 691 692 /* NPA AQ enqueue msg */ 693 struct npa_aq_enq_req { 694 struct mbox_msghdr hdr; 695 u32 aura_id; 696 u8 ctype; 697 u8 op; 698 union { 699 /* Valid when op == WRITE/INIT and ctype == AURA. 700 * LF fills the pool_id in aura.pool_addr. AF will translate 701 * the pool_id to pool context pointer. 702 */ 703 struct npa_aura_s aura; 704 /* Valid when op == WRITE/INIT and ctype == POOL */ 705 struct npa_pool_s pool; 706 }; 707 /* Mask data when op == WRITE (1=write, 0=don't write) */ 708 union { 709 /* Valid when op == WRITE and ctype == AURA */ 710 struct npa_aura_s aura_mask; 711 /* Valid when op == WRITE and ctype == POOL */ 712 struct npa_pool_s pool_mask; 713 }; 714 }; 715 716 struct npa_aq_enq_rsp { 717 struct mbox_msghdr hdr; 718 union { 719 /* Valid when op == READ and ctype == AURA */ 720 struct npa_aura_s aura; 721 /* Valid when op == READ and ctype == POOL */ 722 struct npa_pool_s pool; 723 }; 724 }; 725 726 /* Disable all contexts of type 'ctype' */ 727 struct hwctx_disable_req { 728 struct mbox_msghdr hdr; 729 u8 ctype; 730 }; 731 732 /* NIX mbox message formats */ 733 734 /* NIX mailbox error codes 735 * Range 401 - 500. 736 */ 737 enum nix_af_status { 738 NIX_AF_ERR_PARAM = -401, 739 NIX_AF_ERR_AQ_FULL = -402, 740 NIX_AF_ERR_AQ_ENQUEUE = -403, 741 NIX_AF_ERR_AF_LF_INVALID = -404, 742 NIX_AF_ERR_AF_LF_ALLOC = -405, 743 NIX_AF_ERR_TLX_ALLOC_FAIL = -406, 744 NIX_AF_ERR_TLX_INVALID = -407, 745 NIX_AF_ERR_RSS_SIZE_INVALID = -408, 746 NIX_AF_ERR_RSS_GRPS_INVALID = -409, 747 NIX_AF_ERR_FRS_INVALID = -410, 748 NIX_AF_ERR_RX_LINK_INVALID = -411, 749 NIX_AF_INVAL_TXSCHQ_CFG = -412, 750 NIX_AF_SMQ_FLUSH_FAILED = -413, 751 NIX_AF_ERR_LF_RESET = -414, 752 NIX_AF_ERR_RSS_NOSPC_FIELD = -415, 753 NIX_AF_ERR_RSS_NOSPC_ALGO = -416, 754 NIX_AF_ERR_MARK_CFG_FAIL = -417, 755 NIX_AF_ERR_LSO_CFG_FAIL = -418, 756 NIX_AF_INVAL_NPA_PF_FUNC = -419, 757 NIX_AF_INVAL_SSO_PF_FUNC = -420, 758 NIX_AF_ERR_TX_VTAG_NOSPC = -421, 759 NIX_AF_ERR_RX_VTAG_INUSE = -422, 760 NIX_AF_ERR_PTP_CONFIG_FAIL = -423, 761 NIX_AF_ERR_NPC_KEY_NOT_SUPP = -424, 762 NIX_AF_ERR_INVALID_NIXBLK = -425, 763 NIX_AF_ERR_INVALID_BANDPROF = -426, 764 NIX_AF_ERR_IPOLICER_NOTSUPP = -427, 765 NIX_AF_ERR_BANDPROF_INVAL_REQ = -428, 766 NIX_AF_ERR_CQ_CTX_WRITE_ERR = -429, 767 NIX_AF_ERR_AQ_CTX_RETRY_WRITE = -430, 768 NIX_AF_ERR_LINK_CREDITS = -431, 769 }; 770 771 /* For NIX RX vtag action */ 772 enum nix_rx_vtag0_type { 773 NIX_AF_LFX_RX_VTAG_TYPE0, /* reserved for rx vlan offload */ 774 NIX_AF_LFX_RX_VTAG_TYPE1, 775 NIX_AF_LFX_RX_VTAG_TYPE2, 776 NIX_AF_LFX_RX_VTAG_TYPE3, 777 NIX_AF_LFX_RX_VTAG_TYPE4, 778 NIX_AF_LFX_RX_VTAG_TYPE5, 779 NIX_AF_LFX_RX_VTAG_TYPE6, 780 NIX_AF_LFX_RX_VTAG_TYPE7, 781 }; 782 783 /* For NIX LF context alloc and init */ 784 struct nix_lf_alloc_req { 785 struct mbox_msghdr hdr; 786 int node; 787 u32 rq_cnt; /* No of receive queues */ 788 u32 sq_cnt; /* No of send queues */ 789 u32 cq_cnt; /* No of completion queues */ 790 u8 xqe_sz; 791 u16 rss_sz; 792 u8 rss_grps; 793 u16 npa_func; 794 u16 sso_func; 795 u64 rx_cfg; /* See NIX_AF_LF(0..127)_RX_CFG */ 796 u64 way_mask; 797 #define NIX_LF_RSS_TAG_LSB_AS_ADDER BIT_ULL(0) 798 #define NIX_LF_LBK_BLK_SEL BIT_ULL(1) 799 u64 flags; 800 }; 801 802 struct nix_lf_alloc_rsp { 803 struct mbox_msghdr hdr; 804 u16 sqb_size; 805 u16 rx_chan_base; 806 u16 tx_chan_base; 807 u8 rx_chan_cnt; /* total number of RX channels */ 808 u8 tx_chan_cnt; /* total number of TX channels */ 809 u8 lso_tsov4_idx; 810 u8 lso_tsov6_idx; 811 u8 mac_addr[ETH_ALEN]; 812 u8 lf_rx_stats; /* NIX_AF_CONST1::LF_RX_STATS */ 813 u8 lf_tx_stats; /* NIX_AF_CONST1::LF_TX_STATS */ 814 u16 cints; /* NIX_AF_CONST2::CINTS */ 815 u16 qints; /* NIX_AF_CONST2::QINTS */ 816 u8 cgx_links; /* No. of CGX links present in HW */ 817 u8 lbk_links; /* No. of LBK links present in HW */ 818 u8 sdp_links; /* No. of SDP links present in HW */ 819 u8 tx_link; /* Transmit channel link number */ 820 }; 821 822 struct nix_lf_free_req { 823 struct mbox_msghdr hdr; 824 #define NIX_LF_DISABLE_FLOWS BIT_ULL(0) 825 #define NIX_LF_DONT_FREE_TX_VTAG BIT_ULL(1) 826 u64 flags; 827 }; 828 829 /* CN10K NIX AQ enqueue msg */ 830 struct nix_cn10k_aq_enq_req { 831 struct mbox_msghdr hdr; 832 u32 qidx; 833 u8 ctype; 834 u8 op; 835 union { 836 struct nix_cn10k_rq_ctx_s rq; 837 struct nix_cn10k_sq_ctx_s sq; 838 struct nix_cq_ctx_s cq; 839 struct nix_rsse_s rss; 840 struct nix_rx_mce_s mce; 841 struct nix_bandprof_s prof; 842 }; 843 union { 844 struct nix_cn10k_rq_ctx_s rq_mask; 845 struct nix_cn10k_sq_ctx_s sq_mask; 846 struct nix_cq_ctx_s cq_mask; 847 struct nix_rsse_s rss_mask; 848 struct nix_rx_mce_s mce_mask; 849 struct nix_bandprof_s prof_mask; 850 }; 851 }; 852 853 struct nix_cn10k_aq_enq_rsp { 854 struct mbox_msghdr hdr; 855 union { 856 struct nix_cn10k_rq_ctx_s rq; 857 struct nix_cn10k_sq_ctx_s sq; 858 struct nix_cq_ctx_s cq; 859 struct nix_rsse_s rss; 860 struct nix_rx_mce_s mce; 861 struct nix_bandprof_s prof; 862 }; 863 }; 864 865 /* NIX AQ enqueue msg */ 866 struct nix_aq_enq_req { 867 struct mbox_msghdr hdr; 868 u32 qidx; 869 u8 ctype; 870 u8 op; 871 union { 872 struct nix_rq_ctx_s rq; 873 struct nix_sq_ctx_s sq; 874 struct nix_cq_ctx_s cq; 875 struct nix_rsse_s rss; 876 struct nix_rx_mce_s mce; 877 u64 prof; 878 }; 879 union { 880 struct nix_rq_ctx_s rq_mask; 881 struct nix_sq_ctx_s sq_mask; 882 struct nix_cq_ctx_s cq_mask; 883 struct nix_rsse_s rss_mask; 884 struct nix_rx_mce_s mce_mask; 885 u64 prof_mask; 886 }; 887 }; 888 889 struct nix_aq_enq_rsp { 890 struct mbox_msghdr hdr; 891 union { 892 struct nix_rq_ctx_s rq; 893 struct nix_sq_ctx_s sq; 894 struct nix_cq_ctx_s cq; 895 struct nix_rsse_s rss; 896 struct nix_rx_mce_s mce; 897 struct nix_bandprof_s prof; 898 }; 899 }; 900 901 /* Tx scheduler/shaper mailbox messages */ 902 903 #define MAX_TXSCHQ_PER_FUNC 128 904 905 struct nix_txsch_alloc_req { 906 struct mbox_msghdr hdr; 907 /* Scheduler queue count request at each level */ 908 u16 schq_contig[NIX_TXSCH_LVL_CNT]; /* No of contiguous queues */ 909 u16 schq[NIX_TXSCH_LVL_CNT]; /* No of non-contiguous queues */ 910 }; 911 912 struct nix_txsch_alloc_rsp { 913 struct mbox_msghdr hdr; 914 /* Scheduler queue count allocated at each level */ 915 u16 schq_contig[NIX_TXSCH_LVL_CNT]; 916 u16 schq[NIX_TXSCH_LVL_CNT]; 917 /* Scheduler queue list allocated at each level */ 918 u16 schq_contig_list[NIX_TXSCH_LVL_CNT][MAX_TXSCHQ_PER_FUNC]; 919 u16 schq_list[NIX_TXSCH_LVL_CNT][MAX_TXSCHQ_PER_FUNC]; 920 u8 aggr_level; /* Traffic aggregation scheduler level */ 921 u8 aggr_lvl_rr_prio; /* Aggregation lvl's RR_PRIO config */ 922 u8 link_cfg_lvl; /* LINKX_CFG CSRs mapped to TL3 or TL2's index ? */ 923 }; 924 925 struct nix_txsch_free_req { 926 struct mbox_msghdr hdr; 927 #define TXSCHQ_FREE_ALL BIT_ULL(0) 928 u16 flags; 929 /* Scheduler queue level to be freed */ 930 u16 schq_lvl; 931 /* List of scheduler queues to be freed */ 932 u16 schq; 933 }; 934 935 struct nix_txschq_config { 936 struct mbox_msghdr hdr; 937 u8 lvl; /* SMQ/MDQ/TL4/TL3/TL2/TL1 */ 938 u8 read; 939 #define TXSCHQ_IDX_SHIFT 16 940 #define TXSCHQ_IDX_MASK (BIT_ULL(10) - 1) 941 #define TXSCHQ_IDX(reg, shift) (((reg) >> (shift)) & TXSCHQ_IDX_MASK) 942 u8 num_regs; 943 #define MAX_REGS_PER_MBOX_MSG 20 944 u64 reg[MAX_REGS_PER_MBOX_MSG]; 945 u64 regval[MAX_REGS_PER_MBOX_MSG]; 946 /* All 0's => overwrite with new value */ 947 u64 regval_mask[MAX_REGS_PER_MBOX_MSG]; 948 }; 949 950 struct nix_vtag_config { 951 struct mbox_msghdr hdr; 952 /* '0' for 4 octet VTAG, '1' for 8 octet VTAG */ 953 u8 vtag_size; 954 /* cfg_type is '0' for tx vlan cfg 955 * cfg_type is '1' for rx vlan cfg 956 */ 957 u8 cfg_type; 958 union { 959 /* valid when cfg_type is '0' */ 960 struct { 961 u64 vtag0; 962 u64 vtag1; 963 964 /* cfg_vtag0 & cfg_vtag1 fields are valid 965 * when free_vtag0 & free_vtag1 are '0's. 966 */ 967 /* cfg_vtag0 = 1 to configure vtag0 */ 968 u8 cfg_vtag0 :1; 969 /* cfg_vtag1 = 1 to configure vtag1 */ 970 u8 cfg_vtag1 :1; 971 972 /* vtag0_idx & vtag1_idx are only valid when 973 * both cfg_vtag0 & cfg_vtag1 are '0's, 974 * these fields are used along with free_vtag0 975 * & free_vtag1 to free the nix lf's tx_vlan 976 * configuration. 977 * 978 * Denotes the indices of tx_vtag def registers 979 * that needs to be cleared and freed. 980 */ 981 int vtag0_idx; 982 int vtag1_idx; 983 984 /* free_vtag0 & free_vtag1 fields are valid 985 * when cfg_vtag0 & cfg_vtag1 are '0's. 986 */ 987 /* free_vtag0 = 1 clears vtag0 configuration 988 * vtag0_idx denotes the index to be cleared. 989 */ 990 u8 free_vtag0 :1; 991 /* free_vtag1 = 1 clears vtag1 configuration 992 * vtag1_idx denotes the index to be cleared. 993 */ 994 u8 free_vtag1 :1; 995 } tx; 996 997 /* valid when cfg_type is '1' */ 998 struct { 999 /* rx vtag type index, valid values are in 0..7 range */ 1000 u8 vtag_type; 1001 /* rx vtag strip */ 1002 u8 strip_vtag :1; 1003 /* rx vtag capture */ 1004 u8 capture_vtag :1; 1005 } rx; 1006 }; 1007 }; 1008 1009 struct nix_vtag_config_rsp { 1010 struct mbox_msghdr hdr; 1011 int vtag0_idx; 1012 int vtag1_idx; 1013 /* Indices of tx_vtag def registers used to configure 1014 * tx vtag0 & vtag1 headers, these indices are valid 1015 * when nix_vtag_config mbox requested for vtag0 and/ 1016 * or vtag1 configuration. 1017 */ 1018 }; 1019 1020 struct nix_rss_flowkey_cfg { 1021 struct mbox_msghdr hdr; 1022 int mcam_index; /* MCAM entry index to modify */ 1023 #define NIX_FLOW_KEY_TYPE_PORT BIT(0) 1024 #define NIX_FLOW_KEY_TYPE_IPV4 BIT(1) 1025 #define NIX_FLOW_KEY_TYPE_IPV6 BIT(2) 1026 #define NIX_FLOW_KEY_TYPE_TCP BIT(3) 1027 #define NIX_FLOW_KEY_TYPE_UDP BIT(4) 1028 #define NIX_FLOW_KEY_TYPE_SCTP BIT(5) 1029 #define NIX_FLOW_KEY_TYPE_NVGRE BIT(6) 1030 #define NIX_FLOW_KEY_TYPE_VXLAN BIT(7) 1031 #define NIX_FLOW_KEY_TYPE_GENEVE BIT(8) 1032 #define NIX_FLOW_KEY_TYPE_ETH_DMAC BIT(9) 1033 #define NIX_FLOW_KEY_TYPE_IPV6_EXT BIT(10) 1034 #define NIX_FLOW_KEY_TYPE_GTPU BIT(11) 1035 #define NIX_FLOW_KEY_TYPE_INNR_IPV4 BIT(12) 1036 #define NIX_FLOW_KEY_TYPE_INNR_IPV6 BIT(13) 1037 #define NIX_FLOW_KEY_TYPE_INNR_TCP BIT(14) 1038 #define NIX_FLOW_KEY_TYPE_INNR_UDP BIT(15) 1039 #define NIX_FLOW_KEY_TYPE_INNR_SCTP BIT(16) 1040 #define NIX_FLOW_KEY_TYPE_INNR_ETH_DMAC BIT(17) 1041 #define NIX_FLOW_KEY_TYPE_VLAN BIT(20) 1042 #define NIX_FLOW_KEY_TYPE_IPV4_PROTO BIT(21) 1043 #define NIX_FLOW_KEY_TYPE_AH BIT(22) 1044 #define NIX_FLOW_KEY_TYPE_ESP BIT(23) 1045 u32 flowkey_cfg; /* Flowkey types selected */ 1046 u8 group; /* RSS context or group */ 1047 }; 1048 1049 struct nix_rss_flowkey_cfg_rsp { 1050 struct mbox_msghdr hdr; 1051 u8 alg_idx; /* Selected algo index */ 1052 }; 1053 1054 struct nix_set_mac_addr { 1055 struct mbox_msghdr hdr; 1056 u8 mac_addr[ETH_ALEN]; /* MAC address to be set for this pcifunc */ 1057 }; 1058 1059 struct nix_get_mac_addr_rsp { 1060 struct mbox_msghdr hdr; 1061 u8 mac_addr[ETH_ALEN]; 1062 }; 1063 1064 struct nix_mark_format_cfg { 1065 struct mbox_msghdr hdr; 1066 u8 offset; 1067 u8 y_mask; 1068 u8 y_val; 1069 u8 r_mask; 1070 u8 r_val; 1071 }; 1072 1073 struct nix_mark_format_cfg_rsp { 1074 struct mbox_msghdr hdr; 1075 u8 mark_format_idx; 1076 }; 1077 1078 struct nix_rx_mode { 1079 struct mbox_msghdr hdr; 1080 #define NIX_RX_MODE_UCAST BIT(0) 1081 #define NIX_RX_MODE_PROMISC BIT(1) 1082 #define NIX_RX_MODE_ALLMULTI BIT(2) 1083 #define NIX_RX_MODE_USE_MCE BIT(3) 1084 u16 mode; 1085 }; 1086 1087 struct nix_rx_cfg { 1088 struct mbox_msghdr hdr; 1089 #define NIX_RX_OL3_VERIFY BIT(0) 1090 #define NIX_RX_OL4_VERIFY BIT(1) 1091 u8 len_verify; /* Outer L3/L4 len check */ 1092 #define NIX_RX_CSUM_OL4_VERIFY BIT(0) 1093 u8 csum_verify; /* Outer L4 checksum verification */ 1094 }; 1095 1096 struct nix_frs_cfg { 1097 struct mbox_msghdr hdr; 1098 u8 update_smq; /* Update SMQ's min/max lens */ 1099 u8 update_minlen; /* Set minlen also */ 1100 u8 sdp_link; /* Set SDP RX link */ 1101 u16 maxlen; 1102 u16 minlen; 1103 }; 1104 1105 struct nix_lso_format_cfg { 1106 struct mbox_msghdr hdr; 1107 u64 field_mask; 1108 #define NIX_LSO_FIELD_MAX 8 1109 u64 fields[NIX_LSO_FIELD_MAX]; 1110 }; 1111 1112 struct nix_lso_format_cfg_rsp { 1113 struct mbox_msghdr hdr; 1114 u8 lso_format_idx; 1115 }; 1116 1117 struct nix_bp_cfg_req { 1118 struct mbox_msghdr hdr; 1119 u16 chan_base; /* Starting channel number */ 1120 u8 chan_cnt; /* Number of channels */ 1121 u8 bpid_per_chan; 1122 /* bpid_per_chan = 0 assigns single bp id for range of channels */ 1123 /* bpid_per_chan = 1 assigns separate bp id for each channel */ 1124 }; 1125 1126 /* PF can be mapped to either CGX or LBK interface, 1127 * so maximum 64 channels are possible. 1128 */ 1129 #define NIX_MAX_BPID_CHAN 64 1130 struct nix_bp_cfg_rsp { 1131 struct mbox_msghdr hdr; 1132 u16 chan_bpid[NIX_MAX_BPID_CHAN]; /* Channel and bpid mapping */ 1133 u8 chan_cnt; /* Number of channel for which bpids are assigned */ 1134 }; 1135 1136 /* Global NIX inline IPSec configuration */ 1137 struct nix_inline_ipsec_cfg { 1138 struct mbox_msghdr hdr; 1139 u32 cpt_credit; 1140 struct { 1141 u8 egrp; 1142 u8 opcode; 1143 u16 param1; 1144 u16 param2; 1145 } gen_cfg; 1146 struct { 1147 u16 cpt_pf_func; 1148 u8 cpt_slot; 1149 } inst_qsel; 1150 u8 enable; 1151 }; 1152 1153 /* Per NIX LF inline IPSec configuration */ 1154 struct nix_inline_ipsec_lf_cfg { 1155 struct mbox_msghdr hdr; 1156 u64 sa_base_addr; 1157 struct { 1158 u32 tag_const; 1159 u16 lenm1_max; 1160 u8 sa_pow2_size; 1161 u8 tt; 1162 } ipsec_cfg0; 1163 struct { 1164 u32 sa_idx_max; 1165 u8 sa_idx_w; 1166 } ipsec_cfg1; 1167 u8 enable; 1168 }; 1169 1170 struct nix_hw_info { 1171 struct mbox_msghdr hdr; 1172 u16 rsvs16; 1173 u16 max_mtu; 1174 u16 min_mtu; 1175 u32 rpm_dwrr_mtu; 1176 u32 sdp_dwrr_mtu; 1177 u64 rsvd[16]; /* Add reserved fields for future expansion */ 1178 }; 1179 1180 struct nix_bandprof_alloc_req { 1181 struct mbox_msghdr hdr; 1182 /* Count of profiles needed per layer */ 1183 u16 prof_count[BAND_PROF_NUM_LAYERS]; 1184 }; 1185 1186 struct nix_bandprof_alloc_rsp { 1187 struct mbox_msghdr hdr; 1188 u16 prof_count[BAND_PROF_NUM_LAYERS]; 1189 1190 /* There is no need to allocate morethan 1 bandwidth profile 1191 * per RQ of a PF_FUNC's NIXLF. So limit the maximum 1192 * profiles to 64 per PF_FUNC. 1193 */ 1194 #define MAX_BANDPROF_PER_PFFUNC 64 1195 u16 prof_idx[BAND_PROF_NUM_LAYERS][MAX_BANDPROF_PER_PFFUNC]; 1196 }; 1197 1198 struct nix_bandprof_free_req { 1199 struct mbox_msghdr hdr; 1200 u8 free_all; 1201 u16 prof_count[BAND_PROF_NUM_LAYERS]; 1202 u16 prof_idx[BAND_PROF_NUM_LAYERS][MAX_BANDPROF_PER_PFFUNC]; 1203 }; 1204 1205 struct nix_bandprof_get_hwinfo_rsp { 1206 struct mbox_msghdr hdr; 1207 u16 prof_count[BAND_PROF_NUM_LAYERS]; 1208 u32 policer_timeunit; 1209 }; 1210 1211 /* NPC mbox message structs */ 1212 1213 #define NPC_MCAM_ENTRY_INVALID 0xFFFF 1214 #define NPC_MCAM_INVALID_MAP 0xFFFF 1215 1216 /* NPC mailbox error codes 1217 * Range 701 - 800. 1218 */ 1219 enum npc_af_status { 1220 NPC_MCAM_INVALID_REQ = -701, 1221 NPC_MCAM_ALLOC_DENIED = -702, 1222 NPC_MCAM_ALLOC_FAILED = -703, 1223 NPC_MCAM_PERM_DENIED = -704, 1224 NPC_FLOW_INTF_INVALID = -707, 1225 NPC_FLOW_CHAN_INVALID = -708, 1226 NPC_FLOW_NO_NIXLF = -709, 1227 NPC_FLOW_NOT_SUPPORTED = -710, 1228 NPC_FLOW_VF_PERM_DENIED = -711, 1229 NPC_FLOW_VF_NOT_INIT = -712, 1230 NPC_FLOW_VF_OVERLAP = -713, 1231 }; 1232 1233 struct npc_mcam_alloc_entry_req { 1234 struct mbox_msghdr hdr; 1235 #define NPC_MAX_NONCONTIG_ENTRIES 256 1236 u8 contig; /* Contiguous entries ? */ 1237 #define NPC_MCAM_ANY_PRIO 0 1238 #define NPC_MCAM_LOWER_PRIO 1 1239 #define NPC_MCAM_HIGHER_PRIO 2 1240 u8 priority; /* Lower or higher w.r.t ref_entry */ 1241 u16 ref_entry; 1242 u16 count; /* Number of entries requested */ 1243 }; 1244 1245 struct npc_mcam_alloc_entry_rsp { 1246 struct mbox_msghdr hdr; 1247 u16 entry; /* Entry allocated or start index if contiguous. 1248 * Invalid incase of non-contiguous. 1249 */ 1250 u16 count; /* Number of entries allocated */ 1251 u16 free_count; /* Number of entries available */ 1252 u16 entry_list[NPC_MAX_NONCONTIG_ENTRIES]; 1253 }; 1254 1255 struct npc_mcam_free_entry_req { 1256 struct mbox_msghdr hdr; 1257 u16 entry; /* Entry index to be freed */ 1258 u8 all; /* If all entries allocated to this PFVF to be freed */ 1259 }; 1260 1261 struct mcam_entry { 1262 #define NPC_MAX_KWS_IN_KEY 7 /* Number of keywords in max keywidth */ 1263 u64 kw[NPC_MAX_KWS_IN_KEY]; 1264 u64 kw_mask[NPC_MAX_KWS_IN_KEY]; 1265 u64 action; 1266 u64 vtag_action; 1267 }; 1268 1269 struct npc_mcam_write_entry_req { 1270 struct mbox_msghdr hdr; 1271 struct mcam_entry entry_data; 1272 u16 entry; /* MCAM entry to write this match key */ 1273 u16 cntr; /* Counter for this MCAM entry */ 1274 u8 intf; /* Rx or Tx interface */ 1275 u8 enable_entry;/* Enable this MCAM entry ? */ 1276 u8 set_cntr; /* Set counter for this entry ? */ 1277 }; 1278 1279 /* Enable/Disable a given entry */ 1280 struct npc_mcam_ena_dis_entry_req { 1281 struct mbox_msghdr hdr; 1282 u16 entry; 1283 }; 1284 1285 struct npc_mcam_shift_entry_req { 1286 struct mbox_msghdr hdr; 1287 #define NPC_MCAM_MAX_SHIFTS 64 1288 u16 curr_entry[NPC_MCAM_MAX_SHIFTS]; 1289 u16 new_entry[NPC_MCAM_MAX_SHIFTS]; 1290 u16 shift_count; /* Number of entries to shift */ 1291 }; 1292 1293 struct npc_mcam_shift_entry_rsp { 1294 struct mbox_msghdr hdr; 1295 u16 failed_entry_idx; /* Index in 'curr_entry', not entry itself */ 1296 }; 1297 1298 struct npc_mcam_alloc_counter_req { 1299 struct mbox_msghdr hdr; 1300 u8 contig; /* Contiguous counters ? */ 1301 #define NPC_MAX_NONCONTIG_COUNTERS 64 1302 u16 count; /* Number of counters requested */ 1303 }; 1304 1305 struct npc_mcam_alloc_counter_rsp { 1306 struct mbox_msghdr hdr; 1307 u16 cntr; /* Counter allocated or start index if contiguous. 1308 * Invalid incase of non-contiguous. 1309 */ 1310 u16 count; /* Number of counters allocated */ 1311 u16 cntr_list[NPC_MAX_NONCONTIG_COUNTERS]; 1312 }; 1313 1314 struct npc_mcam_oper_counter_req { 1315 struct mbox_msghdr hdr; 1316 u16 cntr; /* Free a counter or clear/fetch it's stats */ 1317 }; 1318 1319 struct npc_mcam_oper_counter_rsp { 1320 struct mbox_msghdr hdr; 1321 u64 stat; /* valid only while fetching counter's stats */ 1322 }; 1323 1324 struct npc_mcam_unmap_counter_req { 1325 struct mbox_msghdr hdr; 1326 u16 cntr; 1327 u16 entry; /* Entry and counter to be unmapped */ 1328 u8 all; /* Unmap all entries using this counter ? */ 1329 }; 1330 1331 struct npc_mcam_alloc_and_write_entry_req { 1332 struct mbox_msghdr hdr; 1333 struct mcam_entry entry_data; 1334 u16 ref_entry; 1335 u8 priority; /* Lower or higher w.r.t ref_entry */ 1336 u8 intf; /* Rx or Tx interface */ 1337 u8 enable_entry;/* Enable this MCAM entry ? */ 1338 u8 alloc_cntr; /* Allocate counter and map ? */ 1339 }; 1340 1341 struct npc_mcam_alloc_and_write_entry_rsp { 1342 struct mbox_msghdr hdr; 1343 u16 entry; 1344 u16 cntr; 1345 }; 1346 1347 struct npc_get_kex_cfg_rsp { 1348 struct mbox_msghdr hdr; 1349 u64 rx_keyx_cfg; /* NPC_AF_INTF(0)_KEX_CFG */ 1350 u64 tx_keyx_cfg; /* NPC_AF_INTF(1)_KEX_CFG */ 1351 #define NPC_MAX_INTF 2 1352 #define NPC_MAX_LID 8 1353 #define NPC_MAX_LT 16 1354 #define NPC_MAX_LD 2 1355 #define NPC_MAX_LFL 16 1356 /* NPC_AF_KEX_LDATA(0..1)_FLAGS_CFG */ 1357 u64 kex_ld_flags[NPC_MAX_LD]; 1358 /* NPC_AF_INTF(0..1)_LID(0..7)_LT(0..15)_LD(0..1)_CFG */ 1359 u64 intf_lid_lt_ld[NPC_MAX_INTF][NPC_MAX_LID][NPC_MAX_LT][NPC_MAX_LD]; 1360 /* NPC_AF_INTF(0..1)_LDATA(0..1)_FLAGS(0..15)_CFG */ 1361 u64 intf_ld_flags[NPC_MAX_INTF][NPC_MAX_LD][NPC_MAX_LFL]; 1362 #define MKEX_NAME_LEN 128 1363 u8 mkex_pfl_name[MKEX_NAME_LEN]; 1364 }; 1365 1366 struct flow_msg { 1367 unsigned char dmac[6]; 1368 unsigned char smac[6]; 1369 __be16 etype; 1370 __be16 vlan_etype; 1371 __be16 vlan_tci; 1372 union { 1373 __be32 ip4src; 1374 __be32 ip6src[4]; 1375 }; 1376 union { 1377 __be32 ip4dst; 1378 __be32 ip6dst[4]; 1379 }; 1380 u8 tos; 1381 u8 ip_ver; 1382 u8 ip_proto; 1383 u8 tc; 1384 __be16 sport; 1385 __be16 dport; 1386 }; 1387 1388 struct npc_install_flow_req { 1389 struct mbox_msghdr hdr; 1390 struct flow_msg packet; 1391 struct flow_msg mask; 1392 u64 features; 1393 u16 entry; 1394 u16 channel; 1395 u16 chan_mask; 1396 u8 intf; 1397 u8 set_cntr; /* If counter is available set counter for this entry ? */ 1398 u8 default_rule; 1399 u8 append; /* overwrite(0) or append(1) flow to default rule? */ 1400 u16 vf; 1401 /* action */ 1402 u32 index; 1403 u16 match_id; 1404 u8 flow_key_alg; 1405 u8 op; 1406 /* vtag rx action */ 1407 u8 vtag0_type; 1408 u8 vtag0_valid; 1409 u8 vtag1_type; 1410 u8 vtag1_valid; 1411 /* vtag tx action */ 1412 u16 vtag0_def; 1413 u8 vtag0_op; 1414 u16 vtag1_def; 1415 u8 vtag1_op; 1416 }; 1417 1418 struct npc_install_flow_rsp { 1419 struct mbox_msghdr hdr; 1420 int counter; /* negative if no counter else counter number */ 1421 }; 1422 1423 struct npc_delete_flow_req { 1424 struct mbox_msghdr hdr; 1425 u16 entry; 1426 u16 start;/*Disable range of entries */ 1427 u16 end; 1428 u8 all; /* PF + VFs */ 1429 }; 1430 1431 struct npc_mcam_read_entry_req { 1432 struct mbox_msghdr hdr; 1433 u16 entry; /* MCAM entry to read */ 1434 }; 1435 1436 struct npc_mcam_read_entry_rsp { 1437 struct mbox_msghdr hdr; 1438 struct mcam_entry entry_data; 1439 u8 intf; 1440 u8 enable; 1441 }; 1442 1443 struct npc_mcam_read_base_rule_rsp { 1444 struct mbox_msghdr hdr; 1445 struct mcam_entry entry; 1446 }; 1447 1448 struct npc_mcam_get_stats_req { 1449 struct mbox_msghdr hdr; 1450 u16 entry; /* mcam entry */ 1451 }; 1452 1453 struct npc_mcam_get_stats_rsp { 1454 struct mbox_msghdr hdr; 1455 u64 stat; /* counter stats */ 1456 u8 stat_ena; /* enabled */ 1457 }; 1458 1459 struct npc_get_secret_key_req { 1460 struct mbox_msghdr hdr; 1461 u8 intf; 1462 }; 1463 1464 struct npc_get_secret_key_rsp { 1465 struct mbox_msghdr hdr; 1466 u64 secret_key[3]; 1467 }; 1468 1469 enum ptp_op { 1470 PTP_OP_ADJFINE = 0, 1471 PTP_OP_GET_CLOCK = 1, 1472 PTP_OP_GET_TSTMP = 2, 1473 PTP_OP_SET_THRESH = 3, 1474 }; 1475 1476 struct ptp_req { 1477 struct mbox_msghdr hdr; 1478 u8 op; 1479 s64 scaled_ppm; 1480 u64 thresh; 1481 }; 1482 1483 struct ptp_rsp { 1484 struct mbox_msghdr hdr; 1485 u64 clk; 1486 }; 1487 1488 struct set_vf_perm { 1489 struct mbox_msghdr hdr; 1490 u16 vf; 1491 #define RESET_VF_PERM BIT_ULL(0) 1492 #define VF_TRUSTED BIT_ULL(1) 1493 u64 flags; 1494 }; 1495 1496 struct lmtst_tbl_setup_req { 1497 struct mbox_msghdr hdr; 1498 u64 dis_sched_early_comp :1; 1499 u64 sch_ena :1; 1500 u64 dis_line_pref :1; 1501 u64 ssow_pf_func :13; 1502 u16 base_pcifunc; 1503 u8 use_local_lmt_region; 1504 u64 lmt_iova; 1505 u64 rsvd[4]; 1506 }; 1507 1508 /* CPT mailbox error codes 1509 * Range 901 - 1000. 1510 */ 1511 enum cpt_af_status { 1512 CPT_AF_ERR_PARAM = -901, 1513 CPT_AF_ERR_GRP_INVALID = -902, 1514 CPT_AF_ERR_LF_INVALID = -903, 1515 CPT_AF_ERR_ACCESS_DENIED = -904, 1516 CPT_AF_ERR_SSO_PF_FUNC_INVALID = -905, 1517 CPT_AF_ERR_NIX_PF_FUNC_INVALID = -906, 1518 CPT_AF_ERR_INLINE_IPSEC_INB_ENA = -907, 1519 CPT_AF_ERR_INLINE_IPSEC_OUT_ENA = -908 1520 }; 1521 1522 /* CPT mbox message formats */ 1523 struct cpt_rd_wr_reg_msg { 1524 struct mbox_msghdr hdr; 1525 u64 reg_offset; 1526 u64 *ret_val; 1527 u64 val; 1528 u8 is_write; 1529 int blkaddr; 1530 }; 1531 1532 struct cpt_lf_alloc_req_msg { 1533 struct mbox_msghdr hdr; 1534 u16 nix_pf_func; 1535 u16 sso_pf_func; 1536 u16 eng_grpmsk; 1537 int blkaddr; 1538 }; 1539 1540 #define CPT_INLINE_INBOUND 0 1541 #define CPT_INLINE_OUTBOUND 1 1542 1543 /* Mailbox message request format for CPT IPsec 1544 * inline inbound and outbound configuration. 1545 */ 1546 struct cpt_inline_ipsec_cfg_msg { 1547 struct mbox_msghdr hdr; 1548 u8 enable; 1549 u8 slot; 1550 u8 dir; 1551 u8 sso_pf_func_ovrd; 1552 u16 sso_pf_func; /* inbound path SSO_PF_FUNC */ 1553 u16 nix_pf_func; /* outbound path NIX_PF_FUNC */ 1554 }; 1555 1556 /* Mailbox message request and response format for CPT stats. */ 1557 struct cpt_sts_req { 1558 struct mbox_msghdr hdr; 1559 u8 blkaddr; 1560 }; 1561 1562 struct cpt_sts_rsp { 1563 struct mbox_msghdr hdr; 1564 u64 inst_req_pc; 1565 u64 inst_lat_pc; 1566 u64 rd_req_pc; 1567 u64 rd_lat_pc; 1568 u64 rd_uc_pc; 1569 u64 active_cycles_pc; 1570 u64 ctx_mis_pc; 1571 u64 ctx_hit_pc; 1572 u64 ctx_aop_pc; 1573 u64 ctx_aop_lat_pc; 1574 u64 ctx_ifetch_pc; 1575 u64 ctx_ifetch_lat_pc; 1576 u64 ctx_ffetch_pc; 1577 u64 ctx_ffetch_lat_pc; 1578 u64 ctx_wback_pc; 1579 u64 ctx_wback_lat_pc; 1580 u64 ctx_psh_pc; 1581 u64 ctx_psh_lat_pc; 1582 u64 ctx_err; 1583 u64 ctx_enc_id; 1584 u64 ctx_flush_timer; 1585 u64 rxc_time; 1586 u64 rxc_time_cfg; 1587 u64 rxc_active_sts; 1588 u64 rxc_zombie_sts; 1589 u64 busy_sts_ae; 1590 u64 free_sts_ae; 1591 u64 busy_sts_se; 1592 u64 free_sts_se; 1593 u64 busy_sts_ie; 1594 u64 free_sts_ie; 1595 u64 exe_err_info; 1596 u64 cptclk_cnt; 1597 u64 diag; 1598 u64 rxc_dfrg; 1599 u64 x2p_link_cfg0; 1600 u64 x2p_link_cfg1; 1601 }; 1602 1603 /* Mailbox message request format to configure reassembly timeout. */ 1604 struct cpt_rxc_time_cfg_req { 1605 struct mbox_msghdr hdr; 1606 int blkaddr; 1607 u32 step; 1608 u16 zombie_thres; 1609 u16 zombie_limit; 1610 u16 active_thres; 1611 u16 active_limit; 1612 }; 1613 1614 /* Mailbox message request format to request for CPT_INST_S lmtst. */ 1615 struct cpt_inst_lmtst_req { 1616 struct mbox_msghdr hdr; 1617 u64 inst[8]; 1618 u64 rsvd; 1619 }; 1620 1621 struct sdp_node_info { 1622 /* Node to which this PF belons to */ 1623 u8 node_id; 1624 u8 max_vfs; 1625 u8 num_pf_rings; 1626 u8 pf_srn; 1627 #define SDP_MAX_VFS 128 1628 u8 vf_rings[SDP_MAX_VFS]; 1629 }; 1630 1631 struct sdp_chan_info_msg { 1632 struct mbox_msghdr hdr; 1633 struct sdp_node_info info; 1634 }; 1635 1636 struct sdp_get_chan_info_msg { 1637 struct mbox_msghdr hdr; 1638 u16 chan_base; 1639 u16 num_chan; 1640 }; 1641 1642 /* CGX mailbox error codes 1643 * Range 1101 - 1200. 1644 */ 1645 enum cgx_af_status { 1646 LMAC_AF_ERR_INVALID_PARAM = -1101, 1647 LMAC_AF_ERR_PF_NOT_MAPPED = -1102, 1648 LMAC_AF_ERR_PERM_DENIED = -1103, 1649 LMAC_AF_ERR_PFC_ENADIS_PERM_DENIED = -1104, 1650 LMAC_AF_ERR_8023PAUSE_ENADIS_PERM_DENIED = -1105, 1651 LMAC_AF_ERR_CMD_TIMEOUT = -1106, 1652 LMAC_AF_ERR_FIRMWARE_DATA_NOT_MAPPED = -1107, 1653 LMAC_AF_ERR_EXACT_MATCH_TBL_ADD_FAILED = -1108, 1654 LMAC_AF_ERR_EXACT_MATCH_TBL_DEL_FAILED = -1109, 1655 LMAC_AF_ERR_EXACT_MATCH_TBL_LOOK_UP_FAILED = -1110, 1656 }; 1657 1658 #endif /* MBOX_H */ 1659