1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Marvell OcteonTx2 RVU Admin Function driver 3 * 4 * Copyright (C) 2018 Marvell International Ltd. 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 */ 10 11 #ifndef MBOX_H 12 #define MBOX_H 13 14 #include <linux/etherdevice.h> 15 #include <linux/sizes.h> 16 17 #include "rvu_struct.h" 18 #include "common.h" 19 20 #define MBOX_SIZE SZ_64K 21 22 /* AF/PF: PF initiated, PF/VF VF initiated */ 23 #define MBOX_DOWN_RX_START 0 24 #define MBOX_DOWN_RX_SIZE (46 * SZ_1K) 25 #define MBOX_DOWN_TX_START (MBOX_DOWN_RX_START + MBOX_DOWN_RX_SIZE) 26 #define MBOX_DOWN_TX_SIZE (16 * SZ_1K) 27 /* AF/PF: AF initiated, PF/VF PF initiated */ 28 #define MBOX_UP_RX_START (MBOX_DOWN_TX_START + MBOX_DOWN_TX_SIZE) 29 #define MBOX_UP_RX_SIZE SZ_1K 30 #define MBOX_UP_TX_START (MBOX_UP_RX_START + MBOX_UP_RX_SIZE) 31 #define MBOX_UP_TX_SIZE SZ_1K 32 33 #if MBOX_UP_TX_SIZE + MBOX_UP_TX_START != MBOX_SIZE 34 # error "incorrect mailbox area sizes" 35 #endif 36 37 #define INTR_MASK(pfvfs) ((pfvfs < 64) ? (BIT_ULL(pfvfs) - 1) : (~0ull)) 38 39 #define MBOX_RSP_TIMEOUT 2000 /* Time(ms) to wait for mbox response */ 40 41 #define MBOX_MSG_ALIGN 16 /* Align mbox msg start to 16bytes */ 42 43 /* Mailbox directions */ 44 #define MBOX_DIR_AFPF 0 /* AF replies to PF */ 45 #define MBOX_DIR_PFAF 1 /* PF sends messages to AF */ 46 #define MBOX_DIR_PFVF 2 /* PF replies to VF */ 47 #define MBOX_DIR_VFPF 3 /* VF sends messages to PF */ 48 #define MBOX_DIR_AFPF_UP 4 /* AF sends messages to PF */ 49 #define MBOX_DIR_PFAF_UP 5 /* PF replies to AF */ 50 #define MBOX_DIR_PFVF_UP 6 /* PF sends messages to VF */ 51 #define MBOX_DIR_VFPF_UP 7 /* VF replies to PF */ 52 53 struct otx2_mbox_dev { 54 void *mbase; /* This dev's mbox region */ 55 spinlock_t mbox_lock; 56 u16 msg_size; /* Total msg size to be sent */ 57 u16 rsp_size; /* Total rsp size to be sure the reply is ok */ 58 u16 num_msgs; /* No of msgs sent or waiting for response */ 59 u16 msgs_acked; /* No of msgs for which response is received */ 60 }; 61 62 struct otx2_mbox { 63 struct pci_dev *pdev; 64 void *hwbase; /* Mbox region advertised by HW */ 65 void *reg_base;/* CSR base for this dev */ 66 u64 trigger; /* Trigger mbox notification */ 67 u16 tr_shift; /* Mbox trigger shift */ 68 u64 rx_start; /* Offset of Rx region in mbox memory */ 69 u64 tx_start; /* Offset of Tx region in mbox memory */ 70 u16 rx_size; /* Size of Rx region */ 71 u16 tx_size; /* Size of Tx region */ 72 u16 ndevs; /* The number of peers */ 73 struct otx2_mbox_dev *dev; 74 }; 75 76 /* Header which preceeds all mbox messages */ 77 struct mbox_hdr { 78 u64 msg_size; /* Total msgs size embedded */ 79 u16 num_msgs; /* No of msgs embedded */ 80 }; 81 82 /* Header which preceeds every msg and is also part of it */ 83 struct mbox_msghdr { 84 u16 pcifunc; /* Who's sending this msg */ 85 u16 id; /* Mbox message ID */ 86 #define OTX2_MBOX_REQ_SIG (0xdead) 87 #define OTX2_MBOX_RSP_SIG (0xbeef) 88 u16 sig; /* Signature, for validating corrupted msgs */ 89 #define OTX2_MBOX_VERSION (0x0001) 90 u16 ver; /* Version of msg's structure for this ID */ 91 u16 next_msgoff; /* Offset of next msg within mailbox region */ 92 int rc; /* Msg process'ed response code */ 93 }; 94 95 void otx2_mbox_reset(struct otx2_mbox *mbox, int devid); 96 void otx2_mbox_destroy(struct otx2_mbox *mbox); 97 int otx2_mbox_init(struct otx2_mbox *mbox, void __force *hwbase, 98 struct pci_dev *pdev, void __force *reg_base, 99 int direction, int ndevs); 100 void otx2_mbox_msg_send(struct otx2_mbox *mbox, int devid); 101 int otx2_mbox_wait_for_rsp(struct otx2_mbox *mbox, int devid); 102 int otx2_mbox_busy_poll_for_rsp(struct otx2_mbox *mbox, int devid); 103 struct mbox_msghdr *otx2_mbox_alloc_msg_rsp(struct otx2_mbox *mbox, int devid, 104 int size, int size_rsp); 105 struct mbox_msghdr *otx2_mbox_get_rsp(struct otx2_mbox *mbox, int devid, 106 struct mbox_msghdr *msg); 107 int otx2_mbox_check_rsp_msgs(struct otx2_mbox *mbox, int devid); 108 int otx2_reply_invalid_msg(struct otx2_mbox *mbox, int devid, 109 u16 pcifunc, u16 id); 110 bool otx2_mbox_nonempty(struct otx2_mbox *mbox, int devid); 111 const char *otx2_mbox_id2name(u16 id); 112 static inline struct mbox_msghdr *otx2_mbox_alloc_msg(struct otx2_mbox *mbox, 113 int devid, int size) 114 { 115 return otx2_mbox_alloc_msg_rsp(mbox, devid, size, 0); 116 } 117 118 /* Mailbox message types */ 119 #define MBOX_MSG_MASK 0xFFFF 120 #define MBOX_MSG_INVALID 0xFFFE 121 #define MBOX_MSG_MAX 0xFFFF 122 123 #define MBOX_MESSAGES \ 124 /* Generic mbox IDs (range 0x000 - 0x1FF) */ \ 125 M(READY, 0x001, ready, msg_req, ready_msg_rsp) \ 126 M(ATTACH_RESOURCES, 0x002, attach_resources, rsrc_attach, msg_rsp) \ 127 M(DETACH_RESOURCES, 0x003, detach_resources, rsrc_detach, msg_rsp) \ 128 M(MSIX_OFFSET, 0x005, msix_offset, msg_req, msix_offset_rsp) \ 129 M(VF_FLR, 0x006, vf_flr, msg_req, msg_rsp) \ 130 M(PTP_OP, 0x007, ptp_op, ptp_req, ptp_rsp) \ 131 M(GET_HW_CAP, 0x008, get_hw_cap, msg_req, get_hw_cap_rsp) \ 132 /* CGX mbox IDs (range 0x200 - 0x3FF) */ \ 133 M(CGX_START_RXTX, 0x200, cgx_start_rxtx, msg_req, msg_rsp) \ 134 M(CGX_STOP_RXTX, 0x201, cgx_stop_rxtx, msg_req, msg_rsp) \ 135 M(CGX_STATS, 0x202, cgx_stats, msg_req, cgx_stats_rsp) \ 136 M(CGX_MAC_ADDR_SET, 0x203, cgx_mac_addr_set, cgx_mac_addr_set_or_get, \ 137 cgx_mac_addr_set_or_get) \ 138 M(CGX_MAC_ADDR_GET, 0x204, cgx_mac_addr_get, cgx_mac_addr_set_or_get, \ 139 cgx_mac_addr_set_or_get) \ 140 M(CGX_PROMISC_ENABLE, 0x205, cgx_promisc_enable, msg_req, msg_rsp) \ 141 M(CGX_PROMISC_DISABLE, 0x206, cgx_promisc_disable, msg_req, msg_rsp) \ 142 M(CGX_START_LINKEVENTS, 0x207, cgx_start_linkevents, msg_req, msg_rsp) \ 143 M(CGX_STOP_LINKEVENTS, 0x208, cgx_stop_linkevents, msg_req, msg_rsp) \ 144 M(CGX_GET_LINKINFO, 0x209, cgx_get_linkinfo, msg_req, cgx_link_info_msg) \ 145 M(CGX_INTLBK_ENABLE, 0x20A, cgx_intlbk_enable, msg_req, msg_rsp) \ 146 M(CGX_INTLBK_DISABLE, 0x20B, cgx_intlbk_disable, msg_req, msg_rsp) \ 147 M(CGX_PTP_RX_ENABLE, 0x20C, cgx_ptp_rx_enable, msg_req, msg_rsp) \ 148 M(CGX_PTP_RX_DISABLE, 0x20D, cgx_ptp_rx_disable, msg_req, msg_rsp) \ 149 M(CGX_CFG_PAUSE_FRM, 0x20E, cgx_cfg_pause_frm, cgx_pause_frm_cfg, \ 150 cgx_pause_frm_cfg) \ 151 /* NPA mbox IDs (range 0x400 - 0x5FF) */ \ 152 M(NPA_LF_ALLOC, 0x400, npa_lf_alloc, \ 153 npa_lf_alloc_req, npa_lf_alloc_rsp) \ 154 M(NPA_LF_FREE, 0x401, npa_lf_free, msg_req, msg_rsp) \ 155 M(NPA_AQ_ENQ, 0x402, npa_aq_enq, npa_aq_enq_req, npa_aq_enq_rsp) \ 156 M(NPA_HWCTX_DISABLE, 0x403, npa_hwctx_disable, hwctx_disable_req, msg_rsp)\ 157 /* SSO/SSOW mbox IDs (range 0x600 - 0x7FF) */ \ 158 /* TIM mbox IDs (range 0x800 - 0x9FF) */ \ 159 /* CPT mbox IDs (range 0xA00 - 0xBFF) */ \ 160 /* NPC mbox IDs (range 0x6000 - 0x7FFF) */ \ 161 M(NPC_MCAM_ALLOC_ENTRY, 0x6000, npc_mcam_alloc_entry, npc_mcam_alloc_entry_req,\ 162 npc_mcam_alloc_entry_rsp) \ 163 M(NPC_MCAM_FREE_ENTRY, 0x6001, npc_mcam_free_entry, \ 164 npc_mcam_free_entry_req, msg_rsp) \ 165 M(NPC_MCAM_WRITE_ENTRY, 0x6002, npc_mcam_write_entry, \ 166 npc_mcam_write_entry_req, msg_rsp) \ 167 M(NPC_MCAM_ENA_ENTRY, 0x6003, npc_mcam_ena_entry, \ 168 npc_mcam_ena_dis_entry_req, msg_rsp) \ 169 M(NPC_MCAM_DIS_ENTRY, 0x6004, npc_mcam_dis_entry, \ 170 npc_mcam_ena_dis_entry_req, msg_rsp) \ 171 M(NPC_MCAM_SHIFT_ENTRY, 0x6005, npc_mcam_shift_entry, npc_mcam_shift_entry_req,\ 172 npc_mcam_shift_entry_rsp) \ 173 M(NPC_MCAM_ALLOC_COUNTER, 0x6006, npc_mcam_alloc_counter, \ 174 npc_mcam_alloc_counter_req, \ 175 npc_mcam_alloc_counter_rsp) \ 176 M(NPC_MCAM_FREE_COUNTER, 0x6007, npc_mcam_free_counter, \ 177 npc_mcam_oper_counter_req, msg_rsp) \ 178 M(NPC_MCAM_UNMAP_COUNTER, 0x6008, npc_mcam_unmap_counter, \ 179 npc_mcam_unmap_counter_req, msg_rsp) \ 180 M(NPC_MCAM_CLEAR_COUNTER, 0x6009, npc_mcam_clear_counter, \ 181 npc_mcam_oper_counter_req, msg_rsp) \ 182 M(NPC_MCAM_COUNTER_STATS, 0x600a, npc_mcam_counter_stats, \ 183 npc_mcam_oper_counter_req, \ 184 npc_mcam_oper_counter_rsp) \ 185 M(NPC_MCAM_ALLOC_AND_WRITE_ENTRY, 0x600b, npc_mcam_alloc_and_write_entry, \ 186 npc_mcam_alloc_and_write_entry_req, \ 187 npc_mcam_alloc_and_write_entry_rsp) \ 188 M(NPC_GET_KEX_CFG, 0x600c, npc_get_kex_cfg, \ 189 msg_req, npc_get_kex_cfg_rsp) \ 190 /* NIX mbox IDs (range 0x8000 - 0xFFFF) */ \ 191 M(NIX_LF_ALLOC, 0x8000, nix_lf_alloc, \ 192 nix_lf_alloc_req, nix_lf_alloc_rsp) \ 193 M(NIX_LF_FREE, 0x8001, nix_lf_free, msg_req, msg_rsp) \ 194 M(NIX_AQ_ENQ, 0x8002, nix_aq_enq, nix_aq_enq_req, nix_aq_enq_rsp) \ 195 M(NIX_HWCTX_DISABLE, 0x8003, nix_hwctx_disable, \ 196 hwctx_disable_req, msg_rsp) \ 197 M(NIX_TXSCH_ALLOC, 0x8004, nix_txsch_alloc, \ 198 nix_txsch_alloc_req, nix_txsch_alloc_rsp) \ 199 M(NIX_TXSCH_FREE, 0x8005, nix_txsch_free, nix_txsch_free_req, msg_rsp) \ 200 M(NIX_TXSCHQ_CFG, 0x8006, nix_txschq_cfg, nix_txschq_config, msg_rsp) \ 201 M(NIX_STATS_RST, 0x8007, nix_stats_rst, msg_req, msg_rsp) \ 202 M(NIX_VTAG_CFG, 0x8008, nix_vtag_cfg, nix_vtag_config, msg_rsp) \ 203 M(NIX_RSS_FLOWKEY_CFG, 0x8009, nix_rss_flowkey_cfg, \ 204 nix_rss_flowkey_cfg, \ 205 nix_rss_flowkey_cfg_rsp) \ 206 M(NIX_SET_MAC_ADDR, 0x800a, nix_set_mac_addr, nix_set_mac_addr, msg_rsp) \ 207 M(NIX_SET_RX_MODE, 0x800b, nix_set_rx_mode, nix_rx_mode, msg_rsp) \ 208 M(NIX_SET_HW_FRS, 0x800c, nix_set_hw_frs, nix_frs_cfg, msg_rsp) \ 209 M(NIX_LF_START_RX, 0x800d, nix_lf_start_rx, msg_req, msg_rsp) \ 210 M(NIX_LF_STOP_RX, 0x800e, nix_lf_stop_rx, msg_req, msg_rsp) \ 211 M(NIX_MARK_FORMAT_CFG, 0x800f, nix_mark_format_cfg, \ 212 nix_mark_format_cfg, \ 213 nix_mark_format_cfg_rsp) \ 214 M(NIX_SET_RX_CFG, 0x8010, nix_set_rx_cfg, nix_rx_cfg, msg_rsp) \ 215 M(NIX_LSO_FORMAT_CFG, 0x8011, nix_lso_format_cfg, \ 216 nix_lso_format_cfg, \ 217 nix_lso_format_cfg_rsp) \ 218 M(NIX_RXVLAN_ALLOC, 0x8012, nix_rxvlan_alloc, msg_req, msg_rsp) \ 219 M(NIX_LF_PTP_TX_ENABLE, 0x8013, nix_lf_ptp_tx_enable, msg_req, msg_rsp) \ 220 M(NIX_LF_PTP_TX_DISABLE, 0x8014, nix_lf_ptp_tx_disable, msg_req, msg_rsp) \ 221 M(NIX_BP_ENABLE, 0x8016, nix_bp_enable, nix_bp_cfg_req, \ 222 nix_bp_cfg_rsp) \ 223 M(NIX_BP_DISABLE, 0x8017, nix_bp_disable, nix_bp_cfg_req, msg_rsp) \ 224 M(NIX_GET_MAC_ADDR, 0x8018, nix_get_mac_addr, msg_req, nix_get_mac_addr_rsp) \ 225 226 /* Messages initiated by AF (range 0xC00 - 0xDFF) */ 227 #define MBOX_UP_CGX_MESSAGES \ 228 M(CGX_LINK_EVENT, 0xC00, cgx_link_event, cgx_link_info_msg, msg_rsp) 229 230 enum { 231 #define M(_name, _id, _1, _2, _3) MBOX_MSG_ ## _name = _id, 232 MBOX_MESSAGES 233 MBOX_UP_CGX_MESSAGES 234 #undef M 235 }; 236 237 /* Mailbox message formats */ 238 239 #define RVU_DEFAULT_PF_FUNC 0xFFFF 240 241 /* Generic request msg used for those mbox messages which 242 * don't send any data in the request. 243 */ 244 struct msg_req { 245 struct mbox_msghdr hdr; 246 }; 247 248 /* Generic rsponse msg used a ack or response for those mbox 249 * messages which doesn't have a specific rsp msg format. 250 */ 251 struct msg_rsp { 252 struct mbox_msghdr hdr; 253 }; 254 255 /* RVU mailbox error codes 256 * Range 256 - 300. 257 */ 258 enum rvu_af_status { 259 RVU_INVALID_VF_ID = -256, 260 }; 261 262 struct ready_msg_rsp { 263 struct mbox_msghdr hdr; 264 u16 sclk_freq; /* SCLK frequency (in MHz) */ 265 u16 rclk_freq; /* RCLK frequency (in MHz) */ 266 }; 267 268 /* Structure for requesting resource provisioning. 269 * 'modify' flag to be used when either requesting more 270 * or to detach partial of a cetain resource type. 271 * Rest of the fields specify how many of what type to 272 * be attached. 273 */ 274 struct rsrc_attach { 275 struct mbox_msghdr hdr; 276 u8 modify:1; 277 u8 npalf:1; 278 u8 nixlf:1; 279 u16 sso; 280 u16 ssow; 281 u16 timlfs; 282 u16 cptlfs; 283 }; 284 285 /* Structure for relinquishing resources. 286 * 'partial' flag to be used when relinquishing all resources 287 * but only of a certain type. If not set, all resources of all 288 * types provisioned to the RVU function will be detached. 289 */ 290 struct rsrc_detach { 291 struct mbox_msghdr hdr; 292 u8 partial:1; 293 u8 npalf:1; 294 u8 nixlf:1; 295 u8 sso:1; 296 u8 ssow:1; 297 u8 timlfs:1; 298 u8 cptlfs:1; 299 }; 300 301 #define MSIX_VECTOR_INVALID 0xFFFF 302 #define MAX_RVU_BLKLF_CNT 256 303 304 struct msix_offset_rsp { 305 struct mbox_msghdr hdr; 306 u16 npa_msixoff; 307 u16 nix_msixoff; 308 u8 sso; 309 u8 ssow; 310 u8 timlfs; 311 u8 cptlfs; 312 u16 sso_msixoff[MAX_RVU_BLKLF_CNT]; 313 u16 ssow_msixoff[MAX_RVU_BLKLF_CNT]; 314 u16 timlf_msixoff[MAX_RVU_BLKLF_CNT]; 315 u16 cptlf_msixoff[MAX_RVU_BLKLF_CNT]; 316 }; 317 318 struct get_hw_cap_rsp { 319 struct mbox_msghdr hdr; 320 u8 nix_fixed_txschq_mapping; /* Schq mapping fixed or flexible */ 321 u8 nix_shaping; /* Is shaping and coloring supported */ 322 }; 323 324 /* CGX mbox message formats */ 325 326 struct cgx_stats_rsp { 327 struct mbox_msghdr hdr; 328 #define CGX_RX_STATS_COUNT 13 329 #define CGX_TX_STATS_COUNT 18 330 u64 rx_stats[CGX_RX_STATS_COUNT]; 331 u64 tx_stats[CGX_TX_STATS_COUNT]; 332 }; 333 334 /* Structure for requesting the operation for 335 * setting/getting mac address in the CGX interface 336 */ 337 struct cgx_mac_addr_set_or_get { 338 struct mbox_msghdr hdr; 339 u8 mac_addr[ETH_ALEN]; 340 }; 341 342 struct cgx_link_user_info { 343 uint64_t link_up:1; 344 uint64_t full_duplex:1; 345 uint64_t lmac_type_id:4; 346 uint64_t speed:20; /* speed in Mbps */ 347 #define LMACTYPE_STR_LEN 16 348 char lmac_type[LMACTYPE_STR_LEN]; 349 }; 350 351 struct cgx_link_info_msg { 352 struct mbox_msghdr hdr; 353 struct cgx_link_user_info link_info; 354 }; 355 356 struct cgx_pause_frm_cfg { 357 struct mbox_msghdr hdr; 358 u8 set; 359 /* set = 1 if the request is to config pause frames */ 360 /* set = 0 if the request is to fetch pause frames config */ 361 u8 rx_pause; 362 u8 tx_pause; 363 }; 364 365 /* NPA mbox message formats */ 366 367 /* NPA mailbox error codes 368 * Range 301 - 400. 369 */ 370 enum npa_af_status { 371 NPA_AF_ERR_PARAM = -301, 372 NPA_AF_ERR_AQ_FULL = -302, 373 NPA_AF_ERR_AQ_ENQUEUE = -303, 374 NPA_AF_ERR_AF_LF_INVALID = -304, 375 NPA_AF_ERR_AF_LF_ALLOC = -305, 376 NPA_AF_ERR_LF_RESET = -306, 377 }; 378 379 /* For NPA LF context alloc and init */ 380 struct npa_lf_alloc_req { 381 struct mbox_msghdr hdr; 382 int node; 383 int aura_sz; /* No of auras */ 384 u32 nr_pools; /* No of pools */ 385 u64 way_mask; 386 }; 387 388 struct npa_lf_alloc_rsp { 389 struct mbox_msghdr hdr; 390 u32 stack_pg_ptrs; /* No of ptrs per stack page */ 391 u32 stack_pg_bytes; /* Size of stack page */ 392 u16 qints; /* NPA_AF_CONST::QINTS */ 393 }; 394 395 /* NPA AQ enqueue msg */ 396 struct npa_aq_enq_req { 397 struct mbox_msghdr hdr; 398 u32 aura_id; 399 u8 ctype; 400 u8 op; 401 union { 402 /* Valid when op == WRITE/INIT and ctype == AURA. 403 * LF fills the pool_id in aura.pool_addr. AF will translate 404 * the pool_id to pool context pointer. 405 */ 406 struct npa_aura_s aura; 407 /* Valid when op == WRITE/INIT and ctype == POOL */ 408 struct npa_pool_s pool; 409 }; 410 /* Mask data when op == WRITE (1=write, 0=don't write) */ 411 union { 412 /* Valid when op == WRITE and ctype == AURA */ 413 struct npa_aura_s aura_mask; 414 /* Valid when op == WRITE and ctype == POOL */ 415 struct npa_pool_s pool_mask; 416 }; 417 }; 418 419 struct npa_aq_enq_rsp { 420 struct mbox_msghdr hdr; 421 union { 422 /* Valid when op == READ and ctype == AURA */ 423 struct npa_aura_s aura; 424 /* Valid when op == READ and ctype == POOL */ 425 struct npa_pool_s pool; 426 }; 427 }; 428 429 /* Disable all contexts of type 'ctype' */ 430 struct hwctx_disable_req { 431 struct mbox_msghdr hdr; 432 u8 ctype; 433 }; 434 435 /* NIX mbox message formats */ 436 437 /* NIX mailbox error codes 438 * Range 401 - 500. 439 */ 440 enum nix_af_status { 441 NIX_AF_ERR_PARAM = -401, 442 NIX_AF_ERR_AQ_FULL = -402, 443 NIX_AF_ERR_AQ_ENQUEUE = -403, 444 NIX_AF_ERR_AF_LF_INVALID = -404, 445 NIX_AF_ERR_AF_LF_ALLOC = -405, 446 NIX_AF_ERR_TLX_ALLOC_FAIL = -406, 447 NIX_AF_ERR_TLX_INVALID = -407, 448 NIX_AF_ERR_RSS_SIZE_INVALID = -408, 449 NIX_AF_ERR_RSS_GRPS_INVALID = -409, 450 NIX_AF_ERR_FRS_INVALID = -410, 451 NIX_AF_ERR_RX_LINK_INVALID = -411, 452 NIX_AF_INVAL_TXSCHQ_CFG = -412, 453 NIX_AF_SMQ_FLUSH_FAILED = -413, 454 NIX_AF_ERR_LF_RESET = -414, 455 NIX_AF_ERR_RSS_NOSPC_FIELD = -415, 456 NIX_AF_ERR_RSS_NOSPC_ALGO = -416, 457 NIX_AF_ERR_MARK_CFG_FAIL = -417, 458 NIX_AF_ERR_LSO_CFG_FAIL = -418, 459 NIX_AF_INVAL_NPA_PF_FUNC = -419, 460 NIX_AF_INVAL_SSO_PF_FUNC = -420, 461 }; 462 463 /* For NIX LF context alloc and init */ 464 struct nix_lf_alloc_req { 465 struct mbox_msghdr hdr; 466 int node; 467 u32 rq_cnt; /* No of receive queues */ 468 u32 sq_cnt; /* No of send queues */ 469 u32 cq_cnt; /* No of completion queues */ 470 u8 xqe_sz; 471 u16 rss_sz; 472 u8 rss_grps; 473 u16 npa_func; 474 u16 sso_func; 475 u64 rx_cfg; /* See NIX_AF_LF(0..127)_RX_CFG */ 476 u64 way_mask; 477 }; 478 479 struct nix_lf_alloc_rsp { 480 struct mbox_msghdr hdr; 481 u16 sqb_size; 482 u16 rx_chan_base; 483 u16 tx_chan_base; 484 u8 rx_chan_cnt; /* total number of RX channels */ 485 u8 tx_chan_cnt; /* total number of TX channels */ 486 u8 lso_tsov4_idx; 487 u8 lso_tsov6_idx; 488 u8 mac_addr[ETH_ALEN]; 489 u8 lf_rx_stats; /* NIX_AF_CONST1::LF_RX_STATS */ 490 u8 lf_tx_stats; /* NIX_AF_CONST1::LF_TX_STATS */ 491 u16 cints; /* NIX_AF_CONST2::CINTS */ 492 u16 qints; /* NIX_AF_CONST2::QINTS */ 493 }; 494 495 /* NIX AQ enqueue msg */ 496 struct nix_aq_enq_req { 497 struct mbox_msghdr hdr; 498 u32 qidx; 499 u8 ctype; 500 u8 op; 501 union { 502 struct nix_rq_ctx_s rq; 503 struct nix_sq_ctx_s sq; 504 struct nix_cq_ctx_s cq; 505 struct nix_rsse_s rss; 506 struct nix_rx_mce_s mce; 507 }; 508 union { 509 struct nix_rq_ctx_s rq_mask; 510 struct nix_sq_ctx_s sq_mask; 511 struct nix_cq_ctx_s cq_mask; 512 struct nix_rsse_s rss_mask; 513 struct nix_rx_mce_s mce_mask; 514 }; 515 }; 516 517 struct nix_aq_enq_rsp { 518 struct mbox_msghdr hdr; 519 union { 520 struct nix_rq_ctx_s rq; 521 struct nix_sq_ctx_s sq; 522 struct nix_cq_ctx_s cq; 523 struct nix_rsse_s rss; 524 struct nix_rx_mce_s mce; 525 }; 526 }; 527 528 /* Tx scheduler/shaper mailbox messages */ 529 530 #define MAX_TXSCHQ_PER_FUNC 128 531 532 struct nix_txsch_alloc_req { 533 struct mbox_msghdr hdr; 534 /* Scheduler queue count request at each level */ 535 u16 schq_contig[NIX_TXSCH_LVL_CNT]; /* No of contiguous queues */ 536 u16 schq[NIX_TXSCH_LVL_CNT]; /* No of non-contiguous queues */ 537 }; 538 539 struct nix_txsch_alloc_rsp { 540 struct mbox_msghdr hdr; 541 /* Scheduler queue count allocated at each level */ 542 u16 schq_contig[NIX_TXSCH_LVL_CNT]; 543 u16 schq[NIX_TXSCH_LVL_CNT]; 544 /* Scheduler queue list allocated at each level */ 545 u16 schq_contig_list[NIX_TXSCH_LVL_CNT][MAX_TXSCHQ_PER_FUNC]; 546 u16 schq_list[NIX_TXSCH_LVL_CNT][MAX_TXSCHQ_PER_FUNC]; 547 u8 aggr_level; /* Traffic aggregation scheduler level */ 548 u8 aggr_lvl_rr_prio; /* Aggregation lvl's RR_PRIO config */ 549 u8 link_cfg_lvl; /* LINKX_CFG CSRs mapped to TL3 or TL2's index ? */ 550 }; 551 552 struct nix_txsch_free_req { 553 struct mbox_msghdr hdr; 554 #define TXSCHQ_FREE_ALL BIT_ULL(0) 555 u16 flags; 556 /* Scheduler queue level to be freed */ 557 u16 schq_lvl; 558 /* List of scheduler queues to be freed */ 559 u16 schq; 560 }; 561 562 struct nix_txschq_config { 563 struct mbox_msghdr hdr; 564 u8 lvl; /* SMQ/MDQ/TL4/TL3/TL2/TL1 */ 565 #define TXSCHQ_IDX_SHIFT 16 566 #define TXSCHQ_IDX_MASK (BIT_ULL(10) - 1) 567 #define TXSCHQ_IDX(reg, shift) (((reg) >> (shift)) & TXSCHQ_IDX_MASK) 568 u8 num_regs; 569 #define MAX_REGS_PER_MBOX_MSG 20 570 u64 reg[MAX_REGS_PER_MBOX_MSG]; 571 u64 regval[MAX_REGS_PER_MBOX_MSG]; 572 }; 573 574 struct nix_vtag_config { 575 struct mbox_msghdr hdr; 576 /* '0' for 4 octet VTAG, '1' for 8 octet VTAG */ 577 u8 vtag_size; 578 /* cfg_type is '0' for tx vlan cfg 579 * cfg_type is '1' for rx vlan cfg 580 */ 581 u8 cfg_type; 582 union { 583 /* valid when cfg_type is '0' */ 584 struct { 585 /* tx vlan0 tag(C-VLAN) */ 586 u64 vlan0; 587 /* tx vlan1 tag(S-VLAN) */ 588 u64 vlan1; 589 /* insert tx vlan tag */ 590 u8 insert_vlan :1; 591 /* insert tx double vlan tag */ 592 u8 double_vlan :1; 593 } tx; 594 595 /* valid when cfg_type is '1' */ 596 struct { 597 /* rx vtag type index, valid values are in 0..7 range */ 598 u8 vtag_type; 599 /* rx vtag strip */ 600 u8 strip_vtag :1; 601 /* rx vtag capture */ 602 u8 capture_vtag :1; 603 } rx; 604 }; 605 }; 606 607 struct nix_rss_flowkey_cfg { 608 struct mbox_msghdr hdr; 609 int mcam_index; /* MCAM entry index to modify */ 610 #define NIX_FLOW_KEY_TYPE_PORT BIT(0) 611 #define NIX_FLOW_KEY_TYPE_IPV4 BIT(1) 612 #define NIX_FLOW_KEY_TYPE_IPV6 BIT(2) 613 #define NIX_FLOW_KEY_TYPE_TCP BIT(3) 614 #define NIX_FLOW_KEY_TYPE_UDP BIT(4) 615 #define NIX_FLOW_KEY_TYPE_SCTP BIT(5) 616 #define NIX_FLOW_KEY_TYPE_NVGRE BIT(6) 617 #define NIX_FLOW_KEY_TYPE_VXLAN BIT(7) 618 #define NIX_FLOW_KEY_TYPE_GENEVE BIT(8) 619 #define NIX_FLOW_KEY_TYPE_ETH_DMAC BIT(9) 620 #define NIX_FLOW_KEY_TYPE_IPV6_EXT BIT(10) 621 #define NIX_FLOW_KEY_TYPE_GTPU BIT(11) 622 #define NIX_FLOW_KEY_TYPE_INNR_IPV4 BIT(12) 623 #define NIX_FLOW_KEY_TYPE_INNR_IPV6 BIT(13) 624 #define NIX_FLOW_KEY_TYPE_INNR_TCP BIT(14) 625 #define NIX_FLOW_KEY_TYPE_INNR_UDP BIT(15) 626 #define NIX_FLOW_KEY_TYPE_INNR_SCTP BIT(16) 627 #define NIX_FLOW_KEY_TYPE_INNR_ETH_DMAC BIT(17) 628 #define NIX_FLOW_KEY_TYPE_VLAN BIT(20) 629 u32 flowkey_cfg; /* Flowkey types selected */ 630 u8 group; /* RSS context or group */ 631 }; 632 633 struct nix_rss_flowkey_cfg_rsp { 634 struct mbox_msghdr hdr; 635 u8 alg_idx; /* Selected algo index */ 636 }; 637 638 struct nix_set_mac_addr { 639 struct mbox_msghdr hdr; 640 u8 mac_addr[ETH_ALEN]; /* MAC address to be set for this pcifunc */ 641 }; 642 643 struct nix_get_mac_addr_rsp { 644 struct mbox_msghdr hdr; 645 u8 mac_addr[ETH_ALEN]; 646 }; 647 648 struct nix_mark_format_cfg { 649 struct mbox_msghdr hdr; 650 u8 offset; 651 u8 y_mask; 652 u8 y_val; 653 u8 r_mask; 654 u8 r_val; 655 }; 656 657 struct nix_mark_format_cfg_rsp { 658 struct mbox_msghdr hdr; 659 u8 mark_format_idx; 660 }; 661 662 struct nix_rx_mode { 663 struct mbox_msghdr hdr; 664 #define NIX_RX_MODE_UCAST BIT(0) 665 #define NIX_RX_MODE_PROMISC BIT(1) 666 #define NIX_RX_MODE_ALLMULTI BIT(2) 667 u16 mode; 668 }; 669 670 struct nix_rx_cfg { 671 struct mbox_msghdr hdr; 672 #define NIX_RX_OL3_VERIFY BIT(0) 673 #define NIX_RX_OL4_VERIFY BIT(1) 674 u8 len_verify; /* Outer L3/L4 len check */ 675 #define NIX_RX_CSUM_OL4_VERIFY BIT(0) 676 u8 csum_verify; /* Outer L4 checksum verification */ 677 }; 678 679 struct nix_frs_cfg { 680 struct mbox_msghdr hdr; 681 u8 update_smq; /* Update SMQ's min/max lens */ 682 u8 update_minlen; /* Set minlen also */ 683 u8 sdp_link; /* Set SDP RX link */ 684 u16 maxlen; 685 u16 minlen; 686 }; 687 688 struct nix_lso_format_cfg { 689 struct mbox_msghdr hdr; 690 u64 field_mask; 691 #define NIX_LSO_FIELD_MAX 8 692 u64 fields[NIX_LSO_FIELD_MAX]; 693 }; 694 695 struct nix_lso_format_cfg_rsp { 696 struct mbox_msghdr hdr; 697 u8 lso_format_idx; 698 }; 699 700 struct nix_bp_cfg_req { 701 struct mbox_msghdr hdr; 702 u16 chan_base; /* Starting channel number */ 703 u8 chan_cnt; /* Number of channels */ 704 u8 bpid_per_chan; 705 /* bpid_per_chan = 0 assigns single bp id for range of channels */ 706 /* bpid_per_chan = 1 assigns separate bp id for each channel */ 707 }; 708 709 /* PF can be mapped to either CGX or LBK interface, 710 * so maximum 64 channels are possible. 711 */ 712 #define NIX_MAX_BPID_CHAN 64 713 struct nix_bp_cfg_rsp { 714 struct mbox_msghdr hdr; 715 u16 chan_bpid[NIX_MAX_BPID_CHAN]; /* Channel and bpid mapping */ 716 u8 chan_cnt; /* Number of channel for which bpids are assigned */ 717 }; 718 719 /* NPC mbox message structs */ 720 721 #define NPC_MCAM_ENTRY_INVALID 0xFFFF 722 #define NPC_MCAM_INVALID_MAP 0xFFFF 723 724 /* NPC mailbox error codes 725 * Range 701 - 800. 726 */ 727 enum npc_af_status { 728 NPC_MCAM_INVALID_REQ = -701, 729 NPC_MCAM_ALLOC_DENIED = -702, 730 NPC_MCAM_ALLOC_FAILED = -703, 731 NPC_MCAM_PERM_DENIED = -704, 732 }; 733 734 struct npc_mcam_alloc_entry_req { 735 struct mbox_msghdr hdr; 736 #define NPC_MAX_NONCONTIG_ENTRIES 256 737 u8 contig; /* Contiguous entries ? */ 738 #define NPC_MCAM_ANY_PRIO 0 739 #define NPC_MCAM_LOWER_PRIO 1 740 #define NPC_MCAM_HIGHER_PRIO 2 741 u8 priority; /* Lower or higher w.r.t ref_entry */ 742 u16 ref_entry; 743 u16 count; /* Number of entries requested */ 744 }; 745 746 struct npc_mcam_alloc_entry_rsp { 747 struct mbox_msghdr hdr; 748 u16 entry; /* Entry allocated or start index if contiguous. 749 * Invalid incase of non-contiguous. 750 */ 751 u16 count; /* Number of entries allocated */ 752 u16 free_count; /* Number of entries available */ 753 u16 entry_list[NPC_MAX_NONCONTIG_ENTRIES]; 754 }; 755 756 struct npc_mcam_free_entry_req { 757 struct mbox_msghdr hdr; 758 u16 entry; /* Entry index to be freed */ 759 u8 all; /* If all entries allocated to this PFVF to be freed */ 760 }; 761 762 struct mcam_entry { 763 #define NPC_MAX_KWS_IN_KEY 7 /* Number of keywords in max keywidth */ 764 u64 kw[NPC_MAX_KWS_IN_KEY]; 765 u64 kw_mask[NPC_MAX_KWS_IN_KEY]; 766 u64 action; 767 u64 vtag_action; 768 }; 769 770 struct npc_mcam_write_entry_req { 771 struct mbox_msghdr hdr; 772 struct mcam_entry entry_data; 773 u16 entry; /* MCAM entry to write this match key */ 774 u16 cntr; /* Counter for this MCAM entry */ 775 u8 intf; /* Rx or Tx interface */ 776 u8 enable_entry;/* Enable this MCAM entry ? */ 777 u8 set_cntr; /* Set counter for this entry ? */ 778 }; 779 780 /* Enable/Disable a given entry */ 781 struct npc_mcam_ena_dis_entry_req { 782 struct mbox_msghdr hdr; 783 u16 entry; 784 }; 785 786 struct npc_mcam_shift_entry_req { 787 struct mbox_msghdr hdr; 788 #define NPC_MCAM_MAX_SHIFTS 64 789 u16 curr_entry[NPC_MCAM_MAX_SHIFTS]; 790 u16 new_entry[NPC_MCAM_MAX_SHIFTS]; 791 u16 shift_count; /* Number of entries to shift */ 792 }; 793 794 struct npc_mcam_shift_entry_rsp { 795 struct mbox_msghdr hdr; 796 u16 failed_entry_idx; /* Index in 'curr_entry', not entry itself */ 797 }; 798 799 struct npc_mcam_alloc_counter_req { 800 struct mbox_msghdr hdr; 801 u8 contig; /* Contiguous counters ? */ 802 #define NPC_MAX_NONCONTIG_COUNTERS 64 803 u16 count; /* Number of counters requested */ 804 }; 805 806 struct npc_mcam_alloc_counter_rsp { 807 struct mbox_msghdr hdr; 808 u16 cntr; /* Counter allocated or start index if contiguous. 809 * Invalid incase of non-contiguous. 810 */ 811 u16 count; /* Number of counters allocated */ 812 u16 cntr_list[NPC_MAX_NONCONTIG_COUNTERS]; 813 }; 814 815 struct npc_mcam_oper_counter_req { 816 struct mbox_msghdr hdr; 817 u16 cntr; /* Free a counter or clear/fetch it's stats */ 818 }; 819 820 struct npc_mcam_oper_counter_rsp { 821 struct mbox_msghdr hdr; 822 u64 stat; /* valid only while fetching counter's stats */ 823 }; 824 825 struct npc_mcam_unmap_counter_req { 826 struct mbox_msghdr hdr; 827 u16 cntr; 828 u16 entry; /* Entry and counter to be unmapped */ 829 u8 all; /* Unmap all entries using this counter ? */ 830 }; 831 832 struct npc_mcam_alloc_and_write_entry_req { 833 struct mbox_msghdr hdr; 834 struct mcam_entry entry_data; 835 u16 ref_entry; 836 u8 priority; /* Lower or higher w.r.t ref_entry */ 837 u8 intf; /* Rx or Tx interface */ 838 u8 enable_entry;/* Enable this MCAM entry ? */ 839 u8 alloc_cntr; /* Allocate counter and map ? */ 840 }; 841 842 struct npc_mcam_alloc_and_write_entry_rsp { 843 struct mbox_msghdr hdr; 844 u16 entry; 845 u16 cntr; 846 }; 847 848 struct npc_get_kex_cfg_rsp { 849 struct mbox_msghdr hdr; 850 u64 rx_keyx_cfg; /* NPC_AF_INTF(0)_KEX_CFG */ 851 u64 tx_keyx_cfg; /* NPC_AF_INTF(1)_KEX_CFG */ 852 #define NPC_MAX_INTF 2 853 #define NPC_MAX_LID 8 854 #define NPC_MAX_LT 16 855 #define NPC_MAX_LD 2 856 #define NPC_MAX_LFL 16 857 /* NPC_AF_KEX_LDATA(0..1)_FLAGS_CFG */ 858 u64 kex_ld_flags[NPC_MAX_LD]; 859 /* NPC_AF_INTF(0..1)_LID(0..7)_LT(0..15)_LD(0..1)_CFG */ 860 u64 intf_lid_lt_ld[NPC_MAX_INTF][NPC_MAX_LID][NPC_MAX_LT][NPC_MAX_LD]; 861 /* NPC_AF_INTF(0..1)_LDATA(0..1)_FLAGS(0..15)_CFG */ 862 u64 intf_ld_flags[NPC_MAX_INTF][NPC_MAX_LD][NPC_MAX_LFL]; 863 #define MKEX_NAME_LEN 128 864 u8 mkex_pfl_name[MKEX_NAME_LEN]; 865 }; 866 867 enum ptp_op { 868 PTP_OP_ADJFINE = 0, 869 PTP_OP_GET_CLOCK = 1, 870 }; 871 872 struct ptp_req { 873 struct mbox_msghdr hdr; 874 u8 op; 875 s64 scaled_ppm; 876 }; 877 878 struct ptp_rsp { 879 struct mbox_msghdr hdr; 880 u64 clk; 881 }; 882 883 #endif /* MBOX_H */ 884