1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Marvell OcteonTx2 RVU Admin Function driver 3 * 4 * Copyright (C) 2018 Marvell International Ltd. 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 */ 10 11 #ifndef MBOX_H 12 #define MBOX_H 13 14 #include <linux/etherdevice.h> 15 #include <linux/sizes.h> 16 17 #include "rvu_struct.h" 18 #include "common.h" 19 20 #define MBOX_SIZE SZ_64K 21 22 /* AF/PF: PF initiated, PF/VF VF initiated */ 23 #define MBOX_DOWN_RX_START 0 24 #define MBOX_DOWN_RX_SIZE (46 * SZ_1K) 25 #define MBOX_DOWN_TX_START (MBOX_DOWN_RX_START + MBOX_DOWN_RX_SIZE) 26 #define MBOX_DOWN_TX_SIZE (16 * SZ_1K) 27 /* AF/PF: AF initiated, PF/VF PF initiated */ 28 #define MBOX_UP_RX_START (MBOX_DOWN_TX_START + MBOX_DOWN_TX_SIZE) 29 #define MBOX_UP_RX_SIZE SZ_1K 30 #define MBOX_UP_TX_START (MBOX_UP_RX_START + MBOX_UP_RX_SIZE) 31 #define MBOX_UP_TX_SIZE SZ_1K 32 33 #if MBOX_UP_TX_SIZE + MBOX_UP_TX_START != MBOX_SIZE 34 # error "incorrect mailbox area sizes" 35 #endif 36 37 #define INTR_MASK(pfvfs) ((pfvfs < 64) ? (BIT_ULL(pfvfs) - 1) : (~0ull)) 38 39 #define MBOX_RSP_TIMEOUT 3000 /* Time(ms) to wait for mbox response */ 40 41 #define MBOX_MSG_ALIGN 16 /* Align mbox msg start to 16bytes */ 42 43 /* Mailbox directions */ 44 #define MBOX_DIR_AFPF 0 /* AF replies to PF */ 45 #define MBOX_DIR_PFAF 1 /* PF sends messages to AF */ 46 #define MBOX_DIR_PFVF 2 /* PF replies to VF */ 47 #define MBOX_DIR_VFPF 3 /* VF sends messages to PF */ 48 #define MBOX_DIR_AFPF_UP 4 /* AF sends messages to PF */ 49 #define MBOX_DIR_PFAF_UP 5 /* PF replies to AF */ 50 #define MBOX_DIR_PFVF_UP 6 /* PF sends messages to VF */ 51 #define MBOX_DIR_VFPF_UP 7 /* VF replies to PF */ 52 53 struct otx2_mbox_dev { 54 void *mbase; /* This dev's mbox region */ 55 void *hwbase; 56 spinlock_t mbox_lock; 57 u16 msg_size; /* Total msg size to be sent */ 58 u16 rsp_size; /* Total rsp size to be sure the reply is ok */ 59 u16 num_msgs; /* No of msgs sent or waiting for response */ 60 u16 msgs_acked; /* No of msgs for which response is received */ 61 }; 62 63 struct otx2_mbox { 64 struct pci_dev *pdev; 65 void *hwbase; /* Mbox region advertised by HW */ 66 void *reg_base;/* CSR base for this dev */ 67 u64 trigger; /* Trigger mbox notification */ 68 u16 tr_shift; /* Mbox trigger shift */ 69 u64 rx_start; /* Offset of Rx region in mbox memory */ 70 u64 tx_start; /* Offset of Tx region in mbox memory */ 71 u16 rx_size; /* Size of Rx region */ 72 u16 tx_size; /* Size of Tx region */ 73 u16 ndevs; /* The number of peers */ 74 struct otx2_mbox_dev *dev; 75 }; 76 77 /* Header which precedes all mbox messages */ 78 struct mbox_hdr { 79 u64 msg_size; /* Total msgs size embedded */ 80 u16 num_msgs; /* No of msgs embedded */ 81 }; 82 83 /* Header which precedes every msg and is also part of it */ 84 struct mbox_msghdr { 85 u16 pcifunc; /* Who's sending this msg */ 86 u16 id; /* Mbox message ID */ 87 #define OTX2_MBOX_REQ_SIG (0xdead) 88 #define OTX2_MBOX_RSP_SIG (0xbeef) 89 u16 sig; /* Signature, for validating corrupted msgs */ 90 #define OTX2_MBOX_VERSION (0x0007) 91 u16 ver; /* Version of msg's structure for this ID */ 92 u16 next_msgoff; /* Offset of next msg within mailbox region */ 93 int rc; /* Msg process'ed response code */ 94 }; 95 96 void otx2_mbox_reset(struct otx2_mbox *mbox, int devid); 97 void __otx2_mbox_reset(struct otx2_mbox *mbox, int devid); 98 void otx2_mbox_destroy(struct otx2_mbox *mbox); 99 int otx2_mbox_init(struct otx2_mbox *mbox, void __force *hwbase, 100 struct pci_dev *pdev, void __force *reg_base, 101 int direction, int ndevs); 102 int otx2_mbox_regions_init(struct otx2_mbox *mbox, void __force **hwbase, 103 struct pci_dev *pdev, void __force *reg_base, 104 int direction, int ndevs); 105 void otx2_mbox_msg_send(struct otx2_mbox *mbox, int devid); 106 int otx2_mbox_wait_for_rsp(struct otx2_mbox *mbox, int devid); 107 int otx2_mbox_busy_poll_for_rsp(struct otx2_mbox *mbox, int devid); 108 struct mbox_msghdr *otx2_mbox_alloc_msg_rsp(struct otx2_mbox *mbox, int devid, 109 int size, int size_rsp); 110 struct mbox_msghdr *otx2_mbox_get_rsp(struct otx2_mbox *mbox, int devid, 111 struct mbox_msghdr *msg); 112 int otx2_mbox_check_rsp_msgs(struct otx2_mbox *mbox, int devid); 113 int otx2_reply_invalid_msg(struct otx2_mbox *mbox, int devid, 114 u16 pcifunc, u16 id); 115 bool otx2_mbox_nonempty(struct otx2_mbox *mbox, int devid); 116 const char *otx2_mbox_id2name(u16 id); 117 static inline struct mbox_msghdr *otx2_mbox_alloc_msg(struct otx2_mbox *mbox, 118 int devid, int size) 119 { 120 return otx2_mbox_alloc_msg_rsp(mbox, devid, size, 0); 121 } 122 123 /* Mailbox message types */ 124 #define MBOX_MSG_MASK 0xFFFF 125 #define MBOX_MSG_INVALID 0xFFFE 126 #define MBOX_MSG_MAX 0xFFFF 127 128 #define MBOX_MESSAGES \ 129 /* Generic mbox IDs (range 0x000 - 0x1FF) */ \ 130 M(READY, 0x001, ready, msg_req, ready_msg_rsp) \ 131 M(ATTACH_RESOURCES, 0x002, attach_resources, rsrc_attach, msg_rsp) \ 132 M(DETACH_RESOURCES, 0x003, detach_resources, rsrc_detach, msg_rsp) \ 133 M(MSIX_OFFSET, 0x005, msix_offset, msg_req, msix_offset_rsp) \ 134 M(VF_FLR, 0x006, vf_flr, msg_req, msg_rsp) \ 135 M(PTP_OP, 0x007, ptp_op, ptp_req, ptp_rsp) \ 136 M(GET_HW_CAP, 0x008, get_hw_cap, msg_req, get_hw_cap_rsp) \ 137 /* CGX mbox IDs (range 0x200 - 0x3FF) */ \ 138 M(CGX_START_RXTX, 0x200, cgx_start_rxtx, msg_req, msg_rsp) \ 139 M(CGX_STOP_RXTX, 0x201, cgx_stop_rxtx, msg_req, msg_rsp) \ 140 M(CGX_STATS, 0x202, cgx_stats, msg_req, cgx_stats_rsp) \ 141 M(CGX_MAC_ADDR_SET, 0x203, cgx_mac_addr_set, cgx_mac_addr_set_or_get, \ 142 cgx_mac_addr_set_or_get) \ 143 M(CGX_MAC_ADDR_GET, 0x204, cgx_mac_addr_get, cgx_mac_addr_set_or_get, \ 144 cgx_mac_addr_set_or_get) \ 145 M(CGX_PROMISC_ENABLE, 0x205, cgx_promisc_enable, msg_req, msg_rsp) \ 146 M(CGX_PROMISC_DISABLE, 0x206, cgx_promisc_disable, msg_req, msg_rsp) \ 147 M(CGX_START_LINKEVENTS, 0x207, cgx_start_linkevents, msg_req, msg_rsp) \ 148 M(CGX_STOP_LINKEVENTS, 0x208, cgx_stop_linkevents, msg_req, msg_rsp) \ 149 M(CGX_GET_LINKINFO, 0x209, cgx_get_linkinfo, msg_req, cgx_link_info_msg) \ 150 M(CGX_INTLBK_ENABLE, 0x20A, cgx_intlbk_enable, msg_req, msg_rsp) \ 151 M(CGX_INTLBK_DISABLE, 0x20B, cgx_intlbk_disable, msg_req, msg_rsp) \ 152 M(CGX_PTP_RX_ENABLE, 0x20C, cgx_ptp_rx_enable, msg_req, msg_rsp) \ 153 M(CGX_PTP_RX_DISABLE, 0x20D, cgx_ptp_rx_disable, msg_req, msg_rsp) \ 154 M(CGX_CFG_PAUSE_FRM, 0x20E, cgx_cfg_pause_frm, cgx_pause_frm_cfg, \ 155 cgx_pause_frm_cfg) \ 156 M(CGX_FEC_SET, 0x210, cgx_set_fec_param, fec_mode, fec_mode) \ 157 M(CGX_FEC_STATS, 0x211, cgx_fec_stats, msg_req, cgx_fec_stats_rsp) \ 158 M(CGX_GET_PHY_FEC_STATS, 0x212, cgx_get_phy_fec_stats, msg_req, msg_rsp) \ 159 M(CGX_FW_DATA_GET, 0x213, cgx_get_aux_link_info, msg_req, cgx_fw_data) \ 160 M(CGX_SET_LINK_MODE, 0x214, cgx_set_link_mode, cgx_set_link_mode_req,\ 161 cgx_set_link_mode_rsp) \ 162 M(CGX_FEATURES_GET, 0x215, cgx_features_get, msg_req, \ 163 cgx_features_info_msg) \ 164 M(RPM_STATS, 0x216, rpm_stats, msg_req, rpm_stats_rsp) \ 165 /* NPA mbox IDs (range 0x400 - 0x5FF) */ \ 166 /* NPA mbox IDs (range 0x400 - 0x5FF) */ \ 167 M(NPA_LF_ALLOC, 0x400, npa_lf_alloc, \ 168 npa_lf_alloc_req, npa_lf_alloc_rsp) \ 169 M(NPA_LF_FREE, 0x401, npa_lf_free, msg_req, msg_rsp) \ 170 M(NPA_AQ_ENQ, 0x402, npa_aq_enq, npa_aq_enq_req, npa_aq_enq_rsp) \ 171 M(NPA_HWCTX_DISABLE, 0x403, npa_hwctx_disable, hwctx_disable_req, msg_rsp)\ 172 /* SSO/SSOW mbox IDs (range 0x600 - 0x7FF) */ \ 173 /* TIM mbox IDs (range 0x800 - 0x9FF) */ \ 174 /* CPT mbox IDs (range 0xA00 - 0xBFF) */ \ 175 M(CPT_LF_ALLOC, 0xA00, cpt_lf_alloc, cpt_lf_alloc_req_msg, \ 176 msg_rsp) \ 177 M(CPT_LF_FREE, 0xA01, cpt_lf_free, msg_req, msg_rsp) \ 178 M(CPT_RD_WR_REGISTER, 0xA02, cpt_rd_wr_register, cpt_rd_wr_reg_msg, \ 179 cpt_rd_wr_reg_msg) \ 180 /* NPC mbox IDs (range 0x6000 - 0x7FFF) */ \ 181 M(NPC_MCAM_ALLOC_ENTRY, 0x6000, npc_mcam_alloc_entry, npc_mcam_alloc_entry_req,\ 182 npc_mcam_alloc_entry_rsp) \ 183 M(NPC_MCAM_FREE_ENTRY, 0x6001, npc_mcam_free_entry, \ 184 npc_mcam_free_entry_req, msg_rsp) \ 185 M(NPC_MCAM_WRITE_ENTRY, 0x6002, npc_mcam_write_entry, \ 186 npc_mcam_write_entry_req, msg_rsp) \ 187 M(NPC_MCAM_ENA_ENTRY, 0x6003, npc_mcam_ena_entry, \ 188 npc_mcam_ena_dis_entry_req, msg_rsp) \ 189 M(NPC_MCAM_DIS_ENTRY, 0x6004, npc_mcam_dis_entry, \ 190 npc_mcam_ena_dis_entry_req, msg_rsp) \ 191 M(NPC_MCAM_SHIFT_ENTRY, 0x6005, npc_mcam_shift_entry, npc_mcam_shift_entry_req,\ 192 npc_mcam_shift_entry_rsp) \ 193 M(NPC_MCAM_ALLOC_COUNTER, 0x6006, npc_mcam_alloc_counter, \ 194 npc_mcam_alloc_counter_req, \ 195 npc_mcam_alloc_counter_rsp) \ 196 M(NPC_MCAM_FREE_COUNTER, 0x6007, npc_mcam_free_counter, \ 197 npc_mcam_oper_counter_req, msg_rsp) \ 198 M(NPC_MCAM_UNMAP_COUNTER, 0x6008, npc_mcam_unmap_counter, \ 199 npc_mcam_unmap_counter_req, msg_rsp) \ 200 M(NPC_MCAM_CLEAR_COUNTER, 0x6009, npc_mcam_clear_counter, \ 201 npc_mcam_oper_counter_req, msg_rsp) \ 202 M(NPC_MCAM_COUNTER_STATS, 0x600a, npc_mcam_counter_stats, \ 203 npc_mcam_oper_counter_req, \ 204 npc_mcam_oper_counter_rsp) \ 205 M(NPC_MCAM_ALLOC_AND_WRITE_ENTRY, 0x600b, npc_mcam_alloc_and_write_entry, \ 206 npc_mcam_alloc_and_write_entry_req, \ 207 npc_mcam_alloc_and_write_entry_rsp) \ 208 M(NPC_GET_KEX_CFG, 0x600c, npc_get_kex_cfg, \ 209 msg_req, npc_get_kex_cfg_rsp) \ 210 M(NPC_INSTALL_FLOW, 0x600d, npc_install_flow, \ 211 npc_install_flow_req, npc_install_flow_rsp) \ 212 M(NPC_DELETE_FLOW, 0x600e, npc_delete_flow, \ 213 npc_delete_flow_req, msg_rsp) \ 214 M(NPC_MCAM_READ_ENTRY, 0x600f, npc_mcam_read_entry, \ 215 npc_mcam_read_entry_req, \ 216 npc_mcam_read_entry_rsp) \ 217 M(NPC_MCAM_READ_BASE_RULE, 0x6011, npc_read_base_steer_rule, \ 218 msg_req, npc_mcam_read_base_rule_rsp) \ 219 M(NPC_MCAM_GET_STATS, 0x6012, npc_mcam_entry_stats, \ 220 npc_mcam_get_stats_req, \ 221 npc_mcam_get_stats_rsp) \ 222 /* NIX mbox IDs (range 0x8000 - 0xFFFF) */ \ 223 M(NIX_LF_ALLOC, 0x8000, nix_lf_alloc, \ 224 nix_lf_alloc_req, nix_lf_alloc_rsp) \ 225 M(NIX_LF_FREE, 0x8001, nix_lf_free, nix_lf_free_req, msg_rsp) \ 226 M(NIX_AQ_ENQ, 0x8002, nix_aq_enq, nix_aq_enq_req, nix_aq_enq_rsp) \ 227 M(NIX_HWCTX_DISABLE, 0x8003, nix_hwctx_disable, \ 228 hwctx_disable_req, msg_rsp) \ 229 M(NIX_TXSCH_ALLOC, 0x8004, nix_txsch_alloc, \ 230 nix_txsch_alloc_req, nix_txsch_alloc_rsp) \ 231 M(NIX_TXSCH_FREE, 0x8005, nix_txsch_free, nix_txsch_free_req, msg_rsp) \ 232 M(NIX_TXSCHQ_CFG, 0x8006, nix_txschq_cfg, nix_txschq_config, msg_rsp) \ 233 M(NIX_STATS_RST, 0x8007, nix_stats_rst, msg_req, msg_rsp) \ 234 M(NIX_VTAG_CFG, 0x8008, nix_vtag_cfg, nix_vtag_config, \ 235 nix_vtag_config_rsp) \ 236 M(NIX_RSS_FLOWKEY_CFG, 0x8009, nix_rss_flowkey_cfg, \ 237 nix_rss_flowkey_cfg, \ 238 nix_rss_flowkey_cfg_rsp) \ 239 M(NIX_SET_MAC_ADDR, 0x800a, nix_set_mac_addr, nix_set_mac_addr, msg_rsp) \ 240 M(NIX_SET_RX_MODE, 0x800b, nix_set_rx_mode, nix_rx_mode, msg_rsp) \ 241 M(NIX_SET_HW_FRS, 0x800c, nix_set_hw_frs, nix_frs_cfg, msg_rsp) \ 242 M(NIX_LF_START_RX, 0x800d, nix_lf_start_rx, msg_req, msg_rsp) \ 243 M(NIX_LF_STOP_RX, 0x800e, nix_lf_stop_rx, msg_req, msg_rsp) \ 244 M(NIX_MARK_FORMAT_CFG, 0x800f, nix_mark_format_cfg, \ 245 nix_mark_format_cfg, \ 246 nix_mark_format_cfg_rsp) \ 247 M(NIX_SET_RX_CFG, 0x8010, nix_set_rx_cfg, nix_rx_cfg, msg_rsp) \ 248 M(NIX_LSO_FORMAT_CFG, 0x8011, nix_lso_format_cfg, \ 249 nix_lso_format_cfg, \ 250 nix_lso_format_cfg_rsp) \ 251 M(NIX_LF_PTP_TX_ENABLE, 0x8013, nix_lf_ptp_tx_enable, msg_req, msg_rsp) \ 252 M(NIX_LF_PTP_TX_DISABLE, 0x8014, nix_lf_ptp_tx_disable, msg_req, msg_rsp) \ 253 M(NIX_BP_ENABLE, 0x8016, nix_bp_enable, nix_bp_cfg_req, \ 254 nix_bp_cfg_rsp) \ 255 M(NIX_BP_DISABLE, 0x8017, nix_bp_disable, nix_bp_cfg_req, msg_rsp) \ 256 M(NIX_GET_MAC_ADDR, 0x8018, nix_get_mac_addr, msg_req, nix_get_mac_addr_rsp) \ 257 M(NIX_CN10K_AQ_ENQ, 0x8019, nix_cn10k_aq_enq, nix_cn10k_aq_enq_req, \ 258 nix_cn10k_aq_enq_rsp) \ 259 M(NIX_GET_HW_INFO, 0x801a, nix_get_hw_info, msg_req, nix_hw_info) 260 261 /* Messages initiated by AF (range 0xC00 - 0xDFF) */ 262 #define MBOX_UP_CGX_MESSAGES \ 263 M(CGX_LINK_EVENT, 0xC00, cgx_link_event, cgx_link_info_msg, msg_rsp) 264 265 enum { 266 #define M(_name, _id, _1, _2, _3) MBOX_MSG_ ## _name = _id, 267 MBOX_MESSAGES 268 MBOX_UP_CGX_MESSAGES 269 #undef M 270 }; 271 272 /* Mailbox message formats */ 273 274 #define RVU_DEFAULT_PF_FUNC 0xFFFF 275 276 /* Generic request msg used for those mbox messages which 277 * don't send any data in the request. 278 */ 279 struct msg_req { 280 struct mbox_msghdr hdr; 281 }; 282 283 /* Generic response msg used an ack or response for those mbox 284 * messages which don't have a specific rsp msg format. 285 */ 286 struct msg_rsp { 287 struct mbox_msghdr hdr; 288 }; 289 290 /* RVU mailbox error codes 291 * Range 256 - 300. 292 */ 293 enum rvu_af_status { 294 RVU_INVALID_VF_ID = -256, 295 }; 296 297 struct ready_msg_rsp { 298 struct mbox_msghdr hdr; 299 u16 sclk_freq; /* SCLK frequency (in MHz) */ 300 u16 rclk_freq; /* RCLK frequency (in MHz) */ 301 }; 302 303 /* Structure for requesting resource provisioning. 304 * 'modify' flag to be used when either requesting more 305 * or to detach partial of a certain resource type. 306 * Rest of the fields specify how many of what type to 307 * be attached. 308 * To request LFs from two blocks of same type this mailbox 309 * can be sent twice as below: 310 * struct rsrc_attach *attach; 311 * .. Allocate memory for message .. 312 * attach->cptlfs = 3; <3 LFs from CPT0> 313 * .. Send message .. 314 * .. Allocate memory for message .. 315 * attach->modify = 1; 316 * attach->cpt_blkaddr = BLKADDR_CPT1; 317 * attach->cptlfs = 2; <2 LFs from CPT1> 318 * .. Send message .. 319 */ 320 struct rsrc_attach { 321 struct mbox_msghdr hdr; 322 u8 modify:1; 323 u8 npalf:1; 324 u8 nixlf:1; 325 u16 sso; 326 u16 ssow; 327 u16 timlfs; 328 u16 cptlfs; 329 int cpt_blkaddr; /* BLKADDR_CPT0/BLKADDR_CPT1 or 0 for BLKADDR_CPT0 */ 330 }; 331 332 /* Structure for relinquishing resources. 333 * 'partial' flag to be used when relinquishing all resources 334 * but only of a certain type. If not set, all resources of all 335 * types provisioned to the RVU function will be detached. 336 */ 337 struct rsrc_detach { 338 struct mbox_msghdr hdr; 339 u8 partial:1; 340 u8 npalf:1; 341 u8 nixlf:1; 342 u8 sso:1; 343 u8 ssow:1; 344 u8 timlfs:1; 345 u8 cptlfs:1; 346 }; 347 348 #define MSIX_VECTOR_INVALID 0xFFFF 349 #define MAX_RVU_BLKLF_CNT 256 350 351 struct msix_offset_rsp { 352 struct mbox_msghdr hdr; 353 u16 npa_msixoff; 354 u16 nix_msixoff; 355 u8 sso; 356 u8 ssow; 357 u8 timlfs; 358 u8 cptlfs; 359 u16 sso_msixoff[MAX_RVU_BLKLF_CNT]; 360 u16 ssow_msixoff[MAX_RVU_BLKLF_CNT]; 361 u16 timlf_msixoff[MAX_RVU_BLKLF_CNT]; 362 u16 cptlf_msixoff[MAX_RVU_BLKLF_CNT]; 363 u8 cpt1_lfs; 364 u16 cpt1_lf_msixoff[MAX_RVU_BLKLF_CNT]; 365 }; 366 367 struct get_hw_cap_rsp { 368 struct mbox_msghdr hdr; 369 u8 nix_fixed_txschq_mapping; /* Schq mapping fixed or flexible */ 370 u8 nix_shaping; /* Is shaping and coloring supported */ 371 }; 372 373 /* CGX mbox message formats */ 374 375 struct cgx_stats_rsp { 376 struct mbox_msghdr hdr; 377 #define CGX_RX_STATS_COUNT 9 378 #define CGX_TX_STATS_COUNT 18 379 u64 rx_stats[CGX_RX_STATS_COUNT]; 380 u64 tx_stats[CGX_TX_STATS_COUNT]; 381 }; 382 383 struct cgx_fec_stats_rsp { 384 struct mbox_msghdr hdr; 385 u64 fec_corr_blks; 386 u64 fec_uncorr_blks; 387 }; 388 /* Structure for requesting the operation for 389 * setting/getting mac address in the CGX interface 390 */ 391 struct cgx_mac_addr_set_or_get { 392 struct mbox_msghdr hdr; 393 u8 mac_addr[ETH_ALEN]; 394 }; 395 396 struct cgx_link_user_info { 397 uint64_t link_up:1; 398 uint64_t full_duplex:1; 399 uint64_t lmac_type_id:4; 400 uint64_t speed:20; /* speed in Mbps */ 401 uint64_t an:1; /* AN supported or not */ 402 uint64_t fec:2; /* FEC type if enabled else 0 */ 403 #define LMACTYPE_STR_LEN 16 404 char lmac_type[LMACTYPE_STR_LEN]; 405 }; 406 407 struct cgx_link_info_msg { 408 struct mbox_msghdr hdr; 409 struct cgx_link_user_info link_info; 410 }; 411 412 struct cgx_pause_frm_cfg { 413 struct mbox_msghdr hdr; 414 u8 set; 415 /* set = 1 if the request is to config pause frames */ 416 /* set = 0 if the request is to fetch pause frames config */ 417 u8 rx_pause; 418 u8 tx_pause; 419 }; 420 421 enum fec_type { 422 OTX2_FEC_NONE, 423 OTX2_FEC_BASER, 424 OTX2_FEC_RS, 425 OTX2_FEC_STATS_CNT = 2, 426 OTX2_FEC_OFF, 427 }; 428 429 struct fec_mode { 430 struct mbox_msghdr hdr; 431 int fec; 432 }; 433 434 struct sfp_eeprom_s { 435 #define SFP_EEPROM_SIZE 256 436 u16 sff_id; 437 u8 buf[SFP_EEPROM_SIZE]; 438 u64 reserved; 439 }; 440 441 struct phy_s { 442 struct { 443 u64 can_change_mod_type:1; 444 u64 mod_type:1; 445 u64 has_fec_stats:1; 446 } misc; 447 struct fec_stats_s { 448 u32 rsfec_corr_cws; 449 u32 rsfec_uncorr_cws; 450 u32 brfec_corr_blks; 451 u32 brfec_uncorr_blks; 452 } fec_stats; 453 }; 454 455 struct cgx_lmac_fwdata_s { 456 u16 rw_valid; 457 u64 supported_fec; 458 u64 supported_an; 459 u64 supported_link_modes; 460 /* only applicable if AN is supported */ 461 u64 advertised_fec; 462 u64 advertised_link_modes; 463 /* Only applicable if SFP/QSFP slot is present */ 464 struct sfp_eeprom_s sfp_eeprom; 465 struct phy_s phy; 466 #define LMAC_FWDATA_RESERVED_MEM 1021 467 u64 reserved[LMAC_FWDATA_RESERVED_MEM]; 468 }; 469 470 struct cgx_fw_data { 471 struct mbox_msghdr hdr; 472 struct cgx_lmac_fwdata_s fwdata; 473 }; 474 475 struct cgx_set_link_mode_args { 476 u32 speed; 477 u8 duplex; 478 u8 an; 479 u8 ports; 480 u64 mode; 481 }; 482 483 struct cgx_set_link_mode_req { 484 #define AUTONEG_UNKNOWN 0xff 485 struct mbox_msghdr hdr; 486 struct cgx_set_link_mode_args args; 487 }; 488 489 struct cgx_set_link_mode_rsp { 490 struct mbox_msghdr hdr; 491 int status; 492 }; 493 494 #define RVU_LMAC_FEAT_FC BIT_ULL(0) /* pause frames */ 495 #define RVU_LMAC_FEAT_PTP BIT_ULL(1) /* precision time protocol */ 496 #define RVU_MAC_VERSION BIT_ULL(2) 497 #define RVU_MAC_CGX BIT_ULL(3) 498 #define RVU_MAC_RPM BIT_ULL(4) 499 500 struct cgx_features_info_msg { 501 struct mbox_msghdr hdr; 502 u64 lmac_features; 503 }; 504 505 struct rpm_stats_rsp { 506 struct mbox_msghdr hdr; 507 #define RPM_RX_STATS_COUNT 43 508 #define RPM_TX_STATS_COUNT 34 509 u64 rx_stats[RPM_RX_STATS_COUNT]; 510 u64 tx_stats[RPM_TX_STATS_COUNT]; 511 }; 512 513 /* NPA mbox message formats */ 514 515 /* NPA mailbox error codes 516 * Range 301 - 400. 517 */ 518 enum npa_af_status { 519 NPA_AF_ERR_PARAM = -301, 520 NPA_AF_ERR_AQ_FULL = -302, 521 NPA_AF_ERR_AQ_ENQUEUE = -303, 522 NPA_AF_ERR_AF_LF_INVALID = -304, 523 NPA_AF_ERR_AF_LF_ALLOC = -305, 524 NPA_AF_ERR_LF_RESET = -306, 525 }; 526 527 /* For NPA LF context alloc and init */ 528 struct npa_lf_alloc_req { 529 struct mbox_msghdr hdr; 530 int node; 531 int aura_sz; /* No of auras */ 532 u32 nr_pools; /* No of pools */ 533 u64 way_mask; 534 }; 535 536 struct npa_lf_alloc_rsp { 537 struct mbox_msghdr hdr; 538 u32 stack_pg_ptrs; /* No of ptrs per stack page */ 539 u32 stack_pg_bytes; /* Size of stack page */ 540 u16 qints; /* NPA_AF_CONST::QINTS */ 541 }; 542 543 /* NPA AQ enqueue msg */ 544 struct npa_aq_enq_req { 545 struct mbox_msghdr hdr; 546 u32 aura_id; 547 u8 ctype; 548 u8 op; 549 union { 550 /* Valid when op == WRITE/INIT and ctype == AURA. 551 * LF fills the pool_id in aura.pool_addr. AF will translate 552 * the pool_id to pool context pointer. 553 */ 554 struct npa_aura_s aura; 555 /* Valid when op == WRITE/INIT and ctype == POOL */ 556 struct npa_pool_s pool; 557 }; 558 /* Mask data when op == WRITE (1=write, 0=don't write) */ 559 union { 560 /* Valid when op == WRITE and ctype == AURA */ 561 struct npa_aura_s aura_mask; 562 /* Valid when op == WRITE and ctype == POOL */ 563 struct npa_pool_s pool_mask; 564 }; 565 }; 566 567 struct npa_aq_enq_rsp { 568 struct mbox_msghdr hdr; 569 union { 570 /* Valid when op == READ and ctype == AURA */ 571 struct npa_aura_s aura; 572 /* Valid when op == READ and ctype == POOL */ 573 struct npa_pool_s pool; 574 }; 575 }; 576 577 /* Disable all contexts of type 'ctype' */ 578 struct hwctx_disable_req { 579 struct mbox_msghdr hdr; 580 u8 ctype; 581 }; 582 583 /* NIX mbox message formats */ 584 585 /* NIX mailbox error codes 586 * Range 401 - 500. 587 */ 588 enum nix_af_status { 589 NIX_AF_ERR_PARAM = -401, 590 NIX_AF_ERR_AQ_FULL = -402, 591 NIX_AF_ERR_AQ_ENQUEUE = -403, 592 NIX_AF_ERR_AF_LF_INVALID = -404, 593 NIX_AF_ERR_AF_LF_ALLOC = -405, 594 NIX_AF_ERR_TLX_ALLOC_FAIL = -406, 595 NIX_AF_ERR_TLX_INVALID = -407, 596 NIX_AF_ERR_RSS_SIZE_INVALID = -408, 597 NIX_AF_ERR_RSS_GRPS_INVALID = -409, 598 NIX_AF_ERR_FRS_INVALID = -410, 599 NIX_AF_ERR_RX_LINK_INVALID = -411, 600 NIX_AF_INVAL_TXSCHQ_CFG = -412, 601 NIX_AF_SMQ_FLUSH_FAILED = -413, 602 NIX_AF_ERR_LF_RESET = -414, 603 NIX_AF_ERR_RSS_NOSPC_FIELD = -415, 604 NIX_AF_ERR_RSS_NOSPC_ALGO = -416, 605 NIX_AF_ERR_MARK_CFG_FAIL = -417, 606 NIX_AF_ERR_LSO_CFG_FAIL = -418, 607 NIX_AF_INVAL_NPA_PF_FUNC = -419, 608 NIX_AF_INVAL_SSO_PF_FUNC = -420, 609 NIX_AF_ERR_TX_VTAG_NOSPC = -421, 610 NIX_AF_ERR_RX_VTAG_INUSE = -422, 611 NIX_AF_ERR_NPC_KEY_NOT_SUPP = -423, 612 }; 613 614 /* For NIX RX vtag action */ 615 enum nix_rx_vtag0_type { 616 NIX_AF_LFX_RX_VTAG_TYPE0, /* reserved for rx vlan offload */ 617 NIX_AF_LFX_RX_VTAG_TYPE1, 618 NIX_AF_LFX_RX_VTAG_TYPE2, 619 NIX_AF_LFX_RX_VTAG_TYPE3, 620 NIX_AF_LFX_RX_VTAG_TYPE4, 621 NIX_AF_LFX_RX_VTAG_TYPE5, 622 NIX_AF_LFX_RX_VTAG_TYPE6, 623 NIX_AF_LFX_RX_VTAG_TYPE7, 624 }; 625 626 /* For NIX LF context alloc and init */ 627 struct nix_lf_alloc_req { 628 struct mbox_msghdr hdr; 629 int node; 630 u32 rq_cnt; /* No of receive queues */ 631 u32 sq_cnt; /* No of send queues */ 632 u32 cq_cnt; /* No of completion queues */ 633 u8 xqe_sz; 634 u16 rss_sz; 635 u8 rss_grps; 636 u16 npa_func; 637 u16 sso_func; 638 u64 rx_cfg; /* See NIX_AF_LF(0..127)_RX_CFG */ 639 u64 way_mask; 640 }; 641 642 struct nix_lf_alloc_rsp { 643 struct mbox_msghdr hdr; 644 u16 sqb_size; 645 u16 rx_chan_base; 646 u16 tx_chan_base; 647 u8 rx_chan_cnt; /* total number of RX channels */ 648 u8 tx_chan_cnt; /* total number of TX channels */ 649 u8 lso_tsov4_idx; 650 u8 lso_tsov6_idx; 651 u8 mac_addr[ETH_ALEN]; 652 u8 lf_rx_stats; /* NIX_AF_CONST1::LF_RX_STATS */ 653 u8 lf_tx_stats; /* NIX_AF_CONST1::LF_TX_STATS */ 654 u16 cints; /* NIX_AF_CONST2::CINTS */ 655 u16 qints; /* NIX_AF_CONST2::QINTS */ 656 u8 cgx_links; /* No. of CGX links present in HW */ 657 u8 lbk_links; /* No. of LBK links present in HW */ 658 u8 sdp_links; /* No. of SDP links present in HW */ 659 }; 660 661 struct nix_lf_free_req { 662 struct mbox_msghdr hdr; 663 #define NIX_LF_DISABLE_FLOWS BIT_ULL(0) 664 #define NIX_LF_DONT_FREE_TX_VTAG BIT_ULL(1) 665 u64 flags; 666 }; 667 668 /* CN10K NIX AQ enqueue msg */ 669 struct nix_cn10k_aq_enq_req { 670 struct mbox_msghdr hdr; 671 u32 qidx; 672 u8 ctype; 673 u8 op; 674 union { 675 struct nix_cn10k_rq_ctx_s rq; 676 struct nix_cn10k_sq_ctx_s sq; 677 struct nix_cq_ctx_s cq; 678 struct nix_rsse_s rss; 679 struct nix_rx_mce_s mce; 680 }; 681 union { 682 struct nix_cn10k_rq_ctx_s rq_mask; 683 struct nix_cn10k_sq_ctx_s sq_mask; 684 struct nix_cq_ctx_s cq_mask; 685 struct nix_rsse_s rss_mask; 686 struct nix_rx_mce_s mce_mask; 687 }; 688 }; 689 690 struct nix_cn10k_aq_enq_rsp { 691 struct mbox_msghdr hdr; 692 union { 693 struct nix_cn10k_rq_ctx_s rq; 694 struct nix_cn10k_sq_ctx_s sq; 695 struct nix_cq_ctx_s cq; 696 struct nix_rsse_s rss; 697 struct nix_rx_mce_s mce; 698 }; 699 }; 700 701 /* NIX AQ enqueue msg */ 702 struct nix_aq_enq_req { 703 struct mbox_msghdr hdr; 704 u32 qidx; 705 u8 ctype; 706 u8 op; 707 union { 708 struct nix_rq_ctx_s rq; 709 struct nix_sq_ctx_s sq; 710 struct nix_cq_ctx_s cq; 711 struct nix_rsse_s rss; 712 struct nix_rx_mce_s mce; 713 }; 714 union { 715 struct nix_rq_ctx_s rq_mask; 716 struct nix_sq_ctx_s sq_mask; 717 struct nix_cq_ctx_s cq_mask; 718 struct nix_rsse_s rss_mask; 719 struct nix_rx_mce_s mce_mask; 720 }; 721 }; 722 723 struct nix_aq_enq_rsp { 724 struct mbox_msghdr hdr; 725 union { 726 struct nix_rq_ctx_s rq; 727 struct nix_sq_ctx_s sq; 728 struct nix_cq_ctx_s cq; 729 struct nix_rsse_s rss; 730 struct nix_rx_mce_s mce; 731 }; 732 }; 733 734 /* Tx scheduler/shaper mailbox messages */ 735 736 #define MAX_TXSCHQ_PER_FUNC 128 737 738 struct nix_txsch_alloc_req { 739 struct mbox_msghdr hdr; 740 /* Scheduler queue count request at each level */ 741 u16 schq_contig[NIX_TXSCH_LVL_CNT]; /* No of contiguous queues */ 742 u16 schq[NIX_TXSCH_LVL_CNT]; /* No of non-contiguous queues */ 743 }; 744 745 struct nix_txsch_alloc_rsp { 746 struct mbox_msghdr hdr; 747 /* Scheduler queue count allocated at each level */ 748 u16 schq_contig[NIX_TXSCH_LVL_CNT]; 749 u16 schq[NIX_TXSCH_LVL_CNT]; 750 /* Scheduler queue list allocated at each level */ 751 u16 schq_contig_list[NIX_TXSCH_LVL_CNT][MAX_TXSCHQ_PER_FUNC]; 752 u16 schq_list[NIX_TXSCH_LVL_CNT][MAX_TXSCHQ_PER_FUNC]; 753 u8 aggr_level; /* Traffic aggregation scheduler level */ 754 u8 aggr_lvl_rr_prio; /* Aggregation lvl's RR_PRIO config */ 755 u8 link_cfg_lvl; /* LINKX_CFG CSRs mapped to TL3 or TL2's index ? */ 756 }; 757 758 struct nix_txsch_free_req { 759 struct mbox_msghdr hdr; 760 #define TXSCHQ_FREE_ALL BIT_ULL(0) 761 u16 flags; 762 /* Scheduler queue level to be freed */ 763 u16 schq_lvl; 764 /* List of scheduler queues to be freed */ 765 u16 schq; 766 }; 767 768 struct nix_txschq_config { 769 struct mbox_msghdr hdr; 770 u8 lvl; /* SMQ/MDQ/TL4/TL3/TL2/TL1 */ 771 #define TXSCHQ_IDX_SHIFT 16 772 #define TXSCHQ_IDX_MASK (BIT_ULL(10) - 1) 773 #define TXSCHQ_IDX(reg, shift) (((reg) >> (shift)) & TXSCHQ_IDX_MASK) 774 u8 num_regs; 775 #define MAX_REGS_PER_MBOX_MSG 20 776 u64 reg[MAX_REGS_PER_MBOX_MSG]; 777 u64 regval[MAX_REGS_PER_MBOX_MSG]; 778 }; 779 780 struct nix_vtag_config { 781 struct mbox_msghdr hdr; 782 /* '0' for 4 octet VTAG, '1' for 8 octet VTAG */ 783 u8 vtag_size; 784 /* cfg_type is '0' for tx vlan cfg 785 * cfg_type is '1' for rx vlan cfg 786 */ 787 u8 cfg_type; 788 union { 789 /* valid when cfg_type is '0' */ 790 struct { 791 u64 vtag0; 792 u64 vtag1; 793 794 /* cfg_vtag0 & cfg_vtag1 fields are valid 795 * when free_vtag0 & free_vtag1 are '0's. 796 */ 797 /* cfg_vtag0 = 1 to configure vtag0 */ 798 u8 cfg_vtag0 :1; 799 /* cfg_vtag1 = 1 to configure vtag1 */ 800 u8 cfg_vtag1 :1; 801 802 /* vtag0_idx & vtag1_idx are only valid when 803 * both cfg_vtag0 & cfg_vtag1 are '0's, 804 * these fields are used along with free_vtag0 805 * & free_vtag1 to free the nix lf's tx_vlan 806 * configuration. 807 * 808 * Denotes the indices of tx_vtag def registers 809 * that needs to be cleared and freed. 810 */ 811 int vtag0_idx; 812 int vtag1_idx; 813 814 /* free_vtag0 & free_vtag1 fields are valid 815 * when cfg_vtag0 & cfg_vtag1 are '0's. 816 */ 817 /* free_vtag0 = 1 clears vtag0 configuration 818 * vtag0_idx denotes the index to be cleared. 819 */ 820 u8 free_vtag0 :1; 821 /* free_vtag1 = 1 clears vtag1 configuration 822 * vtag1_idx denotes the index to be cleared. 823 */ 824 u8 free_vtag1 :1; 825 } tx; 826 827 /* valid when cfg_type is '1' */ 828 struct { 829 /* rx vtag type index, valid values are in 0..7 range */ 830 u8 vtag_type; 831 /* rx vtag strip */ 832 u8 strip_vtag :1; 833 /* rx vtag capture */ 834 u8 capture_vtag :1; 835 } rx; 836 }; 837 }; 838 839 struct nix_vtag_config_rsp { 840 struct mbox_msghdr hdr; 841 int vtag0_idx; 842 int vtag1_idx; 843 /* Indices of tx_vtag def registers used to configure 844 * tx vtag0 & vtag1 headers, these indices are valid 845 * when nix_vtag_config mbox requested for vtag0 and/ 846 * or vtag1 configuration. 847 */ 848 }; 849 850 struct nix_rss_flowkey_cfg { 851 struct mbox_msghdr hdr; 852 int mcam_index; /* MCAM entry index to modify */ 853 #define NIX_FLOW_KEY_TYPE_PORT BIT(0) 854 #define NIX_FLOW_KEY_TYPE_IPV4 BIT(1) 855 #define NIX_FLOW_KEY_TYPE_IPV6 BIT(2) 856 #define NIX_FLOW_KEY_TYPE_TCP BIT(3) 857 #define NIX_FLOW_KEY_TYPE_UDP BIT(4) 858 #define NIX_FLOW_KEY_TYPE_SCTP BIT(5) 859 #define NIX_FLOW_KEY_TYPE_NVGRE BIT(6) 860 #define NIX_FLOW_KEY_TYPE_VXLAN BIT(7) 861 #define NIX_FLOW_KEY_TYPE_GENEVE BIT(8) 862 #define NIX_FLOW_KEY_TYPE_ETH_DMAC BIT(9) 863 #define NIX_FLOW_KEY_TYPE_IPV6_EXT BIT(10) 864 #define NIX_FLOW_KEY_TYPE_GTPU BIT(11) 865 #define NIX_FLOW_KEY_TYPE_INNR_IPV4 BIT(12) 866 #define NIX_FLOW_KEY_TYPE_INNR_IPV6 BIT(13) 867 #define NIX_FLOW_KEY_TYPE_INNR_TCP BIT(14) 868 #define NIX_FLOW_KEY_TYPE_INNR_UDP BIT(15) 869 #define NIX_FLOW_KEY_TYPE_INNR_SCTP BIT(16) 870 #define NIX_FLOW_KEY_TYPE_INNR_ETH_DMAC BIT(17) 871 #define NIX_FLOW_KEY_TYPE_VLAN BIT(20) 872 #define NIX_FLOW_KEY_TYPE_IPV4_PROTO BIT(21) 873 #define NIX_FLOW_KEY_TYPE_AH BIT(22) 874 #define NIX_FLOW_KEY_TYPE_ESP BIT(23) 875 u32 flowkey_cfg; /* Flowkey types selected */ 876 u8 group; /* RSS context or group */ 877 }; 878 879 struct nix_rss_flowkey_cfg_rsp { 880 struct mbox_msghdr hdr; 881 u8 alg_idx; /* Selected algo index */ 882 }; 883 884 struct nix_set_mac_addr { 885 struct mbox_msghdr hdr; 886 u8 mac_addr[ETH_ALEN]; /* MAC address to be set for this pcifunc */ 887 }; 888 889 struct nix_get_mac_addr_rsp { 890 struct mbox_msghdr hdr; 891 u8 mac_addr[ETH_ALEN]; 892 }; 893 894 struct nix_mark_format_cfg { 895 struct mbox_msghdr hdr; 896 u8 offset; 897 u8 y_mask; 898 u8 y_val; 899 u8 r_mask; 900 u8 r_val; 901 }; 902 903 struct nix_mark_format_cfg_rsp { 904 struct mbox_msghdr hdr; 905 u8 mark_format_idx; 906 }; 907 908 struct nix_rx_mode { 909 struct mbox_msghdr hdr; 910 #define NIX_RX_MODE_UCAST BIT(0) 911 #define NIX_RX_MODE_PROMISC BIT(1) 912 #define NIX_RX_MODE_ALLMULTI BIT(2) 913 u16 mode; 914 }; 915 916 struct nix_rx_cfg { 917 struct mbox_msghdr hdr; 918 #define NIX_RX_OL3_VERIFY BIT(0) 919 #define NIX_RX_OL4_VERIFY BIT(1) 920 u8 len_verify; /* Outer L3/L4 len check */ 921 #define NIX_RX_CSUM_OL4_VERIFY BIT(0) 922 u8 csum_verify; /* Outer L4 checksum verification */ 923 }; 924 925 struct nix_frs_cfg { 926 struct mbox_msghdr hdr; 927 u8 update_smq; /* Update SMQ's min/max lens */ 928 u8 update_minlen; /* Set minlen also */ 929 u8 sdp_link; /* Set SDP RX link */ 930 u16 maxlen; 931 u16 minlen; 932 }; 933 934 struct nix_lso_format_cfg { 935 struct mbox_msghdr hdr; 936 u64 field_mask; 937 #define NIX_LSO_FIELD_MAX 8 938 u64 fields[NIX_LSO_FIELD_MAX]; 939 }; 940 941 struct nix_lso_format_cfg_rsp { 942 struct mbox_msghdr hdr; 943 u8 lso_format_idx; 944 }; 945 946 struct nix_bp_cfg_req { 947 struct mbox_msghdr hdr; 948 u16 chan_base; /* Starting channel number */ 949 u8 chan_cnt; /* Number of channels */ 950 u8 bpid_per_chan; 951 /* bpid_per_chan = 0 assigns single bp id for range of channels */ 952 /* bpid_per_chan = 1 assigns separate bp id for each channel */ 953 }; 954 955 /* PF can be mapped to either CGX or LBK interface, 956 * so maximum 64 channels are possible. 957 */ 958 #define NIX_MAX_BPID_CHAN 64 959 struct nix_bp_cfg_rsp { 960 struct mbox_msghdr hdr; 961 u16 chan_bpid[NIX_MAX_BPID_CHAN]; /* Channel and bpid mapping */ 962 u8 chan_cnt; /* Number of channel for which bpids are assigned */ 963 }; 964 965 struct nix_hw_info { 966 struct mbox_msghdr hdr; 967 u16 max_mtu; 968 u16 min_mtu; 969 }; 970 971 /* NPC mbox message structs */ 972 973 #define NPC_MCAM_ENTRY_INVALID 0xFFFF 974 #define NPC_MCAM_INVALID_MAP 0xFFFF 975 976 /* NPC mailbox error codes 977 * Range 701 - 800. 978 */ 979 enum npc_af_status { 980 NPC_MCAM_INVALID_REQ = -701, 981 NPC_MCAM_ALLOC_DENIED = -702, 982 NPC_MCAM_ALLOC_FAILED = -703, 983 NPC_MCAM_PERM_DENIED = -704, 984 }; 985 986 struct npc_mcam_alloc_entry_req { 987 struct mbox_msghdr hdr; 988 #define NPC_MAX_NONCONTIG_ENTRIES 256 989 u8 contig; /* Contiguous entries ? */ 990 #define NPC_MCAM_ANY_PRIO 0 991 #define NPC_MCAM_LOWER_PRIO 1 992 #define NPC_MCAM_HIGHER_PRIO 2 993 u8 priority; /* Lower or higher w.r.t ref_entry */ 994 u16 ref_entry; 995 u16 count; /* Number of entries requested */ 996 }; 997 998 struct npc_mcam_alloc_entry_rsp { 999 struct mbox_msghdr hdr; 1000 u16 entry; /* Entry allocated or start index if contiguous. 1001 * Invalid incase of non-contiguous. 1002 */ 1003 u16 count; /* Number of entries allocated */ 1004 u16 free_count; /* Number of entries available */ 1005 u16 entry_list[NPC_MAX_NONCONTIG_ENTRIES]; 1006 }; 1007 1008 struct npc_mcam_free_entry_req { 1009 struct mbox_msghdr hdr; 1010 u16 entry; /* Entry index to be freed */ 1011 u8 all; /* If all entries allocated to this PFVF to be freed */ 1012 }; 1013 1014 struct mcam_entry { 1015 #define NPC_MAX_KWS_IN_KEY 7 /* Number of keywords in max keywidth */ 1016 u64 kw[NPC_MAX_KWS_IN_KEY]; 1017 u64 kw_mask[NPC_MAX_KWS_IN_KEY]; 1018 u64 action; 1019 u64 vtag_action; 1020 }; 1021 1022 struct npc_mcam_write_entry_req { 1023 struct mbox_msghdr hdr; 1024 struct mcam_entry entry_data; 1025 u16 entry; /* MCAM entry to write this match key */ 1026 u16 cntr; /* Counter for this MCAM entry */ 1027 u8 intf; /* Rx or Tx interface */ 1028 u8 enable_entry;/* Enable this MCAM entry ? */ 1029 u8 set_cntr; /* Set counter for this entry ? */ 1030 }; 1031 1032 /* Enable/Disable a given entry */ 1033 struct npc_mcam_ena_dis_entry_req { 1034 struct mbox_msghdr hdr; 1035 u16 entry; 1036 }; 1037 1038 struct npc_mcam_shift_entry_req { 1039 struct mbox_msghdr hdr; 1040 #define NPC_MCAM_MAX_SHIFTS 64 1041 u16 curr_entry[NPC_MCAM_MAX_SHIFTS]; 1042 u16 new_entry[NPC_MCAM_MAX_SHIFTS]; 1043 u16 shift_count; /* Number of entries to shift */ 1044 }; 1045 1046 struct npc_mcam_shift_entry_rsp { 1047 struct mbox_msghdr hdr; 1048 u16 failed_entry_idx; /* Index in 'curr_entry', not entry itself */ 1049 }; 1050 1051 struct npc_mcam_alloc_counter_req { 1052 struct mbox_msghdr hdr; 1053 u8 contig; /* Contiguous counters ? */ 1054 #define NPC_MAX_NONCONTIG_COUNTERS 64 1055 u16 count; /* Number of counters requested */ 1056 }; 1057 1058 struct npc_mcam_alloc_counter_rsp { 1059 struct mbox_msghdr hdr; 1060 u16 cntr; /* Counter allocated or start index if contiguous. 1061 * Invalid incase of non-contiguous. 1062 */ 1063 u16 count; /* Number of counters allocated */ 1064 u16 cntr_list[NPC_MAX_NONCONTIG_COUNTERS]; 1065 }; 1066 1067 struct npc_mcam_oper_counter_req { 1068 struct mbox_msghdr hdr; 1069 u16 cntr; /* Free a counter or clear/fetch it's stats */ 1070 }; 1071 1072 struct npc_mcam_oper_counter_rsp { 1073 struct mbox_msghdr hdr; 1074 u64 stat; /* valid only while fetching counter's stats */ 1075 }; 1076 1077 struct npc_mcam_unmap_counter_req { 1078 struct mbox_msghdr hdr; 1079 u16 cntr; 1080 u16 entry; /* Entry and counter to be unmapped */ 1081 u8 all; /* Unmap all entries using this counter ? */ 1082 }; 1083 1084 struct npc_mcam_alloc_and_write_entry_req { 1085 struct mbox_msghdr hdr; 1086 struct mcam_entry entry_data; 1087 u16 ref_entry; 1088 u8 priority; /* Lower or higher w.r.t ref_entry */ 1089 u8 intf; /* Rx or Tx interface */ 1090 u8 enable_entry;/* Enable this MCAM entry ? */ 1091 u8 alloc_cntr; /* Allocate counter and map ? */ 1092 }; 1093 1094 struct npc_mcam_alloc_and_write_entry_rsp { 1095 struct mbox_msghdr hdr; 1096 u16 entry; 1097 u16 cntr; 1098 }; 1099 1100 struct npc_get_kex_cfg_rsp { 1101 struct mbox_msghdr hdr; 1102 u64 rx_keyx_cfg; /* NPC_AF_INTF(0)_KEX_CFG */ 1103 u64 tx_keyx_cfg; /* NPC_AF_INTF(1)_KEX_CFG */ 1104 #define NPC_MAX_INTF 2 1105 #define NPC_MAX_LID 8 1106 #define NPC_MAX_LT 16 1107 #define NPC_MAX_LD 2 1108 #define NPC_MAX_LFL 16 1109 /* NPC_AF_KEX_LDATA(0..1)_FLAGS_CFG */ 1110 u64 kex_ld_flags[NPC_MAX_LD]; 1111 /* NPC_AF_INTF(0..1)_LID(0..7)_LT(0..15)_LD(0..1)_CFG */ 1112 u64 intf_lid_lt_ld[NPC_MAX_INTF][NPC_MAX_LID][NPC_MAX_LT][NPC_MAX_LD]; 1113 /* NPC_AF_INTF(0..1)_LDATA(0..1)_FLAGS(0..15)_CFG */ 1114 u64 intf_ld_flags[NPC_MAX_INTF][NPC_MAX_LD][NPC_MAX_LFL]; 1115 #define MKEX_NAME_LEN 128 1116 u8 mkex_pfl_name[MKEX_NAME_LEN]; 1117 }; 1118 1119 struct flow_msg { 1120 unsigned char dmac[6]; 1121 unsigned char smac[6]; 1122 __be16 etype; 1123 __be16 vlan_etype; 1124 __be16 vlan_tci; 1125 union { 1126 __be32 ip4src; 1127 __be32 ip6src[4]; 1128 }; 1129 union { 1130 __be32 ip4dst; 1131 __be32 ip6dst[4]; 1132 }; 1133 u8 tos; 1134 u8 ip_ver; 1135 u8 ip_proto; 1136 u8 tc; 1137 __be16 sport; 1138 __be16 dport; 1139 }; 1140 1141 struct npc_install_flow_req { 1142 struct mbox_msghdr hdr; 1143 struct flow_msg packet; 1144 struct flow_msg mask; 1145 u64 features; 1146 u16 entry; 1147 u16 channel; 1148 u16 chan_mask; 1149 u8 intf; 1150 u8 set_cntr; /* If counter is available set counter for this entry ? */ 1151 u8 default_rule; 1152 u8 append; /* overwrite(0) or append(1) flow to default rule? */ 1153 u16 vf; 1154 /* action */ 1155 u32 index; 1156 u16 match_id; 1157 u8 flow_key_alg; 1158 u8 op; 1159 /* vtag rx action */ 1160 u8 vtag0_type; 1161 u8 vtag0_valid; 1162 u8 vtag1_type; 1163 u8 vtag1_valid; 1164 /* vtag tx action */ 1165 u16 vtag0_def; 1166 u8 vtag0_op; 1167 u16 vtag1_def; 1168 u8 vtag1_op; 1169 }; 1170 1171 struct npc_install_flow_rsp { 1172 struct mbox_msghdr hdr; 1173 int counter; /* negative if no counter else counter number */ 1174 }; 1175 1176 struct npc_delete_flow_req { 1177 struct mbox_msghdr hdr; 1178 u16 entry; 1179 u16 start;/*Disable range of entries */ 1180 u16 end; 1181 u8 all; /* PF + VFs */ 1182 }; 1183 1184 struct npc_mcam_read_entry_req { 1185 struct mbox_msghdr hdr; 1186 u16 entry; /* MCAM entry to read */ 1187 }; 1188 1189 struct npc_mcam_read_entry_rsp { 1190 struct mbox_msghdr hdr; 1191 struct mcam_entry entry_data; 1192 u8 intf; 1193 u8 enable; 1194 }; 1195 1196 struct npc_mcam_read_base_rule_rsp { 1197 struct mbox_msghdr hdr; 1198 struct mcam_entry entry; 1199 }; 1200 1201 struct npc_mcam_get_stats_req { 1202 struct mbox_msghdr hdr; 1203 u16 entry; /* mcam entry */ 1204 }; 1205 1206 struct npc_mcam_get_stats_rsp { 1207 struct mbox_msghdr hdr; 1208 u64 stat; /* counter stats */ 1209 u8 stat_ena; /* enabled */ 1210 }; 1211 1212 enum ptp_op { 1213 PTP_OP_ADJFINE = 0, 1214 PTP_OP_GET_CLOCK = 1, 1215 }; 1216 1217 struct ptp_req { 1218 struct mbox_msghdr hdr; 1219 u8 op; 1220 s64 scaled_ppm; 1221 }; 1222 1223 struct ptp_rsp { 1224 struct mbox_msghdr hdr; 1225 u64 clk; 1226 }; 1227 1228 /* CPT mailbox error codes 1229 * Range 901 - 1000. 1230 */ 1231 enum cpt_af_status { 1232 CPT_AF_ERR_PARAM = -901, 1233 CPT_AF_ERR_GRP_INVALID = -902, 1234 CPT_AF_ERR_LF_INVALID = -903, 1235 CPT_AF_ERR_ACCESS_DENIED = -904, 1236 CPT_AF_ERR_SSO_PF_FUNC_INVALID = -905, 1237 CPT_AF_ERR_NIX_PF_FUNC_INVALID = -906 1238 }; 1239 1240 /* CPT mbox message formats */ 1241 struct cpt_rd_wr_reg_msg { 1242 struct mbox_msghdr hdr; 1243 u64 reg_offset; 1244 u64 *ret_val; 1245 u64 val; 1246 u8 is_write; 1247 int blkaddr; 1248 }; 1249 1250 struct cpt_lf_alloc_req_msg { 1251 struct mbox_msghdr hdr; 1252 u16 nix_pf_func; 1253 u16 sso_pf_func; 1254 u16 eng_grpmsk; 1255 int blkaddr; 1256 }; 1257 1258 #endif /* MBOX_H */ 1259