1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Marvell OcteonTx2 RVU Admin Function driver 3 * 4 * Copyright (C) 2018 Marvell International Ltd. 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 */ 10 11 #ifndef MBOX_H 12 #define MBOX_H 13 14 #include <linux/etherdevice.h> 15 #include <linux/sizes.h> 16 17 #include "rvu_struct.h" 18 #include "common.h" 19 20 #define MBOX_SIZE SZ_64K 21 22 /* AF/PF: PF initiated, PF/VF VF initiated */ 23 #define MBOX_DOWN_RX_START 0 24 #define MBOX_DOWN_RX_SIZE (46 * SZ_1K) 25 #define MBOX_DOWN_TX_START (MBOX_DOWN_RX_START + MBOX_DOWN_RX_SIZE) 26 #define MBOX_DOWN_TX_SIZE (16 * SZ_1K) 27 /* AF/PF: AF initiated, PF/VF PF initiated */ 28 #define MBOX_UP_RX_START (MBOX_DOWN_TX_START + MBOX_DOWN_TX_SIZE) 29 #define MBOX_UP_RX_SIZE SZ_1K 30 #define MBOX_UP_TX_START (MBOX_UP_RX_START + MBOX_UP_RX_SIZE) 31 #define MBOX_UP_TX_SIZE SZ_1K 32 33 #if MBOX_UP_TX_SIZE + MBOX_UP_TX_START != MBOX_SIZE 34 # error "incorrect mailbox area sizes" 35 #endif 36 37 #define INTR_MASK(pfvfs) ((pfvfs < 64) ? (BIT_ULL(pfvfs) - 1) : (~0ull)) 38 39 #define MBOX_RSP_TIMEOUT 2000 /* Time(ms) to wait for mbox response */ 40 41 #define MBOX_MSG_ALIGN 16 /* Align mbox msg start to 16bytes */ 42 43 /* Mailbox directions */ 44 #define MBOX_DIR_AFPF 0 /* AF replies to PF */ 45 #define MBOX_DIR_PFAF 1 /* PF sends messages to AF */ 46 #define MBOX_DIR_PFVF 2 /* PF replies to VF */ 47 #define MBOX_DIR_VFPF 3 /* VF sends messages to PF */ 48 #define MBOX_DIR_AFPF_UP 4 /* AF sends messages to PF */ 49 #define MBOX_DIR_PFAF_UP 5 /* PF replies to AF */ 50 #define MBOX_DIR_PFVF_UP 6 /* PF sends messages to VF */ 51 #define MBOX_DIR_VFPF_UP 7 /* VF replies to PF */ 52 53 struct otx2_mbox_dev { 54 void *mbase; /* This dev's mbox region */ 55 spinlock_t mbox_lock; 56 u16 msg_size; /* Total msg size to be sent */ 57 u16 rsp_size; /* Total rsp size to be sure the reply is ok */ 58 u16 num_msgs; /* No of msgs sent or waiting for response */ 59 u16 msgs_acked; /* No of msgs for which response is received */ 60 }; 61 62 struct otx2_mbox { 63 struct pci_dev *pdev; 64 void *hwbase; /* Mbox region advertised by HW */ 65 void *reg_base;/* CSR base for this dev */ 66 u64 trigger; /* Trigger mbox notification */ 67 u16 tr_shift; /* Mbox trigger shift */ 68 u64 rx_start; /* Offset of Rx region in mbox memory */ 69 u64 tx_start; /* Offset of Tx region in mbox memory */ 70 u16 rx_size; /* Size of Rx region */ 71 u16 tx_size; /* Size of Tx region */ 72 u16 ndevs; /* The number of peers */ 73 struct otx2_mbox_dev *dev; 74 }; 75 76 /* Header which preceeds all mbox messages */ 77 struct mbox_hdr { 78 u64 msg_size; /* Total msgs size embedded */ 79 u16 num_msgs; /* No of msgs embedded */ 80 }; 81 82 /* Header which preceeds every msg and is also part of it */ 83 struct mbox_msghdr { 84 u16 pcifunc; /* Who's sending this msg */ 85 u16 id; /* Mbox message ID */ 86 #define OTX2_MBOX_REQ_SIG (0xdead) 87 #define OTX2_MBOX_RSP_SIG (0xbeef) 88 u16 sig; /* Signature, for validating corrupted msgs */ 89 #define OTX2_MBOX_VERSION (0x0007) 90 u16 ver; /* Version of msg's structure for this ID */ 91 u16 next_msgoff; /* Offset of next msg within mailbox region */ 92 int rc; /* Msg process'ed response code */ 93 }; 94 95 void otx2_mbox_reset(struct otx2_mbox *mbox, int devid); 96 void __otx2_mbox_reset(struct otx2_mbox *mbox, int devid); 97 void otx2_mbox_destroy(struct otx2_mbox *mbox); 98 int otx2_mbox_init(struct otx2_mbox *mbox, void __force *hwbase, 99 struct pci_dev *pdev, void __force *reg_base, 100 int direction, int ndevs); 101 void otx2_mbox_msg_send(struct otx2_mbox *mbox, int devid); 102 int otx2_mbox_wait_for_rsp(struct otx2_mbox *mbox, int devid); 103 int otx2_mbox_busy_poll_for_rsp(struct otx2_mbox *mbox, int devid); 104 struct mbox_msghdr *otx2_mbox_alloc_msg_rsp(struct otx2_mbox *mbox, int devid, 105 int size, int size_rsp); 106 struct mbox_msghdr *otx2_mbox_get_rsp(struct otx2_mbox *mbox, int devid, 107 struct mbox_msghdr *msg); 108 int otx2_mbox_check_rsp_msgs(struct otx2_mbox *mbox, int devid); 109 int otx2_reply_invalid_msg(struct otx2_mbox *mbox, int devid, 110 u16 pcifunc, u16 id); 111 bool otx2_mbox_nonempty(struct otx2_mbox *mbox, int devid); 112 const char *otx2_mbox_id2name(u16 id); 113 static inline struct mbox_msghdr *otx2_mbox_alloc_msg(struct otx2_mbox *mbox, 114 int devid, int size) 115 { 116 return otx2_mbox_alloc_msg_rsp(mbox, devid, size, 0); 117 } 118 119 /* Mailbox message types */ 120 #define MBOX_MSG_MASK 0xFFFF 121 #define MBOX_MSG_INVALID 0xFFFE 122 #define MBOX_MSG_MAX 0xFFFF 123 124 #define MBOX_MESSAGES \ 125 /* Generic mbox IDs (range 0x000 - 0x1FF) */ \ 126 M(READY, 0x001, ready, msg_req, ready_msg_rsp) \ 127 M(ATTACH_RESOURCES, 0x002, attach_resources, rsrc_attach, msg_rsp) \ 128 M(DETACH_RESOURCES, 0x003, detach_resources, rsrc_detach, msg_rsp) \ 129 M(MSIX_OFFSET, 0x005, msix_offset, msg_req, msix_offset_rsp) \ 130 M(VF_FLR, 0x006, vf_flr, msg_req, msg_rsp) \ 131 M(PTP_OP, 0x007, ptp_op, ptp_req, ptp_rsp) \ 132 M(GET_HW_CAP, 0x008, get_hw_cap, msg_req, get_hw_cap_rsp) \ 133 /* CGX mbox IDs (range 0x200 - 0x3FF) */ \ 134 M(CGX_START_RXTX, 0x200, cgx_start_rxtx, msg_req, msg_rsp) \ 135 M(CGX_STOP_RXTX, 0x201, cgx_stop_rxtx, msg_req, msg_rsp) \ 136 M(CGX_STATS, 0x202, cgx_stats, msg_req, cgx_stats_rsp) \ 137 M(CGX_MAC_ADDR_SET, 0x203, cgx_mac_addr_set, cgx_mac_addr_set_or_get, \ 138 cgx_mac_addr_set_or_get) \ 139 M(CGX_MAC_ADDR_GET, 0x204, cgx_mac_addr_get, cgx_mac_addr_set_or_get, \ 140 cgx_mac_addr_set_or_get) \ 141 M(CGX_PROMISC_ENABLE, 0x205, cgx_promisc_enable, msg_req, msg_rsp) \ 142 M(CGX_PROMISC_DISABLE, 0x206, cgx_promisc_disable, msg_req, msg_rsp) \ 143 M(CGX_START_LINKEVENTS, 0x207, cgx_start_linkevents, msg_req, msg_rsp) \ 144 M(CGX_STOP_LINKEVENTS, 0x208, cgx_stop_linkevents, msg_req, msg_rsp) \ 145 M(CGX_GET_LINKINFO, 0x209, cgx_get_linkinfo, msg_req, cgx_link_info_msg) \ 146 M(CGX_INTLBK_ENABLE, 0x20A, cgx_intlbk_enable, msg_req, msg_rsp) \ 147 M(CGX_INTLBK_DISABLE, 0x20B, cgx_intlbk_disable, msg_req, msg_rsp) \ 148 M(CGX_PTP_RX_ENABLE, 0x20C, cgx_ptp_rx_enable, msg_req, msg_rsp) \ 149 M(CGX_PTP_RX_DISABLE, 0x20D, cgx_ptp_rx_disable, msg_req, msg_rsp) \ 150 M(CGX_CFG_PAUSE_FRM, 0x20E, cgx_cfg_pause_frm, cgx_pause_frm_cfg, \ 151 cgx_pause_frm_cfg) \ 152 /* NPA mbox IDs (range 0x400 - 0x5FF) */ \ 153 M(NPA_LF_ALLOC, 0x400, npa_lf_alloc, \ 154 npa_lf_alloc_req, npa_lf_alloc_rsp) \ 155 M(NPA_LF_FREE, 0x401, npa_lf_free, msg_req, msg_rsp) \ 156 M(NPA_AQ_ENQ, 0x402, npa_aq_enq, npa_aq_enq_req, npa_aq_enq_rsp) \ 157 M(NPA_HWCTX_DISABLE, 0x403, npa_hwctx_disable, hwctx_disable_req, msg_rsp)\ 158 /* SSO/SSOW mbox IDs (range 0x600 - 0x7FF) */ \ 159 /* TIM mbox IDs (range 0x800 - 0x9FF) */ \ 160 /* CPT mbox IDs (range 0xA00 - 0xBFF) */ \ 161 M(CPT_LF_ALLOC, 0xA00, cpt_lf_alloc, cpt_lf_alloc_req_msg, \ 162 msg_rsp) \ 163 M(CPT_LF_FREE, 0xA01, cpt_lf_free, msg_req, msg_rsp) \ 164 M(CPT_RD_WR_REGISTER, 0xA02, cpt_rd_wr_register, cpt_rd_wr_reg_msg, \ 165 cpt_rd_wr_reg_msg) \ 166 /* NPC mbox IDs (range 0x6000 - 0x7FFF) */ \ 167 M(NPC_MCAM_ALLOC_ENTRY, 0x6000, npc_mcam_alloc_entry, npc_mcam_alloc_entry_req,\ 168 npc_mcam_alloc_entry_rsp) \ 169 M(NPC_MCAM_FREE_ENTRY, 0x6001, npc_mcam_free_entry, \ 170 npc_mcam_free_entry_req, msg_rsp) \ 171 M(NPC_MCAM_WRITE_ENTRY, 0x6002, npc_mcam_write_entry, \ 172 npc_mcam_write_entry_req, msg_rsp) \ 173 M(NPC_MCAM_ENA_ENTRY, 0x6003, npc_mcam_ena_entry, \ 174 npc_mcam_ena_dis_entry_req, msg_rsp) \ 175 M(NPC_MCAM_DIS_ENTRY, 0x6004, npc_mcam_dis_entry, \ 176 npc_mcam_ena_dis_entry_req, msg_rsp) \ 177 M(NPC_MCAM_SHIFT_ENTRY, 0x6005, npc_mcam_shift_entry, npc_mcam_shift_entry_req,\ 178 npc_mcam_shift_entry_rsp) \ 179 M(NPC_MCAM_ALLOC_COUNTER, 0x6006, npc_mcam_alloc_counter, \ 180 npc_mcam_alloc_counter_req, \ 181 npc_mcam_alloc_counter_rsp) \ 182 M(NPC_MCAM_FREE_COUNTER, 0x6007, npc_mcam_free_counter, \ 183 npc_mcam_oper_counter_req, msg_rsp) \ 184 M(NPC_MCAM_UNMAP_COUNTER, 0x6008, npc_mcam_unmap_counter, \ 185 npc_mcam_unmap_counter_req, msg_rsp) \ 186 M(NPC_MCAM_CLEAR_COUNTER, 0x6009, npc_mcam_clear_counter, \ 187 npc_mcam_oper_counter_req, msg_rsp) \ 188 M(NPC_MCAM_COUNTER_STATS, 0x600a, npc_mcam_counter_stats, \ 189 npc_mcam_oper_counter_req, \ 190 npc_mcam_oper_counter_rsp) \ 191 M(NPC_MCAM_ALLOC_AND_WRITE_ENTRY, 0x600b, npc_mcam_alloc_and_write_entry, \ 192 npc_mcam_alloc_and_write_entry_req, \ 193 npc_mcam_alloc_and_write_entry_rsp) \ 194 M(NPC_GET_KEX_CFG, 0x600c, npc_get_kex_cfg, \ 195 msg_req, npc_get_kex_cfg_rsp) \ 196 M(NPC_INSTALL_FLOW, 0x600d, npc_install_flow, \ 197 npc_install_flow_req, npc_install_flow_rsp) \ 198 M(NPC_DELETE_FLOW, 0x600e, npc_delete_flow, \ 199 npc_delete_flow_req, msg_rsp) \ 200 M(NPC_MCAM_READ_ENTRY, 0x600f, npc_mcam_read_entry, \ 201 npc_mcam_read_entry_req, \ 202 npc_mcam_read_entry_rsp) \ 203 M(NPC_MCAM_READ_BASE_RULE, 0x6011, npc_read_base_steer_rule, \ 204 msg_req, npc_mcam_read_base_rule_rsp) \ 205 /* NIX mbox IDs (range 0x8000 - 0xFFFF) */ \ 206 M(NIX_LF_ALLOC, 0x8000, nix_lf_alloc, \ 207 nix_lf_alloc_req, nix_lf_alloc_rsp) \ 208 M(NIX_LF_FREE, 0x8001, nix_lf_free, nix_lf_free_req, msg_rsp) \ 209 M(NIX_AQ_ENQ, 0x8002, nix_aq_enq, nix_aq_enq_req, nix_aq_enq_rsp) \ 210 M(NIX_HWCTX_DISABLE, 0x8003, nix_hwctx_disable, \ 211 hwctx_disable_req, msg_rsp) \ 212 M(NIX_TXSCH_ALLOC, 0x8004, nix_txsch_alloc, \ 213 nix_txsch_alloc_req, nix_txsch_alloc_rsp) \ 214 M(NIX_TXSCH_FREE, 0x8005, nix_txsch_free, nix_txsch_free_req, msg_rsp) \ 215 M(NIX_TXSCHQ_CFG, 0x8006, nix_txschq_cfg, nix_txschq_config, msg_rsp) \ 216 M(NIX_STATS_RST, 0x8007, nix_stats_rst, msg_req, msg_rsp) \ 217 M(NIX_VTAG_CFG, 0x8008, nix_vtag_cfg, nix_vtag_config, \ 218 nix_vtag_config_rsp) \ 219 M(NIX_RSS_FLOWKEY_CFG, 0x8009, nix_rss_flowkey_cfg, \ 220 nix_rss_flowkey_cfg, \ 221 nix_rss_flowkey_cfg_rsp) \ 222 M(NIX_SET_MAC_ADDR, 0x800a, nix_set_mac_addr, nix_set_mac_addr, msg_rsp) \ 223 M(NIX_SET_RX_MODE, 0x800b, nix_set_rx_mode, nix_rx_mode, msg_rsp) \ 224 M(NIX_SET_HW_FRS, 0x800c, nix_set_hw_frs, nix_frs_cfg, msg_rsp) \ 225 M(NIX_LF_START_RX, 0x800d, nix_lf_start_rx, msg_req, msg_rsp) \ 226 M(NIX_LF_STOP_RX, 0x800e, nix_lf_stop_rx, msg_req, msg_rsp) \ 227 M(NIX_MARK_FORMAT_CFG, 0x800f, nix_mark_format_cfg, \ 228 nix_mark_format_cfg, \ 229 nix_mark_format_cfg_rsp) \ 230 M(NIX_SET_RX_CFG, 0x8010, nix_set_rx_cfg, nix_rx_cfg, msg_rsp) \ 231 M(NIX_LSO_FORMAT_CFG, 0x8011, nix_lso_format_cfg, \ 232 nix_lso_format_cfg, \ 233 nix_lso_format_cfg_rsp) \ 234 M(NIX_LF_PTP_TX_ENABLE, 0x8013, nix_lf_ptp_tx_enable, msg_req, msg_rsp) \ 235 M(NIX_LF_PTP_TX_DISABLE, 0x8014, nix_lf_ptp_tx_disable, msg_req, msg_rsp) \ 236 M(NIX_BP_ENABLE, 0x8016, nix_bp_enable, nix_bp_cfg_req, \ 237 nix_bp_cfg_rsp) \ 238 M(NIX_BP_DISABLE, 0x8017, nix_bp_disable, nix_bp_cfg_req, msg_rsp) \ 239 M(NIX_GET_MAC_ADDR, 0x8018, nix_get_mac_addr, msg_req, nix_get_mac_addr_rsp) \ 240 241 /* Messages initiated by AF (range 0xC00 - 0xDFF) */ 242 #define MBOX_UP_CGX_MESSAGES \ 243 M(CGX_LINK_EVENT, 0xC00, cgx_link_event, cgx_link_info_msg, msg_rsp) 244 245 enum { 246 #define M(_name, _id, _1, _2, _3) MBOX_MSG_ ## _name = _id, 247 MBOX_MESSAGES 248 MBOX_UP_CGX_MESSAGES 249 #undef M 250 }; 251 252 /* Mailbox message formats */ 253 254 #define RVU_DEFAULT_PF_FUNC 0xFFFF 255 256 /* Generic request msg used for those mbox messages which 257 * don't send any data in the request. 258 */ 259 struct msg_req { 260 struct mbox_msghdr hdr; 261 }; 262 263 /* Generic rsponse msg used a ack or response for those mbox 264 * messages which doesn't have a specific rsp msg format. 265 */ 266 struct msg_rsp { 267 struct mbox_msghdr hdr; 268 }; 269 270 /* RVU mailbox error codes 271 * Range 256 - 300. 272 */ 273 enum rvu_af_status { 274 RVU_INVALID_VF_ID = -256, 275 }; 276 277 struct ready_msg_rsp { 278 struct mbox_msghdr hdr; 279 u16 sclk_freq; /* SCLK frequency (in MHz) */ 280 u16 rclk_freq; /* RCLK frequency (in MHz) */ 281 }; 282 283 /* Structure for requesting resource provisioning. 284 * 'modify' flag to be used when either requesting more 285 * or to detach partial of a cetain resource type. 286 * Rest of the fields specify how many of what type to 287 * be attached. 288 * To request LFs from two blocks of same type this mailbox 289 * can be sent twice as below: 290 * struct rsrc_attach *attach; 291 * .. Allocate memory for message .. 292 * attach->cptlfs = 3; <3 LFs from CPT0> 293 * .. Send message .. 294 * .. Allocate memory for message .. 295 * attach->modify = 1; 296 * attach->cpt_blkaddr = BLKADDR_CPT1; 297 * attach->cptlfs = 2; <2 LFs from CPT1> 298 * .. Send message .. 299 */ 300 struct rsrc_attach { 301 struct mbox_msghdr hdr; 302 u8 modify:1; 303 u8 npalf:1; 304 u8 nixlf:1; 305 u16 sso; 306 u16 ssow; 307 u16 timlfs; 308 u16 cptlfs; 309 int cpt_blkaddr; /* BLKADDR_CPT0/BLKADDR_CPT1 or 0 for BLKADDR_CPT0 */ 310 }; 311 312 /* Structure for relinquishing resources. 313 * 'partial' flag to be used when relinquishing all resources 314 * but only of a certain type. If not set, all resources of all 315 * types provisioned to the RVU function will be detached. 316 */ 317 struct rsrc_detach { 318 struct mbox_msghdr hdr; 319 u8 partial:1; 320 u8 npalf:1; 321 u8 nixlf:1; 322 u8 sso:1; 323 u8 ssow:1; 324 u8 timlfs:1; 325 u8 cptlfs:1; 326 }; 327 328 #define MSIX_VECTOR_INVALID 0xFFFF 329 #define MAX_RVU_BLKLF_CNT 256 330 331 struct msix_offset_rsp { 332 struct mbox_msghdr hdr; 333 u16 npa_msixoff; 334 u16 nix_msixoff; 335 u8 sso; 336 u8 ssow; 337 u8 timlfs; 338 u8 cptlfs; 339 u16 sso_msixoff[MAX_RVU_BLKLF_CNT]; 340 u16 ssow_msixoff[MAX_RVU_BLKLF_CNT]; 341 u16 timlf_msixoff[MAX_RVU_BLKLF_CNT]; 342 u16 cptlf_msixoff[MAX_RVU_BLKLF_CNT]; 343 u8 cpt1_lfs; 344 u16 cpt1_lf_msixoff[MAX_RVU_BLKLF_CNT]; 345 }; 346 347 struct get_hw_cap_rsp { 348 struct mbox_msghdr hdr; 349 u8 nix_fixed_txschq_mapping; /* Schq mapping fixed or flexible */ 350 u8 nix_shaping; /* Is shaping and coloring supported */ 351 }; 352 353 /* CGX mbox message formats */ 354 355 struct cgx_stats_rsp { 356 struct mbox_msghdr hdr; 357 #define CGX_RX_STATS_COUNT 13 358 #define CGX_TX_STATS_COUNT 18 359 u64 rx_stats[CGX_RX_STATS_COUNT]; 360 u64 tx_stats[CGX_TX_STATS_COUNT]; 361 }; 362 363 /* Structure for requesting the operation for 364 * setting/getting mac address in the CGX interface 365 */ 366 struct cgx_mac_addr_set_or_get { 367 struct mbox_msghdr hdr; 368 u8 mac_addr[ETH_ALEN]; 369 }; 370 371 struct cgx_link_user_info { 372 uint64_t link_up:1; 373 uint64_t full_duplex:1; 374 uint64_t lmac_type_id:4; 375 uint64_t speed:20; /* speed in Mbps */ 376 #define LMACTYPE_STR_LEN 16 377 char lmac_type[LMACTYPE_STR_LEN]; 378 }; 379 380 struct cgx_link_info_msg { 381 struct mbox_msghdr hdr; 382 struct cgx_link_user_info link_info; 383 }; 384 385 struct cgx_pause_frm_cfg { 386 struct mbox_msghdr hdr; 387 u8 set; 388 /* set = 1 if the request is to config pause frames */ 389 /* set = 0 if the request is to fetch pause frames config */ 390 u8 rx_pause; 391 u8 tx_pause; 392 }; 393 394 /* NPA mbox message formats */ 395 396 /* NPA mailbox error codes 397 * Range 301 - 400. 398 */ 399 enum npa_af_status { 400 NPA_AF_ERR_PARAM = -301, 401 NPA_AF_ERR_AQ_FULL = -302, 402 NPA_AF_ERR_AQ_ENQUEUE = -303, 403 NPA_AF_ERR_AF_LF_INVALID = -304, 404 NPA_AF_ERR_AF_LF_ALLOC = -305, 405 NPA_AF_ERR_LF_RESET = -306, 406 }; 407 408 /* For NPA LF context alloc and init */ 409 struct npa_lf_alloc_req { 410 struct mbox_msghdr hdr; 411 int node; 412 int aura_sz; /* No of auras */ 413 u32 nr_pools; /* No of pools */ 414 u64 way_mask; 415 }; 416 417 struct npa_lf_alloc_rsp { 418 struct mbox_msghdr hdr; 419 u32 stack_pg_ptrs; /* No of ptrs per stack page */ 420 u32 stack_pg_bytes; /* Size of stack page */ 421 u16 qints; /* NPA_AF_CONST::QINTS */ 422 }; 423 424 /* NPA AQ enqueue msg */ 425 struct npa_aq_enq_req { 426 struct mbox_msghdr hdr; 427 u32 aura_id; 428 u8 ctype; 429 u8 op; 430 union { 431 /* Valid when op == WRITE/INIT and ctype == AURA. 432 * LF fills the pool_id in aura.pool_addr. AF will translate 433 * the pool_id to pool context pointer. 434 */ 435 struct npa_aura_s aura; 436 /* Valid when op == WRITE/INIT and ctype == POOL */ 437 struct npa_pool_s pool; 438 }; 439 /* Mask data when op == WRITE (1=write, 0=don't write) */ 440 union { 441 /* Valid when op == WRITE and ctype == AURA */ 442 struct npa_aura_s aura_mask; 443 /* Valid when op == WRITE and ctype == POOL */ 444 struct npa_pool_s pool_mask; 445 }; 446 }; 447 448 struct npa_aq_enq_rsp { 449 struct mbox_msghdr hdr; 450 union { 451 /* Valid when op == READ and ctype == AURA */ 452 struct npa_aura_s aura; 453 /* Valid when op == READ and ctype == POOL */ 454 struct npa_pool_s pool; 455 }; 456 }; 457 458 /* Disable all contexts of type 'ctype' */ 459 struct hwctx_disable_req { 460 struct mbox_msghdr hdr; 461 u8 ctype; 462 }; 463 464 /* NIX mbox message formats */ 465 466 /* NIX mailbox error codes 467 * Range 401 - 500. 468 */ 469 enum nix_af_status { 470 NIX_AF_ERR_PARAM = -401, 471 NIX_AF_ERR_AQ_FULL = -402, 472 NIX_AF_ERR_AQ_ENQUEUE = -403, 473 NIX_AF_ERR_AF_LF_INVALID = -404, 474 NIX_AF_ERR_AF_LF_ALLOC = -405, 475 NIX_AF_ERR_TLX_ALLOC_FAIL = -406, 476 NIX_AF_ERR_TLX_INVALID = -407, 477 NIX_AF_ERR_RSS_SIZE_INVALID = -408, 478 NIX_AF_ERR_RSS_GRPS_INVALID = -409, 479 NIX_AF_ERR_FRS_INVALID = -410, 480 NIX_AF_ERR_RX_LINK_INVALID = -411, 481 NIX_AF_INVAL_TXSCHQ_CFG = -412, 482 NIX_AF_SMQ_FLUSH_FAILED = -413, 483 NIX_AF_ERR_LF_RESET = -414, 484 NIX_AF_ERR_RSS_NOSPC_FIELD = -415, 485 NIX_AF_ERR_RSS_NOSPC_ALGO = -416, 486 NIX_AF_ERR_MARK_CFG_FAIL = -417, 487 NIX_AF_ERR_LSO_CFG_FAIL = -418, 488 NIX_AF_INVAL_NPA_PF_FUNC = -419, 489 NIX_AF_INVAL_SSO_PF_FUNC = -420, 490 NIX_AF_ERR_TX_VTAG_NOSPC = -421, 491 NIX_AF_ERR_RX_VTAG_INUSE = -422, 492 }; 493 494 /* For NIX RX vtag action */ 495 enum nix_rx_vtag0_type { 496 NIX_AF_LFX_RX_VTAG_TYPE0, /* reserved for rx vlan offload */ 497 NIX_AF_LFX_RX_VTAG_TYPE1, 498 NIX_AF_LFX_RX_VTAG_TYPE2, 499 NIX_AF_LFX_RX_VTAG_TYPE3, 500 NIX_AF_LFX_RX_VTAG_TYPE4, 501 NIX_AF_LFX_RX_VTAG_TYPE5, 502 NIX_AF_LFX_RX_VTAG_TYPE6, 503 NIX_AF_LFX_RX_VTAG_TYPE7, 504 }; 505 506 /* For NIX LF context alloc and init */ 507 struct nix_lf_alloc_req { 508 struct mbox_msghdr hdr; 509 int node; 510 u32 rq_cnt; /* No of receive queues */ 511 u32 sq_cnt; /* No of send queues */ 512 u32 cq_cnt; /* No of completion queues */ 513 u8 xqe_sz; 514 u16 rss_sz; 515 u8 rss_grps; 516 u16 npa_func; 517 u16 sso_func; 518 u64 rx_cfg; /* See NIX_AF_LF(0..127)_RX_CFG */ 519 u64 way_mask; 520 }; 521 522 struct nix_lf_alloc_rsp { 523 struct mbox_msghdr hdr; 524 u16 sqb_size; 525 u16 rx_chan_base; 526 u16 tx_chan_base; 527 u8 rx_chan_cnt; /* total number of RX channels */ 528 u8 tx_chan_cnt; /* total number of TX channels */ 529 u8 lso_tsov4_idx; 530 u8 lso_tsov6_idx; 531 u8 mac_addr[ETH_ALEN]; 532 u8 lf_rx_stats; /* NIX_AF_CONST1::LF_RX_STATS */ 533 u8 lf_tx_stats; /* NIX_AF_CONST1::LF_TX_STATS */ 534 u16 cints; /* NIX_AF_CONST2::CINTS */ 535 u16 qints; /* NIX_AF_CONST2::QINTS */ 536 u8 cgx_links; /* No. of CGX links present in HW */ 537 u8 lbk_links; /* No. of LBK links present in HW */ 538 u8 sdp_links; /* No. of SDP links present in HW */ 539 }; 540 541 struct nix_lf_free_req { 542 struct mbox_msghdr hdr; 543 #define NIX_LF_DISABLE_FLOWS BIT_ULL(0) 544 #define NIX_LF_DONT_FREE_TX_VTAG BIT_ULL(1) 545 u64 flags; 546 }; 547 548 /* NIX AQ enqueue msg */ 549 struct nix_aq_enq_req { 550 struct mbox_msghdr hdr; 551 u32 qidx; 552 u8 ctype; 553 u8 op; 554 union { 555 struct nix_rq_ctx_s rq; 556 struct nix_sq_ctx_s sq; 557 struct nix_cq_ctx_s cq; 558 struct nix_rsse_s rss; 559 struct nix_rx_mce_s mce; 560 }; 561 union { 562 struct nix_rq_ctx_s rq_mask; 563 struct nix_sq_ctx_s sq_mask; 564 struct nix_cq_ctx_s cq_mask; 565 struct nix_rsse_s rss_mask; 566 struct nix_rx_mce_s mce_mask; 567 }; 568 }; 569 570 struct nix_aq_enq_rsp { 571 struct mbox_msghdr hdr; 572 union { 573 struct nix_rq_ctx_s rq; 574 struct nix_sq_ctx_s sq; 575 struct nix_cq_ctx_s cq; 576 struct nix_rsse_s rss; 577 struct nix_rx_mce_s mce; 578 }; 579 }; 580 581 /* Tx scheduler/shaper mailbox messages */ 582 583 #define MAX_TXSCHQ_PER_FUNC 128 584 585 struct nix_txsch_alloc_req { 586 struct mbox_msghdr hdr; 587 /* Scheduler queue count request at each level */ 588 u16 schq_contig[NIX_TXSCH_LVL_CNT]; /* No of contiguous queues */ 589 u16 schq[NIX_TXSCH_LVL_CNT]; /* No of non-contiguous queues */ 590 }; 591 592 struct nix_txsch_alloc_rsp { 593 struct mbox_msghdr hdr; 594 /* Scheduler queue count allocated at each level */ 595 u16 schq_contig[NIX_TXSCH_LVL_CNT]; 596 u16 schq[NIX_TXSCH_LVL_CNT]; 597 /* Scheduler queue list allocated at each level */ 598 u16 schq_contig_list[NIX_TXSCH_LVL_CNT][MAX_TXSCHQ_PER_FUNC]; 599 u16 schq_list[NIX_TXSCH_LVL_CNT][MAX_TXSCHQ_PER_FUNC]; 600 u8 aggr_level; /* Traffic aggregation scheduler level */ 601 u8 aggr_lvl_rr_prio; /* Aggregation lvl's RR_PRIO config */ 602 u8 link_cfg_lvl; /* LINKX_CFG CSRs mapped to TL3 or TL2's index ? */ 603 }; 604 605 struct nix_txsch_free_req { 606 struct mbox_msghdr hdr; 607 #define TXSCHQ_FREE_ALL BIT_ULL(0) 608 u16 flags; 609 /* Scheduler queue level to be freed */ 610 u16 schq_lvl; 611 /* List of scheduler queues to be freed */ 612 u16 schq; 613 }; 614 615 struct nix_txschq_config { 616 struct mbox_msghdr hdr; 617 u8 lvl; /* SMQ/MDQ/TL4/TL3/TL2/TL1 */ 618 #define TXSCHQ_IDX_SHIFT 16 619 #define TXSCHQ_IDX_MASK (BIT_ULL(10) - 1) 620 #define TXSCHQ_IDX(reg, shift) (((reg) >> (shift)) & TXSCHQ_IDX_MASK) 621 u8 num_regs; 622 #define MAX_REGS_PER_MBOX_MSG 20 623 u64 reg[MAX_REGS_PER_MBOX_MSG]; 624 u64 regval[MAX_REGS_PER_MBOX_MSG]; 625 }; 626 627 struct nix_vtag_config { 628 struct mbox_msghdr hdr; 629 /* '0' for 4 octet VTAG, '1' for 8 octet VTAG */ 630 u8 vtag_size; 631 /* cfg_type is '0' for tx vlan cfg 632 * cfg_type is '1' for rx vlan cfg 633 */ 634 u8 cfg_type; 635 union { 636 /* valid when cfg_type is '0' */ 637 struct { 638 u64 vtag0; 639 u64 vtag1; 640 641 /* cfg_vtag0 & cfg_vtag1 fields are valid 642 * when free_vtag0 & free_vtag1 are '0's. 643 */ 644 /* cfg_vtag0 = 1 to configure vtag0 */ 645 u8 cfg_vtag0 :1; 646 /* cfg_vtag1 = 1 to configure vtag1 */ 647 u8 cfg_vtag1 :1; 648 649 /* vtag0_idx & vtag1_idx are only valid when 650 * both cfg_vtag0 & cfg_vtag1 are '0's, 651 * these fields are used along with free_vtag0 652 * & free_vtag1 to free the nix lf's tx_vlan 653 * configuration. 654 * 655 * Denotes the indices of tx_vtag def registers 656 * that needs to be cleared and freed. 657 */ 658 int vtag0_idx; 659 int vtag1_idx; 660 661 /* free_vtag0 & free_vtag1 fields are valid 662 * when cfg_vtag0 & cfg_vtag1 are '0's. 663 */ 664 /* free_vtag0 = 1 clears vtag0 configuration 665 * vtag0_idx denotes the index to be cleared. 666 */ 667 u8 free_vtag0 :1; 668 /* free_vtag1 = 1 clears vtag1 configuration 669 * vtag1_idx denotes the index to be cleared. 670 */ 671 u8 free_vtag1 :1; 672 } tx; 673 674 /* valid when cfg_type is '1' */ 675 struct { 676 /* rx vtag type index, valid values are in 0..7 range */ 677 u8 vtag_type; 678 /* rx vtag strip */ 679 u8 strip_vtag :1; 680 /* rx vtag capture */ 681 u8 capture_vtag :1; 682 } rx; 683 }; 684 }; 685 686 struct nix_vtag_config_rsp { 687 struct mbox_msghdr hdr; 688 int vtag0_idx; 689 int vtag1_idx; 690 /* Indices of tx_vtag def registers used to configure 691 * tx vtag0 & vtag1 headers, these indices are valid 692 * when nix_vtag_config mbox requested for vtag0 and/ 693 * or vtag1 configuration. 694 */ 695 }; 696 697 struct nix_rss_flowkey_cfg { 698 struct mbox_msghdr hdr; 699 int mcam_index; /* MCAM entry index to modify */ 700 #define NIX_FLOW_KEY_TYPE_PORT BIT(0) 701 #define NIX_FLOW_KEY_TYPE_IPV4 BIT(1) 702 #define NIX_FLOW_KEY_TYPE_IPV6 BIT(2) 703 #define NIX_FLOW_KEY_TYPE_TCP BIT(3) 704 #define NIX_FLOW_KEY_TYPE_UDP BIT(4) 705 #define NIX_FLOW_KEY_TYPE_SCTP BIT(5) 706 #define NIX_FLOW_KEY_TYPE_NVGRE BIT(6) 707 #define NIX_FLOW_KEY_TYPE_VXLAN BIT(7) 708 #define NIX_FLOW_KEY_TYPE_GENEVE BIT(8) 709 #define NIX_FLOW_KEY_TYPE_ETH_DMAC BIT(9) 710 #define NIX_FLOW_KEY_TYPE_IPV6_EXT BIT(10) 711 #define NIX_FLOW_KEY_TYPE_GTPU BIT(11) 712 #define NIX_FLOW_KEY_TYPE_INNR_IPV4 BIT(12) 713 #define NIX_FLOW_KEY_TYPE_INNR_IPV6 BIT(13) 714 #define NIX_FLOW_KEY_TYPE_INNR_TCP BIT(14) 715 #define NIX_FLOW_KEY_TYPE_INNR_UDP BIT(15) 716 #define NIX_FLOW_KEY_TYPE_INNR_SCTP BIT(16) 717 #define NIX_FLOW_KEY_TYPE_INNR_ETH_DMAC BIT(17) 718 #define NIX_FLOW_KEY_TYPE_VLAN BIT(20) 719 #define NIX_FLOW_KEY_TYPE_IPV4_PROTO BIT(21) 720 u32 flowkey_cfg; /* Flowkey types selected */ 721 u8 group; /* RSS context or group */ 722 }; 723 724 struct nix_rss_flowkey_cfg_rsp { 725 struct mbox_msghdr hdr; 726 u8 alg_idx; /* Selected algo index */ 727 }; 728 729 struct nix_set_mac_addr { 730 struct mbox_msghdr hdr; 731 u8 mac_addr[ETH_ALEN]; /* MAC address to be set for this pcifunc */ 732 }; 733 734 struct nix_get_mac_addr_rsp { 735 struct mbox_msghdr hdr; 736 u8 mac_addr[ETH_ALEN]; 737 }; 738 739 struct nix_mark_format_cfg { 740 struct mbox_msghdr hdr; 741 u8 offset; 742 u8 y_mask; 743 u8 y_val; 744 u8 r_mask; 745 u8 r_val; 746 }; 747 748 struct nix_mark_format_cfg_rsp { 749 struct mbox_msghdr hdr; 750 u8 mark_format_idx; 751 }; 752 753 struct nix_rx_mode { 754 struct mbox_msghdr hdr; 755 #define NIX_RX_MODE_UCAST BIT(0) 756 #define NIX_RX_MODE_PROMISC BIT(1) 757 #define NIX_RX_MODE_ALLMULTI BIT(2) 758 u16 mode; 759 }; 760 761 struct nix_rx_cfg { 762 struct mbox_msghdr hdr; 763 #define NIX_RX_OL3_VERIFY BIT(0) 764 #define NIX_RX_OL4_VERIFY BIT(1) 765 u8 len_verify; /* Outer L3/L4 len check */ 766 #define NIX_RX_CSUM_OL4_VERIFY BIT(0) 767 u8 csum_verify; /* Outer L4 checksum verification */ 768 }; 769 770 struct nix_frs_cfg { 771 struct mbox_msghdr hdr; 772 u8 update_smq; /* Update SMQ's min/max lens */ 773 u8 update_minlen; /* Set minlen also */ 774 u8 sdp_link; /* Set SDP RX link */ 775 u16 maxlen; 776 u16 minlen; 777 }; 778 779 struct nix_lso_format_cfg { 780 struct mbox_msghdr hdr; 781 u64 field_mask; 782 #define NIX_LSO_FIELD_MAX 8 783 u64 fields[NIX_LSO_FIELD_MAX]; 784 }; 785 786 struct nix_lso_format_cfg_rsp { 787 struct mbox_msghdr hdr; 788 u8 lso_format_idx; 789 }; 790 791 struct nix_bp_cfg_req { 792 struct mbox_msghdr hdr; 793 u16 chan_base; /* Starting channel number */ 794 u8 chan_cnt; /* Number of channels */ 795 u8 bpid_per_chan; 796 /* bpid_per_chan = 0 assigns single bp id for range of channels */ 797 /* bpid_per_chan = 1 assigns separate bp id for each channel */ 798 }; 799 800 /* PF can be mapped to either CGX or LBK interface, 801 * so maximum 64 channels are possible. 802 */ 803 #define NIX_MAX_BPID_CHAN 64 804 struct nix_bp_cfg_rsp { 805 struct mbox_msghdr hdr; 806 u16 chan_bpid[NIX_MAX_BPID_CHAN]; /* Channel and bpid mapping */ 807 u8 chan_cnt; /* Number of channel for which bpids are assigned */ 808 }; 809 810 /* NPC mbox message structs */ 811 812 #define NPC_MCAM_ENTRY_INVALID 0xFFFF 813 #define NPC_MCAM_INVALID_MAP 0xFFFF 814 815 /* NPC mailbox error codes 816 * Range 701 - 800. 817 */ 818 enum npc_af_status { 819 NPC_MCAM_INVALID_REQ = -701, 820 NPC_MCAM_ALLOC_DENIED = -702, 821 NPC_MCAM_ALLOC_FAILED = -703, 822 NPC_MCAM_PERM_DENIED = -704, 823 }; 824 825 struct npc_mcam_alloc_entry_req { 826 struct mbox_msghdr hdr; 827 #define NPC_MAX_NONCONTIG_ENTRIES 256 828 u8 contig; /* Contiguous entries ? */ 829 #define NPC_MCAM_ANY_PRIO 0 830 #define NPC_MCAM_LOWER_PRIO 1 831 #define NPC_MCAM_HIGHER_PRIO 2 832 u8 priority; /* Lower or higher w.r.t ref_entry */ 833 u16 ref_entry; 834 u16 count; /* Number of entries requested */ 835 }; 836 837 struct npc_mcam_alloc_entry_rsp { 838 struct mbox_msghdr hdr; 839 u16 entry; /* Entry allocated or start index if contiguous. 840 * Invalid incase of non-contiguous. 841 */ 842 u16 count; /* Number of entries allocated */ 843 u16 free_count; /* Number of entries available */ 844 u16 entry_list[NPC_MAX_NONCONTIG_ENTRIES]; 845 }; 846 847 struct npc_mcam_free_entry_req { 848 struct mbox_msghdr hdr; 849 u16 entry; /* Entry index to be freed */ 850 u8 all; /* If all entries allocated to this PFVF to be freed */ 851 }; 852 853 struct mcam_entry { 854 #define NPC_MAX_KWS_IN_KEY 7 /* Number of keywords in max keywidth */ 855 u64 kw[NPC_MAX_KWS_IN_KEY]; 856 u64 kw_mask[NPC_MAX_KWS_IN_KEY]; 857 u64 action; 858 u64 vtag_action; 859 }; 860 861 struct npc_mcam_write_entry_req { 862 struct mbox_msghdr hdr; 863 struct mcam_entry entry_data; 864 u16 entry; /* MCAM entry to write this match key */ 865 u16 cntr; /* Counter for this MCAM entry */ 866 u8 intf; /* Rx or Tx interface */ 867 u8 enable_entry;/* Enable this MCAM entry ? */ 868 u8 set_cntr; /* Set counter for this entry ? */ 869 }; 870 871 /* Enable/Disable a given entry */ 872 struct npc_mcam_ena_dis_entry_req { 873 struct mbox_msghdr hdr; 874 u16 entry; 875 }; 876 877 struct npc_mcam_shift_entry_req { 878 struct mbox_msghdr hdr; 879 #define NPC_MCAM_MAX_SHIFTS 64 880 u16 curr_entry[NPC_MCAM_MAX_SHIFTS]; 881 u16 new_entry[NPC_MCAM_MAX_SHIFTS]; 882 u16 shift_count; /* Number of entries to shift */ 883 }; 884 885 struct npc_mcam_shift_entry_rsp { 886 struct mbox_msghdr hdr; 887 u16 failed_entry_idx; /* Index in 'curr_entry', not entry itself */ 888 }; 889 890 struct npc_mcam_alloc_counter_req { 891 struct mbox_msghdr hdr; 892 u8 contig; /* Contiguous counters ? */ 893 #define NPC_MAX_NONCONTIG_COUNTERS 64 894 u16 count; /* Number of counters requested */ 895 }; 896 897 struct npc_mcam_alloc_counter_rsp { 898 struct mbox_msghdr hdr; 899 u16 cntr; /* Counter allocated or start index if contiguous. 900 * Invalid incase of non-contiguous. 901 */ 902 u16 count; /* Number of counters allocated */ 903 u16 cntr_list[NPC_MAX_NONCONTIG_COUNTERS]; 904 }; 905 906 struct npc_mcam_oper_counter_req { 907 struct mbox_msghdr hdr; 908 u16 cntr; /* Free a counter or clear/fetch it's stats */ 909 }; 910 911 struct npc_mcam_oper_counter_rsp { 912 struct mbox_msghdr hdr; 913 u64 stat; /* valid only while fetching counter's stats */ 914 }; 915 916 struct npc_mcam_unmap_counter_req { 917 struct mbox_msghdr hdr; 918 u16 cntr; 919 u16 entry; /* Entry and counter to be unmapped */ 920 u8 all; /* Unmap all entries using this counter ? */ 921 }; 922 923 struct npc_mcam_alloc_and_write_entry_req { 924 struct mbox_msghdr hdr; 925 struct mcam_entry entry_data; 926 u16 ref_entry; 927 u8 priority; /* Lower or higher w.r.t ref_entry */ 928 u8 intf; /* Rx or Tx interface */ 929 u8 enable_entry;/* Enable this MCAM entry ? */ 930 u8 alloc_cntr; /* Allocate counter and map ? */ 931 }; 932 933 struct npc_mcam_alloc_and_write_entry_rsp { 934 struct mbox_msghdr hdr; 935 u16 entry; 936 u16 cntr; 937 }; 938 939 struct npc_get_kex_cfg_rsp { 940 struct mbox_msghdr hdr; 941 u64 rx_keyx_cfg; /* NPC_AF_INTF(0)_KEX_CFG */ 942 u64 tx_keyx_cfg; /* NPC_AF_INTF(1)_KEX_CFG */ 943 #define NPC_MAX_INTF 2 944 #define NPC_MAX_LID 8 945 #define NPC_MAX_LT 16 946 #define NPC_MAX_LD 2 947 #define NPC_MAX_LFL 16 948 /* NPC_AF_KEX_LDATA(0..1)_FLAGS_CFG */ 949 u64 kex_ld_flags[NPC_MAX_LD]; 950 /* NPC_AF_INTF(0..1)_LID(0..7)_LT(0..15)_LD(0..1)_CFG */ 951 u64 intf_lid_lt_ld[NPC_MAX_INTF][NPC_MAX_LID][NPC_MAX_LT][NPC_MAX_LD]; 952 /* NPC_AF_INTF(0..1)_LDATA(0..1)_FLAGS(0..15)_CFG */ 953 u64 intf_ld_flags[NPC_MAX_INTF][NPC_MAX_LD][NPC_MAX_LFL]; 954 #define MKEX_NAME_LEN 128 955 u8 mkex_pfl_name[MKEX_NAME_LEN]; 956 }; 957 958 struct flow_msg { 959 unsigned char dmac[6]; 960 unsigned char smac[6]; 961 __be16 etype; 962 __be16 vlan_etype; 963 __be16 vlan_tci; 964 union { 965 __be32 ip4src; 966 __be32 ip6src[4]; 967 }; 968 union { 969 __be32 ip4dst; 970 __be32 ip6dst[4]; 971 }; 972 u8 tos; 973 u8 ip_ver; 974 u8 ip_proto; 975 u8 tc; 976 __be16 sport; 977 __be16 dport; 978 }; 979 980 struct npc_install_flow_req { 981 struct mbox_msghdr hdr; 982 struct flow_msg packet; 983 struct flow_msg mask; 984 u64 features; 985 u16 entry; 986 u16 channel; 987 u8 intf; 988 u8 set_cntr; /* If counter is available set counter for this entry ? */ 989 u8 default_rule; 990 u8 append; /* overwrite(0) or append(1) flow to default rule? */ 991 u16 vf; 992 /* action */ 993 u32 index; 994 u16 match_id; 995 u8 flow_key_alg; 996 u8 op; 997 /* vtag rx action */ 998 u8 vtag0_type; 999 u8 vtag0_valid; 1000 u8 vtag1_type; 1001 u8 vtag1_valid; 1002 /* vtag tx action */ 1003 u16 vtag0_def; 1004 u8 vtag0_op; 1005 u16 vtag1_def; 1006 u8 vtag1_op; 1007 }; 1008 1009 struct npc_install_flow_rsp { 1010 struct mbox_msghdr hdr; 1011 int counter; /* negative if no counter else counter number */ 1012 }; 1013 1014 struct npc_delete_flow_req { 1015 struct mbox_msghdr hdr; 1016 u16 entry; 1017 u16 start;/*Disable range of entries */ 1018 u16 end; 1019 u8 all; /* PF + VFs */ 1020 }; 1021 1022 struct npc_mcam_read_entry_req { 1023 struct mbox_msghdr hdr; 1024 u16 entry; /* MCAM entry to read */ 1025 }; 1026 1027 struct npc_mcam_read_entry_rsp { 1028 struct mbox_msghdr hdr; 1029 struct mcam_entry entry_data; 1030 u8 intf; 1031 u8 enable; 1032 }; 1033 1034 struct npc_mcam_read_base_rule_rsp { 1035 struct mbox_msghdr hdr; 1036 struct mcam_entry entry; 1037 }; 1038 1039 enum ptp_op { 1040 PTP_OP_ADJFINE = 0, 1041 PTP_OP_GET_CLOCK = 1, 1042 }; 1043 1044 struct ptp_req { 1045 struct mbox_msghdr hdr; 1046 u8 op; 1047 s64 scaled_ppm; 1048 }; 1049 1050 struct ptp_rsp { 1051 struct mbox_msghdr hdr; 1052 u64 clk; 1053 }; 1054 1055 /* CPT mailbox error codes 1056 * Range 901 - 1000. 1057 */ 1058 enum cpt_af_status { 1059 CPT_AF_ERR_PARAM = -901, 1060 CPT_AF_ERR_GRP_INVALID = -902, 1061 CPT_AF_ERR_LF_INVALID = -903, 1062 CPT_AF_ERR_ACCESS_DENIED = -904, 1063 CPT_AF_ERR_SSO_PF_FUNC_INVALID = -905, 1064 CPT_AF_ERR_NIX_PF_FUNC_INVALID = -906 1065 }; 1066 1067 /* CPT mbox message formats */ 1068 struct cpt_rd_wr_reg_msg { 1069 struct mbox_msghdr hdr; 1070 u64 reg_offset; 1071 u64 *ret_val; 1072 u64 val; 1073 u8 is_write; 1074 }; 1075 1076 struct cpt_lf_alloc_req_msg { 1077 struct mbox_msghdr hdr; 1078 u16 nix_pf_func; 1079 u16 sso_pf_func; 1080 u16 eng_grpmsk; 1081 }; 1082 1083 #endif /* MBOX_H */ 1084