1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Marvell OcteonTx2 RVU Admin Function driver 3 * 4 * Copyright (C) 2018 Marvell International Ltd. 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 */ 10 11 #ifndef MBOX_H 12 #define MBOX_H 13 14 #include <linux/etherdevice.h> 15 #include <linux/sizes.h> 16 17 #include "rvu_struct.h" 18 #include "common.h" 19 20 #define MBOX_SIZE SZ_64K 21 22 /* AF/PF: PF initiated, PF/VF VF initiated */ 23 #define MBOX_DOWN_RX_START 0 24 #define MBOX_DOWN_RX_SIZE (46 * SZ_1K) 25 #define MBOX_DOWN_TX_START (MBOX_DOWN_RX_START + MBOX_DOWN_RX_SIZE) 26 #define MBOX_DOWN_TX_SIZE (16 * SZ_1K) 27 /* AF/PF: AF initiated, PF/VF PF initiated */ 28 #define MBOX_UP_RX_START (MBOX_DOWN_TX_START + MBOX_DOWN_TX_SIZE) 29 #define MBOX_UP_RX_SIZE SZ_1K 30 #define MBOX_UP_TX_START (MBOX_UP_RX_START + MBOX_UP_RX_SIZE) 31 #define MBOX_UP_TX_SIZE SZ_1K 32 33 #if MBOX_UP_TX_SIZE + MBOX_UP_TX_START != MBOX_SIZE 34 # error "incorrect mailbox area sizes" 35 #endif 36 37 #define INTR_MASK(pfvfs) ((pfvfs < 64) ? (BIT_ULL(pfvfs) - 1) : (~0ull)) 38 39 #define MBOX_RSP_TIMEOUT 2000 /* Time(ms) to wait for mbox response */ 40 41 #define MBOX_MSG_ALIGN 16 /* Align mbox msg start to 16bytes */ 42 43 /* Mailbox directions */ 44 #define MBOX_DIR_AFPF 0 /* AF replies to PF */ 45 #define MBOX_DIR_PFAF 1 /* PF sends messages to AF */ 46 #define MBOX_DIR_PFVF 2 /* PF replies to VF */ 47 #define MBOX_DIR_VFPF 3 /* VF sends messages to PF */ 48 #define MBOX_DIR_AFPF_UP 4 /* AF sends messages to PF */ 49 #define MBOX_DIR_PFAF_UP 5 /* PF replies to AF */ 50 #define MBOX_DIR_PFVF_UP 6 /* PF sends messages to VF */ 51 #define MBOX_DIR_VFPF_UP 7 /* VF replies to PF */ 52 53 struct otx2_mbox_dev { 54 void *mbase; /* This dev's mbox region */ 55 spinlock_t mbox_lock; 56 u16 msg_size; /* Total msg size to be sent */ 57 u16 rsp_size; /* Total rsp size to be sure the reply is ok */ 58 u16 num_msgs; /* No of msgs sent or waiting for response */ 59 u16 msgs_acked; /* No of msgs for which response is received */ 60 }; 61 62 struct otx2_mbox { 63 struct pci_dev *pdev; 64 void *hwbase; /* Mbox region advertised by HW */ 65 void *reg_base;/* CSR base for this dev */ 66 u64 trigger; /* Trigger mbox notification */ 67 u16 tr_shift; /* Mbox trigger shift */ 68 u64 rx_start; /* Offset of Rx region in mbox memory */ 69 u64 tx_start; /* Offset of Tx region in mbox memory */ 70 u16 rx_size; /* Size of Rx region */ 71 u16 tx_size; /* Size of Tx region */ 72 u16 ndevs; /* The number of peers */ 73 struct otx2_mbox_dev *dev; 74 }; 75 76 /* Header which preceeds all mbox messages */ 77 struct mbox_hdr { 78 u64 msg_size; /* Total msgs size embedded */ 79 u16 num_msgs; /* No of msgs embedded */ 80 }; 81 82 /* Header which preceeds every msg and is also part of it */ 83 struct mbox_msghdr { 84 u16 pcifunc; /* Who's sending this msg */ 85 u16 id; /* Mbox message ID */ 86 #define OTX2_MBOX_REQ_SIG (0xdead) 87 #define OTX2_MBOX_RSP_SIG (0xbeef) 88 u16 sig; /* Signature, for validating corrupted msgs */ 89 #define OTX2_MBOX_VERSION (0x0001) 90 u16 ver; /* Version of msg's structure for this ID */ 91 u16 next_msgoff; /* Offset of next msg within mailbox region */ 92 int rc; /* Msg process'ed response code */ 93 }; 94 95 void otx2_mbox_reset(struct otx2_mbox *mbox, int devid); 96 void otx2_mbox_destroy(struct otx2_mbox *mbox); 97 int otx2_mbox_init(struct otx2_mbox *mbox, void __force *hwbase, 98 struct pci_dev *pdev, void __force *reg_base, 99 int direction, int ndevs); 100 void otx2_mbox_msg_send(struct otx2_mbox *mbox, int devid); 101 int otx2_mbox_wait_for_rsp(struct otx2_mbox *mbox, int devid); 102 int otx2_mbox_busy_poll_for_rsp(struct otx2_mbox *mbox, int devid); 103 struct mbox_msghdr *otx2_mbox_alloc_msg_rsp(struct otx2_mbox *mbox, int devid, 104 int size, int size_rsp); 105 struct mbox_msghdr *otx2_mbox_get_rsp(struct otx2_mbox *mbox, int devid, 106 struct mbox_msghdr *msg); 107 int otx2_mbox_check_rsp_msgs(struct otx2_mbox *mbox, int devid); 108 int otx2_reply_invalid_msg(struct otx2_mbox *mbox, int devid, 109 u16 pcifunc, u16 id); 110 bool otx2_mbox_nonempty(struct otx2_mbox *mbox, int devid); 111 const char *otx2_mbox_id2name(u16 id); 112 static inline struct mbox_msghdr *otx2_mbox_alloc_msg(struct otx2_mbox *mbox, 113 int devid, int size) 114 { 115 return otx2_mbox_alloc_msg_rsp(mbox, devid, size, 0); 116 } 117 118 /* Mailbox message types */ 119 #define MBOX_MSG_MASK 0xFFFF 120 #define MBOX_MSG_INVALID 0xFFFE 121 #define MBOX_MSG_MAX 0xFFFF 122 123 #define MBOX_MESSAGES \ 124 /* Generic mbox IDs (range 0x000 - 0x1FF) */ \ 125 M(READY, 0x001, ready, msg_req, ready_msg_rsp) \ 126 M(ATTACH_RESOURCES, 0x002, attach_resources, rsrc_attach, msg_rsp) \ 127 M(DETACH_RESOURCES, 0x003, detach_resources, rsrc_detach, msg_rsp) \ 128 M(MSIX_OFFSET, 0x004, msix_offset, msg_req, msix_offset_rsp) \ 129 M(VF_FLR, 0x006, vf_flr, msg_req, msg_rsp) \ 130 M(GET_HW_CAP, 0x008, get_hw_cap, msg_req, get_hw_cap_rsp) \ 131 /* CGX mbox IDs (range 0x200 - 0x3FF) */ \ 132 M(CGX_START_RXTX, 0x200, cgx_start_rxtx, msg_req, msg_rsp) \ 133 M(CGX_STOP_RXTX, 0x201, cgx_stop_rxtx, msg_req, msg_rsp) \ 134 M(CGX_STATS, 0x202, cgx_stats, msg_req, cgx_stats_rsp) \ 135 M(CGX_MAC_ADDR_SET, 0x203, cgx_mac_addr_set, cgx_mac_addr_set_or_get, \ 136 cgx_mac_addr_set_or_get) \ 137 M(CGX_MAC_ADDR_GET, 0x204, cgx_mac_addr_get, cgx_mac_addr_set_or_get, \ 138 cgx_mac_addr_set_or_get) \ 139 M(CGX_PROMISC_ENABLE, 0x205, cgx_promisc_enable, msg_req, msg_rsp) \ 140 M(CGX_PROMISC_DISABLE, 0x206, cgx_promisc_disable, msg_req, msg_rsp) \ 141 M(CGX_START_LINKEVENTS, 0x207, cgx_start_linkevents, msg_req, msg_rsp) \ 142 M(CGX_STOP_LINKEVENTS, 0x208, cgx_stop_linkevents, msg_req, msg_rsp) \ 143 M(CGX_GET_LINKINFO, 0x209, cgx_get_linkinfo, msg_req, cgx_link_info_msg) \ 144 M(CGX_INTLBK_ENABLE, 0x20A, cgx_intlbk_enable, msg_req, msg_rsp) \ 145 M(CGX_INTLBK_DISABLE, 0x20B, cgx_intlbk_disable, msg_req, msg_rsp) \ 146 /* NPA mbox IDs (range 0x400 - 0x5FF) */ \ 147 M(NPA_LF_ALLOC, 0x400, npa_lf_alloc, \ 148 npa_lf_alloc_req, npa_lf_alloc_rsp) \ 149 M(NPA_LF_FREE, 0x401, npa_lf_free, msg_req, msg_rsp) \ 150 M(NPA_AQ_ENQ, 0x402, npa_aq_enq, npa_aq_enq_req, npa_aq_enq_rsp) \ 151 M(NPA_HWCTX_DISABLE, 0x403, npa_hwctx_disable, hwctx_disable_req, msg_rsp)\ 152 /* SSO/SSOW mbox IDs (range 0x600 - 0x7FF) */ \ 153 /* TIM mbox IDs (range 0x800 - 0x9FF) */ \ 154 /* CPT mbox IDs (range 0xA00 - 0xBFF) */ \ 155 /* NPC mbox IDs (range 0x6000 - 0x7FFF) */ \ 156 M(NPC_MCAM_ALLOC_ENTRY, 0x6000, npc_mcam_alloc_entry, npc_mcam_alloc_entry_req,\ 157 npc_mcam_alloc_entry_rsp) \ 158 M(NPC_MCAM_FREE_ENTRY, 0x6001, npc_mcam_free_entry, \ 159 npc_mcam_free_entry_req, msg_rsp) \ 160 M(NPC_MCAM_WRITE_ENTRY, 0x6002, npc_mcam_write_entry, \ 161 npc_mcam_write_entry_req, msg_rsp) \ 162 M(NPC_MCAM_ENA_ENTRY, 0x6003, npc_mcam_ena_entry, \ 163 npc_mcam_ena_dis_entry_req, msg_rsp) \ 164 M(NPC_MCAM_DIS_ENTRY, 0x6004, npc_mcam_dis_entry, \ 165 npc_mcam_ena_dis_entry_req, msg_rsp) \ 166 M(NPC_MCAM_SHIFT_ENTRY, 0x6005, npc_mcam_shift_entry, npc_mcam_shift_entry_req,\ 167 npc_mcam_shift_entry_rsp) \ 168 M(NPC_MCAM_ALLOC_COUNTER, 0x6006, npc_mcam_alloc_counter, \ 169 npc_mcam_alloc_counter_req, \ 170 npc_mcam_alloc_counter_rsp) \ 171 M(NPC_MCAM_FREE_COUNTER, 0x6007, npc_mcam_free_counter, \ 172 npc_mcam_oper_counter_req, msg_rsp) \ 173 M(NPC_MCAM_UNMAP_COUNTER, 0x6008, npc_mcam_unmap_counter, \ 174 npc_mcam_unmap_counter_req, msg_rsp) \ 175 M(NPC_MCAM_CLEAR_COUNTER, 0x6009, npc_mcam_clear_counter, \ 176 npc_mcam_oper_counter_req, msg_rsp) \ 177 M(NPC_MCAM_COUNTER_STATS, 0x600a, npc_mcam_counter_stats, \ 178 npc_mcam_oper_counter_req, \ 179 npc_mcam_oper_counter_rsp) \ 180 M(NPC_MCAM_ALLOC_AND_WRITE_ENTRY, 0x600b, npc_mcam_alloc_and_write_entry, \ 181 npc_mcam_alloc_and_write_entry_req, \ 182 npc_mcam_alloc_and_write_entry_rsp) \ 183 M(NPC_GET_KEX_CFG, 0x600c, npc_get_kex_cfg, \ 184 msg_req, npc_get_kex_cfg_rsp) \ 185 /* NIX mbox IDs (range 0x8000 - 0xFFFF) */ \ 186 M(NIX_LF_ALLOC, 0x8000, nix_lf_alloc, \ 187 nix_lf_alloc_req, nix_lf_alloc_rsp) \ 188 M(NIX_LF_FREE, 0x8001, nix_lf_free, msg_req, msg_rsp) \ 189 M(NIX_AQ_ENQ, 0x8002, nix_aq_enq, nix_aq_enq_req, nix_aq_enq_rsp) \ 190 M(NIX_HWCTX_DISABLE, 0x8003, nix_hwctx_disable, \ 191 hwctx_disable_req, msg_rsp) \ 192 M(NIX_TXSCH_ALLOC, 0x8004, nix_txsch_alloc, \ 193 nix_txsch_alloc_req, nix_txsch_alloc_rsp) \ 194 M(NIX_TXSCH_FREE, 0x8005, nix_txsch_free, nix_txsch_free_req, msg_rsp) \ 195 M(NIX_TXSCHQ_CFG, 0x8006, nix_txschq_cfg, nix_txschq_config, msg_rsp) \ 196 M(NIX_STATS_RST, 0x8007, nix_stats_rst, msg_req, msg_rsp) \ 197 M(NIX_VTAG_CFG, 0x8008, nix_vtag_cfg, nix_vtag_config, msg_rsp) \ 198 M(NIX_RSS_FLOWKEY_CFG, 0x8009, nix_rss_flowkey_cfg, \ 199 nix_rss_flowkey_cfg, \ 200 nix_rss_flowkey_cfg_rsp) \ 201 M(NIX_SET_MAC_ADDR, 0x800a, nix_set_mac_addr, nix_set_mac_addr, msg_rsp) \ 202 M(NIX_SET_RX_MODE, 0x800b, nix_set_rx_mode, nix_rx_mode, msg_rsp) \ 203 M(NIX_SET_HW_FRS, 0x800c, nix_set_hw_frs, nix_frs_cfg, msg_rsp) \ 204 M(NIX_LF_START_RX, 0x800d, nix_lf_start_rx, msg_req, msg_rsp) \ 205 M(NIX_LF_STOP_RX, 0x800e, nix_lf_stop_rx, msg_req, msg_rsp) \ 206 M(NIX_MARK_FORMAT_CFG, 0x800f, nix_mark_format_cfg, \ 207 nix_mark_format_cfg, \ 208 nix_mark_format_cfg_rsp) \ 209 M(NIX_SET_RX_CFG, 0x8010, nix_set_rx_cfg, nix_rx_cfg, msg_rsp) \ 210 M(NIX_LSO_FORMAT_CFG, 0x8011, nix_lso_format_cfg, \ 211 nix_lso_format_cfg, \ 212 nix_lso_format_cfg_rsp) \ 213 M(NIX_RXVLAN_ALLOC, 0x8012, nix_rxvlan_alloc, msg_req, msg_rsp) 214 215 /* Messages initiated by AF (range 0xC00 - 0xDFF) */ 216 #define MBOX_UP_CGX_MESSAGES \ 217 M(CGX_LINK_EVENT, 0xC00, cgx_link_event, cgx_link_info_msg, msg_rsp) 218 219 enum { 220 #define M(_name, _id, _1, _2, _3) MBOX_MSG_ ## _name = _id, 221 MBOX_MESSAGES 222 MBOX_UP_CGX_MESSAGES 223 #undef M 224 }; 225 226 /* Mailbox message formats */ 227 228 #define RVU_DEFAULT_PF_FUNC 0xFFFF 229 230 /* Generic request msg used for those mbox messages which 231 * don't send any data in the request. 232 */ 233 struct msg_req { 234 struct mbox_msghdr hdr; 235 }; 236 237 /* Generic rsponse msg used a ack or response for those mbox 238 * messages which doesn't have a specific rsp msg format. 239 */ 240 struct msg_rsp { 241 struct mbox_msghdr hdr; 242 }; 243 244 /* RVU mailbox error codes 245 * Range 256 - 300. 246 */ 247 enum rvu_af_status { 248 RVU_INVALID_VF_ID = -256, 249 }; 250 251 struct ready_msg_rsp { 252 struct mbox_msghdr hdr; 253 u16 sclk_feq; /* SCLK frequency */ 254 }; 255 256 /* Structure for requesting resource provisioning. 257 * 'modify' flag to be used when either requesting more 258 * or to detach partial of a cetain resource type. 259 * Rest of the fields specify how many of what type to 260 * be attached. 261 */ 262 struct rsrc_attach { 263 struct mbox_msghdr hdr; 264 u8 modify:1; 265 u8 npalf:1; 266 u8 nixlf:1; 267 u16 sso; 268 u16 ssow; 269 u16 timlfs; 270 u16 cptlfs; 271 }; 272 273 /* Structure for relinquishing resources. 274 * 'partial' flag to be used when relinquishing all resources 275 * but only of a certain type. If not set, all resources of all 276 * types provisioned to the RVU function will be detached. 277 */ 278 struct rsrc_detach { 279 struct mbox_msghdr hdr; 280 u8 partial:1; 281 u8 npalf:1; 282 u8 nixlf:1; 283 u8 sso:1; 284 u8 ssow:1; 285 u8 timlfs:1; 286 u8 cptlfs:1; 287 }; 288 289 #define MSIX_VECTOR_INVALID 0xFFFF 290 #define MAX_RVU_BLKLF_CNT 256 291 292 struct msix_offset_rsp { 293 struct mbox_msghdr hdr; 294 u16 npa_msixoff; 295 u16 nix_msixoff; 296 u8 sso; 297 u8 ssow; 298 u8 timlfs; 299 u8 cptlfs; 300 u16 sso_msixoff[MAX_RVU_BLKLF_CNT]; 301 u16 ssow_msixoff[MAX_RVU_BLKLF_CNT]; 302 u16 timlf_msixoff[MAX_RVU_BLKLF_CNT]; 303 u16 cptlf_msixoff[MAX_RVU_BLKLF_CNT]; 304 }; 305 306 struct get_hw_cap_rsp { 307 struct mbox_msghdr hdr; 308 u8 nix_fixed_txschq_mapping; /* Schq mapping fixed or flexible */ 309 u8 nix_shaping; /* Is shaping and coloring supported */ 310 }; 311 312 /* CGX mbox message formats */ 313 314 struct cgx_stats_rsp { 315 struct mbox_msghdr hdr; 316 #define CGX_RX_STATS_COUNT 13 317 #define CGX_TX_STATS_COUNT 18 318 u64 rx_stats[CGX_RX_STATS_COUNT]; 319 u64 tx_stats[CGX_TX_STATS_COUNT]; 320 }; 321 322 /* Structure for requesting the operation for 323 * setting/getting mac address in the CGX interface 324 */ 325 struct cgx_mac_addr_set_or_get { 326 struct mbox_msghdr hdr; 327 u8 mac_addr[ETH_ALEN]; 328 }; 329 330 struct cgx_link_user_info { 331 uint64_t link_up:1; 332 uint64_t full_duplex:1; 333 uint64_t lmac_type_id:4; 334 uint64_t speed:20; /* speed in Mbps */ 335 #define LMACTYPE_STR_LEN 16 336 char lmac_type[LMACTYPE_STR_LEN]; 337 }; 338 339 struct cgx_link_info_msg { 340 struct mbox_msghdr hdr; 341 struct cgx_link_user_info link_info; 342 }; 343 344 /* NPA mbox message formats */ 345 346 /* NPA mailbox error codes 347 * Range 301 - 400. 348 */ 349 enum npa_af_status { 350 NPA_AF_ERR_PARAM = -301, 351 NPA_AF_ERR_AQ_FULL = -302, 352 NPA_AF_ERR_AQ_ENQUEUE = -303, 353 NPA_AF_ERR_AF_LF_INVALID = -304, 354 NPA_AF_ERR_AF_LF_ALLOC = -305, 355 NPA_AF_ERR_LF_RESET = -306, 356 }; 357 358 /* For NPA LF context alloc and init */ 359 struct npa_lf_alloc_req { 360 struct mbox_msghdr hdr; 361 int node; 362 int aura_sz; /* No of auras */ 363 u32 nr_pools; /* No of pools */ 364 u64 way_mask; 365 }; 366 367 struct npa_lf_alloc_rsp { 368 struct mbox_msghdr hdr; 369 u32 stack_pg_ptrs; /* No of ptrs per stack page */ 370 u32 stack_pg_bytes; /* Size of stack page */ 371 u16 qints; /* NPA_AF_CONST::QINTS */ 372 }; 373 374 /* NPA AQ enqueue msg */ 375 struct npa_aq_enq_req { 376 struct mbox_msghdr hdr; 377 u32 aura_id; 378 u8 ctype; 379 u8 op; 380 union { 381 /* Valid when op == WRITE/INIT and ctype == AURA. 382 * LF fills the pool_id in aura.pool_addr. AF will translate 383 * the pool_id to pool context pointer. 384 */ 385 struct npa_aura_s aura; 386 /* Valid when op == WRITE/INIT and ctype == POOL */ 387 struct npa_pool_s pool; 388 }; 389 /* Mask data when op == WRITE (1=write, 0=don't write) */ 390 union { 391 /* Valid when op == WRITE and ctype == AURA */ 392 struct npa_aura_s aura_mask; 393 /* Valid when op == WRITE and ctype == POOL */ 394 struct npa_pool_s pool_mask; 395 }; 396 }; 397 398 struct npa_aq_enq_rsp { 399 struct mbox_msghdr hdr; 400 union { 401 /* Valid when op == READ and ctype == AURA */ 402 struct npa_aura_s aura; 403 /* Valid when op == READ and ctype == POOL */ 404 struct npa_pool_s pool; 405 }; 406 }; 407 408 /* Disable all contexts of type 'ctype' */ 409 struct hwctx_disable_req { 410 struct mbox_msghdr hdr; 411 u8 ctype; 412 }; 413 414 /* NIX mbox message formats */ 415 416 /* NIX mailbox error codes 417 * Range 401 - 500. 418 */ 419 enum nix_af_status { 420 NIX_AF_ERR_PARAM = -401, 421 NIX_AF_ERR_AQ_FULL = -402, 422 NIX_AF_ERR_AQ_ENQUEUE = -403, 423 NIX_AF_ERR_AF_LF_INVALID = -404, 424 NIX_AF_ERR_AF_LF_ALLOC = -405, 425 NIX_AF_ERR_TLX_ALLOC_FAIL = -406, 426 NIX_AF_ERR_TLX_INVALID = -407, 427 NIX_AF_ERR_RSS_SIZE_INVALID = -408, 428 NIX_AF_ERR_RSS_GRPS_INVALID = -409, 429 NIX_AF_ERR_FRS_INVALID = -410, 430 NIX_AF_ERR_RX_LINK_INVALID = -411, 431 NIX_AF_INVAL_TXSCHQ_CFG = -412, 432 NIX_AF_SMQ_FLUSH_FAILED = -413, 433 NIX_AF_ERR_LF_RESET = -414, 434 NIX_AF_ERR_RSS_NOSPC_FIELD = -415, 435 NIX_AF_ERR_RSS_NOSPC_ALGO = -416, 436 NIX_AF_ERR_MARK_CFG_FAIL = -417, 437 NIX_AF_ERR_LSO_CFG_FAIL = -418, 438 NIX_AF_INVAL_NPA_PF_FUNC = -419, 439 NIX_AF_INVAL_SSO_PF_FUNC = -420, 440 }; 441 442 /* For NIX LF context alloc and init */ 443 struct nix_lf_alloc_req { 444 struct mbox_msghdr hdr; 445 int node; 446 u32 rq_cnt; /* No of receive queues */ 447 u32 sq_cnt; /* No of send queues */ 448 u32 cq_cnt; /* No of completion queues */ 449 u8 xqe_sz; 450 u16 rss_sz; 451 u8 rss_grps; 452 u16 npa_func; 453 u16 sso_func; 454 u64 rx_cfg; /* See NIX_AF_LF(0..127)_RX_CFG */ 455 u64 way_mask; 456 }; 457 458 struct nix_lf_alloc_rsp { 459 struct mbox_msghdr hdr; 460 u16 sqb_size; 461 u16 rx_chan_base; 462 u16 tx_chan_base; 463 u8 rx_chan_cnt; /* total number of RX channels */ 464 u8 tx_chan_cnt; /* total number of TX channels */ 465 u8 lso_tsov4_idx; 466 u8 lso_tsov6_idx; 467 u8 mac_addr[ETH_ALEN]; 468 u8 lf_rx_stats; /* NIX_AF_CONST1::LF_RX_STATS */ 469 u8 lf_tx_stats; /* NIX_AF_CONST1::LF_TX_STATS */ 470 u16 cints; /* NIX_AF_CONST2::CINTS */ 471 u16 qints; /* NIX_AF_CONST2::QINTS */ 472 }; 473 474 /* NIX AQ enqueue msg */ 475 struct nix_aq_enq_req { 476 struct mbox_msghdr hdr; 477 u32 qidx; 478 u8 ctype; 479 u8 op; 480 union { 481 struct nix_rq_ctx_s rq; 482 struct nix_sq_ctx_s sq; 483 struct nix_cq_ctx_s cq; 484 struct nix_rsse_s rss; 485 struct nix_rx_mce_s mce; 486 }; 487 union { 488 struct nix_rq_ctx_s rq_mask; 489 struct nix_sq_ctx_s sq_mask; 490 struct nix_cq_ctx_s cq_mask; 491 struct nix_rsse_s rss_mask; 492 struct nix_rx_mce_s mce_mask; 493 }; 494 }; 495 496 struct nix_aq_enq_rsp { 497 struct mbox_msghdr hdr; 498 union { 499 struct nix_rq_ctx_s rq; 500 struct nix_sq_ctx_s sq; 501 struct nix_cq_ctx_s cq; 502 struct nix_rsse_s rss; 503 struct nix_rx_mce_s mce; 504 }; 505 }; 506 507 /* Tx scheduler/shaper mailbox messages */ 508 509 #define MAX_TXSCHQ_PER_FUNC 128 510 511 struct nix_txsch_alloc_req { 512 struct mbox_msghdr hdr; 513 /* Scheduler queue count request at each level */ 514 u16 schq_contig[NIX_TXSCH_LVL_CNT]; /* No of contiguous queues */ 515 u16 schq[NIX_TXSCH_LVL_CNT]; /* No of non-contiguous queues */ 516 }; 517 518 struct nix_txsch_alloc_rsp { 519 struct mbox_msghdr hdr; 520 /* Scheduler queue count allocated at each level */ 521 u16 schq_contig[NIX_TXSCH_LVL_CNT]; 522 u16 schq[NIX_TXSCH_LVL_CNT]; 523 /* Scheduler queue list allocated at each level */ 524 u16 schq_contig_list[NIX_TXSCH_LVL_CNT][MAX_TXSCHQ_PER_FUNC]; 525 u16 schq_list[NIX_TXSCH_LVL_CNT][MAX_TXSCHQ_PER_FUNC]; 526 u8 aggr_level; /* Traffic aggregation scheduler level */ 527 u8 aggr_lvl_rr_prio; /* Aggregation lvl's RR_PRIO config */ 528 u8 link_cfg_lvl; /* LINKX_CFG CSRs mapped to TL3 or TL2's index ? */ 529 }; 530 531 struct nix_txsch_free_req { 532 struct mbox_msghdr hdr; 533 #define TXSCHQ_FREE_ALL BIT_ULL(0) 534 u16 flags; 535 /* Scheduler queue level to be freed */ 536 u16 schq_lvl; 537 /* List of scheduler queues to be freed */ 538 u16 schq; 539 }; 540 541 struct nix_txschq_config { 542 struct mbox_msghdr hdr; 543 u8 lvl; /* SMQ/MDQ/TL4/TL3/TL2/TL1 */ 544 #define TXSCHQ_IDX_SHIFT 16 545 #define TXSCHQ_IDX_MASK (BIT_ULL(10) - 1) 546 #define TXSCHQ_IDX(reg, shift) (((reg) >> (shift)) & TXSCHQ_IDX_MASK) 547 u8 num_regs; 548 #define MAX_REGS_PER_MBOX_MSG 20 549 u64 reg[MAX_REGS_PER_MBOX_MSG]; 550 u64 regval[MAX_REGS_PER_MBOX_MSG]; 551 }; 552 553 struct nix_vtag_config { 554 struct mbox_msghdr hdr; 555 /* '0' for 4 octet VTAG, '1' for 8 octet VTAG */ 556 u8 vtag_size; 557 /* cfg_type is '0' for tx vlan cfg 558 * cfg_type is '1' for rx vlan cfg 559 */ 560 u8 cfg_type; 561 union { 562 /* valid when cfg_type is '0' */ 563 struct { 564 /* tx vlan0 tag(C-VLAN) */ 565 u64 vlan0; 566 /* tx vlan1 tag(S-VLAN) */ 567 u64 vlan1; 568 /* insert tx vlan tag */ 569 u8 insert_vlan :1; 570 /* insert tx double vlan tag */ 571 u8 double_vlan :1; 572 } tx; 573 574 /* valid when cfg_type is '1' */ 575 struct { 576 /* rx vtag type index, valid values are in 0..7 range */ 577 u8 vtag_type; 578 /* rx vtag strip */ 579 u8 strip_vtag :1; 580 /* rx vtag capture */ 581 u8 capture_vtag :1; 582 } rx; 583 }; 584 }; 585 586 struct nix_rss_flowkey_cfg { 587 struct mbox_msghdr hdr; 588 int mcam_index; /* MCAM entry index to modify */ 589 #define NIX_FLOW_KEY_TYPE_PORT BIT(0) 590 #define NIX_FLOW_KEY_TYPE_IPV4 BIT(1) 591 #define NIX_FLOW_KEY_TYPE_IPV6 BIT(2) 592 #define NIX_FLOW_KEY_TYPE_TCP BIT(3) 593 #define NIX_FLOW_KEY_TYPE_UDP BIT(4) 594 #define NIX_FLOW_KEY_TYPE_SCTP BIT(5) 595 #define NIX_FLOW_KEY_TYPE_NVGRE BIT(6) 596 #define NIX_FLOW_KEY_TYPE_VXLAN BIT(7) 597 #define NIX_FLOW_KEY_TYPE_GENEVE BIT(8) 598 #define NIX_FLOW_KEY_TYPE_ETH_DMAC BIT(9) 599 #define NIX_FLOW_KEY_TYPE_IPV6_EXT BIT(10) 600 #define NIX_FLOW_KEY_TYPE_GTPU BIT(11) 601 #define NIX_FLOW_KEY_TYPE_INNR_IPV4 BIT(12) 602 #define NIX_FLOW_KEY_TYPE_INNR_IPV6 BIT(13) 603 #define NIX_FLOW_KEY_TYPE_INNR_TCP BIT(14) 604 #define NIX_FLOW_KEY_TYPE_INNR_UDP BIT(15) 605 #define NIX_FLOW_KEY_TYPE_INNR_SCTP BIT(16) 606 #define NIX_FLOW_KEY_TYPE_INNR_ETH_DMAC BIT(17) 607 u32 flowkey_cfg; /* Flowkey types selected */ 608 u8 group; /* RSS context or group */ 609 }; 610 611 struct nix_rss_flowkey_cfg_rsp { 612 struct mbox_msghdr hdr; 613 u8 alg_idx; /* Selected algo index */ 614 }; 615 616 struct nix_set_mac_addr { 617 struct mbox_msghdr hdr; 618 u8 mac_addr[ETH_ALEN]; /* MAC address to be set for this pcifunc */ 619 }; 620 621 struct nix_mark_format_cfg { 622 struct mbox_msghdr hdr; 623 u8 offset; 624 u8 y_mask; 625 u8 y_val; 626 u8 r_mask; 627 u8 r_val; 628 }; 629 630 struct nix_mark_format_cfg_rsp { 631 struct mbox_msghdr hdr; 632 u8 mark_format_idx; 633 }; 634 635 struct nix_rx_mode { 636 struct mbox_msghdr hdr; 637 #define NIX_RX_MODE_UCAST BIT(0) 638 #define NIX_RX_MODE_PROMISC BIT(1) 639 #define NIX_RX_MODE_ALLMULTI BIT(2) 640 u16 mode; 641 }; 642 643 struct nix_rx_cfg { 644 struct mbox_msghdr hdr; 645 #define NIX_RX_OL3_VERIFY BIT(0) 646 #define NIX_RX_OL4_VERIFY BIT(1) 647 u8 len_verify; /* Outer L3/L4 len check */ 648 #define NIX_RX_CSUM_OL4_VERIFY BIT(0) 649 u8 csum_verify; /* Outer L4 checksum verification */ 650 }; 651 652 struct nix_frs_cfg { 653 struct mbox_msghdr hdr; 654 u8 update_smq; /* Update SMQ's min/max lens */ 655 u8 update_minlen; /* Set minlen also */ 656 u8 sdp_link; /* Set SDP RX link */ 657 u16 maxlen; 658 u16 minlen; 659 }; 660 661 struct nix_lso_format_cfg { 662 struct mbox_msghdr hdr; 663 u64 field_mask; 664 #define NIX_LSO_FIELD_MAX 8 665 u64 fields[NIX_LSO_FIELD_MAX]; 666 }; 667 668 struct nix_lso_format_cfg_rsp { 669 struct mbox_msghdr hdr; 670 u8 lso_format_idx; 671 }; 672 673 /* NPC mbox message structs */ 674 675 #define NPC_MCAM_ENTRY_INVALID 0xFFFF 676 #define NPC_MCAM_INVALID_MAP 0xFFFF 677 678 /* NPC mailbox error codes 679 * Range 701 - 800. 680 */ 681 enum npc_af_status { 682 NPC_MCAM_INVALID_REQ = -701, 683 NPC_MCAM_ALLOC_DENIED = -702, 684 NPC_MCAM_ALLOC_FAILED = -703, 685 NPC_MCAM_PERM_DENIED = -704, 686 }; 687 688 struct npc_mcam_alloc_entry_req { 689 struct mbox_msghdr hdr; 690 #define NPC_MAX_NONCONTIG_ENTRIES 256 691 u8 contig; /* Contiguous entries ? */ 692 #define NPC_MCAM_ANY_PRIO 0 693 #define NPC_MCAM_LOWER_PRIO 1 694 #define NPC_MCAM_HIGHER_PRIO 2 695 u8 priority; /* Lower or higher w.r.t ref_entry */ 696 u16 ref_entry; 697 u16 count; /* Number of entries requested */ 698 }; 699 700 struct npc_mcam_alloc_entry_rsp { 701 struct mbox_msghdr hdr; 702 u16 entry; /* Entry allocated or start index if contiguous. 703 * Invalid incase of non-contiguous. 704 */ 705 u16 count; /* Number of entries allocated */ 706 u16 free_count; /* Number of entries available */ 707 u16 entry_list[NPC_MAX_NONCONTIG_ENTRIES]; 708 }; 709 710 struct npc_mcam_free_entry_req { 711 struct mbox_msghdr hdr; 712 u16 entry; /* Entry index to be freed */ 713 u8 all; /* If all entries allocated to this PFVF to be freed */ 714 }; 715 716 struct mcam_entry { 717 #define NPC_MAX_KWS_IN_KEY 7 /* Number of keywords in max keywidth */ 718 u64 kw[NPC_MAX_KWS_IN_KEY]; 719 u64 kw_mask[NPC_MAX_KWS_IN_KEY]; 720 u64 action; 721 u64 vtag_action; 722 }; 723 724 struct npc_mcam_write_entry_req { 725 struct mbox_msghdr hdr; 726 struct mcam_entry entry_data; 727 u16 entry; /* MCAM entry to write this match key */ 728 u16 cntr; /* Counter for this MCAM entry */ 729 u8 intf; /* Rx or Tx interface */ 730 u8 enable_entry;/* Enable this MCAM entry ? */ 731 u8 set_cntr; /* Set counter for this entry ? */ 732 }; 733 734 /* Enable/Disable a given entry */ 735 struct npc_mcam_ena_dis_entry_req { 736 struct mbox_msghdr hdr; 737 u16 entry; 738 }; 739 740 struct npc_mcam_shift_entry_req { 741 struct mbox_msghdr hdr; 742 #define NPC_MCAM_MAX_SHIFTS 64 743 u16 curr_entry[NPC_MCAM_MAX_SHIFTS]; 744 u16 new_entry[NPC_MCAM_MAX_SHIFTS]; 745 u16 shift_count; /* Number of entries to shift */ 746 }; 747 748 struct npc_mcam_shift_entry_rsp { 749 struct mbox_msghdr hdr; 750 u16 failed_entry_idx; /* Index in 'curr_entry', not entry itself */ 751 }; 752 753 struct npc_mcam_alloc_counter_req { 754 struct mbox_msghdr hdr; 755 u8 contig; /* Contiguous counters ? */ 756 #define NPC_MAX_NONCONTIG_COUNTERS 64 757 u16 count; /* Number of counters requested */ 758 }; 759 760 struct npc_mcam_alloc_counter_rsp { 761 struct mbox_msghdr hdr; 762 u16 cntr; /* Counter allocated or start index if contiguous. 763 * Invalid incase of non-contiguous. 764 */ 765 u16 count; /* Number of counters allocated */ 766 u16 cntr_list[NPC_MAX_NONCONTIG_COUNTERS]; 767 }; 768 769 struct npc_mcam_oper_counter_req { 770 struct mbox_msghdr hdr; 771 u16 cntr; /* Free a counter or clear/fetch it's stats */ 772 }; 773 774 struct npc_mcam_oper_counter_rsp { 775 struct mbox_msghdr hdr; 776 u64 stat; /* valid only while fetching counter's stats */ 777 }; 778 779 struct npc_mcam_unmap_counter_req { 780 struct mbox_msghdr hdr; 781 u16 cntr; 782 u16 entry; /* Entry and counter to be unmapped */ 783 u8 all; /* Unmap all entries using this counter ? */ 784 }; 785 786 struct npc_mcam_alloc_and_write_entry_req { 787 struct mbox_msghdr hdr; 788 struct mcam_entry entry_data; 789 u16 ref_entry; 790 u8 priority; /* Lower or higher w.r.t ref_entry */ 791 u8 intf; /* Rx or Tx interface */ 792 u8 enable_entry;/* Enable this MCAM entry ? */ 793 u8 alloc_cntr; /* Allocate counter and map ? */ 794 }; 795 796 struct npc_mcam_alloc_and_write_entry_rsp { 797 struct mbox_msghdr hdr; 798 u16 entry; 799 u16 cntr; 800 }; 801 802 struct npc_get_kex_cfg_rsp { 803 struct mbox_msghdr hdr; 804 u64 rx_keyx_cfg; /* NPC_AF_INTF(0)_KEX_CFG */ 805 u64 tx_keyx_cfg; /* NPC_AF_INTF(1)_KEX_CFG */ 806 #define NPC_MAX_INTF 2 807 #define NPC_MAX_LID 8 808 #define NPC_MAX_LT 16 809 #define NPC_MAX_LD 2 810 #define NPC_MAX_LFL 16 811 /* NPC_AF_KEX_LDATA(0..1)_FLAGS_CFG */ 812 u64 kex_ld_flags[NPC_MAX_LD]; 813 /* NPC_AF_INTF(0..1)_LID(0..7)_LT(0..15)_LD(0..1)_CFG */ 814 u64 intf_lid_lt_ld[NPC_MAX_INTF][NPC_MAX_LID][NPC_MAX_LT][NPC_MAX_LD]; 815 /* NPC_AF_INTF(0..1)_LDATA(0..1)_FLAGS(0..15)_CFG */ 816 u64 intf_ld_flags[NPC_MAX_INTF][NPC_MAX_LD][NPC_MAX_LFL]; 817 #define MKEX_NAME_LEN 128 818 u8 mkex_pfl_name[MKEX_NAME_LEN]; 819 }; 820 821 #endif /* MBOX_H */ 822