1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Marvell OcteonTx2 RVU Admin Function driver 3 * 4 * Copyright (C) 2018 Marvell International Ltd. 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 */ 10 11 #ifndef MBOX_H 12 #define MBOX_H 13 14 #include <linux/etherdevice.h> 15 #include <linux/sizes.h> 16 17 #include "rvu_struct.h" 18 #include "common.h" 19 20 #define MBOX_SIZE SZ_64K 21 22 /* AF/PF: PF initiated, PF/VF VF initiated */ 23 #define MBOX_DOWN_RX_START 0 24 #define MBOX_DOWN_RX_SIZE (46 * SZ_1K) 25 #define MBOX_DOWN_TX_START (MBOX_DOWN_RX_START + MBOX_DOWN_RX_SIZE) 26 #define MBOX_DOWN_TX_SIZE (16 * SZ_1K) 27 /* AF/PF: AF initiated, PF/VF PF initiated */ 28 #define MBOX_UP_RX_START (MBOX_DOWN_TX_START + MBOX_DOWN_TX_SIZE) 29 #define MBOX_UP_RX_SIZE SZ_1K 30 #define MBOX_UP_TX_START (MBOX_UP_RX_START + MBOX_UP_RX_SIZE) 31 #define MBOX_UP_TX_SIZE SZ_1K 32 33 #if MBOX_UP_TX_SIZE + MBOX_UP_TX_START != MBOX_SIZE 34 # error "incorrect mailbox area sizes" 35 #endif 36 37 #define INTR_MASK(pfvfs) ((pfvfs < 64) ? (BIT_ULL(pfvfs) - 1) : (~0ull)) 38 39 #define MBOX_RSP_TIMEOUT 3000 /* Time(ms) to wait for mbox response */ 40 41 #define MBOX_MSG_ALIGN 16 /* Align mbox msg start to 16bytes */ 42 43 /* Mailbox directions */ 44 #define MBOX_DIR_AFPF 0 /* AF replies to PF */ 45 #define MBOX_DIR_PFAF 1 /* PF sends messages to AF */ 46 #define MBOX_DIR_PFVF 2 /* PF replies to VF */ 47 #define MBOX_DIR_VFPF 3 /* VF sends messages to PF */ 48 #define MBOX_DIR_AFPF_UP 4 /* AF sends messages to PF */ 49 #define MBOX_DIR_PFAF_UP 5 /* PF replies to AF */ 50 #define MBOX_DIR_PFVF_UP 6 /* PF sends messages to VF */ 51 #define MBOX_DIR_VFPF_UP 7 /* VF replies to PF */ 52 53 struct otx2_mbox_dev { 54 void *mbase; /* This dev's mbox region */ 55 void *hwbase; 56 spinlock_t mbox_lock; 57 u16 msg_size; /* Total msg size to be sent */ 58 u16 rsp_size; /* Total rsp size to be sure the reply is ok */ 59 u16 num_msgs; /* No of msgs sent or waiting for response */ 60 u16 msgs_acked; /* No of msgs for which response is received */ 61 }; 62 63 struct otx2_mbox { 64 struct pci_dev *pdev; 65 void *hwbase; /* Mbox region advertised by HW */ 66 void *reg_base;/* CSR base for this dev */ 67 u64 trigger; /* Trigger mbox notification */ 68 u16 tr_shift; /* Mbox trigger shift */ 69 u64 rx_start; /* Offset of Rx region in mbox memory */ 70 u64 tx_start; /* Offset of Tx region in mbox memory */ 71 u16 rx_size; /* Size of Rx region */ 72 u16 tx_size; /* Size of Tx region */ 73 u16 ndevs; /* The number of peers */ 74 struct otx2_mbox_dev *dev; 75 }; 76 77 /* Header which precedes all mbox messages */ 78 struct mbox_hdr { 79 u64 msg_size; /* Total msgs size embedded */ 80 u16 num_msgs; /* No of msgs embedded */ 81 }; 82 83 /* Header which precedes every msg and is also part of it */ 84 struct mbox_msghdr { 85 u16 pcifunc; /* Who's sending this msg */ 86 u16 id; /* Mbox message ID */ 87 #define OTX2_MBOX_REQ_SIG (0xdead) 88 #define OTX2_MBOX_RSP_SIG (0xbeef) 89 u16 sig; /* Signature, for validating corrupted msgs */ 90 #define OTX2_MBOX_VERSION (0x0007) 91 u16 ver; /* Version of msg's structure for this ID */ 92 u16 next_msgoff; /* Offset of next msg within mailbox region */ 93 int rc; /* Msg process'ed response code */ 94 }; 95 96 void otx2_mbox_reset(struct otx2_mbox *mbox, int devid); 97 void __otx2_mbox_reset(struct otx2_mbox *mbox, int devid); 98 void otx2_mbox_destroy(struct otx2_mbox *mbox); 99 int otx2_mbox_init(struct otx2_mbox *mbox, void __force *hwbase, 100 struct pci_dev *pdev, void __force *reg_base, 101 int direction, int ndevs); 102 int otx2_mbox_regions_init(struct otx2_mbox *mbox, void __force **hwbase, 103 struct pci_dev *pdev, void __force *reg_base, 104 int direction, int ndevs); 105 void otx2_mbox_msg_send(struct otx2_mbox *mbox, int devid); 106 int otx2_mbox_wait_for_rsp(struct otx2_mbox *mbox, int devid); 107 int otx2_mbox_busy_poll_for_rsp(struct otx2_mbox *mbox, int devid); 108 struct mbox_msghdr *otx2_mbox_alloc_msg_rsp(struct otx2_mbox *mbox, int devid, 109 int size, int size_rsp); 110 struct mbox_msghdr *otx2_mbox_get_rsp(struct otx2_mbox *mbox, int devid, 111 struct mbox_msghdr *msg); 112 int otx2_mbox_check_rsp_msgs(struct otx2_mbox *mbox, int devid); 113 int otx2_reply_invalid_msg(struct otx2_mbox *mbox, int devid, 114 u16 pcifunc, u16 id); 115 bool otx2_mbox_nonempty(struct otx2_mbox *mbox, int devid); 116 const char *otx2_mbox_id2name(u16 id); 117 static inline struct mbox_msghdr *otx2_mbox_alloc_msg(struct otx2_mbox *mbox, 118 int devid, int size) 119 { 120 return otx2_mbox_alloc_msg_rsp(mbox, devid, size, 0); 121 } 122 123 /* Mailbox message types */ 124 #define MBOX_MSG_MASK 0xFFFF 125 #define MBOX_MSG_INVALID 0xFFFE 126 #define MBOX_MSG_MAX 0xFFFF 127 128 #define MBOX_MESSAGES \ 129 /* Generic mbox IDs (range 0x000 - 0x1FF) */ \ 130 M(READY, 0x001, ready, msg_req, ready_msg_rsp) \ 131 M(ATTACH_RESOURCES, 0x002, attach_resources, rsrc_attach, msg_rsp) \ 132 M(DETACH_RESOURCES, 0x003, detach_resources, rsrc_detach, msg_rsp) \ 133 M(MSIX_OFFSET, 0x005, msix_offset, msg_req, msix_offset_rsp) \ 134 M(VF_FLR, 0x006, vf_flr, msg_req, msg_rsp) \ 135 M(PTP_OP, 0x007, ptp_op, ptp_req, ptp_rsp) \ 136 M(GET_HW_CAP, 0x008, get_hw_cap, msg_req, get_hw_cap_rsp) \ 137 /* CGX mbox IDs (range 0x200 - 0x3FF) */ \ 138 M(CGX_START_RXTX, 0x200, cgx_start_rxtx, msg_req, msg_rsp) \ 139 M(CGX_STOP_RXTX, 0x201, cgx_stop_rxtx, msg_req, msg_rsp) \ 140 M(CGX_STATS, 0x202, cgx_stats, msg_req, cgx_stats_rsp) \ 141 M(CGX_MAC_ADDR_SET, 0x203, cgx_mac_addr_set, cgx_mac_addr_set_or_get, \ 142 cgx_mac_addr_set_or_get) \ 143 M(CGX_MAC_ADDR_GET, 0x204, cgx_mac_addr_get, cgx_mac_addr_set_or_get, \ 144 cgx_mac_addr_set_or_get) \ 145 M(CGX_PROMISC_ENABLE, 0x205, cgx_promisc_enable, msg_req, msg_rsp) \ 146 M(CGX_PROMISC_DISABLE, 0x206, cgx_promisc_disable, msg_req, msg_rsp) \ 147 M(CGX_START_LINKEVENTS, 0x207, cgx_start_linkevents, msg_req, msg_rsp) \ 148 M(CGX_STOP_LINKEVENTS, 0x208, cgx_stop_linkevents, msg_req, msg_rsp) \ 149 M(CGX_GET_LINKINFO, 0x209, cgx_get_linkinfo, msg_req, cgx_link_info_msg) \ 150 M(CGX_INTLBK_ENABLE, 0x20A, cgx_intlbk_enable, msg_req, msg_rsp) \ 151 M(CGX_INTLBK_DISABLE, 0x20B, cgx_intlbk_disable, msg_req, msg_rsp) \ 152 M(CGX_PTP_RX_ENABLE, 0x20C, cgx_ptp_rx_enable, msg_req, msg_rsp) \ 153 M(CGX_PTP_RX_DISABLE, 0x20D, cgx_ptp_rx_disable, msg_req, msg_rsp) \ 154 M(CGX_CFG_PAUSE_FRM, 0x20E, cgx_cfg_pause_frm, cgx_pause_frm_cfg, \ 155 cgx_pause_frm_cfg) \ 156 M(CGX_FEC_SET, 0x210, cgx_set_fec_param, fec_mode, fec_mode) \ 157 M(CGX_FEC_STATS, 0x211, cgx_fec_stats, msg_req, cgx_fec_stats_rsp) \ 158 M(CGX_GET_PHY_FEC_STATS, 0x212, cgx_get_phy_fec_stats, msg_req, msg_rsp) \ 159 M(CGX_FW_DATA_GET, 0x213, cgx_get_aux_link_info, msg_req, cgx_fw_data) \ 160 M(CGX_SET_LINK_MODE, 0x214, cgx_set_link_mode, cgx_set_link_mode_req,\ 161 cgx_set_link_mode_rsp) \ 162 M(CGX_FEATURES_GET, 0x215, cgx_features_get, msg_req, \ 163 cgx_features_info_msg) \ 164 M(RPM_STATS, 0x216, rpm_stats, msg_req, rpm_stats_rsp) \ 165 /* NPA mbox IDs (range 0x400 - 0x5FF) */ \ 166 /* NPA mbox IDs (range 0x400 - 0x5FF) */ \ 167 M(NPA_LF_ALLOC, 0x400, npa_lf_alloc, \ 168 npa_lf_alloc_req, npa_lf_alloc_rsp) \ 169 M(NPA_LF_FREE, 0x401, npa_lf_free, msg_req, msg_rsp) \ 170 M(NPA_AQ_ENQ, 0x402, npa_aq_enq, npa_aq_enq_req, npa_aq_enq_rsp) \ 171 M(NPA_HWCTX_DISABLE, 0x403, npa_hwctx_disable, hwctx_disable_req, msg_rsp)\ 172 /* SSO/SSOW mbox IDs (range 0x600 - 0x7FF) */ \ 173 /* TIM mbox IDs (range 0x800 - 0x9FF) */ \ 174 /* CPT mbox IDs (range 0xA00 - 0xBFF) */ \ 175 M(CPT_LF_ALLOC, 0xA00, cpt_lf_alloc, cpt_lf_alloc_req_msg, \ 176 msg_rsp) \ 177 M(CPT_LF_FREE, 0xA01, cpt_lf_free, msg_req, msg_rsp) \ 178 M(CPT_RD_WR_REGISTER, 0xA02, cpt_rd_wr_register, cpt_rd_wr_reg_msg, \ 179 cpt_rd_wr_reg_msg) \ 180 M(CPT_STATS, 0xA05, cpt_sts, cpt_sts_req, cpt_sts_rsp) \ 181 M(CPT_RXC_TIME_CFG, 0xA06, cpt_rxc_time_cfg, cpt_rxc_time_cfg_req, \ 182 msg_rsp) \ 183 /* NPC mbox IDs (range 0x6000 - 0x7FFF) */ \ 184 M(NPC_MCAM_ALLOC_ENTRY, 0x6000, npc_mcam_alloc_entry, npc_mcam_alloc_entry_req,\ 185 npc_mcam_alloc_entry_rsp) \ 186 M(NPC_MCAM_FREE_ENTRY, 0x6001, npc_mcam_free_entry, \ 187 npc_mcam_free_entry_req, msg_rsp) \ 188 M(NPC_MCAM_WRITE_ENTRY, 0x6002, npc_mcam_write_entry, \ 189 npc_mcam_write_entry_req, msg_rsp) \ 190 M(NPC_MCAM_ENA_ENTRY, 0x6003, npc_mcam_ena_entry, \ 191 npc_mcam_ena_dis_entry_req, msg_rsp) \ 192 M(NPC_MCAM_DIS_ENTRY, 0x6004, npc_mcam_dis_entry, \ 193 npc_mcam_ena_dis_entry_req, msg_rsp) \ 194 M(NPC_MCAM_SHIFT_ENTRY, 0x6005, npc_mcam_shift_entry, npc_mcam_shift_entry_req,\ 195 npc_mcam_shift_entry_rsp) \ 196 M(NPC_MCAM_ALLOC_COUNTER, 0x6006, npc_mcam_alloc_counter, \ 197 npc_mcam_alloc_counter_req, \ 198 npc_mcam_alloc_counter_rsp) \ 199 M(NPC_MCAM_FREE_COUNTER, 0x6007, npc_mcam_free_counter, \ 200 npc_mcam_oper_counter_req, msg_rsp) \ 201 M(NPC_MCAM_UNMAP_COUNTER, 0x6008, npc_mcam_unmap_counter, \ 202 npc_mcam_unmap_counter_req, msg_rsp) \ 203 M(NPC_MCAM_CLEAR_COUNTER, 0x6009, npc_mcam_clear_counter, \ 204 npc_mcam_oper_counter_req, msg_rsp) \ 205 M(NPC_MCAM_COUNTER_STATS, 0x600a, npc_mcam_counter_stats, \ 206 npc_mcam_oper_counter_req, \ 207 npc_mcam_oper_counter_rsp) \ 208 M(NPC_MCAM_ALLOC_AND_WRITE_ENTRY, 0x600b, npc_mcam_alloc_and_write_entry, \ 209 npc_mcam_alloc_and_write_entry_req, \ 210 npc_mcam_alloc_and_write_entry_rsp) \ 211 M(NPC_GET_KEX_CFG, 0x600c, npc_get_kex_cfg, \ 212 msg_req, npc_get_kex_cfg_rsp) \ 213 M(NPC_INSTALL_FLOW, 0x600d, npc_install_flow, \ 214 npc_install_flow_req, npc_install_flow_rsp) \ 215 M(NPC_DELETE_FLOW, 0x600e, npc_delete_flow, \ 216 npc_delete_flow_req, msg_rsp) \ 217 M(NPC_MCAM_READ_ENTRY, 0x600f, npc_mcam_read_entry, \ 218 npc_mcam_read_entry_req, \ 219 npc_mcam_read_entry_rsp) \ 220 M(NPC_MCAM_READ_BASE_RULE, 0x6011, npc_read_base_steer_rule, \ 221 msg_req, npc_mcam_read_base_rule_rsp) \ 222 M(NPC_MCAM_GET_STATS, 0x6012, npc_mcam_entry_stats, \ 223 npc_mcam_get_stats_req, \ 224 npc_mcam_get_stats_rsp) \ 225 /* NIX mbox IDs (range 0x8000 - 0xFFFF) */ \ 226 M(NIX_LF_ALLOC, 0x8000, nix_lf_alloc, \ 227 nix_lf_alloc_req, nix_lf_alloc_rsp) \ 228 M(NIX_LF_FREE, 0x8001, nix_lf_free, nix_lf_free_req, msg_rsp) \ 229 M(NIX_AQ_ENQ, 0x8002, nix_aq_enq, nix_aq_enq_req, nix_aq_enq_rsp) \ 230 M(NIX_HWCTX_DISABLE, 0x8003, nix_hwctx_disable, \ 231 hwctx_disable_req, msg_rsp) \ 232 M(NIX_TXSCH_ALLOC, 0x8004, nix_txsch_alloc, \ 233 nix_txsch_alloc_req, nix_txsch_alloc_rsp) \ 234 M(NIX_TXSCH_FREE, 0x8005, nix_txsch_free, nix_txsch_free_req, msg_rsp) \ 235 M(NIX_TXSCHQ_CFG, 0x8006, nix_txschq_cfg, nix_txschq_config, msg_rsp) \ 236 M(NIX_STATS_RST, 0x8007, nix_stats_rst, msg_req, msg_rsp) \ 237 M(NIX_VTAG_CFG, 0x8008, nix_vtag_cfg, nix_vtag_config, \ 238 nix_vtag_config_rsp) \ 239 M(NIX_RSS_FLOWKEY_CFG, 0x8009, nix_rss_flowkey_cfg, \ 240 nix_rss_flowkey_cfg, \ 241 nix_rss_flowkey_cfg_rsp) \ 242 M(NIX_SET_MAC_ADDR, 0x800a, nix_set_mac_addr, nix_set_mac_addr, msg_rsp) \ 243 M(NIX_SET_RX_MODE, 0x800b, nix_set_rx_mode, nix_rx_mode, msg_rsp) \ 244 M(NIX_SET_HW_FRS, 0x800c, nix_set_hw_frs, nix_frs_cfg, msg_rsp) \ 245 M(NIX_LF_START_RX, 0x800d, nix_lf_start_rx, msg_req, msg_rsp) \ 246 M(NIX_LF_STOP_RX, 0x800e, nix_lf_stop_rx, msg_req, msg_rsp) \ 247 M(NIX_MARK_FORMAT_CFG, 0x800f, nix_mark_format_cfg, \ 248 nix_mark_format_cfg, \ 249 nix_mark_format_cfg_rsp) \ 250 M(NIX_SET_RX_CFG, 0x8010, nix_set_rx_cfg, nix_rx_cfg, msg_rsp) \ 251 M(NIX_LSO_FORMAT_CFG, 0x8011, nix_lso_format_cfg, \ 252 nix_lso_format_cfg, \ 253 nix_lso_format_cfg_rsp) \ 254 M(NIX_LF_PTP_TX_ENABLE, 0x8013, nix_lf_ptp_tx_enable, msg_req, msg_rsp) \ 255 M(NIX_LF_PTP_TX_DISABLE, 0x8014, nix_lf_ptp_tx_disable, msg_req, msg_rsp) \ 256 M(NIX_BP_ENABLE, 0x8016, nix_bp_enable, nix_bp_cfg_req, \ 257 nix_bp_cfg_rsp) \ 258 M(NIX_BP_DISABLE, 0x8017, nix_bp_disable, nix_bp_cfg_req, msg_rsp) \ 259 M(NIX_GET_MAC_ADDR, 0x8018, nix_get_mac_addr, msg_req, nix_get_mac_addr_rsp) \ 260 M(NIX_CN10K_AQ_ENQ, 0x8019, nix_cn10k_aq_enq, nix_cn10k_aq_enq_req, \ 261 nix_cn10k_aq_enq_rsp) \ 262 M(NIX_GET_HW_INFO, 0x801a, nix_get_hw_info, msg_req, nix_hw_info) 263 264 /* Messages initiated by AF (range 0xC00 - 0xDFF) */ 265 #define MBOX_UP_CGX_MESSAGES \ 266 M(CGX_LINK_EVENT, 0xC00, cgx_link_event, cgx_link_info_msg, msg_rsp) 267 268 enum { 269 #define M(_name, _id, _1, _2, _3) MBOX_MSG_ ## _name = _id, 270 MBOX_MESSAGES 271 MBOX_UP_CGX_MESSAGES 272 #undef M 273 }; 274 275 /* Mailbox message formats */ 276 277 #define RVU_DEFAULT_PF_FUNC 0xFFFF 278 279 /* Generic request msg used for those mbox messages which 280 * don't send any data in the request. 281 */ 282 struct msg_req { 283 struct mbox_msghdr hdr; 284 }; 285 286 /* Generic response msg used an ack or response for those mbox 287 * messages which don't have a specific rsp msg format. 288 */ 289 struct msg_rsp { 290 struct mbox_msghdr hdr; 291 }; 292 293 /* RVU mailbox error codes 294 * Range 256 - 300. 295 */ 296 enum rvu_af_status { 297 RVU_INVALID_VF_ID = -256, 298 }; 299 300 struct ready_msg_rsp { 301 struct mbox_msghdr hdr; 302 u16 sclk_freq; /* SCLK frequency (in MHz) */ 303 u16 rclk_freq; /* RCLK frequency (in MHz) */ 304 }; 305 306 /* Structure for requesting resource provisioning. 307 * 'modify' flag to be used when either requesting more 308 * or to detach partial of a certain resource type. 309 * Rest of the fields specify how many of what type to 310 * be attached. 311 * To request LFs from two blocks of same type this mailbox 312 * can be sent twice as below: 313 * struct rsrc_attach *attach; 314 * .. Allocate memory for message .. 315 * attach->cptlfs = 3; <3 LFs from CPT0> 316 * .. Send message .. 317 * .. Allocate memory for message .. 318 * attach->modify = 1; 319 * attach->cpt_blkaddr = BLKADDR_CPT1; 320 * attach->cptlfs = 2; <2 LFs from CPT1> 321 * .. Send message .. 322 */ 323 struct rsrc_attach { 324 struct mbox_msghdr hdr; 325 u8 modify:1; 326 u8 npalf:1; 327 u8 nixlf:1; 328 u16 sso; 329 u16 ssow; 330 u16 timlfs; 331 u16 cptlfs; 332 int cpt_blkaddr; /* BLKADDR_CPT0/BLKADDR_CPT1 or 0 for BLKADDR_CPT0 */ 333 }; 334 335 /* Structure for relinquishing resources. 336 * 'partial' flag to be used when relinquishing all resources 337 * but only of a certain type. If not set, all resources of all 338 * types provisioned to the RVU function will be detached. 339 */ 340 struct rsrc_detach { 341 struct mbox_msghdr hdr; 342 u8 partial:1; 343 u8 npalf:1; 344 u8 nixlf:1; 345 u8 sso:1; 346 u8 ssow:1; 347 u8 timlfs:1; 348 u8 cptlfs:1; 349 }; 350 351 #define MSIX_VECTOR_INVALID 0xFFFF 352 #define MAX_RVU_BLKLF_CNT 256 353 354 struct msix_offset_rsp { 355 struct mbox_msghdr hdr; 356 u16 npa_msixoff; 357 u16 nix_msixoff; 358 u8 sso; 359 u8 ssow; 360 u8 timlfs; 361 u8 cptlfs; 362 u16 sso_msixoff[MAX_RVU_BLKLF_CNT]; 363 u16 ssow_msixoff[MAX_RVU_BLKLF_CNT]; 364 u16 timlf_msixoff[MAX_RVU_BLKLF_CNT]; 365 u16 cptlf_msixoff[MAX_RVU_BLKLF_CNT]; 366 u8 cpt1_lfs; 367 u16 cpt1_lf_msixoff[MAX_RVU_BLKLF_CNT]; 368 }; 369 370 struct get_hw_cap_rsp { 371 struct mbox_msghdr hdr; 372 u8 nix_fixed_txschq_mapping; /* Schq mapping fixed or flexible */ 373 u8 nix_shaping; /* Is shaping and coloring supported */ 374 }; 375 376 /* CGX mbox message formats */ 377 378 struct cgx_stats_rsp { 379 struct mbox_msghdr hdr; 380 #define CGX_RX_STATS_COUNT 9 381 #define CGX_TX_STATS_COUNT 18 382 u64 rx_stats[CGX_RX_STATS_COUNT]; 383 u64 tx_stats[CGX_TX_STATS_COUNT]; 384 }; 385 386 struct cgx_fec_stats_rsp { 387 struct mbox_msghdr hdr; 388 u64 fec_corr_blks; 389 u64 fec_uncorr_blks; 390 }; 391 /* Structure for requesting the operation for 392 * setting/getting mac address in the CGX interface 393 */ 394 struct cgx_mac_addr_set_or_get { 395 struct mbox_msghdr hdr; 396 u8 mac_addr[ETH_ALEN]; 397 }; 398 399 struct cgx_link_user_info { 400 uint64_t link_up:1; 401 uint64_t full_duplex:1; 402 uint64_t lmac_type_id:4; 403 uint64_t speed:20; /* speed in Mbps */ 404 uint64_t an:1; /* AN supported or not */ 405 uint64_t fec:2; /* FEC type if enabled else 0 */ 406 #define LMACTYPE_STR_LEN 16 407 char lmac_type[LMACTYPE_STR_LEN]; 408 }; 409 410 struct cgx_link_info_msg { 411 struct mbox_msghdr hdr; 412 struct cgx_link_user_info link_info; 413 }; 414 415 struct cgx_pause_frm_cfg { 416 struct mbox_msghdr hdr; 417 u8 set; 418 /* set = 1 if the request is to config pause frames */ 419 /* set = 0 if the request is to fetch pause frames config */ 420 u8 rx_pause; 421 u8 tx_pause; 422 }; 423 424 enum fec_type { 425 OTX2_FEC_NONE, 426 OTX2_FEC_BASER, 427 OTX2_FEC_RS, 428 OTX2_FEC_STATS_CNT = 2, 429 OTX2_FEC_OFF, 430 }; 431 432 struct fec_mode { 433 struct mbox_msghdr hdr; 434 int fec; 435 }; 436 437 struct sfp_eeprom_s { 438 #define SFP_EEPROM_SIZE 256 439 u16 sff_id; 440 u8 buf[SFP_EEPROM_SIZE]; 441 u64 reserved; 442 }; 443 444 struct phy_s { 445 struct { 446 u64 can_change_mod_type:1; 447 u64 mod_type:1; 448 u64 has_fec_stats:1; 449 } misc; 450 struct fec_stats_s { 451 u32 rsfec_corr_cws; 452 u32 rsfec_uncorr_cws; 453 u32 brfec_corr_blks; 454 u32 brfec_uncorr_blks; 455 } fec_stats; 456 }; 457 458 struct cgx_lmac_fwdata_s { 459 u16 rw_valid; 460 u64 supported_fec; 461 u64 supported_an; 462 u64 supported_link_modes; 463 /* only applicable if AN is supported */ 464 u64 advertised_fec; 465 u64 advertised_link_modes; 466 /* Only applicable if SFP/QSFP slot is present */ 467 struct sfp_eeprom_s sfp_eeprom; 468 struct phy_s phy; 469 #define LMAC_FWDATA_RESERVED_MEM 1021 470 u64 reserved[LMAC_FWDATA_RESERVED_MEM]; 471 }; 472 473 struct cgx_fw_data { 474 struct mbox_msghdr hdr; 475 struct cgx_lmac_fwdata_s fwdata; 476 }; 477 478 struct cgx_set_link_mode_args { 479 u32 speed; 480 u8 duplex; 481 u8 an; 482 u8 ports; 483 u64 mode; 484 }; 485 486 struct cgx_set_link_mode_req { 487 #define AUTONEG_UNKNOWN 0xff 488 struct mbox_msghdr hdr; 489 struct cgx_set_link_mode_args args; 490 }; 491 492 struct cgx_set_link_mode_rsp { 493 struct mbox_msghdr hdr; 494 int status; 495 }; 496 497 #define RVU_LMAC_FEAT_FC BIT_ULL(0) /* pause frames */ 498 #define RVU_LMAC_FEAT_PTP BIT_ULL(1) /* precision time protocol */ 499 #define RVU_MAC_VERSION BIT_ULL(2) 500 #define RVU_MAC_CGX BIT_ULL(3) 501 #define RVU_MAC_RPM BIT_ULL(4) 502 503 struct cgx_features_info_msg { 504 struct mbox_msghdr hdr; 505 u64 lmac_features; 506 }; 507 508 struct rpm_stats_rsp { 509 struct mbox_msghdr hdr; 510 #define RPM_RX_STATS_COUNT 43 511 #define RPM_TX_STATS_COUNT 34 512 u64 rx_stats[RPM_RX_STATS_COUNT]; 513 u64 tx_stats[RPM_TX_STATS_COUNT]; 514 }; 515 516 /* NPA mbox message formats */ 517 518 /* NPA mailbox error codes 519 * Range 301 - 400. 520 */ 521 enum npa_af_status { 522 NPA_AF_ERR_PARAM = -301, 523 NPA_AF_ERR_AQ_FULL = -302, 524 NPA_AF_ERR_AQ_ENQUEUE = -303, 525 NPA_AF_ERR_AF_LF_INVALID = -304, 526 NPA_AF_ERR_AF_LF_ALLOC = -305, 527 NPA_AF_ERR_LF_RESET = -306, 528 }; 529 530 /* For NPA LF context alloc and init */ 531 struct npa_lf_alloc_req { 532 struct mbox_msghdr hdr; 533 int node; 534 int aura_sz; /* No of auras */ 535 u32 nr_pools; /* No of pools */ 536 u64 way_mask; 537 }; 538 539 struct npa_lf_alloc_rsp { 540 struct mbox_msghdr hdr; 541 u32 stack_pg_ptrs; /* No of ptrs per stack page */ 542 u32 stack_pg_bytes; /* Size of stack page */ 543 u16 qints; /* NPA_AF_CONST::QINTS */ 544 }; 545 546 /* NPA AQ enqueue msg */ 547 struct npa_aq_enq_req { 548 struct mbox_msghdr hdr; 549 u32 aura_id; 550 u8 ctype; 551 u8 op; 552 union { 553 /* Valid when op == WRITE/INIT and ctype == AURA. 554 * LF fills the pool_id in aura.pool_addr. AF will translate 555 * the pool_id to pool context pointer. 556 */ 557 struct npa_aura_s aura; 558 /* Valid when op == WRITE/INIT and ctype == POOL */ 559 struct npa_pool_s pool; 560 }; 561 /* Mask data when op == WRITE (1=write, 0=don't write) */ 562 union { 563 /* Valid when op == WRITE and ctype == AURA */ 564 struct npa_aura_s aura_mask; 565 /* Valid when op == WRITE and ctype == POOL */ 566 struct npa_pool_s pool_mask; 567 }; 568 }; 569 570 struct npa_aq_enq_rsp { 571 struct mbox_msghdr hdr; 572 union { 573 /* Valid when op == READ and ctype == AURA */ 574 struct npa_aura_s aura; 575 /* Valid when op == READ and ctype == POOL */ 576 struct npa_pool_s pool; 577 }; 578 }; 579 580 /* Disable all contexts of type 'ctype' */ 581 struct hwctx_disable_req { 582 struct mbox_msghdr hdr; 583 u8 ctype; 584 }; 585 586 /* NIX mbox message formats */ 587 588 /* NIX mailbox error codes 589 * Range 401 - 500. 590 */ 591 enum nix_af_status { 592 NIX_AF_ERR_PARAM = -401, 593 NIX_AF_ERR_AQ_FULL = -402, 594 NIX_AF_ERR_AQ_ENQUEUE = -403, 595 NIX_AF_ERR_AF_LF_INVALID = -404, 596 NIX_AF_ERR_AF_LF_ALLOC = -405, 597 NIX_AF_ERR_TLX_ALLOC_FAIL = -406, 598 NIX_AF_ERR_TLX_INVALID = -407, 599 NIX_AF_ERR_RSS_SIZE_INVALID = -408, 600 NIX_AF_ERR_RSS_GRPS_INVALID = -409, 601 NIX_AF_ERR_FRS_INVALID = -410, 602 NIX_AF_ERR_RX_LINK_INVALID = -411, 603 NIX_AF_INVAL_TXSCHQ_CFG = -412, 604 NIX_AF_SMQ_FLUSH_FAILED = -413, 605 NIX_AF_ERR_LF_RESET = -414, 606 NIX_AF_ERR_RSS_NOSPC_FIELD = -415, 607 NIX_AF_ERR_RSS_NOSPC_ALGO = -416, 608 NIX_AF_ERR_MARK_CFG_FAIL = -417, 609 NIX_AF_ERR_LSO_CFG_FAIL = -418, 610 NIX_AF_INVAL_NPA_PF_FUNC = -419, 611 NIX_AF_INVAL_SSO_PF_FUNC = -420, 612 NIX_AF_ERR_TX_VTAG_NOSPC = -421, 613 NIX_AF_ERR_RX_VTAG_INUSE = -422, 614 NIX_AF_ERR_NPC_KEY_NOT_SUPP = -423, 615 }; 616 617 /* For NIX RX vtag action */ 618 enum nix_rx_vtag0_type { 619 NIX_AF_LFX_RX_VTAG_TYPE0, /* reserved for rx vlan offload */ 620 NIX_AF_LFX_RX_VTAG_TYPE1, 621 NIX_AF_LFX_RX_VTAG_TYPE2, 622 NIX_AF_LFX_RX_VTAG_TYPE3, 623 NIX_AF_LFX_RX_VTAG_TYPE4, 624 NIX_AF_LFX_RX_VTAG_TYPE5, 625 NIX_AF_LFX_RX_VTAG_TYPE6, 626 NIX_AF_LFX_RX_VTAG_TYPE7, 627 }; 628 629 /* For NIX LF context alloc and init */ 630 struct nix_lf_alloc_req { 631 struct mbox_msghdr hdr; 632 int node; 633 u32 rq_cnt; /* No of receive queues */ 634 u32 sq_cnt; /* No of send queues */ 635 u32 cq_cnt; /* No of completion queues */ 636 u8 xqe_sz; 637 u16 rss_sz; 638 u8 rss_grps; 639 u16 npa_func; 640 u16 sso_func; 641 u64 rx_cfg; /* See NIX_AF_LF(0..127)_RX_CFG */ 642 u64 way_mask; 643 }; 644 645 struct nix_lf_alloc_rsp { 646 struct mbox_msghdr hdr; 647 u16 sqb_size; 648 u16 rx_chan_base; 649 u16 tx_chan_base; 650 u8 rx_chan_cnt; /* total number of RX channels */ 651 u8 tx_chan_cnt; /* total number of TX channels */ 652 u8 lso_tsov4_idx; 653 u8 lso_tsov6_idx; 654 u8 mac_addr[ETH_ALEN]; 655 u8 lf_rx_stats; /* NIX_AF_CONST1::LF_RX_STATS */ 656 u8 lf_tx_stats; /* NIX_AF_CONST1::LF_TX_STATS */ 657 u16 cints; /* NIX_AF_CONST2::CINTS */ 658 u16 qints; /* NIX_AF_CONST2::QINTS */ 659 u8 cgx_links; /* No. of CGX links present in HW */ 660 u8 lbk_links; /* No. of LBK links present in HW */ 661 u8 sdp_links; /* No. of SDP links present in HW */ 662 }; 663 664 struct nix_lf_free_req { 665 struct mbox_msghdr hdr; 666 #define NIX_LF_DISABLE_FLOWS BIT_ULL(0) 667 #define NIX_LF_DONT_FREE_TX_VTAG BIT_ULL(1) 668 u64 flags; 669 }; 670 671 /* CN10K NIX AQ enqueue msg */ 672 struct nix_cn10k_aq_enq_req { 673 struct mbox_msghdr hdr; 674 u32 qidx; 675 u8 ctype; 676 u8 op; 677 union { 678 struct nix_cn10k_rq_ctx_s rq; 679 struct nix_cn10k_sq_ctx_s sq; 680 struct nix_cq_ctx_s cq; 681 struct nix_rsse_s rss; 682 struct nix_rx_mce_s mce; 683 }; 684 union { 685 struct nix_cn10k_rq_ctx_s rq_mask; 686 struct nix_cn10k_sq_ctx_s sq_mask; 687 struct nix_cq_ctx_s cq_mask; 688 struct nix_rsse_s rss_mask; 689 struct nix_rx_mce_s mce_mask; 690 }; 691 }; 692 693 struct nix_cn10k_aq_enq_rsp { 694 struct mbox_msghdr hdr; 695 union { 696 struct nix_cn10k_rq_ctx_s rq; 697 struct nix_cn10k_sq_ctx_s sq; 698 struct nix_cq_ctx_s cq; 699 struct nix_rsse_s rss; 700 struct nix_rx_mce_s mce; 701 }; 702 }; 703 704 /* NIX AQ enqueue msg */ 705 struct nix_aq_enq_req { 706 struct mbox_msghdr hdr; 707 u32 qidx; 708 u8 ctype; 709 u8 op; 710 union { 711 struct nix_rq_ctx_s rq; 712 struct nix_sq_ctx_s sq; 713 struct nix_cq_ctx_s cq; 714 struct nix_rsse_s rss; 715 struct nix_rx_mce_s mce; 716 }; 717 union { 718 struct nix_rq_ctx_s rq_mask; 719 struct nix_sq_ctx_s sq_mask; 720 struct nix_cq_ctx_s cq_mask; 721 struct nix_rsse_s rss_mask; 722 struct nix_rx_mce_s mce_mask; 723 }; 724 }; 725 726 struct nix_aq_enq_rsp { 727 struct mbox_msghdr hdr; 728 union { 729 struct nix_rq_ctx_s rq; 730 struct nix_sq_ctx_s sq; 731 struct nix_cq_ctx_s cq; 732 struct nix_rsse_s rss; 733 struct nix_rx_mce_s mce; 734 }; 735 }; 736 737 /* Tx scheduler/shaper mailbox messages */ 738 739 #define MAX_TXSCHQ_PER_FUNC 128 740 741 struct nix_txsch_alloc_req { 742 struct mbox_msghdr hdr; 743 /* Scheduler queue count request at each level */ 744 u16 schq_contig[NIX_TXSCH_LVL_CNT]; /* No of contiguous queues */ 745 u16 schq[NIX_TXSCH_LVL_CNT]; /* No of non-contiguous queues */ 746 }; 747 748 struct nix_txsch_alloc_rsp { 749 struct mbox_msghdr hdr; 750 /* Scheduler queue count allocated at each level */ 751 u16 schq_contig[NIX_TXSCH_LVL_CNT]; 752 u16 schq[NIX_TXSCH_LVL_CNT]; 753 /* Scheduler queue list allocated at each level */ 754 u16 schq_contig_list[NIX_TXSCH_LVL_CNT][MAX_TXSCHQ_PER_FUNC]; 755 u16 schq_list[NIX_TXSCH_LVL_CNT][MAX_TXSCHQ_PER_FUNC]; 756 u8 aggr_level; /* Traffic aggregation scheduler level */ 757 u8 aggr_lvl_rr_prio; /* Aggregation lvl's RR_PRIO config */ 758 u8 link_cfg_lvl; /* LINKX_CFG CSRs mapped to TL3 or TL2's index ? */ 759 }; 760 761 struct nix_txsch_free_req { 762 struct mbox_msghdr hdr; 763 #define TXSCHQ_FREE_ALL BIT_ULL(0) 764 u16 flags; 765 /* Scheduler queue level to be freed */ 766 u16 schq_lvl; 767 /* List of scheduler queues to be freed */ 768 u16 schq; 769 }; 770 771 struct nix_txschq_config { 772 struct mbox_msghdr hdr; 773 u8 lvl; /* SMQ/MDQ/TL4/TL3/TL2/TL1 */ 774 #define TXSCHQ_IDX_SHIFT 16 775 #define TXSCHQ_IDX_MASK (BIT_ULL(10) - 1) 776 #define TXSCHQ_IDX(reg, shift) (((reg) >> (shift)) & TXSCHQ_IDX_MASK) 777 u8 num_regs; 778 #define MAX_REGS_PER_MBOX_MSG 20 779 u64 reg[MAX_REGS_PER_MBOX_MSG]; 780 u64 regval[MAX_REGS_PER_MBOX_MSG]; 781 }; 782 783 struct nix_vtag_config { 784 struct mbox_msghdr hdr; 785 /* '0' for 4 octet VTAG, '1' for 8 octet VTAG */ 786 u8 vtag_size; 787 /* cfg_type is '0' for tx vlan cfg 788 * cfg_type is '1' for rx vlan cfg 789 */ 790 u8 cfg_type; 791 union { 792 /* valid when cfg_type is '0' */ 793 struct { 794 u64 vtag0; 795 u64 vtag1; 796 797 /* cfg_vtag0 & cfg_vtag1 fields are valid 798 * when free_vtag0 & free_vtag1 are '0's. 799 */ 800 /* cfg_vtag0 = 1 to configure vtag0 */ 801 u8 cfg_vtag0 :1; 802 /* cfg_vtag1 = 1 to configure vtag1 */ 803 u8 cfg_vtag1 :1; 804 805 /* vtag0_idx & vtag1_idx are only valid when 806 * both cfg_vtag0 & cfg_vtag1 are '0's, 807 * these fields are used along with free_vtag0 808 * & free_vtag1 to free the nix lf's tx_vlan 809 * configuration. 810 * 811 * Denotes the indices of tx_vtag def registers 812 * that needs to be cleared and freed. 813 */ 814 int vtag0_idx; 815 int vtag1_idx; 816 817 /* free_vtag0 & free_vtag1 fields are valid 818 * when cfg_vtag0 & cfg_vtag1 are '0's. 819 */ 820 /* free_vtag0 = 1 clears vtag0 configuration 821 * vtag0_idx denotes the index to be cleared. 822 */ 823 u8 free_vtag0 :1; 824 /* free_vtag1 = 1 clears vtag1 configuration 825 * vtag1_idx denotes the index to be cleared. 826 */ 827 u8 free_vtag1 :1; 828 } tx; 829 830 /* valid when cfg_type is '1' */ 831 struct { 832 /* rx vtag type index, valid values are in 0..7 range */ 833 u8 vtag_type; 834 /* rx vtag strip */ 835 u8 strip_vtag :1; 836 /* rx vtag capture */ 837 u8 capture_vtag :1; 838 } rx; 839 }; 840 }; 841 842 struct nix_vtag_config_rsp { 843 struct mbox_msghdr hdr; 844 int vtag0_idx; 845 int vtag1_idx; 846 /* Indices of tx_vtag def registers used to configure 847 * tx vtag0 & vtag1 headers, these indices are valid 848 * when nix_vtag_config mbox requested for vtag0 and/ 849 * or vtag1 configuration. 850 */ 851 }; 852 853 struct nix_rss_flowkey_cfg { 854 struct mbox_msghdr hdr; 855 int mcam_index; /* MCAM entry index to modify */ 856 #define NIX_FLOW_KEY_TYPE_PORT BIT(0) 857 #define NIX_FLOW_KEY_TYPE_IPV4 BIT(1) 858 #define NIX_FLOW_KEY_TYPE_IPV6 BIT(2) 859 #define NIX_FLOW_KEY_TYPE_TCP BIT(3) 860 #define NIX_FLOW_KEY_TYPE_UDP BIT(4) 861 #define NIX_FLOW_KEY_TYPE_SCTP BIT(5) 862 #define NIX_FLOW_KEY_TYPE_NVGRE BIT(6) 863 #define NIX_FLOW_KEY_TYPE_VXLAN BIT(7) 864 #define NIX_FLOW_KEY_TYPE_GENEVE BIT(8) 865 #define NIX_FLOW_KEY_TYPE_ETH_DMAC BIT(9) 866 #define NIX_FLOW_KEY_TYPE_IPV6_EXT BIT(10) 867 #define NIX_FLOW_KEY_TYPE_GTPU BIT(11) 868 #define NIX_FLOW_KEY_TYPE_INNR_IPV4 BIT(12) 869 #define NIX_FLOW_KEY_TYPE_INNR_IPV6 BIT(13) 870 #define NIX_FLOW_KEY_TYPE_INNR_TCP BIT(14) 871 #define NIX_FLOW_KEY_TYPE_INNR_UDP BIT(15) 872 #define NIX_FLOW_KEY_TYPE_INNR_SCTP BIT(16) 873 #define NIX_FLOW_KEY_TYPE_INNR_ETH_DMAC BIT(17) 874 #define NIX_FLOW_KEY_TYPE_VLAN BIT(20) 875 #define NIX_FLOW_KEY_TYPE_IPV4_PROTO BIT(21) 876 #define NIX_FLOW_KEY_TYPE_AH BIT(22) 877 #define NIX_FLOW_KEY_TYPE_ESP BIT(23) 878 u32 flowkey_cfg; /* Flowkey types selected */ 879 u8 group; /* RSS context or group */ 880 }; 881 882 struct nix_rss_flowkey_cfg_rsp { 883 struct mbox_msghdr hdr; 884 u8 alg_idx; /* Selected algo index */ 885 }; 886 887 struct nix_set_mac_addr { 888 struct mbox_msghdr hdr; 889 u8 mac_addr[ETH_ALEN]; /* MAC address to be set for this pcifunc */ 890 }; 891 892 struct nix_get_mac_addr_rsp { 893 struct mbox_msghdr hdr; 894 u8 mac_addr[ETH_ALEN]; 895 }; 896 897 struct nix_mark_format_cfg { 898 struct mbox_msghdr hdr; 899 u8 offset; 900 u8 y_mask; 901 u8 y_val; 902 u8 r_mask; 903 u8 r_val; 904 }; 905 906 struct nix_mark_format_cfg_rsp { 907 struct mbox_msghdr hdr; 908 u8 mark_format_idx; 909 }; 910 911 struct nix_rx_mode { 912 struct mbox_msghdr hdr; 913 #define NIX_RX_MODE_UCAST BIT(0) 914 #define NIX_RX_MODE_PROMISC BIT(1) 915 #define NIX_RX_MODE_ALLMULTI BIT(2) 916 u16 mode; 917 }; 918 919 struct nix_rx_cfg { 920 struct mbox_msghdr hdr; 921 #define NIX_RX_OL3_VERIFY BIT(0) 922 #define NIX_RX_OL4_VERIFY BIT(1) 923 u8 len_verify; /* Outer L3/L4 len check */ 924 #define NIX_RX_CSUM_OL4_VERIFY BIT(0) 925 u8 csum_verify; /* Outer L4 checksum verification */ 926 }; 927 928 struct nix_frs_cfg { 929 struct mbox_msghdr hdr; 930 u8 update_smq; /* Update SMQ's min/max lens */ 931 u8 update_minlen; /* Set minlen also */ 932 u8 sdp_link; /* Set SDP RX link */ 933 u16 maxlen; 934 u16 minlen; 935 }; 936 937 struct nix_lso_format_cfg { 938 struct mbox_msghdr hdr; 939 u64 field_mask; 940 #define NIX_LSO_FIELD_MAX 8 941 u64 fields[NIX_LSO_FIELD_MAX]; 942 }; 943 944 struct nix_lso_format_cfg_rsp { 945 struct mbox_msghdr hdr; 946 u8 lso_format_idx; 947 }; 948 949 struct nix_bp_cfg_req { 950 struct mbox_msghdr hdr; 951 u16 chan_base; /* Starting channel number */ 952 u8 chan_cnt; /* Number of channels */ 953 u8 bpid_per_chan; 954 /* bpid_per_chan = 0 assigns single bp id for range of channels */ 955 /* bpid_per_chan = 1 assigns separate bp id for each channel */ 956 }; 957 958 /* PF can be mapped to either CGX or LBK interface, 959 * so maximum 64 channels are possible. 960 */ 961 #define NIX_MAX_BPID_CHAN 64 962 struct nix_bp_cfg_rsp { 963 struct mbox_msghdr hdr; 964 u16 chan_bpid[NIX_MAX_BPID_CHAN]; /* Channel and bpid mapping */ 965 u8 chan_cnt; /* Number of channel for which bpids are assigned */ 966 }; 967 968 struct nix_hw_info { 969 struct mbox_msghdr hdr; 970 u16 max_mtu; 971 u16 min_mtu; 972 }; 973 974 /* NPC mbox message structs */ 975 976 #define NPC_MCAM_ENTRY_INVALID 0xFFFF 977 #define NPC_MCAM_INVALID_MAP 0xFFFF 978 979 /* NPC mailbox error codes 980 * Range 701 - 800. 981 */ 982 enum npc_af_status { 983 NPC_MCAM_INVALID_REQ = -701, 984 NPC_MCAM_ALLOC_DENIED = -702, 985 NPC_MCAM_ALLOC_FAILED = -703, 986 NPC_MCAM_PERM_DENIED = -704, 987 }; 988 989 struct npc_mcam_alloc_entry_req { 990 struct mbox_msghdr hdr; 991 #define NPC_MAX_NONCONTIG_ENTRIES 256 992 u8 contig; /* Contiguous entries ? */ 993 #define NPC_MCAM_ANY_PRIO 0 994 #define NPC_MCAM_LOWER_PRIO 1 995 #define NPC_MCAM_HIGHER_PRIO 2 996 u8 priority; /* Lower or higher w.r.t ref_entry */ 997 u16 ref_entry; 998 u16 count; /* Number of entries requested */ 999 }; 1000 1001 struct npc_mcam_alloc_entry_rsp { 1002 struct mbox_msghdr hdr; 1003 u16 entry; /* Entry allocated or start index if contiguous. 1004 * Invalid incase of non-contiguous. 1005 */ 1006 u16 count; /* Number of entries allocated */ 1007 u16 free_count; /* Number of entries available */ 1008 u16 entry_list[NPC_MAX_NONCONTIG_ENTRIES]; 1009 }; 1010 1011 struct npc_mcam_free_entry_req { 1012 struct mbox_msghdr hdr; 1013 u16 entry; /* Entry index to be freed */ 1014 u8 all; /* If all entries allocated to this PFVF to be freed */ 1015 }; 1016 1017 struct mcam_entry { 1018 #define NPC_MAX_KWS_IN_KEY 7 /* Number of keywords in max keywidth */ 1019 u64 kw[NPC_MAX_KWS_IN_KEY]; 1020 u64 kw_mask[NPC_MAX_KWS_IN_KEY]; 1021 u64 action; 1022 u64 vtag_action; 1023 }; 1024 1025 struct npc_mcam_write_entry_req { 1026 struct mbox_msghdr hdr; 1027 struct mcam_entry entry_data; 1028 u16 entry; /* MCAM entry to write this match key */ 1029 u16 cntr; /* Counter for this MCAM entry */ 1030 u8 intf; /* Rx or Tx interface */ 1031 u8 enable_entry;/* Enable this MCAM entry ? */ 1032 u8 set_cntr; /* Set counter for this entry ? */ 1033 }; 1034 1035 /* Enable/Disable a given entry */ 1036 struct npc_mcam_ena_dis_entry_req { 1037 struct mbox_msghdr hdr; 1038 u16 entry; 1039 }; 1040 1041 struct npc_mcam_shift_entry_req { 1042 struct mbox_msghdr hdr; 1043 #define NPC_MCAM_MAX_SHIFTS 64 1044 u16 curr_entry[NPC_MCAM_MAX_SHIFTS]; 1045 u16 new_entry[NPC_MCAM_MAX_SHIFTS]; 1046 u16 shift_count; /* Number of entries to shift */ 1047 }; 1048 1049 struct npc_mcam_shift_entry_rsp { 1050 struct mbox_msghdr hdr; 1051 u16 failed_entry_idx; /* Index in 'curr_entry', not entry itself */ 1052 }; 1053 1054 struct npc_mcam_alloc_counter_req { 1055 struct mbox_msghdr hdr; 1056 u8 contig; /* Contiguous counters ? */ 1057 #define NPC_MAX_NONCONTIG_COUNTERS 64 1058 u16 count; /* Number of counters requested */ 1059 }; 1060 1061 struct npc_mcam_alloc_counter_rsp { 1062 struct mbox_msghdr hdr; 1063 u16 cntr; /* Counter allocated or start index if contiguous. 1064 * Invalid incase of non-contiguous. 1065 */ 1066 u16 count; /* Number of counters allocated */ 1067 u16 cntr_list[NPC_MAX_NONCONTIG_COUNTERS]; 1068 }; 1069 1070 struct npc_mcam_oper_counter_req { 1071 struct mbox_msghdr hdr; 1072 u16 cntr; /* Free a counter or clear/fetch it's stats */ 1073 }; 1074 1075 struct npc_mcam_oper_counter_rsp { 1076 struct mbox_msghdr hdr; 1077 u64 stat; /* valid only while fetching counter's stats */ 1078 }; 1079 1080 struct npc_mcam_unmap_counter_req { 1081 struct mbox_msghdr hdr; 1082 u16 cntr; 1083 u16 entry; /* Entry and counter to be unmapped */ 1084 u8 all; /* Unmap all entries using this counter ? */ 1085 }; 1086 1087 struct npc_mcam_alloc_and_write_entry_req { 1088 struct mbox_msghdr hdr; 1089 struct mcam_entry entry_data; 1090 u16 ref_entry; 1091 u8 priority; /* Lower or higher w.r.t ref_entry */ 1092 u8 intf; /* Rx or Tx interface */ 1093 u8 enable_entry;/* Enable this MCAM entry ? */ 1094 u8 alloc_cntr; /* Allocate counter and map ? */ 1095 }; 1096 1097 struct npc_mcam_alloc_and_write_entry_rsp { 1098 struct mbox_msghdr hdr; 1099 u16 entry; 1100 u16 cntr; 1101 }; 1102 1103 struct npc_get_kex_cfg_rsp { 1104 struct mbox_msghdr hdr; 1105 u64 rx_keyx_cfg; /* NPC_AF_INTF(0)_KEX_CFG */ 1106 u64 tx_keyx_cfg; /* NPC_AF_INTF(1)_KEX_CFG */ 1107 #define NPC_MAX_INTF 2 1108 #define NPC_MAX_LID 8 1109 #define NPC_MAX_LT 16 1110 #define NPC_MAX_LD 2 1111 #define NPC_MAX_LFL 16 1112 /* NPC_AF_KEX_LDATA(0..1)_FLAGS_CFG */ 1113 u64 kex_ld_flags[NPC_MAX_LD]; 1114 /* NPC_AF_INTF(0..1)_LID(0..7)_LT(0..15)_LD(0..1)_CFG */ 1115 u64 intf_lid_lt_ld[NPC_MAX_INTF][NPC_MAX_LID][NPC_MAX_LT][NPC_MAX_LD]; 1116 /* NPC_AF_INTF(0..1)_LDATA(0..1)_FLAGS(0..15)_CFG */ 1117 u64 intf_ld_flags[NPC_MAX_INTF][NPC_MAX_LD][NPC_MAX_LFL]; 1118 #define MKEX_NAME_LEN 128 1119 u8 mkex_pfl_name[MKEX_NAME_LEN]; 1120 }; 1121 1122 struct flow_msg { 1123 unsigned char dmac[6]; 1124 unsigned char smac[6]; 1125 __be16 etype; 1126 __be16 vlan_etype; 1127 __be16 vlan_tci; 1128 union { 1129 __be32 ip4src; 1130 __be32 ip6src[4]; 1131 }; 1132 union { 1133 __be32 ip4dst; 1134 __be32 ip6dst[4]; 1135 }; 1136 u8 tos; 1137 u8 ip_ver; 1138 u8 ip_proto; 1139 u8 tc; 1140 __be16 sport; 1141 __be16 dport; 1142 }; 1143 1144 struct npc_install_flow_req { 1145 struct mbox_msghdr hdr; 1146 struct flow_msg packet; 1147 struct flow_msg mask; 1148 u64 features; 1149 u16 entry; 1150 u16 channel; 1151 u16 chan_mask; 1152 u8 intf; 1153 u8 set_cntr; /* If counter is available set counter for this entry ? */ 1154 u8 default_rule; 1155 u8 append; /* overwrite(0) or append(1) flow to default rule? */ 1156 u16 vf; 1157 /* action */ 1158 u32 index; 1159 u16 match_id; 1160 u8 flow_key_alg; 1161 u8 op; 1162 /* vtag rx action */ 1163 u8 vtag0_type; 1164 u8 vtag0_valid; 1165 u8 vtag1_type; 1166 u8 vtag1_valid; 1167 /* vtag tx action */ 1168 u16 vtag0_def; 1169 u8 vtag0_op; 1170 u16 vtag1_def; 1171 u8 vtag1_op; 1172 }; 1173 1174 struct npc_install_flow_rsp { 1175 struct mbox_msghdr hdr; 1176 int counter; /* negative if no counter else counter number */ 1177 }; 1178 1179 struct npc_delete_flow_req { 1180 struct mbox_msghdr hdr; 1181 u16 entry; 1182 u16 start;/*Disable range of entries */ 1183 u16 end; 1184 u8 all; /* PF + VFs */ 1185 }; 1186 1187 struct npc_mcam_read_entry_req { 1188 struct mbox_msghdr hdr; 1189 u16 entry; /* MCAM entry to read */ 1190 }; 1191 1192 struct npc_mcam_read_entry_rsp { 1193 struct mbox_msghdr hdr; 1194 struct mcam_entry entry_data; 1195 u8 intf; 1196 u8 enable; 1197 }; 1198 1199 struct npc_mcam_read_base_rule_rsp { 1200 struct mbox_msghdr hdr; 1201 struct mcam_entry entry; 1202 }; 1203 1204 struct npc_mcam_get_stats_req { 1205 struct mbox_msghdr hdr; 1206 u16 entry; /* mcam entry */ 1207 }; 1208 1209 struct npc_mcam_get_stats_rsp { 1210 struct mbox_msghdr hdr; 1211 u64 stat; /* counter stats */ 1212 u8 stat_ena; /* enabled */ 1213 }; 1214 1215 enum ptp_op { 1216 PTP_OP_ADJFINE = 0, 1217 PTP_OP_GET_CLOCK = 1, 1218 }; 1219 1220 struct ptp_req { 1221 struct mbox_msghdr hdr; 1222 u8 op; 1223 s64 scaled_ppm; 1224 }; 1225 1226 struct ptp_rsp { 1227 struct mbox_msghdr hdr; 1228 u64 clk; 1229 }; 1230 1231 /* CPT mailbox error codes 1232 * Range 901 - 1000. 1233 */ 1234 enum cpt_af_status { 1235 CPT_AF_ERR_PARAM = -901, 1236 CPT_AF_ERR_GRP_INVALID = -902, 1237 CPT_AF_ERR_LF_INVALID = -903, 1238 CPT_AF_ERR_ACCESS_DENIED = -904, 1239 CPT_AF_ERR_SSO_PF_FUNC_INVALID = -905, 1240 CPT_AF_ERR_NIX_PF_FUNC_INVALID = -906 1241 }; 1242 1243 /* CPT mbox message formats */ 1244 struct cpt_rd_wr_reg_msg { 1245 struct mbox_msghdr hdr; 1246 u64 reg_offset; 1247 u64 *ret_val; 1248 u64 val; 1249 u8 is_write; 1250 int blkaddr; 1251 }; 1252 1253 struct cpt_lf_alloc_req_msg { 1254 struct mbox_msghdr hdr; 1255 u16 nix_pf_func; 1256 u16 sso_pf_func; 1257 u16 eng_grpmsk; 1258 int blkaddr; 1259 }; 1260 1261 /* Mailbox message request and response format for CPT stats. */ 1262 struct cpt_sts_req { 1263 struct mbox_msghdr hdr; 1264 u8 blkaddr; 1265 }; 1266 1267 struct cpt_sts_rsp { 1268 struct mbox_msghdr hdr; 1269 u64 inst_req_pc; 1270 u64 inst_lat_pc; 1271 u64 rd_req_pc; 1272 u64 rd_lat_pc; 1273 u64 rd_uc_pc; 1274 u64 active_cycles_pc; 1275 u64 ctx_mis_pc; 1276 u64 ctx_hit_pc; 1277 u64 ctx_aop_pc; 1278 u64 ctx_aop_lat_pc; 1279 u64 ctx_ifetch_pc; 1280 u64 ctx_ifetch_lat_pc; 1281 u64 ctx_ffetch_pc; 1282 u64 ctx_ffetch_lat_pc; 1283 u64 ctx_wback_pc; 1284 u64 ctx_wback_lat_pc; 1285 u64 ctx_psh_pc; 1286 u64 ctx_psh_lat_pc; 1287 u64 ctx_err; 1288 u64 ctx_enc_id; 1289 u64 ctx_flush_timer; 1290 u64 rxc_time; 1291 u64 rxc_time_cfg; 1292 u64 rxc_active_sts; 1293 u64 rxc_zombie_sts; 1294 u64 busy_sts_ae; 1295 u64 free_sts_ae; 1296 u64 busy_sts_se; 1297 u64 free_sts_se; 1298 u64 busy_sts_ie; 1299 u64 free_sts_ie; 1300 u64 exe_err_info; 1301 u64 cptclk_cnt; 1302 u64 diag; 1303 u64 rxc_dfrg; 1304 u64 x2p_link_cfg0; 1305 u64 x2p_link_cfg1; 1306 }; 1307 1308 /* Mailbox message request format to configure reassembly timeout. */ 1309 struct cpt_rxc_time_cfg_req { 1310 struct mbox_msghdr hdr; 1311 int blkaddr; 1312 u32 step; 1313 u16 zombie_thres; 1314 u16 zombie_limit; 1315 u16 active_thres; 1316 u16 active_limit; 1317 }; 1318 1319 #endif /* MBOX_H */ 1320