1 /* SPDX-License-Identifier: GPL-2.0 2 * Marvell OcteonTx2 RVU Admin Function driver 3 * 4 * Copyright (C) 2018 Marvell International Ltd. 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 */ 10 11 #ifndef MBOX_H 12 #define MBOX_H 13 14 #include <linux/etherdevice.h> 15 #include <linux/sizes.h> 16 17 #include "rvu_struct.h" 18 #include "common.h" 19 20 #define MBOX_SIZE SZ_64K 21 22 /* AF/PF: PF initiated, PF/VF VF initiated */ 23 #define MBOX_DOWN_RX_START 0 24 #define MBOX_DOWN_RX_SIZE (46 * SZ_1K) 25 #define MBOX_DOWN_TX_START (MBOX_DOWN_RX_START + MBOX_DOWN_RX_SIZE) 26 #define MBOX_DOWN_TX_SIZE (16 * SZ_1K) 27 /* AF/PF: AF initiated, PF/VF PF initiated */ 28 #define MBOX_UP_RX_START (MBOX_DOWN_TX_START + MBOX_DOWN_TX_SIZE) 29 #define MBOX_UP_RX_SIZE SZ_1K 30 #define MBOX_UP_TX_START (MBOX_UP_RX_START + MBOX_UP_RX_SIZE) 31 #define MBOX_UP_TX_SIZE SZ_1K 32 33 #if MBOX_UP_TX_SIZE + MBOX_UP_TX_START != MBOX_SIZE 34 # error "incorrect mailbox area sizes" 35 #endif 36 37 #define INTR_MASK(pfvfs) ((pfvfs < 64) ? (BIT_ULL(pfvfs) - 1) : (~0ull)) 38 39 #define MBOX_RSP_TIMEOUT 1000 /* in ms, Time to wait for mbox response */ 40 41 #define MBOX_MSG_ALIGN 16 /* Align mbox msg start to 16bytes */ 42 43 /* Mailbox directions */ 44 #define MBOX_DIR_AFPF 0 /* AF replies to PF */ 45 #define MBOX_DIR_PFAF 1 /* PF sends messages to AF */ 46 #define MBOX_DIR_PFVF 2 /* PF replies to VF */ 47 #define MBOX_DIR_VFPF 3 /* VF sends messages to PF */ 48 #define MBOX_DIR_AFPF_UP 4 /* AF sends messages to PF */ 49 #define MBOX_DIR_PFAF_UP 5 /* PF replies to AF */ 50 #define MBOX_DIR_PFVF_UP 6 /* PF sends messages to VF */ 51 #define MBOX_DIR_VFPF_UP 7 /* VF replies to PF */ 52 53 struct otx2_mbox_dev { 54 void *mbase; /* This dev's mbox region */ 55 spinlock_t mbox_lock; 56 u16 msg_size; /* Total msg size to be sent */ 57 u16 rsp_size; /* Total rsp size to be sure the reply is ok */ 58 u16 num_msgs; /* No of msgs sent or waiting for response */ 59 u16 msgs_acked; /* No of msgs for which response is received */ 60 }; 61 62 struct otx2_mbox { 63 struct pci_dev *pdev; 64 void *hwbase; /* Mbox region advertised by HW */ 65 void *reg_base;/* CSR base for this dev */ 66 u64 trigger; /* Trigger mbox notification */ 67 u16 tr_shift; /* Mbox trigger shift */ 68 u64 rx_start; /* Offset of Rx region in mbox memory */ 69 u64 tx_start; /* Offset of Tx region in mbox memory */ 70 u16 rx_size; /* Size of Rx region */ 71 u16 tx_size; /* Size of Tx region */ 72 u16 ndevs; /* The number of peers */ 73 struct otx2_mbox_dev *dev; 74 }; 75 76 /* Header which preceeds all mbox messages */ 77 struct mbox_hdr { 78 u16 num_msgs; /* No of msgs embedded */ 79 }; 80 81 /* Header which preceeds every msg and is also part of it */ 82 struct mbox_msghdr { 83 u16 pcifunc; /* Who's sending this msg */ 84 u16 id; /* Mbox message ID */ 85 #define OTX2_MBOX_REQ_SIG (0xdead) 86 #define OTX2_MBOX_RSP_SIG (0xbeef) 87 u16 sig; /* Signature, for validating corrupted msgs */ 88 #define OTX2_MBOX_VERSION (0x0001) 89 u16 ver; /* Version of msg's structure for this ID */ 90 u16 next_msgoff; /* Offset of next msg within mailbox region */ 91 int rc; /* Msg process'ed response code */ 92 }; 93 94 void otx2_mbox_reset(struct otx2_mbox *mbox, int devid); 95 void otx2_mbox_destroy(struct otx2_mbox *mbox); 96 int otx2_mbox_init(struct otx2_mbox *mbox, void __force *hwbase, 97 struct pci_dev *pdev, void __force *reg_base, 98 int direction, int ndevs); 99 void otx2_mbox_msg_send(struct otx2_mbox *mbox, int devid); 100 int otx2_mbox_wait_for_rsp(struct otx2_mbox *mbox, int devid); 101 int otx2_mbox_busy_poll_for_rsp(struct otx2_mbox *mbox, int devid); 102 struct mbox_msghdr *otx2_mbox_alloc_msg_rsp(struct otx2_mbox *mbox, int devid, 103 int size, int size_rsp); 104 struct mbox_msghdr *otx2_mbox_get_rsp(struct otx2_mbox *mbox, int devid, 105 struct mbox_msghdr *msg); 106 int otx2_reply_invalid_msg(struct otx2_mbox *mbox, int devid, 107 u16 pcifunc, u16 id); 108 bool otx2_mbox_nonempty(struct otx2_mbox *mbox, int devid); 109 const char *otx2_mbox_id2name(u16 id); 110 static inline struct mbox_msghdr *otx2_mbox_alloc_msg(struct otx2_mbox *mbox, 111 int devid, int size) 112 { 113 return otx2_mbox_alloc_msg_rsp(mbox, devid, size, 0); 114 } 115 116 /* Mailbox message types */ 117 #define MBOX_MSG_MASK 0xFFFF 118 #define MBOX_MSG_INVALID 0xFFFE 119 #define MBOX_MSG_MAX 0xFFFF 120 121 #define MBOX_MESSAGES \ 122 /* Generic mbox IDs (range 0x000 - 0x1FF) */ \ 123 M(READY, 0x001, ready, msg_req, ready_msg_rsp) \ 124 M(ATTACH_RESOURCES, 0x002, attach_resources, rsrc_attach, msg_rsp) \ 125 M(DETACH_RESOURCES, 0x003, detach_resources, rsrc_detach, msg_rsp) \ 126 M(MSIX_OFFSET, 0x004, msix_offset, msg_req, msix_offset_rsp) \ 127 M(VF_FLR, 0x006, vf_flr, msg_req, msg_rsp) \ 128 /* CGX mbox IDs (range 0x200 - 0x3FF) */ \ 129 M(CGX_START_RXTX, 0x200, cgx_start_rxtx, msg_req, msg_rsp) \ 130 M(CGX_STOP_RXTX, 0x201, cgx_stop_rxtx, msg_req, msg_rsp) \ 131 M(CGX_STATS, 0x202, cgx_stats, msg_req, cgx_stats_rsp) \ 132 M(CGX_MAC_ADDR_SET, 0x203, cgx_mac_addr_set, cgx_mac_addr_set_or_get, \ 133 cgx_mac_addr_set_or_get) \ 134 M(CGX_MAC_ADDR_GET, 0x204, cgx_mac_addr_get, cgx_mac_addr_set_or_get, \ 135 cgx_mac_addr_set_or_get) \ 136 M(CGX_PROMISC_ENABLE, 0x205, cgx_promisc_enable, msg_req, msg_rsp) \ 137 M(CGX_PROMISC_DISABLE, 0x206, cgx_promisc_disable, msg_req, msg_rsp) \ 138 M(CGX_START_LINKEVENTS, 0x207, cgx_start_linkevents, msg_req, msg_rsp) \ 139 M(CGX_STOP_LINKEVENTS, 0x208, cgx_stop_linkevents, msg_req, msg_rsp) \ 140 M(CGX_GET_LINKINFO, 0x209, cgx_get_linkinfo, msg_req, cgx_link_info_msg) \ 141 M(CGX_INTLBK_ENABLE, 0x20A, cgx_intlbk_enable, msg_req, msg_rsp) \ 142 M(CGX_INTLBK_DISABLE, 0x20B, cgx_intlbk_disable, msg_req, msg_rsp) \ 143 /* NPA mbox IDs (range 0x400 - 0x5FF) */ \ 144 M(NPA_LF_ALLOC, 0x400, npa_lf_alloc, \ 145 npa_lf_alloc_req, npa_lf_alloc_rsp) \ 146 M(NPA_LF_FREE, 0x401, npa_lf_free, msg_req, msg_rsp) \ 147 M(NPA_AQ_ENQ, 0x402, npa_aq_enq, npa_aq_enq_req, npa_aq_enq_rsp) \ 148 M(NPA_HWCTX_DISABLE, 0x403, npa_hwctx_disable, hwctx_disable_req, msg_rsp)\ 149 /* SSO/SSOW mbox IDs (range 0x600 - 0x7FF) */ \ 150 /* TIM mbox IDs (range 0x800 - 0x9FF) */ \ 151 /* CPT mbox IDs (range 0xA00 - 0xBFF) */ \ 152 /* NPC mbox IDs (range 0x6000 - 0x7FFF) */ \ 153 M(NPC_MCAM_ALLOC_ENTRY, 0x6000, npc_mcam_alloc_entry, npc_mcam_alloc_entry_req,\ 154 npc_mcam_alloc_entry_rsp) \ 155 M(NPC_MCAM_FREE_ENTRY, 0x6001, npc_mcam_free_entry, \ 156 npc_mcam_free_entry_req, msg_rsp) \ 157 M(NPC_MCAM_WRITE_ENTRY, 0x6002, npc_mcam_write_entry, \ 158 npc_mcam_write_entry_req, msg_rsp) \ 159 M(NPC_MCAM_ENA_ENTRY, 0x6003, npc_mcam_ena_entry, \ 160 npc_mcam_ena_dis_entry_req, msg_rsp) \ 161 M(NPC_MCAM_DIS_ENTRY, 0x6004, npc_mcam_dis_entry, \ 162 npc_mcam_ena_dis_entry_req, msg_rsp) \ 163 M(NPC_MCAM_SHIFT_ENTRY, 0x6005, npc_mcam_shift_entry, npc_mcam_shift_entry_req,\ 164 npc_mcam_shift_entry_rsp) \ 165 M(NPC_MCAM_ALLOC_COUNTER, 0x6006, npc_mcam_alloc_counter, \ 166 npc_mcam_alloc_counter_req, \ 167 npc_mcam_alloc_counter_rsp) \ 168 M(NPC_MCAM_FREE_COUNTER, 0x6007, npc_mcam_free_counter, \ 169 npc_mcam_oper_counter_req, msg_rsp) \ 170 M(NPC_MCAM_UNMAP_COUNTER, 0x6008, npc_mcam_unmap_counter, \ 171 npc_mcam_unmap_counter_req, msg_rsp) \ 172 M(NPC_MCAM_CLEAR_COUNTER, 0x6009, npc_mcam_clear_counter, \ 173 npc_mcam_oper_counter_req, msg_rsp) \ 174 M(NPC_MCAM_COUNTER_STATS, 0x600a, npc_mcam_counter_stats, \ 175 npc_mcam_oper_counter_req, \ 176 npc_mcam_oper_counter_rsp) \ 177 M(NPC_MCAM_ALLOC_AND_WRITE_ENTRY, 0x600b, npc_mcam_alloc_and_write_entry, \ 178 npc_mcam_alloc_and_write_entry_req, \ 179 npc_mcam_alloc_and_write_entry_rsp) \ 180 M(NPC_GET_KEX_CFG, 0x600c, npc_get_kex_cfg, \ 181 msg_req, npc_get_kex_cfg_rsp) \ 182 /* NIX mbox IDs (range 0x8000 - 0xFFFF) */ \ 183 M(NIX_LF_ALLOC, 0x8000, nix_lf_alloc, \ 184 nix_lf_alloc_req, nix_lf_alloc_rsp) \ 185 M(NIX_LF_FREE, 0x8001, nix_lf_free, msg_req, msg_rsp) \ 186 M(NIX_AQ_ENQ, 0x8002, nix_aq_enq, nix_aq_enq_req, nix_aq_enq_rsp) \ 187 M(NIX_HWCTX_DISABLE, 0x8003, nix_hwctx_disable, \ 188 hwctx_disable_req, msg_rsp) \ 189 M(NIX_TXSCH_ALLOC, 0x8004, nix_txsch_alloc, \ 190 nix_txsch_alloc_req, nix_txsch_alloc_rsp) \ 191 M(NIX_TXSCH_FREE, 0x8005, nix_txsch_free, nix_txsch_free_req, msg_rsp) \ 192 M(NIX_TXSCHQ_CFG, 0x8006, nix_txschq_cfg, nix_txschq_config, msg_rsp) \ 193 M(NIX_STATS_RST, 0x8007, nix_stats_rst, msg_req, msg_rsp) \ 194 M(NIX_VTAG_CFG, 0x8008, nix_vtag_cfg, nix_vtag_config, msg_rsp) \ 195 M(NIX_RSS_FLOWKEY_CFG, 0x8009, nix_rss_flowkey_cfg, \ 196 nix_rss_flowkey_cfg, msg_rsp) \ 197 M(NIX_SET_MAC_ADDR, 0x800a, nix_set_mac_addr, nix_set_mac_addr, msg_rsp) \ 198 M(NIX_SET_RX_MODE, 0x800b, nix_set_rx_mode, nix_rx_mode, msg_rsp) \ 199 M(NIX_SET_HW_FRS, 0x800c, nix_set_hw_frs, nix_frs_cfg, msg_rsp) \ 200 M(NIX_LF_START_RX, 0x800d, nix_lf_start_rx, msg_req, msg_rsp) \ 201 M(NIX_LF_STOP_RX, 0x800e, nix_lf_stop_rx, msg_req, msg_rsp) \ 202 M(NIX_RXVLAN_ALLOC, 0x8012, nix_rxvlan_alloc, msg_req, msg_rsp) 203 204 /* Messages initiated by AF (range 0xC00 - 0xDFF) */ 205 #define MBOX_UP_CGX_MESSAGES \ 206 M(CGX_LINK_EVENT, 0xC00, cgx_link_event, cgx_link_info_msg, msg_rsp) 207 208 enum { 209 #define M(_name, _id, _1, _2, _3) MBOX_MSG_ ## _name = _id, 210 MBOX_MESSAGES 211 MBOX_UP_CGX_MESSAGES 212 #undef M 213 }; 214 215 /* Mailbox message formats */ 216 217 #define RVU_DEFAULT_PF_FUNC 0xFFFF 218 219 /* Generic request msg used for those mbox messages which 220 * don't send any data in the request. 221 */ 222 struct msg_req { 223 struct mbox_msghdr hdr; 224 }; 225 226 /* Generic rsponse msg used a ack or response for those mbox 227 * messages which doesn't have a specific rsp msg format. 228 */ 229 struct msg_rsp { 230 struct mbox_msghdr hdr; 231 }; 232 233 /* RVU mailbox error codes 234 * Range 256 - 300. 235 */ 236 enum rvu_af_status { 237 RVU_INVALID_VF_ID = -256, 238 }; 239 240 struct ready_msg_rsp { 241 struct mbox_msghdr hdr; 242 u16 sclk_feq; /* SCLK frequency */ 243 }; 244 245 /* Structure for requesting resource provisioning. 246 * 'modify' flag to be used when either requesting more 247 * or to detach partial of a cetain resource type. 248 * Rest of the fields specify how many of what type to 249 * be attached. 250 */ 251 struct rsrc_attach { 252 struct mbox_msghdr hdr; 253 u8 modify:1; 254 u8 npalf:1; 255 u8 nixlf:1; 256 u16 sso; 257 u16 ssow; 258 u16 timlfs; 259 u16 cptlfs; 260 }; 261 262 /* Structure for relinquishing resources. 263 * 'partial' flag to be used when relinquishing all resources 264 * but only of a certain type. If not set, all resources of all 265 * types provisioned to the RVU function will be detached. 266 */ 267 struct rsrc_detach { 268 struct mbox_msghdr hdr; 269 u8 partial:1; 270 u8 npalf:1; 271 u8 nixlf:1; 272 u8 sso:1; 273 u8 ssow:1; 274 u8 timlfs:1; 275 u8 cptlfs:1; 276 }; 277 278 #define MSIX_VECTOR_INVALID 0xFFFF 279 #define MAX_RVU_BLKLF_CNT 256 280 281 struct msix_offset_rsp { 282 struct mbox_msghdr hdr; 283 u16 npa_msixoff; 284 u16 nix_msixoff; 285 u8 sso; 286 u8 ssow; 287 u8 timlfs; 288 u8 cptlfs; 289 u16 sso_msixoff[MAX_RVU_BLKLF_CNT]; 290 u16 ssow_msixoff[MAX_RVU_BLKLF_CNT]; 291 u16 timlf_msixoff[MAX_RVU_BLKLF_CNT]; 292 u16 cptlf_msixoff[MAX_RVU_BLKLF_CNT]; 293 }; 294 295 /* CGX mbox message formats */ 296 297 struct cgx_stats_rsp { 298 struct mbox_msghdr hdr; 299 #define CGX_RX_STATS_COUNT 13 300 #define CGX_TX_STATS_COUNT 18 301 u64 rx_stats[CGX_RX_STATS_COUNT]; 302 u64 tx_stats[CGX_TX_STATS_COUNT]; 303 }; 304 305 /* Structure for requesting the operation for 306 * setting/getting mac address in the CGX interface 307 */ 308 struct cgx_mac_addr_set_or_get { 309 struct mbox_msghdr hdr; 310 u8 mac_addr[ETH_ALEN]; 311 }; 312 313 struct cgx_link_user_info { 314 uint64_t link_up:1; 315 uint64_t full_duplex:1; 316 uint64_t lmac_type_id:4; 317 uint64_t speed:20; /* speed in Mbps */ 318 #define LMACTYPE_STR_LEN 16 319 char lmac_type[LMACTYPE_STR_LEN]; 320 }; 321 322 struct cgx_link_info_msg { 323 struct mbox_msghdr hdr; 324 struct cgx_link_user_info link_info; 325 }; 326 327 /* NPA mbox message formats */ 328 329 /* NPA mailbox error codes 330 * Range 301 - 400. 331 */ 332 enum npa_af_status { 333 NPA_AF_ERR_PARAM = -301, 334 NPA_AF_ERR_AQ_FULL = -302, 335 NPA_AF_ERR_AQ_ENQUEUE = -303, 336 NPA_AF_ERR_AF_LF_INVALID = -304, 337 NPA_AF_ERR_AF_LF_ALLOC = -305, 338 NPA_AF_ERR_LF_RESET = -306, 339 }; 340 341 /* For NPA LF context alloc and init */ 342 struct npa_lf_alloc_req { 343 struct mbox_msghdr hdr; 344 int node; 345 int aura_sz; /* No of auras */ 346 u32 nr_pools; /* No of pools */ 347 }; 348 349 struct npa_lf_alloc_rsp { 350 struct mbox_msghdr hdr; 351 u32 stack_pg_ptrs; /* No of ptrs per stack page */ 352 u32 stack_pg_bytes; /* Size of stack page */ 353 u16 qints; /* NPA_AF_CONST::QINTS */ 354 }; 355 356 /* NPA AQ enqueue msg */ 357 struct npa_aq_enq_req { 358 struct mbox_msghdr hdr; 359 u32 aura_id; 360 u8 ctype; 361 u8 op; 362 union { 363 /* Valid when op == WRITE/INIT and ctype == AURA. 364 * LF fills the pool_id in aura.pool_addr. AF will translate 365 * the pool_id to pool context pointer. 366 */ 367 struct npa_aura_s aura; 368 /* Valid when op == WRITE/INIT and ctype == POOL */ 369 struct npa_pool_s pool; 370 }; 371 /* Mask data when op == WRITE (1=write, 0=don't write) */ 372 union { 373 /* Valid when op == WRITE and ctype == AURA */ 374 struct npa_aura_s aura_mask; 375 /* Valid when op == WRITE and ctype == POOL */ 376 struct npa_pool_s pool_mask; 377 }; 378 }; 379 380 struct npa_aq_enq_rsp { 381 struct mbox_msghdr hdr; 382 union { 383 /* Valid when op == READ and ctype == AURA */ 384 struct npa_aura_s aura; 385 /* Valid when op == READ and ctype == POOL */ 386 struct npa_pool_s pool; 387 }; 388 }; 389 390 /* Disable all contexts of type 'ctype' */ 391 struct hwctx_disable_req { 392 struct mbox_msghdr hdr; 393 u8 ctype; 394 }; 395 396 /* NIX mbox message formats */ 397 398 /* NIX mailbox error codes 399 * Range 401 - 500. 400 */ 401 enum nix_af_status { 402 NIX_AF_ERR_PARAM = -401, 403 NIX_AF_ERR_AQ_FULL = -402, 404 NIX_AF_ERR_AQ_ENQUEUE = -403, 405 NIX_AF_ERR_AF_LF_INVALID = -404, 406 NIX_AF_ERR_AF_LF_ALLOC = -405, 407 NIX_AF_ERR_TLX_ALLOC_FAIL = -406, 408 NIX_AF_ERR_TLX_INVALID = -407, 409 NIX_AF_ERR_RSS_SIZE_INVALID = -408, 410 NIX_AF_ERR_RSS_GRPS_INVALID = -409, 411 NIX_AF_ERR_FRS_INVALID = -410, 412 NIX_AF_ERR_RX_LINK_INVALID = -411, 413 NIX_AF_INVAL_TXSCHQ_CFG = -412, 414 NIX_AF_SMQ_FLUSH_FAILED = -413, 415 NIX_AF_ERR_LF_RESET = -414, 416 NIX_AF_INVAL_NPA_PF_FUNC = -419, 417 NIX_AF_INVAL_SSO_PF_FUNC = -420, 418 }; 419 420 /* For NIX LF context alloc and init */ 421 struct nix_lf_alloc_req { 422 struct mbox_msghdr hdr; 423 int node; 424 u32 rq_cnt; /* No of receive queues */ 425 u32 sq_cnt; /* No of send queues */ 426 u32 cq_cnt; /* No of completion queues */ 427 u8 xqe_sz; 428 u16 rss_sz; 429 u8 rss_grps; 430 u16 npa_func; 431 u16 sso_func; 432 u64 rx_cfg; /* See NIX_AF_LF(0..127)_RX_CFG */ 433 }; 434 435 struct nix_lf_alloc_rsp { 436 struct mbox_msghdr hdr; 437 u16 sqb_size; 438 u16 rx_chan_base; 439 u16 tx_chan_base; 440 u8 rx_chan_cnt; /* total number of RX channels */ 441 u8 tx_chan_cnt; /* total number of TX channels */ 442 u8 lso_tsov4_idx; 443 u8 lso_tsov6_idx; 444 u8 mac_addr[ETH_ALEN]; 445 u8 lf_rx_stats; /* NIX_AF_CONST1::LF_RX_STATS */ 446 u8 lf_tx_stats; /* NIX_AF_CONST1::LF_TX_STATS */ 447 u16 cints; /* NIX_AF_CONST2::CINTS */ 448 u16 qints; /* NIX_AF_CONST2::QINTS */ 449 }; 450 451 /* NIX AQ enqueue msg */ 452 struct nix_aq_enq_req { 453 struct mbox_msghdr hdr; 454 u32 qidx; 455 u8 ctype; 456 u8 op; 457 union { 458 struct nix_rq_ctx_s rq; 459 struct nix_sq_ctx_s sq; 460 struct nix_cq_ctx_s cq; 461 struct nix_rsse_s rss; 462 struct nix_rx_mce_s mce; 463 }; 464 union { 465 struct nix_rq_ctx_s rq_mask; 466 struct nix_sq_ctx_s sq_mask; 467 struct nix_cq_ctx_s cq_mask; 468 struct nix_rsse_s rss_mask; 469 struct nix_rx_mce_s mce_mask; 470 }; 471 }; 472 473 struct nix_aq_enq_rsp { 474 struct mbox_msghdr hdr; 475 union { 476 struct nix_rq_ctx_s rq; 477 struct nix_sq_ctx_s sq; 478 struct nix_cq_ctx_s cq; 479 struct nix_rsse_s rss; 480 struct nix_rx_mce_s mce; 481 }; 482 }; 483 484 /* Tx scheduler/shaper mailbox messages */ 485 486 #define MAX_TXSCHQ_PER_FUNC 128 487 488 struct nix_txsch_alloc_req { 489 struct mbox_msghdr hdr; 490 /* Scheduler queue count request at each level */ 491 u16 schq_contig[NIX_TXSCH_LVL_CNT]; /* No of contiguous queues */ 492 u16 schq[NIX_TXSCH_LVL_CNT]; /* No of non-contiguous queues */ 493 }; 494 495 struct nix_txsch_alloc_rsp { 496 struct mbox_msghdr hdr; 497 /* Scheduler queue count allocated at each level */ 498 u16 schq_contig[NIX_TXSCH_LVL_CNT]; 499 u16 schq[NIX_TXSCH_LVL_CNT]; 500 /* Scheduler queue list allocated at each level */ 501 u16 schq_contig_list[NIX_TXSCH_LVL_CNT][MAX_TXSCHQ_PER_FUNC]; 502 u16 schq_list[NIX_TXSCH_LVL_CNT][MAX_TXSCHQ_PER_FUNC]; 503 }; 504 505 struct nix_txsch_free_req { 506 struct mbox_msghdr hdr; 507 #define TXSCHQ_FREE_ALL BIT_ULL(0) 508 u16 flags; 509 /* Scheduler queue level to be freed */ 510 u16 schq_lvl; 511 /* List of scheduler queues to be freed */ 512 u16 schq; 513 }; 514 515 struct nix_txschq_config { 516 struct mbox_msghdr hdr; 517 u8 lvl; /* SMQ/MDQ/TL4/TL3/TL2/TL1 */ 518 #define TXSCHQ_IDX_SHIFT 16 519 #define TXSCHQ_IDX_MASK (BIT_ULL(10) - 1) 520 #define TXSCHQ_IDX(reg, shift) (((reg) >> (shift)) & TXSCHQ_IDX_MASK) 521 u8 num_regs; 522 #define MAX_REGS_PER_MBOX_MSG 20 523 u64 reg[MAX_REGS_PER_MBOX_MSG]; 524 u64 regval[MAX_REGS_PER_MBOX_MSG]; 525 }; 526 527 struct nix_vtag_config { 528 struct mbox_msghdr hdr; 529 /* '0' for 4 octet VTAG, '1' for 8 octet VTAG */ 530 u8 vtag_size; 531 /* cfg_type is '0' for tx vlan cfg 532 * cfg_type is '1' for rx vlan cfg 533 */ 534 u8 cfg_type; 535 union { 536 /* valid when cfg_type is '0' */ 537 struct { 538 /* tx vlan0 tag(C-VLAN) */ 539 u64 vlan0; 540 /* tx vlan1 tag(S-VLAN) */ 541 u64 vlan1; 542 /* insert tx vlan tag */ 543 u8 insert_vlan :1; 544 /* insert tx double vlan tag */ 545 u8 double_vlan :1; 546 } tx; 547 548 /* valid when cfg_type is '1' */ 549 struct { 550 /* rx vtag type index, valid values are in 0..7 range */ 551 u8 vtag_type; 552 /* rx vtag strip */ 553 u8 strip_vtag :1; 554 /* rx vtag capture */ 555 u8 capture_vtag :1; 556 } rx; 557 }; 558 }; 559 560 struct nix_rss_flowkey_cfg { 561 struct mbox_msghdr hdr; 562 int mcam_index; /* MCAM entry index to modify */ 563 u32 flowkey_cfg; /* Flowkey types selected */ 564 u8 group; /* RSS context or group */ 565 }; 566 567 struct nix_set_mac_addr { 568 struct mbox_msghdr hdr; 569 u8 mac_addr[ETH_ALEN]; /* MAC address to be set for this pcifunc */ 570 }; 571 572 struct nix_rx_mode { 573 struct mbox_msghdr hdr; 574 #define NIX_RX_MODE_UCAST BIT(0) 575 #define NIX_RX_MODE_PROMISC BIT(1) 576 #define NIX_RX_MODE_ALLMULTI BIT(2) 577 u16 mode; 578 }; 579 580 struct nix_frs_cfg { 581 struct mbox_msghdr hdr; 582 u8 update_smq; /* Update SMQ's min/max lens */ 583 u8 update_minlen; /* Set minlen also */ 584 u8 sdp_link; /* Set SDP RX link */ 585 u16 maxlen; 586 u16 minlen; 587 }; 588 589 /* NPC mbox message structs */ 590 591 #define NPC_MCAM_ENTRY_INVALID 0xFFFF 592 #define NPC_MCAM_INVALID_MAP 0xFFFF 593 594 /* NPC mailbox error codes 595 * Range 701 - 800. 596 */ 597 enum npc_af_status { 598 NPC_MCAM_INVALID_REQ = -701, 599 NPC_MCAM_ALLOC_DENIED = -702, 600 NPC_MCAM_ALLOC_FAILED = -703, 601 NPC_MCAM_PERM_DENIED = -704, 602 }; 603 604 struct npc_mcam_alloc_entry_req { 605 struct mbox_msghdr hdr; 606 #define NPC_MAX_NONCONTIG_ENTRIES 256 607 u8 contig; /* Contiguous entries ? */ 608 #define NPC_MCAM_ANY_PRIO 0 609 #define NPC_MCAM_LOWER_PRIO 1 610 #define NPC_MCAM_HIGHER_PRIO 2 611 u8 priority; /* Lower or higher w.r.t ref_entry */ 612 u16 ref_entry; 613 u16 count; /* Number of entries requested */ 614 }; 615 616 struct npc_mcam_alloc_entry_rsp { 617 struct mbox_msghdr hdr; 618 u16 entry; /* Entry allocated or start index if contiguous. 619 * Invalid incase of non-contiguous. 620 */ 621 u16 count; /* Number of entries allocated */ 622 u16 free_count; /* Number of entries available */ 623 u16 entry_list[NPC_MAX_NONCONTIG_ENTRIES]; 624 }; 625 626 struct npc_mcam_free_entry_req { 627 struct mbox_msghdr hdr; 628 u16 entry; /* Entry index to be freed */ 629 u8 all; /* If all entries allocated to this PFVF to be freed */ 630 }; 631 632 struct mcam_entry { 633 #define NPC_MAX_KWS_IN_KEY 7 /* Number of keywords in max keywidth */ 634 u64 kw[NPC_MAX_KWS_IN_KEY]; 635 u64 kw_mask[NPC_MAX_KWS_IN_KEY]; 636 u64 action; 637 u64 vtag_action; 638 }; 639 640 struct npc_mcam_write_entry_req { 641 struct mbox_msghdr hdr; 642 struct mcam_entry entry_data; 643 u16 entry; /* MCAM entry to write this match key */ 644 u16 cntr; /* Counter for this MCAM entry */ 645 u8 intf; /* Rx or Tx interface */ 646 u8 enable_entry;/* Enable this MCAM entry ? */ 647 u8 set_cntr; /* Set counter for this entry ? */ 648 }; 649 650 /* Enable/Disable a given entry */ 651 struct npc_mcam_ena_dis_entry_req { 652 struct mbox_msghdr hdr; 653 u16 entry; 654 }; 655 656 struct npc_mcam_shift_entry_req { 657 struct mbox_msghdr hdr; 658 #define NPC_MCAM_MAX_SHIFTS 64 659 u16 curr_entry[NPC_MCAM_MAX_SHIFTS]; 660 u16 new_entry[NPC_MCAM_MAX_SHIFTS]; 661 u16 shift_count; /* Number of entries to shift */ 662 }; 663 664 struct npc_mcam_shift_entry_rsp { 665 struct mbox_msghdr hdr; 666 u16 failed_entry_idx; /* Index in 'curr_entry', not entry itself */ 667 }; 668 669 struct npc_mcam_alloc_counter_req { 670 struct mbox_msghdr hdr; 671 u8 contig; /* Contiguous counters ? */ 672 #define NPC_MAX_NONCONTIG_COUNTERS 64 673 u16 count; /* Number of counters requested */ 674 }; 675 676 struct npc_mcam_alloc_counter_rsp { 677 struct mbox_msghdr hdr; 678 u16 cntr; /* Counter allocated or start index if contiguous. 679 * Invalid incase of non-contiguous. 680 */ 681 u16 count; /* Number of counters allocated */ 682 u16 cntr_list[NPC_MAX_NONCONTIG_COUNTERS]; 683 }; 684 685 struct npc_mcam_oper_counter_req { 686 struct mbox_msghdr hdr; 687 u16 cntr; /* Free a counter or clear/fetch it's stats */ 688 }; 689 690 struct npc_mcam_oper_counter_rsp { 691 struct mbox_msghdr hdr; 692 u64 stat; /* valid only while fetching counter's stats */ 693 }; 694 695 struct npc_mcam_unmap_counter_req { 696 struct mbox_msghdr hdr; 697 u16 cntr; 698 u16 entry; /* Entry and counter to be unmapped */ 699 u8 all; /* Unmap all entries using this counter ? */ 700 }; 701 702 struct npc_mcam_alloc_and_write_entry_req { 703 struct mbox_msghdr hdr; 704 struct mcam_entry entry_data; 705 u16 ref_entry; 706 u8 priority; /* Lower or higher w.r.t ref_entry */ 707 u8 intf; /* Rx or Tx interface */ 708 u8 enable_entry;/* Enable this MCAM entry ? */ 709 u8 alloc_cntr; /* Allocate counter and map ? */ 710 }; 711 712 struct npc_mcam_alloc_and_write_entry_rsp { 713 struct mbox_msghdr hdr; 714 u16 entry; 715 u16 cntr; 716 }; 717 718 struct npc_get_kex_cfg_rsp { 719 struct mbox_msghdr hdr; 720 u64 rx_keyx_cfg; /* NPC_AF_INTF(0)_KEX_CFG */ 721 u64 tx_keyx_cfg; /* NPC_AF_INTF(1)_KEX_CFG */ 722 #define NPC_MAX_INTF 2 723 #define NPC_MAX_LID 8 724 #define NPC_MAX_LT 16 725 #define NPC_MAX_LD 2 726 #define NPC_MAX_LFL 16 727 /* NPC_AF_KEX_LDATA(0..1)_FLAGS_CFG */ 728 u64 kex_ld_flags[NPC_MAX_LD]; 729 /* NPC_AF_INTF(0..1)_LID(0..7)_LT(0..15)_LD(0..1)_CFG */ 730 u64 intf_lid_lt_ld[NPC_MAX_INTF][NPC_MAX_LID][NPC_MAX_LT][NPC_MAX_LD]; 731 /* NPC_AF_INTF(0..1)_LDATA(0..1)_FLAGS(0..15)_CFG */ 732 u64 intf_ld_flags[NPC_MAX_INTF][NPC_MAX_LD][NPC_MAX_LFL]; 733 }; 734 735 #endif /* MBOX_H */ 736