1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Marvell RVU Admin Function driver 3 * 4 * Copyright (C) 2018 Marvell. 5 * 6 */ 7 8 #ifndef MBOX_H 9 #define MBOX_H 10 11 #include <linux/etherdevice.h> 12 #include <linux/sizes.h> 13 14 #include "rvu_struct.h" 15 #include "common.h" 16 17 #define MBOX_SIZE SZ_64K 18 19 /* AF/PF: PF initiated, PF/VF VF initiated */ 20 #define MBOX_DOWN_RX_START 0 21 #define MBOX_DOWN_RX_SIZE (46 * SZ_1K) 22 #define MBOX_DOWN_TX_START (MBOX_DOWN_RX_START + MBOX_DOWN_RX_SIZE) 23 #define MBOX_DOWN_TX_SIZE (16 * SZ_1K) 24 /* AF/PF: AF initiated, PF/VF PF initiated */ 25 #define MBOX_UP_RX_START (MBOX_DOWN_TX_START + MBOX_DOWN_TX_SIZE) 26 #define MBOX_UP_RX_SIZE SZ_1K 27 #define MBOX_UP_TX_START (MBOX_UP_RX_START + MBOX_UP_RX_SIZE) 28 #define MBOX_UP_TX_SIZE SZ_1K 29 30 #if MBOX_UP_TX_SIZE + MBOX_UP_TX_START != MBOX_SIZE 31 # error "incorrect mailbox area sizes" 32 #endif 33 34 #define INTR_MASK(pfvfs) ((pfvfs < 64) ? (BIT_ULL(pfvfs) - 1) : (~0ull)) 35 36 #define MBOX_RSP_TIMEOUT 6000 /* Time(ms) to wait for mbox response */ 37 38 #define MBOX_MSG_ALIGN 16 /* Align mbox msg start to 16bytes */ 39 40 /* Mailbox directions */ 41 #define MBOX_DIR_AFPF 0 /* AF replies to PF */ 42 #define MBOX_DIR_PFAF 1 /* PF sends messages to AF */ 43 #define MBOX_DIR_PFVF 2 /* PF replies to VF */ 44 #define MBOX_DIR_VFPF 3 /* VF sends messages to PF */ 45 #define MBOX_DIR_AFPF_UP 4 /* AF sends messages to PF */ 46 #define MBOX_DIR_PFAF_UP 5 /* PF replies to AF */ 47 #define MBOX_DIR_PFVF_UP 6 /* PF sends messages to VF */ 48 #define MBOX_DIR_VFPF_UP 7 /* VF replies to PF */ 49 50 struct otx2_mbox_dev { 51 void *mbase; /* This dev's mbox region */ 52 void *hwbase; 53 spinlock_t mbox_lock; 54 u16 msg_size; /* Total msg size to be sent */ 55 u16 rsp_size; /* Total rsp size to be sure the reply is ok */ 56 u16 num_msgs; /* No of msgs sent or waiting for response */ 57 u16 msgs_acked; /* No of msgs for which response is received */ 58 }; 59 60 struct otx2_mbox { 61 struct pci_dev *pdev; 62 void *hwbase; /* Mbox region advertised by HW */ 63 void *reg_base;/* CSR base for this dev */ 64 u64 trigger; /* Trigger mbox notification */ 65 u16 tr_shift; /* Mbox trigger shift */ 66 u64 rx_start; /* Offset of Rx region in mbox memory */ 67 u64 tx_start; /* Offset of Tx region in mbox memory */ 68 u16 rx_size; /* Size of Rx region */ 69 u16 tx_size; /* Size of Tx region */ 70 u16 ndevs; /* The number of peers */ 71 struct otx2_mbox_dev *dev; 72 }; 73 74 /* Header which precedes all mbox messages */ 75 struct mbox_hdr { 76 u64 msg_size; /* Total msgs size embedded */ 77 u16 num_msgs; /* No of msgs embedded */ 78 }; 79 80 /* Header which precedes every msg and is also part of it */ 81 struct mbox_msghdr { 82 u16 pcifunc; /* Who's sending this msg */ 83 u16 id; /* Mbox message ID */ 84 #define OTX2_MBOX_REQ_SIG (0xdead) 85 #define OTX2_MBOX_RSP_SIG (0xbeef) 86 u16 sig; /* Signature, for validating corrupted msgs */ 87 #define OTX2_MBOX_VERSION (0x000a) 88 u16 ver; /* Version of msg's structure for this ID */ 89 u16 next_msgoff; /* Offset of next msg within mailbox region */ 90 int rc; /* Msg process'ed response code */ 91 }; 92 93 void otx2_mbox_reset(struct otx2_mbox *mbox, int devid); 94 void __otx2_mbox_reset(struct otx2_mbox *mbox, int devid); 95 void otx2_mbox_destroy(struct otx2_mbox *mbox); 96 int otx2_mbox_init(struct otx2_mbox *mbox, void __force *hwbase, 97 struct pci_dev *pdev, void __force *reg_base, 98 int direction, int ndevs); 99 int otx2_mbox_regions_init(struct otx2_mbox *mbox, void __force **hwbase, 100 struct pci_dev *pdev, void __force *reg_base, 101 int direction, int ndevs); 102 void otx2_mbox_msg_send(struct otx2_mbox *mbox, int devid); 103 int otx2_mbox_wait_for_rsp(struct otx2_mbox *mbox, int devid); 104 int otx2_mbox_busy_poll_for_rsp(struct otx2_mbox *mbox, int devid); 105 struct mbox_msghdr *otx2_mbox_alloc_msg_rsp(struct otx2_mbox *mbox, int devid, 106 int size, int size_rsp); 107 struct mbox_msghdr *otx2_mbox_get_rsp(struct otx2_mbox *mbox, int devid, 108 struct mbox_msghdr *msg); 109 int otx2_mbox_check_rsp_msgs(struct otx2_mbox *mbox, int devid); 110 int otx2_reply_invalid_msg(struct otx2_mbox *mbox, int devid, 111 u16 pcifunc, u16 id); 112 bool otx2_mbox_nonempty(struct otx2_mbox *mbox, int devid); 113 const char *otx2_mbox_id2name(u16 id); 114 static inline struct mbox_msghdr *otx2_mbox_alloc_msg(struct otx2_mbox *mbox, 115 int devid, int size) 116 { 117 return otx2_mbox_alloc_msg_rsp(mbox, devid, size, 0); 118 } 119 120 /* Mailbox message types */ 121 #define MBOX_MSG_MASK 0xFFFF 122 #define MBOX_MSG_INVALID 0xFFFE 123 #define MBOX_MSG_MAX 0xFFFF 124 125 #define MBOX_MESSAGES \ 126 /* Generic mbox IDs (range 0x000 - 0x1FF) */ \ 127 M(READY, 0x001, ready, msg_req, ready_msg_rsp) \ 128 M(ATTACH_RESOURCES, 0x002, attach_resources, rsrc_attach, msg_rsp) \ 129 M(DETACH_RESOURCES, 0x003, detach_resources, rsrc_detach, msg_rsp) \ 130 M(FREE_RSRC_CNT, 0x004, free_rsrc_cnt, msg_req, free_rsrcs_rsp) \ 131 M(MSIX_OFFSET, 0x005, msix_offset, msg_req, msix_offset_rsp) \ 132 M(VF_FLR, 0x006, vf_flr, msg_req, msg_rsp) \ 133 M(PTP_OP, 0x007, ptp_op, ptp_req, ptp_rsp) \ 134 M(GET_HW_CAP, 0x008, get_hw_cap, msg_req, get_hw_cap_rsp) \ 135 M(LMTST_TBL_SETUP, 0x00a, lmtst_tbl_setup, lmtst_tbl_setup_req, \ 136 msg_rsp) \ 137 M(SET_VF_PERM, 0x00b, set_vf_perm, set_vf_perm, msg_rsp) \ 138 /* CGX mbox IDs (range 0x200 - 0x3FF) */ \ 139 M(CGX_START_RXTX, 0x200, cgx_start_rxtx, msg_req, msg_rsp) \ 140 M(CGX_STOP_RXTX, 0x201, cgx_stop_rxtx, msg_req, msg_rsp) \ 141 M(CGX_STATS, 0x202, cgx_stats, msg_req, cgx_stats_rsp) \ 142 M(CGX_MAC_ADDR_SET, 0x203, cgx_mac_addr_set, cgx_mac_addr_set_or_get, \ 143 cgx_mac_addr_set_or_get) \ 144 M(CGX_MAC_ADDR_GET, 0x204, cgx_mac_addr_get, cgx_mac_addr_set_or_get, \ 145 cgx_mac_addr_set_or_get) \ 146 M(CGX_PROMISC_ENABLE, 0x205, cgx_promisc_enable, msg_req, msg_rsp) \ 147 M(CGX_PROMISC_DISABLE, 0x206, cgx_promisc_disable, msg_req, msg_rsp) \ 148 M(CGX_START_LINKEVENTS, 0x207, cgx_start_linkevents, msg_req, msg_rsp) \ 149 M(CGX_STOP_LINKEVENTS, 0x208, cgx_stop_linkevents, msg_req, msg_rsp) \ 150 M(CGX_GET_LINKINFO, 0x209, cgx_get_linkinfo, msg_req, cgx_link_info_msg) \ 151 M(CGX_INTLBK_ENABLE, 0x20A, cgx_intlbk_enable, msg_req, msg_rsp) \ 152 M(CGX_INTLBK_DISABLE, 0x20B, cgx_intlbk_disable, msg_req, msg_rsp) \ 153 M(CGX_PTP_RX_ENABLE, 0x20C, cgx_ptp_rx_enable, msg_req, msg_rsp) \ 154 M(CGX_PTP_RX_DISABLE, 0x20D, cgx_ptp_rx_disable, msg_req, msg_rsp) \ 155 M(CGX_CFG_PAUSE_FRM, 0x20E, cgx_cfg_pause_frm, cgx_pause_frm_cfg, \ 156 cgx_pause_frm_cfg) \ 157 M(CGX_FW_DATA_GET, 0x20F, cgx_get_aux_link_info, msg_req, cgx_fw_data) \ 158 M(CGX_FEC_SET, 0x210, cgx_set_fec_param, fec_mode, fec_mode) \ 159 M(CGX_MAC_ADDR_ADD, 0x211, cgx_mac_addr_add, cgx_mac_addr_add_req, \ 160 cgx_mac_addr_add_rsp) \ 161 M(CGX_MAC_ADDR_DEL, 0x212, cgx_mac_addr_del, cgx_mac_addr_del_req, \ 162 msg_rsp) \ 163 M(CGX_MAC_MAX_ENTRIES_GET, 0x213, cgx_mac_max_entries_get, msg_req, \ 164 cgx_max_dmac_entries_get_rsp) \ 165 M(CGX_FEC_STATS, 0x217, cgx_fec_stats, msg_req, cgx_fec_stats_rsp) \ 166 M(CGX_SET_LINK_MODE, 0x218, cgx_set_link_mode, cgx_set_link_mode_req,\ 167 cgx_set_link_mode_rsp) \ 168 M(CGX_GET_PHY_FEC_STATS, 0x219, cgx_get_phy_fec_stats, msg_req, msg_rsp) \ 169 M(CGX_FEATURES_GET, 0x21B, cgx_features_get, msg_req, \ 170 cgx_features_info_msg) \ 171 M(RPM_STATS, 0x21C, rpm_stats, msg_req, rpm_stats_rsp) \ 172 M(CGX_MAC_ADDR_RESET, 0x21D, cgx_mac_addr_reset, cgx_mac_addr_reset_req, \ 173 msg_rsp) \ 174 M(CGX_MAC_ADDR_UPDATE, 0x21E, cgx_mac_addr_update, cgx_mac_addr_update_req, \ 175 cgx_mac_addr_update_rsp) \ 176 M(CGX_PRIO_FLOW_CTRL_CFG, 0x21F, cgx_prio_flow_ctrl_cfg, cgx_pfc_cfg, \ 177 cgx_pfc_rsp) \ 178 /* NPA mbox IDs (range 0x400 - 0x5FF) */ \ 179 M(NPA_LF_ALLOC, 0x400, npa_lf_alloc, \ 180 npa_lf_alloc_req, npa_lf_alloc_rsp) \ 181 M(NPA_LF_FREE, 0x401, npa_lf_free, msg_req, msg_rsp) \ 182 M(NPA_AQ_ENQ, 0x402, npa_aq_enq, npa_aq_enq_req, npa_aq_enq_rsp) \ 183 M(NPA_HWCTX_DISABLE, 0x403, npa_hwctx_disable, hwctx_disable_req, msg_rsp)\ 184 /* SSO/SSOW mbox IDs (range 0x600 - 0x7FF) */ \ 185 /* TIM mbox IDs (range 0x800 - 0x9FF) */ \ 186 /* CPT mbox IDs (range 0xA00 - 0xBFF) */ \ 187 M(CPT_LF_ALLOC, 0xA00, cpt_lf_alloc, cpt_lf_alloc_req_msg, \ 188 msg_rsp) \ 189 M(CPT_LF_FREE, 0xA01, cpt_lf_free, msg_req, msg_rsp) \ 190 M(CPT_RD_WR_REGISTER, 0xA02, cpt_rd_wr_register, cpt_rd_wr_reg_msg, \ 191 cpt_rd_wr_reg_msg) \ 192 M(CPT_INLINE_IPSEC_CFG, 0xA04, cpt_inline_ipsec_cfg, \ 193 cpt_inline_ipsec_cfg_msg, msg_rsp) \ 194 M(CPT_STATS, 0xA05, cpt_sts, cpt_sts_req, cpt_sts_rsp) \ 195 M(CPT_RXC_TIME_CFG, 0xA06, cpt_rxc_time_cfg, cpt_rxc_time_cfg_req, \ 196 msg_rsp) \ 197 M(CPT_CTX_CACHE_SYNC, 0xA07, cpt_ctx_cache_sync, msg_req, msg_rsp) \ 198 /* SDP mbox IDs (range 0x1000 - 0x11FF) */ \ 199 M(SET_SDP_CHAN_INFO, 0x1000, set_sdp_chan_info, sdp_chan_info_msg, msg_rsp) \ 200 M(GET_SDP_CHAN_INFO, 0x1001, get_sdp_chan_info, msg_req, sdp_get_chan_info_msg) \ 201 /* NPC mbox IDs (range 0x6000 - 0x7FFF) */ \ 202 M(NPC_MCAM_ALLOC_ENTRY, 0x6000, npc_mcam_alloc_entry, npc_mcam_alloc_entry_req,\ 203 npc_mcam_alloc_entry_rsp) \ 204 M(NPC_MCAM_FREE_ENTRY, 0x6001, npc_mcam_free_entry, \ 205 npc_mcam_free_entry_req, msg_rsp) \ 206 M(NPC_MCAM_WRITE_ENTRY, 0x6002, npc_mcam_write_entry, \ 207 npc_mcam_write_entry_req, msg_rsp) \ 208 M(NPC_MCAM_ENA_ENTRY, 0x6003, npc_mcam_ena_entry, \ 209 npc_mcam_ena_dis_entry_req, msg_rsp) \ 210 M(NPC_MCAM_DIS_ENTRY, 0x6004, npc_mcam_dis_entry, \ 211 npc_mcam_ena_dis_entry_req, msg_rsp) \ 212 M(NPC_MCAM_SHIFT_ENTRY, 0x6005, npc_mcam_shift_entry, npc_mcam_shift_entry_req,\ 213 npc_mcam_shift_entry_rsp) \ 214 M(NPC_MCAM_ALLOC_COUNTER, 0x6006, npc_mcam_alloc_counter, \ 215 npc_mcam_alloc_counter_req, \ 216 npc_mcam_alloc_counter_rsp) \ 217 M(NPC_MCAM_FREE_COUNTER, 0x6007, npc_mcam_free_counter, \ 218 npc_mcam_oper_counter_req, msg_rsp) \ 219 M(NPC_MCAM_UNMAP_COUNTER, 0x6008, npc_mcam_unmap_counter, \ 220 npc_mcam_unmap_counter_req, msg_rsp) \ 221 M(NPC_MCAM_CLEAR_COUNTER, 0x6009, npc_mcam_clear_counter, \ 222 npc_mcam_oper_counter_req, msg_rsp) \ 223 M(NPC_MCAM_COUNTER_STATS, 0x600a, npc_mcam_counter_stats, \ 224 npc_mcam_oper_counter_req, \ 225 npc_mcam_oper_counter_rsp) \ 226 M(NPC_MCAM_ALLOC_AND_WRITE_ENTRY, 0x600b, npc_mcam_alloc_and_write_entry, \ 227 npc_mcam_alloc_and_write_entry_req, \ 228 npc_mcam_alloc_and_write_entry_rsp) \ 229 M(NPC_GET_KEX_CFG, 0x600c, npc_get_kex_cfg, \ 230 msg_req, npc_get_kex_cfg_rsp) \ 231 M(NPC_INSTALL_FLOW, 0x600d, npc_install_flow, \ 232 npc_install_flow_req, npc_install_flow_rsp) \ 233 M(NPC_DELETE_FLOW, 0x600e, npc_delete_flow, \ 234 npc_delete_flow_req, msg_rsp) \ 235 M(NPC_MCAM_READ_ENTRY, 0x600f, npc_mcam_read_entry, \ 236 npc_mcam_read_entry_req, \ 237 npc_mcam_read_entry_rsp) \ 238 M(NPC_SET_PKIND, 0x6010, npc_set_pkind, \ 239 npc_set_pkind, msg_rsp) \ 240 M(NPC_MCAM_READ_BASE_RULE, 0x6011, npc_read_base_steer_rule, \ 241 msg_req, npc_mcam_read_base_rule_rsp) \ 242 M(NPC_MCAM_GET_STATS, 0x6012, npc_mcam_entry_stats, \ 243 npc_mcam_get_stats_req, \ 244 npc_mcam_get_stats_rsp) \ 245 M(NPC_GET_SECRET_KEY, 0x6013, npc_get_secret_key, \ 246 npc_get_secret_key_req, \ 247 npc_get_secret_key_rsp) \ 248 M(NPC_GET_FIELD_STATUS, 0x6014, npc_get_field_status, \ 249 npc_get_field_status_req, \ 250 npc_get_field_status_rsp) \ 251 /* NIX mbox IDs (range 0x8000 - 0xFFFF) */ \ 252 M(NIX_LF_ALLOC, 0x8000, nix_lf_alloc, \ 253 nix_lf_alloc_req, nix_lf_alloc_rsp) \ 254 M(NIX_LF_FREE, 0x8001, nix_lf_free, nix_lf_free_req, msg_rsp) \ 255 M(NIX_AQ_ENQ, 0x8002, nix_aq_enq, nix_aq_enq_req, nix_aq_enq_rsp) \ 256 M(NIX_HWCTX_DISABLE, 0x8003, nix_hwctx_disable, \ 257 hwctx_disable_req, msg_rsp) \ 258 M(NIX_TXSCH_ALLOC, 0x8004, nix_txsch_alloc, \ 259 nix_txsch_alloc_req, nix_txsch_alloc_rsp) \ 260 M(NIX_TXSCH_FREE, 0x8005, nix_txsch_free, nix_txsch_free_req, msg_rsp) \ 261 M(NIX_TXSCHQ_CFG, 0x8006, nix_txschq_cfg, nix_txschq_config, \ 262 nix_txschq_config) \ 263 M(NIX_STATS_RST, 0x8007, nix_stats_rst, msg_req, msg_rsp) \ 264 M(NIX_VTAG_CFG, 0x8008, nix_vtag_cfg, nix_vtag_config, \ 265 nix_vtag_config_rsp) \ 266 M(NIX_RSS_FLOWKEY_CFG, 0x8009, nix_rss_flowkey_cfg, \ 267 nix_rss_flowkey_cfg, \ 268 nix_rss_flowkey_cfg_rsp) \ 269 M(NIX_SET_MAC_ADDR, 0x800a, nix_set_mac_addr, nix_set_mac_addr, msg_rsp) \ 270 M(NIX_SET_RX_MODE, 0x800b, nix_set_rx_mode, nix_rx_mode, msg_rsp) \ 271 M(NIX_SET_HW_FRS, 0x800c, nix_set_hw_frs, nix_frs_cfg, msg_rsp) \ 272 M(NIX_LF_START_RX, 0x800d, nix_lf_start_rx, msg_req, msg_rsp) \ 273 M(NIX_LF_STOP_RX, 0x800e, nix_lf_stop_rx, msg_req, msg_rsp) \ 274 M(NIX_MARK_FORMAT_CFG, 0x800f, nix_mark_format_cfg, \ 275 nix_mark_format_cfg, \ 276 nix_mark_format_cfg_rsp) \ 277 M(NIX_SET_RX_CFG, 0x8010, nix_set_rx_cfg, nix_rx_cfg, msg_rsp) \ 278 M(NIX_LSO_FORMAT_CFG, 0x8011, nix_lso_format_cfg, \ 279 nix_lso_format_cfg, \ 280 nix_lso_format_cfg_rsp) \ 281 M(NIX_LF_PTP_TX_ENABLE, 0x8013, nix_lf_ptp_tx_enable, msg_req, msg_rsp) \ 282 M(NIX_LF_PTP_TX_DISABLE, 0x8014, nix_lf_ptp_tx_disable, msg_req, msg_rsp) \ 283 M(NIX_BP_ENABLE, 0x8016, nix_bp_enable, nix_bp_cfg_req, \ 284 nix_bp_cfg_rsp) \ 285 M(NIX_BP_DISABLE, 0x8017, nix_bp_disable, nix_bp_cfg_req, msg_rsp) \ 286 M(NIX_GET_MAC_ADDR, 0x8018, nix_get_mac_addr, msg_req, nix_get_mac_addr_rsp) \ 287 M(NIX_INLINE_IPSEC_CFG, 0x8019, nix_inline_ipsec_cfg, \ 288 nix_inline_ipsec_cfg, msg_rsp) \ 289 M(NIX_INLINE_IPSEC_LF_CFG, 0x801a, nix_inline_ipsec_lf_cfg, \ 290 nix_inline_ipsec_lf_cfg, msg_rsp) \ 291 M(NIX_CN10K_AQ_ENQ, 0x801b, nix_cn10k_aq_enq, nix_cn10k_aq_enq_req, \ 292 nix_cn10k_aq_enq_rsp) \ 293 M(NIX_GET_HW_INFO, 0x801c, nix_get_hw_info, msg_req, nix_hw_info) \ 294 M(NIX_BANDPROF_ALLOC, 0x801d, nix_bandprof_alloc, nix_bandprof_alloc_req, \ 295 nix_bandprof_alloc_rsp) \ 296 M(NIX_BANDPROF_FREE, 0x801e, nix_bandprof_free, nix_bandprof_free_req, \ 297 msg_rsp) \ 298 M(NIX_BANDPROF_GET_HWINFO, 0x801f, nix_bandprof_get_hwinfo, msg_req, \ 299 nix_bandprof_get_hwinfo_rsp) \ 300 M(NIX_READ_INLINE_IPSEC_CFG, 0x8023, nix_read_inline_ipsec_cfg, \ 301 msg_req, nix_inline_ipsec_cfg) \ 302 /* MCS mbox IDs (range 0xA000 - 0xBFFF) */ \ 303 M(MCS_ALLOC_RESOURCES, 0xa000, mcs_alloc_resources, mcs_alloc_rsrc_req, \ 304 mcs_alloc_rsrc_rsp) \ 305 M(MCS_FREE_RESOURCES, 0xa001, mcs_free_resources, mcs_free_rsrc_req, msg_rsp) \ 306 M(MCS_FLOWID_ENTRY_WRITE, 0xa002, mcs_flowid_entry_write, mcs_flowid_entry_write_req, \ 307 msg_rsp) \ 308 M(MCS_SECY_PLCY_WRITE, 0xa003, mcs_secy_plcy_write, mcs_secy_plcy_write_req, \ 309 msg_rsp) \ 310 M(MCS_RX_SC_CAM_WRITE, 0xa004, mcs_rx_sc_cam_write, mcs_rx_sc_cam_write_req, \ 311 msg_rsp) \ 312 M(MCS_SA_PLCY_WRITE, 0xa005, mcs_sa_plcy_write, mcs_sa_plcy_write_req, \ 313 msg_rsp) \ 314 M(MCS_TX_SC_SA_MAP_WRITE, 0xa006, mcs_tx_sc_sa_map_write, mcs_tx_sc_sa_map, \ 315 msg_rsp) \ 316 M(MCS_RX_SC_SA_MAP_WRITE, 0xa007, mcs_rx_sc_sa_map_write, mcs_rx_sc_sa_map, \ 317 msg_rsp) \ 318 M(MCS_FLOWID_ENA_ENTRY, 0xa008, mcs_flowid_ena_entry, mcs_flowid_ena_dis_entry, \ 319 msg_rsp) \ 320 M(MCS_PN_TABLE_WRITE, 0xa009, mcs_pn_table_write, mcs_pn_table_write_req, \ 321 msg_rsp) \ 322 M(MCS_SET_ACTIVE_LMAC, 0xa00a, mcs_set_active_lmac, mcs_set_active_lmac, \ 323 msg_rsp) \ 324 M(MCS_GET_HW_INFO, 0xa00b, mcs_get_hw_info, msg_req, mcs_hw_info) \ 325 M(MCS_GET_FLOWID_STATS, 0xa00c, mcs_get_flowid_stats, mcs_stats_req, \ 326 mcs_flowid_stats) \ 327 M(MCS_GET_SECY_STATS, 0xa00d, mcs_get_secy_stats, mcs_stats_req, \ 328 mcs_secy_stats) \ 329 M(MCS_GET_SC_STATS, 0xa00e, mcs_get_sc_stats, mcs_stats_req, mcs_sc_stats) \ 330 M(MCS_GET_SA_STATS, 0xa00f, mcs_get_sa_stats, mcs_stats_req, mcs_sa_stats) \ 331 M(MCS_GET_PORT_STATS, 0xa010, mcs_get_port_stats, mcs_stats_req, \ 332 mcs_port_stats) \ 333 M(MCS_CLEAR_STATS, 0xa011, mcs_clear_stats, mcs_clear_stats, msg_rsp) \ 334 M(MCS_INTR_CFG, 0xa012, mcs_intr_cfg, mcs_intr_cfg, msg_rsp) \ 335 M(MCS_SET_LMAC_MODE, 0xa013, mcs_set_lmac_mode, mcs_set_lmac_mode, msg_rsp) \ 336 M(MCS_SET_PN_THRESHOLD, 0xa014, mcs_set_pn_threshold, mcs_set_pn_threshold, \ 337 msg_rsp) \ 338 M(MCS_ALLOC_CTRL_PKT_RULE, 0xa015, mcs_alloc_ctrl_pkt_rule, \ 339 mcs_alloc_ctrl_pkt_rule_req, \ 340 mcs_alloc_ctrl_pkt_rule_rsp) \ 341 M(MCS_FREE_CTRL_PKT_RULE, 0xa016, mcs_free_ctrl_pkt_rule, \ 342 mcs_free_ctrl_pkt_rule_req, msg_rsp) \ 343 M(MCS_CTRL_PKT_RULE_WRITE, 0xa017, mcs_ctrl_pkt_rule_write, \ 344 mcs_ctrl_pkt_rule_write_req, msg_rsp) \ 345 M(MCS_PORT_RESET, 0xa018, mcs_port_reset, mcs_port_reset_req, msg_rsp) \ 346 M(MCS_PORT_CFG_SET, 0xa019, mcs_port_cfg_set, mcs_port_cfg_set_req, msg_rsp)\ 347 M(MCS_PORT_CFG_GET, 0xa020, mcs_port_cfg_get, mcs_port_cfg_get_req, \ 348 mcs_port_cfg_get_rsp) \ 349 M(MCS_CUSTOM_TAG_CFG_GET, 0xa021, mcs_custom_tag_cfg_get, \ 350 mcs_custom_tag_cfg_get_req, \ 351 mcs_custom_tag_cfg_get_rsp) 352 353 /* Messages initiated by AF (range 0xC00 - 0xEFF) */ 354 #define MBOX_UP_CGX_MESSAGES \ 355 M(CGX_LINK_EVENT, 0xC00, cgx_link_event, cgx_link_info_msg, msg_rsp) 356 357 #define MBOX_UP_CPT_MESSAGES \ 358 M(CPT_INST_LMTST, 0xD00, cpt_inst_lmtst, cpt_inst_lmtst_req, msg_rsp) 359 360 #define MBOX_UP_MCS_MESSAGES \ 361 M(MCS_INTR_NOTIFY, 0xE00, mcs_intr_notify, mcs_intr_info, msg_rsp) 362 363 enum { 364 #define M(_name, _id, _1, _2, _3) MBOX_MSG_ ## _name = _id, 365 MBOX_MESSAGES 366 MBOX_UP_CGX_MESSAGES 367 MBOX_UP_CPT_MESSAGES 368 MBOX_UP_MCS_MESSAGES 369 #undef M 370 }; 371 372 /* Mailbox message formats */ 373 374 #define RVU_DEFAULT_PF_FUNC 0xFFFF 375 376 /* Generic request msg used for those mbox messages which 377 * don't send any data in the request. 378 */ 379 struct msg_req { 380 struct mbox_msghdr hdr; 381 }; 382 383 /* Generic response msg used an ack or response for those mbox 384 * messages which don't have a specific rsp msg format. 385 */ 386 struct msg_rsp { 387 struct mbox_msghdr hdr; 388 }; 389 390 /* RVU mailbox error codes 391 * Range 256 - 300. 392 */ 393 enum rvu_af_status { 394 RVU_INVALID_VF_ID = -256, 395 }; 396 397 struct ready_msg_rsp { 398 struct mbox_msghdr hdr; 399 u16 sclk_freq; /* SCLK frequency (in MHz) */ 400 u16 rclk_freq; /* RCLK frequency (in MHz) */ 401 }; 402 403 /* Structure for requesting resource provisioning. 404 * 'modify' flag to be used when either requesting more 405 * or to detach partial of a certain resource type. 406 * Rest of the fields specify how many of what type to 407 * be attached. 408 * To request LFs from two blocks of same type this mailbox 409 * can be sent twice as below: 410 * struct rsrc_attach *attach; 411 * .. Allocate memory for message .. 412 * attach->cptlfs = 3; <3 LFs from CPT0> 413 * .. Send message .. 414 * .. Allocate memory for message .. 415 * attach->modify = 1; 416 * attach->cpt_blkaddr = BLKADDR_CPT1; 417 * attach->cptlfs = 2; <2 LFs from CPT1> 418 * .. Send message .. 419 */ 420 struct rsrc_attach { 421 struct mbox_msghdr hdr; 422 u8 modify:1; 423 u8 npalf:1; 424 u8 nixlf:1; 425 u16 sso; 426 u16 ssow; 427 u16 timlfs; 428 u16 cptlfs; 429 int cpt_blkaddr; /* BLKADDR_CPT0/BLKADDR_CPT1 or 0 for BLKADDR_CPT0 */ 430 }; 431 432 /* Structure for relinquishing resources. 433 * 'partial' flag to be used when relinquishing all resources 434 * but only of a certain type. If not set, all resources of all 435 * types provisioned to the RVU function will be detached. 436 */ 437 struct rsrc_detach { 438 struct mbox_msghdr hdr; 439 u8 partial:1; 440 u8 npalf:1; 441 u8 nixlf:1; 442 u8 sso:1; 443 u8 ssow:1; 444 u8 timlfs:1; 445 u8 cptlfs:1; 446 }; 447 448 /* Number of resources available to the caller. 449 * In reply to MBOX_MSG_FREE_RSRC_CNT. 450 */ 451 struct free_rsrcs_rsp { 452 struct mbox_msghdr hdr; 453 u16 schq[NIX_TXSCH_LVL_CNT]; 454 u16 sso; 455 u16 tim; 456 u16 ssow; 457 u16 cpt; 458 u8 npa; 459 u8 nix; 460 u16 schq_nix1[NIX_TXSCH_LVL_CNT]; 461 u8 nix1; 462 u8 cpt1; 463 u8 ree0; 464 u8 ree1; 465 }; 466 467 #define MSIX_VECTOR_INVALID 0xFFFF 468 #define MAX_RVU_BLKLF_CNT 256 469 470 struct msix_offset_rsp { 471 struct mbox_msghdr hdr; 472 u16 npa_msixoff; 473 u16 nix_msixoff; 474 u16 sso; 475 u16 ssow; 476 u16 timlfs; 477 u16 cptlfs; 478 u16 sso_msixoff[MAX_RVU_BLKLF_CNT]; 479 u16 ssow_msixoff[MAX_RVU_BLKLF_CNT]; 480 u16 timlf_msixoff[MAX_RVU_BLKLF_CNT]; 481 u16 cptlf_msixoff[MAX_RVU_BLKLF_CNT]; 482 u16 cpt1_lfs; 483 u16 ree0_lfs; 484 u16 ree1_lfs; 485 u16 cpt1_lf_msixoff[MAX_RVU_BLKLF_CNT]; 486 u16 ree0_lf_msixoff[MAX_RVU_BLKLF_CNT]; 487 u16 ree1_lf_msixoff[MAX_RVU_BLKLF_CNT]; 488 }; 489 490 struct get_hw_cap_rsp { 491 struct mbox_msghdr hdr; 492 u8 nix_fixed_txschq_mapping; /* Schq mapping fixed or flexible */ 493 u8 nix_shaping; /* Is shaping and coloring supported */ 494 u8 npc_hash_extract; /* Is hash extract supported */ 495 }; 496 497 /* CGX mbox message formats */ 498 499 struct cgx_stats_rsp { 500 struct mbox_msghdr hdr; 501 #define CGX_RX_STATS_COUNT 9 502 #define CGX_TX_STATS_COUNT 18 503 u64 rx_stats[CGX_RX_STATS_COUNT]; 504 u64 tx_stats[CGX_TX_STATS_COUNT]; 505 }; 506 507 struct cgx_fec_stats_rsp { 508 struct mbox_msghdr hdr; 509 u64 fec_corr_blks; 510 u64 fec_uncorr_blks; 511 }; 512 /* Structure for requesting the operation for 513 * setting/getting mac address in the CGX interface 514 */ 515 struct cgx_mac_addr_set_or_get { 516 struct mbox_msghdr hdr; 517 u8 mac_addr[ETH_ALEN]; 518 u32 index; 519 }; 520 521 /* Structure for requesting the operation to 522 * add DMAC filter entry into CGX interface 523 */ 524 struct cgx_mac_addr_add_req { 525 struct mbox_msghdr hdr; 526 u8 mac_addr[ETH_ALEN]; 527 }; 528 529 /* Structure for response against the operation to 530 * add DMAC filter entry into CGX interface 531 */ 532 struct cgx_mac_addr_add_rsp { 533 struct mbox_msghdr hdr; 534 u32 index; 535 }; 536 537 /* Structure for requesting the operation to 538 * delete DMAC filter entry from CGX interface 539 */ 540 struct cgx_mac_addr_del_req { 541 struct mbox_msghdr hdr; 542 u32 index; 543 }; 544 545 /* Structure for response against the operation to 546 * get maximum supported DMAC filter entries 547 */ 548 struct cgx_max_dmac_entries_get_rsp { 549 struct mbox_msghdr hdr; 550 u32 max_dmac_filters; 551 }; 552 553 struct cgx_link_user_info { 554 uint64_t link_up:1; 555 uint64_t full_duplex:1; 556 uint64_t lmac_type_id:4; 557 uint64_t speed:20; /* speed in Mbps */ 558 uint64_t an:1; /* AN supported or not */ 559 uint64_t fec:2; /* FEC type if enabled else 0 */ 560 #define LMACTYPE_STR_LEN 16 561 char lmac_type[LMACTYPE_STR_LEN]; 562 }; 563 564 struct cgx_link_info_msg { 565 struct mbox_msghdr hdr; 566 struct cgx_link_user_info link_info; 567 }; 568 569 struct cgx_pause_frm_cfg { 570 struct mbox_msghdr hdr; 571 u8 set; 572 /* set = 1 if the request is to config pause frames */ 573 /* set = 0 if the request is to fetch pause frames config */ 574 u8 rx_pause; 575 u8 tx_pause; 576 }; 577 578 enum fec_type { 579 OTX2_FEC_NONE, 580 OTX2_FEC_BASER, 581 OTX2_FEC_RS, 582 OTX2_FEC_STATS_CNT = 2, 583 OTX2_FEC_OFF, 584 }; 585 586 struct fec_mode { 587 struct mbox_msghdr hdr; 588 int fec; 589 }; 590 591 struct sfp_eeprom_s { 592 #define SFP_EEPROM_SIZE 256 593 u16 sff_id; 594 u8 buf[SFP_EEPROM_SIZE]; 595 u64 reserved; 596 }; 597 598 struct phy_s { 599 struct { 600 u64 can_change_mod_type:1; 601 u64 mod_type:1; 602 u64 has_fec_stats:1; 603 } misc; 604 struct fec_stats_s { 605 u32 rsfec_corr_cws; 606 u32 rsfec_uncorr_cws; 607 u32 brfec_corr_blks; 608 u32 brfec_uncorr_blks; 609 } fec_stats; 610 }; 611 612 struct cgx_lmac_fwdata_s { 613 u16 rw_valid; 614 u64 supported_fec; 615 u64 supported_an; 616 u64 supported_link_modes; 617 /* only applicable if AN is supported */ 618 u64 advertised_fec; 619 u64 advertised_link_modes; 620 /* Only applicable if SFP/QSFP slot is present */ 621 struct sfp_eeprom_s sfp_eeprom; 622 struct phy_s phy; 623 #define LMAC_FWDATA_RESERVED_MEM 1021 624 u64 reserved[LMAC_FWDATA_RESERVED_MEM]; 625 }; 626 627 struct cgx_fw_data { 628 struct mbox_msghdr hdr; 629 struct cgx_lmac_fwdata_s fwdata; 630 }; 631 632 struct cgx_set_link_mode_args { 633 u32 speed; 634 u8 duplex; 635 u8 an; 636 u8 ports; 637 u64 mode; 638 }; 639 640 struct cgx_set_link_mode_req { 641 #define AUTONEG_UNKNOWN 0xff 642 struct mbox_msghdr hdr; 643 struct cgx_set_link_mode_args args; 644 }; 645 646 struct cgx_set_link_mode_rsp { 647 struct mbox_msghdr hdr; 648 int status; 649 }; 650 651 struct cgx_mac_addr_reset_req { 652 struct mbox_msghdr hdr; 653 u32 index; 654 }; 655 656 struct cgx_mac_addr_update_req { 657 struct mbox_msghdr hdr; 658 u8 mac_addr[ETH_ALEN]; 659 u32 index; 660 }; 661 662 struct cgx_mac_addr_update_rsp { 663 struct mbox_msghdr hdr; 664 u32 index; 665 }; 666 667 #define RVU_LMAC_FEAT_FC BIT_ULL(0) /* pause frames */ 668 #define RVU_LMAC_FEAT_HIGIG2 BIT_ULL(1) 669 /* flow control from physical link higig2 messages */ 670 #define RVU_LMAC_FEAT_PTP BIT_ULL(2) /* precison time protocol */ 671 #define RVU_LMAC_FEAT_DMACF BIT_ULL(3) /* DMAC FILTER */ 672 #define RVU_MAC_VERSION BIT_ULL(4) 673 #define RVU_MAC_CGX BIT_ULL(5) 674 #define RVU_MAC_RPM BIT_ULL(6) 675 676 struct cgx_features_info_msg { 677 struct mbox_msghdr hdr; 678 u64 lmac_features; 679 }; 680 681 struct rpm_stats_rsp { 682 struct mbox_msghdr hdr; 683 #define RPM_RX_STATS_COUNT 43 684 #define RPM_TX_STATS_COUNT 34 685 u64 rx_stats[RPM_RX_STATS_COUNT]; 686 u64 tx_stats[RPM_TX_STATS_COUNT]; 687 }; 688 689 struct cgx_pfc_cfg { 690 struct mbox_msghdr hdr; 691 u8 rx_pause; 692 u8 tx_pause; 693 u16 pfc_en; /* bitmap indicating pfc enabled traffic classes */ 694 }; 695 696 struct cgx_pfc_rsp { 697 struct mbox_msghdr hdr; 698 u8 rx_pause; 699 u8 tx_pause; 700 }; 701 702 /* NPA mbox message formats */ 703 704 struct npc_set_pkind { 705 struct mbox_msghdr hdr; 706 #define OTX2_PRIV_FLAGS_DEFAULT BIT_ULL(0) 707 #define OTX2_PRIV_FLAGS_CUSTOM BIT_ULL(63) 708 u64 mode; 709 #define PKIND_TX BIT_ULL(0) 710 #define PKIND_RX BIT_ULL(1) 711 u8 dir; 712 u8 pkind; /* valid only in case custom flag */ 713 u8 var_len_off; /* Offset of custom header length field. 714 * Valid only for pkind NPC_RX_CUSTOM_PRE_L2_PKIND 715 */ 716 u8 var_len_off_mask; /* Mask for length with in offset */ 717 u8 shift_dir; /* shift direction to get length of the header at var_len_off */ 718 }; 719 720 /* NPA mbox message formats */ 721 722 /* NPA mailbox error codes 723 * Range 301 - 400. 724 */ 725 enum npa_af_status { 726 NPA_AF_ERR_PARAM = -301, 727 NPA_AF_ERR_AQ_FULL = -302, 728 NPA_AF_ERR_AQ_ENQUEUE = -303, 729 NPA_AF_ERR_AF_LF_INVALID = -304, 730 NPA_AF_ERR_AF_LF_ALLOC = -305, 731 NPA_AF_ERR_LF_RESET = -306, 732 }; 733 734 /* For NPA LF context alloc and init */ 735 struct npa_lf_alloc_req { 736 struct mbox_msghdr hdr; 737 int node; 738 int aura_sz; /* No of auras */ 739 u32 nr_pools; /* No of pools */ 740 u64 way_mask; 741 }; 742 743 struct npa_lf_alloc_rsp { 744 struct mbox_msghdr hdr; 745 u32 stack_pg_ptrs; /* No of ptrs per stack page */ 746 u32 stack_pg_bytes; /* Size of stack page */ 747 u16 qints; /* NPA_AF_CONST::QINTS */ 748 u8 cache_lines; /*BATCH ALLOC DMA */ 749 }; 750 751 /* NPA AQ enqueue msg */ 752 struct npa_aq_enq_req { 753 struct mbox_msghdr hdr; 754 u32 aura_id; 755 u8 ctype; 756 u8 op; 757 union { 758 /* Valid when op == WRITE/INIT and ctype == AURA. 759 * LF fills the pool_id in aura.pool_addr. AF will translate 760 * the pool_id to pool context pointer. 761 */ 762 struct npa_aura_s aura; 763 /* Valid when op == WRITE/INIT and ctype == POOL */ 764 struct npa_pool_s pool; 765 }; 766 /* Mask data when op == WRITE (1=write, 0=don't write) */ 767 union { 768 /* Valid when op == WRITE and ctype == AURA */ 769 struct npa_aura_s aura_mask; 770 /* Valid when op == WRITE and ctype == POOL */ 771 struct npa_pool_s pool_mask; 772 }; 773 }; 774 775 struct npa_aq_enq_rsp { 776 struct mbox_msghdr hdr; 777 union { 778 /* Valid when op == READ and ctype == AURA */ 779 struct npa_aura_s aura; 780 /* Valid when op == READ and ctype == POOL */ 781 struct npa_pool_s pool; 782 }; 783 }; 784 785 /* Disable all contexts of type 'ctype' */ 786 struct hwctx_disable_req { 787 struct mbox_msghdr hdr; 788 u8 ctype; 789 }; 790 791 /* NIX mbox message formats */ 792 793 /* NIX mailbox error codes 794 * Range 401 - 500. 795 */ 796 enum nix_af_status { 797 NIX_AF_ERR_PARAM = -401, 798 NIX_AF_ERR_AQ_FULL = -402, 799 NIX_AF_ERR_AQ_ENQUEUE = -403, 800 NIX_AF_ERR_AF_LF_INVALID = -404, 801 NIX_AF_ERR_AF_LF_ALLOC = -405, 802 NIX_AF_ERR_TLX_ALLOC_FAIL = -406, 803 NIX_AF_ERR_TLX_INVALID = -407, 804 NIX_AF_ERR_RSS_SIZE_INVALID = -408, 805 NIX_AF_ERR_RSS_GRPS_INVALID = -409, 806 NIX_AF_ERR_FRS_INVALID = -410, 807 NIX_AF_ERR_RX_LINK_INVALID = -411, 808 NIX_AF_INVAL_TXSCHQ_CFG = -412, 809 NIX_AF_SMQ_FLUSH_FAILED = -413, 810 NIX_AF_ERR_LF_RESET = -414, 811 NIX_AF_ERR_RSS_NOSPC_FIELD = -415, 812 NIX_AF_ERR_RSS_NOSPC_ALGO = -416, 813 NIX_AF_ERR_MARK_CFG_FAIL = -417, 814 NIX_AF_ERR_LSO_CFG_FAIL = -418, 815 NIX_AF_INVAL_NPA_PF_FUNC = -419, 816 NIX_AF_INVAL_SSO_PF_FUNC = -420, 817 NIX_AF_ERR_TX_VTAG_NOSPC = -421, 818 NIX_AF_ERR_RX_VTAG_INUSE = -422, 819 NIX_AF_ERR_PTP_CONFIG_FAIL = -423, 820 NIX_AF_ERR_NPC_KEY_NOT_SUPP = -424, 821 NIX_AF_ERR_INVALID_NIXBLK = -425, 822 NIX_AF_ERR_INVALID_BANDPROF = -426, 823 NIX_AF_ERR_IPOLICER_NOTSUPP = -427, 824 NIX_AF_ERR_BANDPROF_INVAL_REQ = -428, 825 NIX_AF_ERR_CQ_CTX_WRITE_ERR = -429, 826 NIX_AF_ERR_AQ_CTX_RETRY_WRITE = -430, 827 NIX_AF_ERR_LINK_CREDITS = -431, 828 }; 829 830 /* For NIX RX vtag action */ 831 enum nix_rx_vtag0_type { 832 NIX_AF_LFX_RX_VTAG_TYPE0, /* reserved for rx vlan offload */ 833 NIX_AF_LFX_RX_VTAG_TYPE1, 834 NIX_AF_LFX_RX_VTAG_TYPE2, 835 NIX_AF_LFX_RX_VTAG_TYPE3, 836 NIX_AF_LFX_RX_VTAG_TYPE4, 837 NIX_AF_LFX_RX_VTAG_TYPE5, 838 NIX_AF_LFX_RX_VTAG_TYPE6, 839 NIX_AF_LFX_RX_VTAG_TYPE7, 840 }; 841 842 /* For NIX LF context alloc and init */ 843 struct nix_lf_alloc_req { 844 struct mbox_msghdr hdr; 845 int node; 846 u32 rq_cnt; /* No of receive queues */ 847 u32 sq_cnt; /* No of send queues */ 848 u32 cq_cnt; /* No of completion queues */ 849 u8 xqe_sz; 850 u16 rss_sz; 851 u8 rss_grps; 852 u16 npa_func; 853 u16 sso_func; 854 u64 rx_cfg; /* See NIX_AF_LF(0..127)_RX_CFG */ 855 u64 way_mask; 856 #define NIX_LF_RSS_TAG_LSB_AS_ADDER BIT_ULL(0) 857 #define NIX_LF_LBK_BLK_SEL BIT_ULL(1) 858 u64 flags; 859 }; 860 861 struct nix_lf_alloc_rsp { 862 struct mbox_msghdr hdr; 863 u16 sqb_size; 864 u16 rx_chan_base; 865 u16 tx_chan_base; 866 u8 rx_chan_cnt; /* total number of RX channels */ 867 u8 tx_chan_cnt; /* total number of TX channels */ 868 u8 lso_tsov4_idx; 869 u8 lso_tsov6_idx; 870 u8 mac_addr[ETH_ALEN]; 871 u8 lf_rx_stats; /* NIX_AF_CONST1::LF_RX_STATS */ 872 u8 lf_tx_stats; /* NIX_AF_CONST1::LF_TX_STATS */ 873 u16 cints; /* NIX_AF_CONST2::CINTS */ 874 u16 qints; /* NIX_AF_CONST2::QINTS */ 875 u8 cgx_links; /* No. of CGX links present in HW */ 876 u8 lbk_links; /* No. of LBK links present in HW */ 877 u8 sdp_links; /* No. of SDP links present in HW */ 878 u8 tx_link; /* Transmit channel link number */ 879 }; 880 881 struct nix_lf_free_req { 882 struct mbox_msghdr hdr; 883 #define NIX_LF_DISABLE_FLOWS BIT_ULL(0) 884 #define NIX_LF_DONT_FREE_TX_VTAG BIT_ULL(1) 885 u64 flags; 886 }; 887 888 /* CN10K NIX AQ enqueue msg */ 889 struct nix_cn10k_aq_enq_req { 890 struct mbox_msghdr hdr; 891 u32 qidx; 892 u8 ctype; 893 u8 op; 894 union { 895 struct nix_cn10k_rq_ctx_s rq; 896 struct nix_cn10k_sq_ctx_s sq; 897 struct nix_cq_ctx_s cq; 898 struct nix_rsse_s rss; 899 struct nix_rx_mce_s mce; 900 struct nix_bandprof_s prof; 901 }; 902 union { 903 struct nix_cn10k_rq_ctx_s rq_mask; 904 struct nix_cn10k_sq_ctx_s sq_mask; 905 struct nix_cq_ctx_s cq_mask; 906 struct nix_rsse_s rss_mask; 907 struct nix_rx_mce_s mce_mask; 908 struct nix_bandprof_s prof_mask; 909 }; 910 }; 911 912 struct nix_cn10k_aq_enq_rsp { 913 struct mbox_msghdr hdr; 914 union { 915 struct nix_cn10k_rq_ctx_s rq; 916 struct nix_cn10k_sq_ctx_s sq; 917 struct nix_cq_ctx_s cq; 918 struct nix_rsse_s rss; 919 struct nix_rx_mce_s mce; 920 struct nix_bandprof_s prof; 921 }; 922 }; 923 924 /* NIX AQ enqueue msg */ 925 struct nix_aq_enq_req { 926 struct mbox_msghdr hdr; 927 u32 qidx; 928 u8 ctype; 929 u8 op; 930 union { 931 struct nix_rq_ctx_s rq; 932 struct nix_sq_ctx_s sq; 933 struct nix_cq_ctx_s cq; 934 struct nix_rsse_s rss; 935 struct nix_rx_mce_s mce; 936 u64 prof; 937 }; 938 union { 939 struct nix_rq_ctx_s rq_mask; 940 struct nix_sq_ctx_s sq_mask; 941 struct nix_cq_ctx_s cq_mask; 942 struct nix_rsse_s rss_mask; 943 struct nix_rx_mce_s mce_mask; 944 u64 prof_mask; 945 }; 946 }; 947 948 struct nix_aq_enq_rsp { 949 struct mbox_msghdr hdr; 950 union { 951 struct nix_rq_ctx_s rq; 952 struct nix_sq_ctx_s sq; 953 struct nix_cq_ctx_s cq; 954 struct nix_rsse_s rss; 955 struct nix_rx_mce_s mce; 956 struct nix_bandprof_s prof; 957 }; 958 }; 959 960 /* Tx scheduler/shaper mailbox messages */ 961 962 #define MAX_TXSCHQ_PER_FUNC 128 963 964 struct nix_txsch_alloc_req { 965 struct mbox_msghdr hdr; 966 /* Scheduler queue count request at each level */ 967 u16 schq_contig[NIX_TXSCH_LVL_CNT]; /* No of contiguous queues */ 968 u16 schq[NIX_TXSCH_LVL_CNT]; /* No of non-contiguous queues */ 969 }; 970 971 struct nix_txsch_alloc_rsp { 972 struct mbox_msghdr hdr; 973 /* Scheduler queue count allocated at each level */ 974 u16 schq_contig[NIX_TXSCH_LVL_CNT]; 975 u16 schq[NIX_TXSCH_LVL_CNT]; 976 /* Scheduler queue list allocated at each level */ 977 u16 schq_contig_list[NIX_TXSCH_LVL_CNT][MAX_TXSCHQ_PER_FUNC]; 978 u16 schq_list[NIX_TXSCH_LVL_CNT][MAX_TXSCHQ_PER_FUNC]; 979 u8 aggr_level; /* Traffic aggregation scheduler level */ 980 u8 aggr_lvl_rr_prio; /* Aggregation lvl's RR_PRIO config */ 981 u8 link_cfg_lvl; /* LINKX_CFG CSRs mapped to TL3 or TL2's index ? */ 982 }; 983 984 struct nix_txsch_free_req { 985 struct mbox_msghdr hdr; 986 #define TXSCHQ_FREE_ALL BIT_ULL(0) 987 u16 flags; 988 /* Scheduler queue level to be freed */ 989 u16 schq_lvl; 990 /* List of scheduler queues to be freed */ 991 u16 schq; 992 }; 993 994 struct nix_txschq_config { 995 struct mbox_msghdr hdr; 996 u8 lvl; /* SMQ/MDQ/TL4/TL3/TL2/TL1 */ 997 u8 read; 998 #define TXSCHQ_IDX_SHIFT 16 999 #define TXSCHQ_IDX_MASK (BIT_ULL(10) - 1) 1000 #define TXSCHQ_IDX(reg, shift) (((reg) >> (shift)) & TXSCHQ_IDX_MASK) 1001 u8 num_regs; 1002 #define MAX_REGS_PER_MBOX_MSG 20 1003 u64 reg[MAX_REGS_PER_MBOX_MSG]; 1004 u64 regval[MAX_REGS_PER_MBOX_MSG]; 1005 /* All 0's => overwrite with new value */ 1006 u64 regval_mask[MAX_REGS_PER_MBOX_MSG]; 1007 }; 1008 1009 struct nix_vtag_config { 1010 struct mbox_msghdr hdr; 1011 /* '0' for 4 octet VTAG, '1' for 8 octet VTAG */ 1012 u8 vtag_size; 1013 /* cfg_type is '0' for tx vlan cfg 1014 * cfg_type is '1' for rx vlan cfg 1015 */ 1016 u8 cfg_type; 1017 union { 1018 /* valid when cfg_type is '0' */ 1019 struct { 1020 u64 vtag0; 1021 u64 vtag1; 1022 1023 /* cfg_vtag0 & cfg_vtag1 fields are valid 1024 * when free_vtag0 & free_vtag1 are '0's. 1025 */ 1026 /* cfg_vtag0 = 1 to configure vtag0 */ 1027 u8 cfg_vtag0 :1; 1028 /* cfg_vtag1 = 1 to configure vtag1 */ 1029 u8 cfg_vtag1 :1; 1030 1031 /* vtag0_idx & vtag1_idx are only valid when 1032 * both cfg_vtag0 & cfg_vtag1 are '0's, 1033 * these fields are used along with free_vtag0 1034 * & free_vtag1 to free the nix lf's tx_vlan 1035 * configuration. 1036 * 1037 * Denotes the indices of tx_vtag def registers 1038 * that needs to be cleared and freed. 1039 */ 1040 int vtag0_idx; 1041 int vtag1_idx; 1042 1043 /* free_vtag0 & free_vtag1 fields are valid 1044 * when cfg_vtag0 & cfg_vtag1 are '0's. 1045 */ 1046 /* free_vtag0 = 1 clears vtag0 configuration 1047 * vtag0_idx denotes the index to be cleared. 1048 */ 1049 u8 free_vtag0 :1; 1050 /* free_vtag1 = 1 clears vtag1 configuration 1051 * vtag1_idx denotes the index to be cleared. 1052 */ 1053 u8 free_vtag1 :1; 1054 } tx; 1055 1056 /* valid when cfg_type is '1' */ 1057 struct { 1058 /* rx vtag type index, valid values are in 0..7 range */ 1059 u8 vtag_type; 1060 /* rx vtag strip */ 1061 u8 strip_vtag :1; 1062 /* rx vtag capture */ 1063 u8 capture_vtag :1; 1064 } rx; 1065 }; 1066 }; 1067 1068 struct nix_vtag_config_rsp { 1069 struct mbox_msghdr hdr; 1070 int vtag0_idx; 1071 int vtag1_idx; 1072 /* Indices of tx_vtag def registers used to configure 1073 * tx vtag0 & vtag1 headers, these indices are valid 1074 * when nix_vtag_config mbox requested for vtag0 and/ 1075 * or vtag1 configuration. 1076 */ 1077 }; 1078 1079 struct nix_rss_flowkey_cfg { 1080 struct mbox_msghdr hdr; 1081 int mcam_index; /* MCAM entry index to modify */ 1082 #define NIX_FLOW_KEY_TYPE_PORT BIT(0) 1083 #define NIX_FLOW_KEY_TYPE_IPV4 BIT(1) 1084 #define NIX_FLOW_KEY_TYPE_IPV6 BIT(2) 1085 #define NIX_FLOW_KEY_TYPE_TCP BIT(3) 1086 #define NIX_FLOW_KEY_TYPE_UDP BIT(4) 1087 #define NIX_FLOW_KEY_TYPE_SCTP BIT(5) 1088 #define NIX_FLOW_KEY_TYPE_NVGRE BIT(6) 1089 #define NIX_FLOW_KEY_TYPE_VXLAN BIT(7) 1090 #define NIX_FLOW_KEY_TYPE_GENEVE BIT(8) 1091 #define NIX_FLOW_KEY_TYPE_ETH_DMAC BIT(9) 1092 #define NIX_FLOW_KEY_TYPE_IPV6_EXT BIT(10) 1093 #define NIX_FLOW_KEY_TYPE_GTPU BIT(11) 1094 #define NIX_FLOW_KEY_TYPE_INNR_IPV4 BIT(12) 1095 #define NIX_FLOW_KEY_TYPE_INNR_IPV6 BIT(13) 1096 #define NIX_FLOW_KEY_TYPE_INNR_TCP BIT(14) 1097 #define NIX_FLOW_KEY_TYPE_INNR_UDP BIT(15) 1098 #define NIX_FLOW_KEY_TYPE_INNR_SCTP BIT(16) 1099 #define NIX_FLOW_KEY_TYPE_INNR_ETH_DMAC BIT(17) 1100 #define NIX_FLOW_KEY_TYPE_VLAN BIT(20) 1101 #define NIX_FLOW_KEY_TYPE_IPV4_PROTO BIT(21) 1102 #define NIX_FLOW_KEY_TYPE_AH BIT(22) 1103 #define NIX_FLOW_KEY_TYPE_ESP BIT(23) 1104 u32 flowkey_cfg; /* Flowkey types selected */ 1105 u8 group; /* RSS context or group */ 1106 }; 1107 1108 struct nix_rss_flowkey_cfg_rsp { 1109 struct mbox_msghdr hdr; 1110 u8 alg_idx; /* Selected algo index */ 1111 }; 1112 1113 struct nix_set_mac_addr { 1114 struct mbox_msghdr hdr; 1115 u8 mac_addr[ETH_ALEN]; /* MAC address to be set for this pcifunc */ 1116 }; 1117 1118 struct nix_get_mac_addr_rsp { 1119 struct mbox_msghdr hdr; 1120 u8 mac_addr[ETH_ALEN]; 1121 }; 1122 1123 struct nix_mark_format_cfg { 1124 struct mbox_msghdr hdr; 1125 u8 offset; 1126 u8 y_mask; 1127 u8 y_val; 1128 u8 r_mask; 1129 u8 r_val; 1130 }; 1131 1132 struct nix_mark_format_cfg_rsp { 1133 struct mbox_msghdr hdr; 1134 u8 mark_format_idx; 1135 }; 1136 1137 struct nix_rx_mode { 1138 struct mbox_msghdr hdr; 1139 #define NIX_RX_MODE_UCAST BIT(0) 1140 #define NIX_RX_MODE_PROMISC BIT(1) 1141 #define NIX_RX_MODE_ALLMULTI BIT(2) 1142 #define NIX_RX_MODE_USE_MCE BIT(3) 1143 u16 mode; 1144 }; 1145 1146 struct nix_rx_cfg { 1147 struct mbox_msghdr hdr; 1148 #define NIX_RX_OL3_VERIFY BIT(0) 1149 #define NIX_RX_OL4_VERIFY BIT(1) 1150 u8 len_verify; /* Outer L3/L4 len check */ 1151 #define NIX_RX_CSUM_OL4_VERIFY BIT(0) 1152 u8 csum_verify; /* Outer L4 checksum verification */ 1153 }; 1154 1155 struct nix_frs_cfg { 1156 struct mbox_msghdr hdr; 1157 u8 update_smq; /* Update SMQ's min/max lens */ 1158 u8 update_minlen; /* Set minlen also */ 1159 u8 sdp_link; /* Set SDP RX link */ 1160 u16 maxlen; 1161 u16 minlen; 1162 }; 1163 1164 struct nix_lso_format_cfg { 1165 struct mbox_msghdr hdr; 1166 u64 field_mask; 1167 #define NIX_LSO_FIELD_MAX 8 1168 u64 fields[NIX_LSO_FIELD_MAX]; 1169 }; 1170 1171 struct nix_lso_format_cfg_rsp { 1172 struct mbox_msghdr hdr; 1173 u8 lso_format_idx; 1174 }; 1175 1176 struct nix_bp_cfg_req { 1177 struct mbox_msghdr hdr; 1178 u16 chan_base; /* Starting channel number */ 1179 u8 chan_cnt; /* Number of channels */ 1180 u8 bpid_per_chan; 1181 /* bpid_per_chan = 0 assigns single bp id for range of channels */ 1182 /* bpid_per_chan = 1 assigns separate bp id for each channel */ 1183 }; 1184 1185 /* PF can be mapped to either CGX or LBK interface, 1186 * so maximum 64 channels are possible. 1187 */ 1188 #define NIX_MAX_BPID_CHAN 64 1189 struct nix_bp_cfg_rsp { 1190 struct mbox_msghdr hdr; 1191 u16 chan_bpid[NIX_MAX_BPID_CHAN]; /* Channel and bpid mapping */ 1192 u8 chan_cnt; /* Number of channel for which bpids are assigned */ 1193 }; 1194 1195 /* Global NIX inline IPSec configuration */ 1196 struct nix_inline_ipsec_cfg { 1197 struct mbox_msghdr hdr; 1198 u32 cpt_credit; 1199 struct { 1200 u8 egrp; 1201 u16 opcode; 1202 u16 param1; 1203 u16 param2; 1204 } gen_cfg; 1205 struct { 1206 u16 cpt_pf_func; 1207 u8 cpt_slot; 1208 } inst_qsel; 1209 u8 enable; 1210 u16 bpid; 1211 u32 credit_th; 1212 }; 1213 1214 /* Per NIX LF inline IPSec configuration */ 1215 struct nix_inline_ipsec_lf_cfg { 1216 struct mbox_msghdr hdr; 1217 u64 sa_base_addr; 1218 struct { 1219 u32 tag_const; 1220 u16 lenm1_max; 1221 u8 sa_pow2_size; 1222 u8 tt; 1223 } ipsec_cfg0; 1224 struct { 1225 u32 sa_idx_max; 1226 u8 sa_idx_w; 1227 } ipsec_cfg1; 1228 u8 enable; 1229 }; 1230 1231 struct nix_hw_info { 1232 struct mbox_msghdr hdr; 1233 u16 rsvs16; 1234 u16 max_mtu; 1235 u16 min_mtu; 1236 u32 rpm_dwrr_mtu; 1237 u32 sdp_dwrr_mtu; 1238 u64 rsvd[16]; /* Add reserved fields for future expansion */ 1239 }; 1240 1241 struct nix_bandprof_alloc_req { 1242 struct mbox_msghdr hdr; 1243 /* Count of profiles needed per layer */ 1244 u16 prof_count[BAND_PROF_NUM_LAYERS]; 1245 }; 1246 1247 struct nix_bandprof_alloc_rsp { 1248 struct mbox_msghdr hdr; 1249 u16 prof_count[BAND_PROF_NUM_LAYERS]; 1250 1251 /* There is no need to allocate morethan 1 bandwidth profile 1252 * per RQ of a PF_FUNC's NIXLF. So limit the maximum 1253 * profiles to 64 per PF_FUNC. 1254 */ 1255 #define MAX_BANDPROF_PER_PFFUNC 64 1256 u16 prof_idx[BAND_PROF_NUM_LAYERS][MAX_BANDPROF_PER_PFFUNC]; 1257 }; 1258 1259 struct nix_bandprof_free_req { 1260 struct mbox_msghdr hdr; 1261 u8 free_all; 1262 u16 prof_count[BAND_PROF_NUM_LAYERS]; 1263 u16 prof_idx[BAND_PROF_NUM_LAYERS][MAX_BANDPROF_PER_PFFUNC]; 1264 }; 1265 1266 struct nix_bandprof_get_hwinfo_rsp { 1267 struct mbox_msghdr hdr; 1268 u16 prof_count[BAND_PROF_NUM_LAYERS]; 1269 u32 policer_timeunit; 1270 }; 1271 1272 /* NPC mbox message structs */ 1273 1274 #define NPC_MCAM_ENTRY_INVALID 0xFFFF 1275 #define NPC_MCAM_INVALID_MAP 0xFFFF 1276 1277 /* NPC mailbox error codes 1278 * Range 701 - 800. 1279 */ 1280 enum npc_af_status { 1281 NPC_MCAM_INVALID_REQ = -701, 1282 NPC_MCAM_ALLOC_DENIED = -702, 1283 NPC_MCAM_ALLOC_FAILED = -703, 1284 NPC_MCAM_PERM_DENIED = -704, 1285 NPC_FLOW_INTF_INVALID = -707, 1286 NPC_FLOW_CHAN_INVALID = -708, 1287 NPC_FLOW_NO_NIXLF = -709, 1288 NPC_FLOW_NOT_SUPPORTED = -710, 1289 NPC_FLOW_VF_PERM_DENIED = -711, 1290 NPC_FLOW_VF_NOT_INIT = -712, 1291 NPC_FLOW_VF_OVERLAP = -713, 1292 }; 1293 1294 struct npc_mcam_alloc_entry_req { 1295 struct mbox_msghdr hdr; 1296 #define NPC_MAX_NONCONTIG_ENTRIES 256 1297 u8 contig; /* Contiguous entries ? */ 1298 #define NPC_MCAM_ANY_PRIO 0 1299 #define NPC_MCAM_LOWER_PRIO 1 1300 #define NPC_MCAM_HIGHER_PRIO 2 1301 u8 priority; /* Lower or higher w.r.t ref_entry */ 1302 u16 ref_entry; 1303 u16 count; /* Number of entries requested */ 1304 }; 1305 1306 struct npc_mcam_alloc_entry_rsp { 1307 struct mbox_msghdr hdr; 1308 u16 entry; /* Entry allocated or start index if contiguous. 1309 * Invalid incase of non-contiguous. 1310 */ 1311 u16 count; /* Number of entries allocated */ 1312 u16 free_count; /* Number of entries available */ 1313 u16 entry_list[NPC_MAX_NONCONTIG_ENTRIES]; 1314 }; 1315 1316 struct npc_mcam_free_entry_req { 1317 struct mbox_msghdr hdr; 1318 u16 entry; /* Entry index to be freed */ 1319 u8 all; /* If all entries allocated to this PFVF to be freed */ 1320 }; 1321 1322 struct mcam_entry { 1323 #define NPC_MAX_KWS_IN_KEY 7 /* Number of keywords in max keywidth */ 1324 u64 kw[NPC_MAX_KWS_IN_KEY]; 1325 u64 kw_mask[NPC_MAX_KWS_IN_KEY]; 1326 u64 action; 1327 u64 vtag_action; 1328 }; 1329 1330 struct npc_mcam_write_entry_req { 1331 struct mbox_msghdr hdr; 1332 struct mcam_entry entry_data; 1333 u16 entry; /* MCAM entry to write this match key */ 1334 u16 cntr; /* Counter for this MCAM entry */ 1335 u8 intf; /* Rx or Tx interface */ 1336 u8 enable_entry;/* Enable this MCAM entry ? */ 1337 u8 set_cntr; /* Set counter for this entry ? */ 1338 }; 1339 1340 /* Enable/Disable a given entry */ 1341 struct npc_mcam_ena_dis_entry_req { 1342 struct mbox_msghdr hdr; 1343 u16 entry; 1344 }; 1345 1346 struct npc_mcam_shift_entry_req { 1347 struct mbox_msghdr hdr; 1348 #define NPC_MCAM_MAX_SHIFTS 64 1349 u16 curr_entry[NPC_MCAM_MAX_SHIFTS]; 1350 u16 new_entry[NPC_MCAM_MAX_SHIFTS]; 1351 u16 shift_count; /* Number of entries to shift */ 1352 }; 1353 1354 struct npc_mcam_shift_entry_rsp { 1355 struct mbox_msghdr hdr; 1356 u16 failed_entry_idx; /* Index in 'curr_entry', not entry itself */ 1357 }; 1358 1359 struct npc_mcam_alloc_counter_req { 1360 struct mbox_msghdr hdr; 1361 u8 contig; /* Contiguous counters ? */ 1362 #define NPC_MAX_NONCONTIG_COUNTERS 64 1363 u16 count; /* Number of counters requested */ 1364 }; 1365 1366 struct npc_mcam_alloc_counter_rsp { 1367 struct mbox_msghdr hdr; 1368 u16 cntr; /* Counter allocated or start index if contiguous. 1369 * Invalid incase of non-contiguous. 1370 */ 1371 u16 count; /* Number of counters allocated */ 1372 u16 cntr_list[NPC_MAX_NONCONTIG_COUNTERS]; 1373 }; 1374 1375 struct npc_mcam_oper_counter_req { 1376 struct mbox_msghdr hdr; 1377 u16 cntr; /* Free a counter or clear/fetch it's stats */ 1378 }; 1379 1380 struct npc_mcam_oper_counter_rsp { 1381 struct mbox_msghdr hdr; 1382 u64 stat; /* valid only while fetching counter's stats */ 1383 }; 1384 1385 struct npc_mcam_unmap_counter_req { 1386 struct mbox_msghdr hdr; 1387 u16 cntr; 1388 u16 entry; /* Entry and counter to be unmapped */ 1389 u8 all; /* Unmap all entries using this counter ? */ 1390 }; 1391 1392 struct npc_mcam_alloc_and_write_entry_req { 1393 struct mbox_msghdr hdr; 1394 struct mcam_entry entry_data; 1395 u16 ref_entry; 1396 u8 priority; /* Lower or higher w.r.t ref_entry */ 1397 u8 intf; /* Rx or Tx interface */ 1398 u8 enable_entry;/* Enable this MCAM entry ? */ 1399 u8 alloc_cntr; /* Allocate counter and map ? */ 1400 }; 1401 1402 struct npc_mcam_alloc_and_write_entry_rsp { 1403 struct mbox_msghdr hdr; 1404 u16 entry; 1405 u16 cntr; 1406 }; 1407 1408 struct npc_get_kex_cfg_rsp { 1409 struct mbox_msghdr hdr; 1410 u64 rx_keyx_cfg; /* NPC_AF_INTF(0)_KEX_CFG */ 1411 u64 tx_keyx_cfg; /* NPC_AF_INTF(1)_KEX_CFG */ 1412 #define NPC_MAX_INTF 2 1413 #define NPC_MAX_LID 8 1414 #define NPC_MAX_LT 16 1415 #define NPC_MAX_LD 2 1416 #define NPC_MAX_LFL 16 1417 /* NPC_AF_KEX_LDATA(0..1)_FLAGS_CFG */ 1418 u64 kex_ld_flags[NPC_MAX_LD]; 1419 /* NPC_AF_INTF(0..1)_LID(0..7)_LT(0..15)_LD(0..1)_CFG */ 1420 u64 intf_lid_lt_ld[NPC_MAX_INTF][NPC_MAX_LID][NPC_MAX_LT][NPC_MAX_LD]; 1421 /* NPC_AF_INTF(0..1)_LDATA(0..1)_FLAGS(0..15)_CFG */ 1422 u64 intf_ld_flags[NPC_MAX_INTF][NPC_MAX_LD][NPC_MAX_LFL]; 1423 #define MKEX_NAME_LEN 128 1424 u8 mkex_pfl_name[MKEX_NAME_LEN]; 1425 }; 1426 1427 struct flow_msg { 1428 unsigned char dmac[6]; 1429 unsigned char smac[6]; 1430 __be16 etype; 1431 __be16 vlan_etype; 1432 __be16 vlan_tci; 1433 union { 1434 __be32 ip4src; 1435 __be32 ip6src[4]; 1436 }; 1437 union { 1438 __be32 ip4dst; 1439 __be32 ip6dst[4]; 1440 }; 1441 u8 tos; 1442 u8 ip_ver; 1443 u8 ip_proto; 1444 u8 tc; 1445 __be16 sport; 1446 __be16 dport; 1447 union { 1448 u8 ip_flag; 1449 u8 next_header; 1450 }; 1451 }; 1452 1453 struct npc_install_flow_req { 1454 struct mbox_msghdr hdr; 1455 struct flow_msg packet; 1456 struct flow_msg mask; 1457 u64 features; 1458 u16 entry; 1459 u16 channel; 1460 u16 chan_mask; 1461 u8 intf; 1462 u8 set_cntr; /* If counter is available set counter for this entry ? */ 1463 u8 default_rule; 1464 u8 append; /* overwrite(0) or append(1) flow to default rule? */ 1465 u16 vf; 1466 /* action */ 1467 u32 index; 1468 u16 match_id; 1469 u8 flow_key_alg; 1470 u8 op; 1471 /* vtag rx action */ 1472 u8 vtag0_type; 1473 u8 vtag0_valid; 1474 u8 vtag1_type; 1475 u8 vtag1_valid; 1476 /* vtag tx action */ 1477 u16 vtag0_def; 1478 u8 vtag0_op; 1479 u16 vtag1_def; 1480 u8 vtag1_op; 1481 }; 1482 1483 struct npc_install_flow_rsp { 1484 struct mbox_msghdr hdr; 1485 int counter; /* negative if no counter else counter number */ 1486 }; 1487 1488 struct npc_delete_flow_req { 1489 struct mbox_msghdr hdr; 1490 u16 entry; 1491 u16 start;/*Disable range of entries */ 1492 u16 end; 1493 u8 all; /* PF + VFs */ 1494 }; 1495 1496 struct npc_mcam_read_entry_req { 1497 struct mbox_msghdr hdr; 1498 u16 entry; /* MCAM entry to read */ 1499 }; 1500 1501 struct npc_mcam_read_entry_rsp { 1502 struct mbox_msghdr hdr; 1503 struct mcam_entry entry_data; 1504 u8 intf; 1505 u8 enable; 1506 }; 1507 1508 struct npc_mcam_read_base_rule_rsp { 1509 struct mbox_msghdr hdr; 1510 struct mcam_entry entry; 1511 }; 1512 1513 struct npc_mcam_get_stats_req { 1514 struct mbox_msghdr hdr; 1515 u16 entry; /* mcam entry */ 1516 }; 1517 1518 struct npc_mcam_get_stats_rsp { 1519 struct mbox_msghdr hdr; 1520 u64 stat; /* counter stats */ 1521 u8 stat_ena; /* enabled */ 1522 }; 1523 1524 struct npc_get_secret_key_req { 1525 struct mbox_msghdr hdr; 1526 u8 intf; 1527 }; 1528 1529 struct npc_get_secret_key_rsp { 1530 struct mbox_msghdr hdr; 1531 u64 secret_key[3]; 1532 }; 1533 1534 enum ptp_op { 1535 PTP_OP_ADJFINE = 0, 1536 PTP_OP_GET_CLOCK = 1, 1537 PTP_OP_GET_TSTMP = 2, 1538 PTP_OP_SET_THRESH = 3, 1539 PTP_OP_EXTTS_ON = 4, 1540 }; 1541 1542 struct ptp_req { 1543 struct mbox_msghdr hdr; 1544 u8 op; 1545 s64 scaled_ppm; 1546 u64 thresh; 1547 int extts_on; 1548 }; 1549 1550 struct ptp_rsp { 1551 struct mbox_msghdr hdr; 1552 u64 clk; 1553 }; 1554 1555 struct npc_get_field_status_req { 1556 struct mbox_msghdr hdr; 1557 u8 intf; 1558 u8 field; 1559 }; 1560 1561 struct npc_get_field_status_rsp { 1562 struct mbox_msghdr hdr; 1563 u8 enable; 1564 }; 1565 1566 struct set_vf_perm { 1567 struct mbox_msghdr hdr; 1568 u16 vf; 1569 #define RESET_VF_PERM BIT_ULL(0) 1570 #define VF_TRUSTED BIT_ULL(1) 1571 u64 flags; 1572 }; 1573 1574 struct lmtst_tbl_setup_req { 1575 struct mbox_msghdr hdr; 1576 u64 dis_sched_early_comp :1; 1577 u64 sch_ena :1; 1578 u64 dis_line_pref :1; 1579 u64 ssow_pf_func :13; 1580 u16 base_pcifunc; 1581 u8 use_local_lmt_region; 1582 u64 lmt_iova; 1583 u64 rsvd[4]; 1584 }; 1585 1586 /* CPT mailbox error codes 1587 * Range 901 - 1000. 1588 */ 1589 enum cpt_af_status { 1590 CPT_AF_ERR_PARAM = -901, 1591 CPT_AF_ERR_GRP_INVALID = -902, 1592 CPT_AF_ERR_LF_INVALID = -903, 1593 CPT_AF_ERR_ACCESS_DENIED = -904, 1594 CPT_AF_ERR_SSO_PF_FUNC_INVALID = -905, 1595 CPT_AF_ERR_NIX_PF_FUNC_INVALID = -906, 1596 CPT_AF_ERR_INLINE_IPSEC_INB_ENA = -907, 1597 CPT_AF_ERR_INLINE_IPSEC_OUT_ENA = -908 1598 }; 1599 1600 /* CPT mbox message formats */ 1601 struct cpt_rd_wr_reg_msg { 1602 struct mbox_msghdr hdr; 1603 u64 reg_offset; 1604 u64 *ret_val; 1605 u64 val; 1606 u8 is_write; 1607 int blkaddr; 1608 }; 1609 1610 struct cpt_lf_alloc_req_msg { 1611 struct mbox_msghdr hdr; 1612 u16 nix_pf_func; 1613 u16 sso_pf_func; 1614 u16 eng_grpmsk; 1615 int blkaddr; 1616 }; 1617 1618 #define CPT_INLINE_INBOUND 0 1619 #define CPT_INLINE_OUTBOUND 1 1620 1621 /* Mailbox message request format for CPT IPsec 1622 * inline inbound and outbound configuration. 1623 */ 1624 struct cpt_inline_ipsec_cfg_msg { 1625 struct mbox_msghdr hdr; 1626 u8 enable; 1627 u8 slot; 1628 u8 dir; 1629 u8 sso_pf_func_ovrd; 1630 u16 sso_pf_func; /* inbound path SSO_PF_FUNC */ 1631 u16 nix_pf_func; /* outbound path NIX_PF_FUNC */ 1632 }; 1633 1634 /* Mailbox message request and response format for CPT stats. */ 1635 struct cpt_sts_req { 1636 struct mbox_msghdr hdr; 1637 u8 blkaddr; 1638 }; 1639 1640 struct cpt_sts_rsp { 1641 struct mbox_msghdr hdr; 1642 u64 inst_req_pc; 1643 u64 inst_lat_pc; 1644 u64 rd_req_pc; 1645 u64 rd_lat_pc; 1646 u64 rd_uc_pc; 1647 u64 active_cycles_pc; 1648 u64 ctx_mis_pc; 1649 u64 ctx_hit_pc; 1650 u64 ctx_aop_pc; 1651 u64 ctx_aop_lat_pc; 1652 u64 ctx_ifetch_pc; 1653 u64 ctx_ifetch_lat_pc; 1654 u64 ctx_ffetch_pc; 1655 u64 ctx_ffetch_lat_pc; 1656 u64 ctx_wback_pc; 1657 u64 ctx_wback_lat_pc; 1658 u64 ctx_psh_pc; 1659 u64 ctx_psh_lat_pc; 1660 u64 ctx_err; 1661 u64 ctx_enc_id; 1662 u64 ctx_flush_timer; 1663 u64 rxc_time; 1664 u64 rxc_time_cfg; 1665 u64 rxc_active_sts; 1666 u64 rxc_zombie_sts; 1667 u64 busy_sts_ae; 1668 u64 free_sts_ae; 1669 u64 busy_sts_se; 1670 u64 free_sts_se; 1671 u64 busy_sts_ie; 1672 u64 free_sts_ie; 1673 u64 exe_err_info; 1674 u64 cptclk_cnt; 1675 u64 diag; 1676 u64 rxc_dfrg; 1677 u64 x2p_link_cfg0; 1678 u64 x2p_link_cfg1; 1679 }; 1680 1681 /* Mailbox message request format to configure reassembly timeout. */ 1682 struct cpt_rxc_time_cfg_req { 1683 struct mbox_msghdr hdr; 1684 int blkaddr; 1685 u32 step; 1686 u16 zombie_thres; 1687 u16 zombie_limit; 1688 u16 active_thres; 1689 u16 active_limit; 1690 }; 1691 1692 /* Mailbox message request format to request for CPT_INST_S lmtst. */ 1693 struct cpt_inst_lmtst_req { 1694 struct mbox_msghdr hdr; 1695 u64 inst[8]; 1696 u64 rsvd; 1697 }; 1698 1699 struct sdp_node_info { 1700 /* Node to which this PF belons to */ 1701 u8 node_id; 1702 u8 max_vfs; 1703 u8 num_pf_rings; 1704 u8 pf_srn; 1705 #define SDP_MAX_VFS 128 1706 u8 vf_rings[SDP_MAX_VFS]; 1707 }; 1708 1709 struct sdp_chan_info_msg { 1710 struct mbox_msghdr hdr; 1711 struct sdp_node_info info; 1712 }; 1713 1714 struct sdp_get_chan_info_msg { 1715 struct mbox_msghdr hdr; 1716 u16 chan_base; 1717 u16 num_chan; 1718 }; 1719 1720 /* CGX mailbox error codes 1721 * Range 1101 - 1200. 1722 */ 1723 enum cgx_af_status { 1724 LMAC_AF_ERR_INVALID_PARAM = -1101, 1725 LMAC_AF_ERR_PF_NOT_MAPPED = -1102, 1726 LMAC_AF_ERR_PERM_DENIED = -1103, 1727 LMAC_AF_ERR_PFC_ENADIS_PERM_DENIED = -1104, 1728 LMAC_AF_ERR_8023PAUSE_ENADIS_PERM_DENIED = -1105, 1729 LMAC_AF_ERR_CMD_TIMEOUT = -1106, 1730 LMAC_AF_ERR_FIRMWARE_DATA_NOT_MAPPED = -1107, 1731 LMAC_AF_ERR_EXACT_MATCH_TBL_ADD_FAILED = -1108, 1732 LMAC_AF_ERR_EXACT_MATCH_TBL_DEL_FAILED = -1109, 1733 LMAC_AF_ERR_EXACT_MATCH_TBL_LOOK_UP_FAILED = -1110, 1734 }; 1735 1736 enum mcs_direction { 1737 MCS_RX, 1738 MCS_TX, 1739 }; 1740 1741 enum mcs_rsrc_type { 1742 MCS_RSRC_TYPE_FLOWID, 1743 MCS_RSRC_TYPE_SECY, 1744 MCS_RSRC_TYPE_SC, 1745 MCS_RSRC_TYPE_SA, 1746 }; 1747 1748 struct mcs_alloc_rsrc_req { 1749 struct mbox_msghdr hdr; 1750 u8 rsrc_type; 1751 u8 rsrc_cnt; /* Resources count */ 1752 u8 mcs_id; /* MCS block ID */ 1753 u8 dir; /* Macsec ingress or egress side */ 1754 u8 all; /* Allocate all resource type one each */ 1755 u64 rsvd; 1756 }; 1757 1758 struct mcs_alloc_rsrc_rsp { 1759 struct mbox_msghdr hdr; 1760 u8 flow_ids[128]; /* Index of reserved entries */ 1761 u8 secy_ids[128]; 1762 u8 sc_ids[128]; 1763 u8 sa_ids[256]; 1764 u8 rsrc_type; 1765 u8 rsrc_cnt; /* No of entries reserved */ 1766 u8 mcs_id; 1767 u8 dir; 1768 u8 all; 1769 u8 rsvd[256]; /* reserved fields for future expansion */ 1770 }; 1771 1772 struct mcs_free_rsrc_req { 1773 struct mbox_msghdr hdr; 1774 u8 rsrc_id; /* Index of the entry to be freed */ 1775 u8 rsrc_type; 1776 u8 mcs_id; 1777 u8 dir; 1778 u8 all; /* Free all the cam resources */ 1779 u64 rsvd; 1780 }; 1781 1782 struct mcs_flowid_entry_write_req { 1783 struct mbox_msghdr hdr; 1784 u64 data[4]; 1785 u64 mask[4]; 1786 u64 sci; /* CNF10K-B for tx_secy_mem_map */ 1787 u8 flow_id; 1788 u8 secy_id; /* secyid for which flowid is mapped */ 1789 u8 sc_id; /* Valid if dir = MCS_TX, SC_CAM id mapped to flowid */ 1790 u8 ena; /* Enable tcam entry */ 1791 u8 ctrl_pkt; 1792 u8 mcs_id; 1793 u8 dir; 1794 u64 rsvd; 1795 }; 1796 1797 struct mcs_secy_plcy_write_req { 1798 struct mbox_msghdr hdr; 1799 u64 plcy; 1800 u8 secy_id; 1801 u8 mcs_id; 1802 u8 dir; 1803 u64 rsvd; 1804 }; 1805 1806 /* RX SC_CAM mapping */ 1807 struct mcs_rx_sc_cam_write_req { 1808 struct mbox_msghdr hdr; 1809 u64 sci; /* SCI */ 1810 u64 secy_id; /* secy index mapped to SC */ 1811 u8 sc_id; /* SC CAM entry index */ 1812 u8 mcs_id; 1813 u64 rsvd; 1814 }; 1815 1816 struct mcs_sa_plcy_write_req { 1817 struct mbox_msghdr hdr; 1818 u64 plcy[2][9]; /* Support 2 SA policy */ 1819 u8 sa_index[2]; 1820 u8 sa_cnt; 1821 u8 mcs_id; 1822 u8 dir; 1823 u64 rsvd; 1824 }; 1825 1826 struct mcs_tx_sc_sa_map { 1827 struct mbox_msghdr hdr; 1828 u8 sa_index0; 1829 u8 sa_index1; 1830 u8 rekey_ena; 1831 u8 sa_index0_vld; 1832 u8 sa_index1_vld; 1833 u8 tx_sa_active; 1834 u64 sectag_sci; 1835 u8 sc_id; /* used as index for SA_MEM_MAP */ 1836 u8 mcs_id; 1837 u64 rsvd; 1838 }; 1839 1840 struct mcs_rx_sc_sa_map { 1841 struct mbox_msghdr hdr; 1842 u8 sa_index; 1843 u8 sa_in_use; 1844 u8 sc_id; 1845 u8 an; /* value range 0-3, sc_id + an used as index SA_MEM_MAP */ 1846 u8 mcs_id; 1847 u64 rsvd; 1848 }; 1849 1850 struct mcs_flowid_ena_dis_entry { 1851 struct mbox_msghdr hdr; 1852 u8 flow_id; 1853 u8 ena; 1854 u8 mcs_id; 1855 u8 dir; 1856 u64 rsvd; 1857 }; 1858 1859 struct mcs_pn_table_write_req { 1860 struct mbox_msghdr hdr; 1861 u64 next_pn; 1862 u8 pn_id; 1863 u8 mcs_id; 1864 u8 dir; 1865 u64 rsvd; 1866 }; 1867 1868 struct mcs_hw_info { 1869 struct mbox_msghdr hdr; 1870 u8 num_mcs_blks; /* Number of MCS blocks */ 1871 u8 tcam_entries; /* RX/TX Tcam entries per mcs block */ 1872 u8 secy_entries; /* RX/TX SECY entries per mcs block */ 1873 u8 sc_entries; /* RX/TX SC CAM entries per mcs block */ 1874 u8 sa_entries; /* PN table entries = SA entries */ 1875 u64 rsvd[16]; 1876 }; 1877 1878 struct mcs_set_active_lmac { 1879 struct mbox_msghdr hdr; 1880 u32 lmac_bmap; /* bitmap of active lmac per mcs block */ 1881 u8 mcs_id; 1882 u16 chan_base; /* MCS channel base */ 1883 u64 rsvd; 1884 }; 1885 1886 struct mcs_set_lmac_mode { 1887 struct mbox_msghdr hdr; 1888 u8 mode; /* 1:Bypass 0:Operational */ 1889 u8 lmac_id; 1890 u8 mcs_id; 1891 u64 rsvd; 1892 }; 1893 1894 struct mcs_port_reset_req { 1895 struct mbox_msghdr hdr; 1896 u8 reset; 1897 u8 mcs_id; 1898 u8 port_id; 1899 u64 rsvd; 1900 }; 1901 1902 struct mcs_port_cfg_set_req { 1903 struct mbox_msghdr hdr; 1904 u8 cstm_tag_rel_mode_sel; 1905 u8 custom_hdr_enb; 1906 u8 fifo_skid; 1907 u8 port_mode; 1908 u8 port_id; 1909 u8 mcs_id; 1910 u64 rsvd; 1911 }; 1912 1913 struct mcs_port_cfg_get_req { 1914 struct mbox_msghdr hdr; 1915 u8 port_id; 1916 u8 mcs_id; 1917 u64 rsvd; 1918 }; 1919 1920 struct mcs_port_cfg_get_rsp { 1921 struct mbox_msghdr hdr; 1922 u8 cstm_tag_rel_mode_sel; 1923 u8 custom_hdr_enb; 1924 u8 fifo_skid; 1925 u8 port_mode; 1926 u8 port_id; 1927 u8 mcs_id; 1928 u64 rsvd; 1929 }; 1930 1931 struct mcs_custom_tag_cfg_get_req { 1932 struct mbox_msghdr hdr; 1933 u8 mcs_id; 1934 u8 dir; 1935 u64 rsvd; 1936 }; 1937 1938 struct mcs_custom_tag_cfg_get_rsp { 1939 struct mbox_msghdr hdr; 1940 u16 cstm_etype[8]; 1941 u8 cstm_indx[8]; 1942 u8 cstm_etype_en; 1943 u8 mcs_id; 1944 u8 dir; 1945 u64 rsvd; 1946 }; 1947 1948 /* MCS mailbox error codes 1949 * Range 1201 - 1300. 1950 */ 1951 enum mcs_af_status { 1952 MCS_AF_ERR_INVALID_MCSID = -1201, 1953 MCS_AF_ERR_NOT_MAPPED = -1202, 1954 }; 1955 1956 struct mcs_set_pn_threshold { 1957 struct mbox_msghdr hdr; 1958 u64 threshold; 1959 u8 xpn; /* '1' for setting xpn threshold */ 1960 u8 mcs_id; 1961 u8 dir; 1962 u64 rsvd; 1963 }; 1964 1965 enum mcs_ctrl_pkt_rulew_type { 1966 MCS_CTRL_PKT_RULE_TYPE_ETH, 1967 MCS_CTRL_PKT_RULE_TYPE_DA, 1968 MCS_CTRL_PKT_RULE_TYPE_RANGE, 1969 MCS_CTRL_PKT_RULE_TYPE_COMBO, 1970 MCS_CTRL_PKT_RULE_TYPE_MAC, 1971 }; 1972 1973 struct mcs_alloc_ctrl_pkt_rule_req { 1974 struct mbox_msghdr hdr; 1975 u8 rule_type; 1976 u8 mcs_id; /* MCS block ID */ 1977 u8 dir; /* Macsec ingress or egress side */ 1978 u64 rsvd; 1979 }; 1980 1981 struct mcs_alloc_ctrl_pkt_rule_rsp { 1982 struct mbox_msghdr hdr; 1983 u8 rule_idx; 1984 u8 rule_type; 1985 u8 mcs_id; 1986 u8 dir; 1987 u64 rsvd; 1988 }; 1989 1990 struct mcs_free_ctrl_pkt_rule_req { 1991 struct mbox_msghdr hdr; 1992 u8 rule_idx; 1993 u8 rule_type; 1994 u8 mcs_id; 1995 u8 dir; 1996 u8 all; 1997 u64 rsvd; 1998 }; 1999 2000 struct mcs_ctrl_pkt_rule_write_req { 2001 struct mbox_msghdr hdr; 2002 u64 data0; 2003 u64 data1; 2004 u64 data2; 2005 u8 rule_idx; 2006 u8 rule_type; 2007 u8 mcs_id; 2008 u8 dir; 2009 u64 rsvd; 2010 }; 2011 2012 struct mcs_stats_req { 2013 struct mbox_msghdr hdr; 2014 u8 id; 2015 u8 mcs_id; 2016 u8 dir; 2017 u64 rsvd; 2018 }; 2019 2020 struct mcs_flowid_stats { 2021 struct mbox_msghdr hdr; 2022 u64 tcam_hit_cnt; 2023 u64 rsvd; 2024 }; 2025 2026 struct mcs_secy_stats { 2027 struct mbox_msghdr hdr; 2028 u64 ctl_pkt_bcast_cnt; 2029 u64 ctl_pkt_mcast_cnt; 2030 u64 ctl_pkt_ucast_cnt; 2031 u64 ctl_octet_cnt; 2032 u64 unctl_pkt_bcast_cnt; 2033 u64 unctl_pkt_mcast_cnt; 2034 u64 unctl_pkt_ucast_cnt; 2035 u64 unctl_octet_cnt; 2036 /* Valid only for RX */ 2037 u64 octet_decrypted_cnt; 2038 u64 octet_validated_cnt; 2039 u64 pkt_port_disabled_cnt; 2040 u64 pkt_badtag_cnt; 2041 u64 pkt_nosa_cnt; 2042 u64 pkt_nosaerror_cnt; 2043 u64 pkt_tagged_ctl_cnt; 2044 u64 pkt_untaged_cnt; 2045 u64 pkt_ctl_cnt; /* CN10K-B */ 2046 u64 pkt_notag_cnt; /* CNF10K-B */ 2047 /* Valid only for TX */ 2048 u64 octet_encrypted_cnt; 2049 u64 octet_protected_cnt; 2050 u64 pkt_noactivesa_cnt; 2051 u64 pkt_toolong_cnt; 2052 u64 pkt_untagged_cnt; 2053 u64 rsvd[4]; 2054 }; 2055 2056 struct mcs_port_stats { 2057 struct mbox_msghdr hdr; 2058 u64 tcam_miss_cnt; 2059 u64 parser_err_cnt; 2060 u64 preempt_err_cnt; /* CNF10K-B */ 2061 u64 sectag_insert_err_cnt; 2062 u64 rsvd[4]; 2063 }; 2064 2065 /* Only for CN10K-B */ 2066 struct mcs_sa_stats { 2067 struct mbox_msghdr hdr; 2068 /* RX */ 2069 u64 pkt_invalid_cnt; 2070 u64 pkt_nosaerror_cnt; 2071 u64 pkt_notvalid_cnt; 2072 u64 pkt_ok_cnt; 2073 u64 pkt_nosa_cnt; 2074 /* TX */ 2075 u64 pkt_encrypt_cnt; 2076 u64 pkt_protected_cnt; 2077 u64 rsvd[4]; 2078 }; 2079 2080 struct mcs_sc_stats { 2081 struct mbox_msghdr hdr; 2082 /* RX */ 2083 u64 hit_cnt; 2084 u64 pkt_invalid_cnt; 2085 u64 pkt_late_cnt; 2086 u64 pkt_notvalid_cnt; 2087 u64 pkt_unchecked_cnt; 2088 u64 pkt_delay_cnt; /* CNF10K-B */ 2089 u64 pkt_ok_cnt; /* CNF10K-B */ 2090 u64 octet_decrypt_cnt; /* CN10K-B */ 2091 u64 octet_validate_cnt; /* CN10K-B */ 2092 /* TX */ 2093 u64 pkt_encrypt_cnt; 2094 u64 pkt_protected_cnt; 2095 u64 octet_encrypt_cnt; /* CN10K-B */ 2096 u64 octet_protected_cnt; /* CN10K-B */ 2097 u64 rsvd[4]; 2098 }; 2099 2100 struct mcs_clear_stats { 2101 struct mbox_msghdr hdr; 2102 #define MCS_FLOWID_STATS 0 2103 #define MCS_SECY_STATS 1 2104 #define MCS_SC_STATS 2 2105 #define MCS_SA_STATS 3 2106 #define MCS_PORT_STATS 4 2107 u8 type; /* FLOWID, SECY, SC, SA, PORT */ 2108 u8 id; /* type = PORT, If id = FF(invalid) port no is derived from pcifunc */ 2109 u8 mcs_id; 2110 u8 dir; 2111 u8 all; /* All resources stats mapped to PF are cleared */ 2112 }; 2113 2114 struct mcs_intr_cfg { 2115 struct mbox_msghdr hdr; 2116 #define MCS_CPM_RX_SECTAG_V_EQ1_INT BIT_ULL(0) 2117 #define MCS_CPM_RX_SECTAG_E_EQ0_C_EQ1_INT BIT_ULL(1) 2118 #define MCS_CPM_RX_SECTAG_SL_GTE48_INT BIT_ULL(2) 2119 #define MCS_CPM_RX_SECTAG_ES_EQ1_SC_EQ1_INT BIT_ULL(3) 2120 #define MCS_CPM_RX_SECTAG_SC_EQ1_SCB_EQ1_INT BIT_ULL(4) 2121 #define MCS_CPM_RX_PACKET_XPN_EQ0_INT BIT_ULL(5) 2122 #define MCS_CPM_RX_PN_THRESH_REACHED_INT BIT_ULL(6) 2123 #define MCS_CPM_TX_PACKET_XPN_EQ0_INT BIT_ULL(7) 2124 #define MCS_CPM_TX_PN_THRESH_REACHED_INT BIT_ULL(8) 2125 #define MCS_CPM_TX_SA_NOT_VALID_INT BIT_ULL(9) 2126 #define MCS_BBE_RX_DFIFO_OVERFLOW_INT BIT_ULL(10) 2127 #define MCS_BBE_RX_PLFIFO_OVERFLOW_INT BIT_ULL(11) 2128 #define MCS_BBE_TX_DFIFO_OVERFLOW_INT BIT_ULL(12) 2129 #define MCS_BBE_TX_PLFIFO_OVERFLOW_INT BIT_ULL(13) 2130 #define MCS_PAB_RX_CHAN_OVERFLOW_INT BIT_ULL(14) 2131 #define MCS_PAB_TX_CHAN_OVERFLOW_INT BIT_ULL(15) 2132 u64 intr_mask; /* Interrupt enable mask */ 2133 u8 mcs_id; 2134 u8 lmac_id; 2135 u64 rsvd; 2136 }; 2137 2138 struct mcs_intr_info { 2139 struct mbox_msghdr hdr; 2140 u64 intr_mask; 2141 int sa_id; 2142 u8 mcs_id; 2143 u8 lmac_id; 2144 u64 rsvd; 2145 }; 2146 2147 #endif /* MBOX_H */ 2148