1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Marvell OcteonTx2 RVU Admin Function driver 3 * 4 * Copyright (C) 2018 Marvell International Ltd. 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 */ 10 11 #ifndef MBOX_H 12 #define MBOX_H 13 14 #include <linux/etherdevice.h> 15 #include <linux/sizes.h> 16 17 #include "rvu_struct.h" 18 #include "common.h" 19 20 #define MBOX_SIZE SZ_64K 21 22 /* AF/PF: PF initiated, PF/VF VF initiated */ 23 #define MBOX_DOWN_RX_START 0 24 #define MBOX_DOWN_RX_SIZE (46 * SZ_1K) 25 #define MBOX_DOWN_TX_START (MBOX_DOWN_RX_START + MBOX_DOWN_RX_SIZE) 26 #define MBOX_DOWN_TX_SIZE (16 * SZ_1K) 27 /* AF/PF: AF initiated, PF/VF PF initiated */ 28 #define MBOX_UP_RX_START (MBOX_DOWN_TX_START + MBOX_DOWN_TX_SIZE) 29 #define MBOX_UP_RX_SIZE SZ_1K 30 #define MBOX_UP_TX_START (MBOX_UP_RX_START + MBOX_UP_RX_SIZE) 31 #define MBOX_UP_TX_SIZE SZ_1K 32 33 #if MBOX_UP_TX_SIZE + MBOX_UP_TX_START != MBOX_SIZE 34 # error "incorrect mailbox area sizes" 35 #endif 36 37 #define INTR_MASK(pfvfs) ((pfvfs < 64) ? (BIT_ULL(pfvfs) - 1) : (~0ull)) 38 39 #define MBOX_RSP_TIMEOUT 3000 /* Time(ms) to wait for mbox response */ 40 41 #define MBOX_MSG_ALIGN 16 /* Align mbox msg start to 16bytes */ 42 43 /* Mailbox directions */ 44 #define MBOX_DIR_AFPF 0 /* AF replies to PF */ 45 #define MBOX_DIR_PFAF 1 /* PF sends messages to AF */ 46 #define MBOX_DIR_PFVF 2 /* PF replies to VF */ 47 #define MBOX_DIR_VFPF 3 /* VF sends messages to PF */ 48 #define MBOX_DIR_AFPF_UP 4 /* AF sends messages to PF */ 49 #define MBOX_DIR_PFAF_UP 5 /* PF replies to AF */ 50 #define MBOX_DIR_PFVF_UP 6 /* PF sends messages to VF */ 51 #define MBOX_DIR_VFPF_UP 7 /* VF replies to PF */ 52 53 struct otx2_mbox_dev { 54 void *mbase; /* This dev's mbox region */ 55 void *hwbase; 56 spinlock_t mbox_lock; 57 u16 msg_size; /* Total msg size to be sent */ 58 u16 rsp_size; /* Total rsp size to be sure the reply is ok */ 59 u16 num_msgs; /* No of msgs sent or waiting for response */ 60 u16 msgs_acked; /* No of msgs for which response is received */ 61 }; 62 63 struct otx2_mbox { 64 struct pci_dev *pdev; 65 void *hwbase; /* Mbox region advertised by HW */ 66 void *reg_base;/* CSR base for this dev */ 67 u64 trigger; /* Trigger mbox notification */ 68 u16 tr_shift; /* Mbox trigger shift */ 69 u64 rx_start; /* Offset of Rx region in mbox memory */ 70 u64 tx_start; /* Offset of Tx region in mbox memory */ 71 u16 rx_size; /* Size of Rx region */ 72 u16 tx_size; /* Size of Tx region */ 73 u16 ndevs; /* The number of peers */ 74 struct otx2_mbox_dev *dev; 75 }; 76 77 /* Header which preceeds all mbox messages */ 78 struct mbox_hdr { 79 u64 msg_size; /* Total msgs size embedded */ 80 u16 num_msgs; /* No of msgs embedded */ 81 }; 82 83 /* Header which preceeds every msg and is also part of it */ 84 struct mbox_msghdr { 85 u16 pcifunc; /* Who's sending this msg */ 86 u16 id; /* Mbox message ID */ 87 #define OTX2_MBOX_REQ_SIG (0xdead) 88 #define OTX2_MBOX_RSP_SIG (0xbeef) 89 u16 sig; /* Signature, for validating corrupted msgs */ 90 #define OTX2_MBOX_VERSION (0x0007) 91 u16 ver; /* Version of msg's structure for this ID */ 92 u16 next_msgoff; /* Offset of next msg within mailbox region */ 93 int rc; /* Msg process'ed response code */ 94 }; 95 96 void otx2_mbox_reset(struct otx2_mbox *mbox, int devid); 97 void __otx2_mbox_reset(struct otx2_mbox *mbox, int devid); 98 void otx2_mbox_destroy(struct otx2_mbox *mbox); 99 int otx2_mbox_init(struct otx2_mbox *mbox, void __force *hwbase, 100 struct pci_dev *pdev, void __force *reg_base, 101 int direction, int ndevs); 102 int otx2_mbox_regions_init(struct otx2_mbox *mbox, void __force **hwbase, 103 struct pci_dev *pdev, void __force *reg_base, 104 int direction, int ndevs); 105 void otx2_mbox_msg_send(struct otx2_mbox *mbox, int devid); 106 int otx2_mbox_wait_for_rsp(struct otx2_mbox *mbox, int devid); 107 int otx2_mbox_busy_poll_for_rsp(struct otx2_mbox *mbox, int devid); 108 struct mbox_msghdr *otx2_mbox_alloc_msg_rsp(struct otx2_mbox *mbox, int devid, 109 int size, int size_rsp); 110 struct mbox_msghdr *otx2_mbox_get_rsp(struct otx2_mbox *mbox, int devid, 111 struct mbox_msghdr *msg); 112 int otx2_mbox_check_rsp_msgs(struct otx2_mbox *mbox, int devid); 113 int otx2_reply_invalid_msg(struct otx2_mbox *mbox, int devid, 114 u16 pcifunc, u16 id); 115 bool otx2_mbox_nonempty(struct otx2_mbox *mbox, int devid); 116 const char *otx2_mbox_id2name(u16 id); 117 static inline struct mbox_msghdr *otx2_mbox_alloc_msg(struct otx2_mbox *mbox, 118 int devid, int size) 119 { 120 return otx2_mbox_alloc_msg_rsp(mbox, devid, size, 0); 121 } 122 123 /* Mailbox message types */ 124 #define MBOX_MSG_MASK 0xFFFF 125 #define MBOX_MSG_INVALID 0xFFFE 126 #define MBOX_MSG_MAX 0xFFFF 127 128 #define MBOX_MESSAGES \ 129 /* Generic mbox IDs (range 0x000 - 0x1FF) */ \ 130 M(READY, 0x001, ready, msg_req, ready_msg_rsp) \ 131 M(ATTACH_RESOURCES, 0x002, attach_resources, rsrc_attach, msg_rsp) \ 132 M(DETACH_RESOURCES, 0x003, detach_resources, rsrc_detach, msg_rsp) \ 133 M(MSIX_OFFSET, 0x005, msix_offset, msg_req, msix_offset_rsp) \ 134 M(VF_FLR, 0x006, vf_flr, msg_req, msg_rsp) \ 135 M(PTP_OP, 0x007, ptp_op, ptp_req, ptp_rsp) \ 136 M(GET_HW_CAP, 0x008, get_hw_cap, msg_req, get_hw_cap_rsp) \ 137 /* CGX mbox IDs (range 0x200 - 0x3FF) */ \ 138 M(CGX_START_RXTX, 0x200, cgx_start_rxtx, msg_req, msg_rsp) \ 139 M(CGX_STOP_RXTX, 0x201, cgx_stop_rxtx, msg_req, msg_rsp) \ 140 M(CGX_STATS, 0x202, cgx_stats, msg_req, cgx_stats_rsp) \ 141 M(CGX_MAC_ADDR_SET, 0x203, cgx_mac_addr_set, cgx_mac_addr_set_or_get, \ 142 cgx_mac_addr_set_or_get) \ 143 M(CGX_MAC_ADDR_GET, 0x204, cgx_mac_addr_get, cgx_mac_addr_set_or_get, \ 144 cgx_mac_addr_set_or_get) \ 145 M(CGX_PROMISC_ENABLE, 0x205, cgx_promisc_enable, msg_req, msg_rsp) \ 146 M(CGX_PROMISC_DISABLE, 0x206, cgx_promisc_disable, msg_req, msg_rsp) \ 147 M(CGX_START_LINKEVENTS, 0x207, cgx_start_linkevents, msg_req, msg_rsp) \ 148 M(CGX_STOP_LINKEVENTS, 0x208, cgx_stop_linkevents, msg_req, msg_rsp) \ 149 M(CGX_GET_LINKINFO, 0x209, cgx_get_linkinfo, msg_req, cgx_link_info_msg) \ 150 M(CGX_INTLBK_ENABLE, 0x20A, cgx_intlbk_enable, msg_req, msg_rsp) \ 151 M(CGX_INTLBK_DISABLE, 0x20B, cgx_intlbk_disable, msg_req, msg_rsp) \ 152 M(CGX_PTP_RX_ENABLE, 0x20C, cgx_ptp_rx_enable, msg_req, msg_rsp) \ 153 M(CGX_PTP_RX_DISABLE, 0x20D, cgx_ptp_rx_disable, msg_req, msg_rsp) \ 154 M(CGX_CFG_PAUSE_FRM, 0x20E, cgx_cfg_pause_frm, cgx_pause_frm_cfg, \ 155 cgx_pause_frm_cfg) \ 156 M(CGX_FEC_SET, 0x210, cgx_set_fec_param, fec_mode, fec_mode) \ 157 M(CGX_FEC_STATS, 0x211, cgx_fec_stats, msg_req, cgx_fec_stats_rsp) \ 158 M(CGX_GET_PHY_FEC_STATS, 0x212, cgx_get_phy_fec_stats, msg_req, msg_rsp) \ 159 M(CGX_FW_DATA_GET, 0x213, cgx_get_aux_link_info, msg_req, cgx_fw_data) \ 160 M(CGX_SET_LINK_MODE, 0x214, cgx_set_link_mode, cgx_set_link_mode_req,\ 161 cgx_set_link_mode_rsp) \ 162 M(CGX_FEATURES_GET, 0x215, cgx_features_get, msg_req, \ 163 cgx_features_info_msg) \ 164 M(RPM_STATS, 0x216, rpm_stats, msg_req, rpm_stats_rsp) \ 165 /* NPA mbox IDs (range 0x400 - 0x5FF) */ \ 166 /* NPA mbox IDs (range 0x400 - 0x5FF) */ \ 167 M(NPA_LF_ALLOC, 0x400, npa_lf_alloc, \ 168 npa_lf_alloc_req, npa_lf_alloc_rsp) \ 169 M(NPA_LF_FREE, 0x401, npa_lf_free, msg_req, msg_rsp) \ 170 M(NPA_AQ_ENQ, 0x402, npa_aq_enq, npa_aq_enq_req, npa_aq_enq_rsp) \ 171 M(NPA_HWCTX_DISABLE, 0x403, npa_hwctx_disable, hwctx_disable_req, msg_rsp)\ 172 /* SSO/SSOW mbox IDs (range 0x600 - 0x7FF) */ \ 173 /* TIM mbox IDs (range 0x800 - 0x9FF) */ \ 174 /* CPT mbox IDs (range 0xA00 - 0xBFF) */ \ 175 M(CPT_LF_ALLOC, 0xA00, cpt_lf_alloc, cpt_lf_alloc_req_msg, \ 176 msg_rsp) \ 177 M(CPT_LF_FREE, 0xA01, cpt_lf_free, msg_req, msg_rsp) \ 178 M(CPT_RD_WR_REGISTER, 0xA02, cpt_rd_wr_register, cpt_rd_wr_reg_msg, \ 179 cpt_rd_wr_reg_msg) \ 180 /* NPC mbox IDs (range 0x6000 - 0x7FFF) */ \ 181 M(NPC_MCAM_ALLOC_ENTRY, 0x6000, npc_mcam_alloc_entry, npc_mcam_alloc_entry_req,\ 182 npc_mcam_alloc_entry_rsp) \ 183 M(NPC_MCAM_FREE_ENTRY, 0x6001, npc_mcam_free_entry, \ 184 npc_mcam_free_entry_req, msg_rsp) \ 185 M(NPC_MCAM_WRITE_ENTRY, 0x6002, npc_mcam_write_entry, \ 186 npc_mcam_write_entry_req, msg_rsp) \ 187 M(NPC_MCAM_ENA_ENTRY, 0x6003, npc_mcam_ena_entry, \ 188 npc_mcam_ena_dis_entry_req, msg_rsp) \ 189 M(NPC_MCAM_DIS_ENTRY, 0x6004, npc_mcam_dis_entry, \ 190 npc_mcam_ena_dis_entry_req, msg_rsp) \ 191 M(NPC_MCAM_SHIFT_ENTRY, 0x6005, npc_mcam_shift_entry, npc_mcam_shift_entry_req,\ 192 npc_mcam_shift_entry_rsp) \ 193 M(NPC_MCAM_ALLOC_COUNTER, 0x6006, npc_mcam_alloc_counter, \ 194 npc_mcam_alloc_counter_req, \ 195 npc_mcam_alloc_counter_rsp) \ 196 M(NPC_MCAM_FREE_COUNTER, 0x6007, npc_mcam_free_counter, \ 197 npc_mcam_oper_counter_req, msg_rsp) \ 198 M(NPC_MCAM_UNMAP_COUNTER, 0x6008, npc_mcam_unmap_counter, \ 199 npc_mcam_unmap_counter_req, msg_rsp) \ 200 M(NPC_MCAM_CLEAR_COUNTER, 0x6009, npc_mcam_clear_counter, \ 201 npc_mcam_oper_counter_req, msg_rsp) \ 202 M(NPC_MCAM_COUNTER_STATS, 0x600a, npc_mcam_counter_stats, \ 203 npc_mcam_oper_counter_req, \ 204 npc_mcam_oper_counter_rsp) \ 205 M(NPC_MCAM_ALLOC_AND_WRITE_ENTRY, 0x600b, npc_mcam_alloc_and_write_entry, \ 206 npc_mcam_alloc_and_write_entry_req, \ 207 npc_mcam_alloc_and_write_entry_rsp) \ 208 M(NPC_GET_KEX_CFG, 0x600c, npc_get_kex_cfg, \ 209 msg_req, npc_get_kex_cfg_rsp) \ 210 M(NPC_INSTALL_FLOW, 0x600d, npc_install_flow, \ 211 npc_install_flow_req, npc_install_flow_rsp) \ 212 M(NPC_DELETE_FLOW, 0x600e, npc_delete_flow, \ 213 npc_delete_flow_req, msg_rsp) \ 214 M(NPC_MCAM_READ_ENTRY, 0x600f, npc_mcam_read_entry, \ 215 npc_mcam_read_entry_req, \ 216 npc_mcam_read_entry_rsp) \ 217 M(NPC_MCAM_READ_BASE_RULE, 0x6011, npc_read_base_steer_rule, \ 218 msg_req, npc_mcam_read_base_rule_rsp) \ 219 /* NIX mbox IDs (range 0x8000 - 0xFFFF) */ \ 220 M(NIX_LF_ALLOC, 0x8000, nix_lf_alloc, \ 221 nix_lf_alloc_req, nix_lf_alloc_rsp) \ 222 M(NIX_LF_FREE, 0x8001, nix_lf_free, nix_lf_free_req, msg_rsp) \ 223 M(NIX_AQ_ENQ, 0x8002, nix_aq_enq, nix_aq_enq_req, nix_aq_enq_rsp) \ 224 M(NIX_HWCTX_DISABLE, 0x8003, nix_hwctx_disable, \ 225 hwctx_disable_req, msg_rsp) \ 226 M(NIX_TXSCH_ALLOC, 0x8004, nix_txsch_alloc, \ 227 nix_txsch_alloc_req, nix_txsch_alloc_rsp) \ 228 M(NIX_TXSCH_FREE, 0x8005, nix_txsch_free, nix_txsch_free_req, msg_rsp) \ 229 M(NIX_TXSCHQ_CFG, 0x8006, nix_txschq_cfg, nix_txschq_config, msg_rsp) \ 230 M(NIX_STATS_RST, 0x8007, nix_stats_rst, msg_req, msg_rsp) \ 231 M(NIX_VTAG_CFG, 0x8008, nix_vtag_cfg, nix_vtag_config, \ 232 nix_vtag_config_rsp) \ 233 M(NIX_RSS_FLOWKEY_CFG, 0x8009, nix_rss_flowkey_cfg, \ 234 nix_rss_flowkey_cfg, \ 235 nix_rss_flowkey_cfg_rsp) \ 236 M(NIX_SET_MAC_ADDR, 0x800a, nix_set_mac_addr, nix_set_mac_addr, msg_rsp) \ 237 M(NIX_SET_RX_MODE, 0x800b, nix_set_rx_mode, nix_rx_mode, msg_rsp) \ 238 M(NIX_SET_HW_FRS, 0x800c, nix_set_hw_frs, nix_frs_cfg, msg_rsp) \ 239 M(NIX_LF_START_RX, 0x800d, nix_lf_start_rx, msg_req, msg_rsp) \ 240 M(NIX_LF_STOP_RX, 0x800e, nix_lf_stop_rx, msg_req, msg_rsp) \ 241 M(NIX_MARK_FORMAT_CFG, 0x800f, nix_mark_format_cfg, \ 242 nix_mark_format_cfg, \ 243 nix_mark_format_cfg_rsp) \ 244 M(NIX_SET_RX_CFG, 0x8010, nix_set_rx_cfg, nix_rx_cfg, msg_rsp) \ 245 M(NIX_LSO_FORMAT_CFG, 0x8011, nix_lso_format_cfg, \ 246 nix_lso_format_cfg, \ 247 nix_lso_format_cfg_rsp) \ 248 M(NIX_LF_PTP_TX_ENABLE, 0x8013, nix_lf_ptp_tx_enable, msg_req, msg_rsp) \ 249 M(NIX_LF_PTP_TX_DISABLE, 0x8014, nix_lf_ptp_tx_disable, msg_req, msg_rsp) \ 250 M(NIX_BP_ENABLE, 0x8016, nix_bp_enable, nix_bp_cfg_req, \ 251 nix_bp_cfg_rsp) \ 252 M(NIX_BP_DISABLE, 0x8017, nix_bp_disable, nix_bp_cfg_req, msg_rsp) \ 253 M(NIX_GET_MAC_ADDR, 0x8018, nix_get_mac_addr, msg_req, nix_get_mac_addr_rsp) \ 254 M(NIX_CN10K_AQ_ENQ, 0x8019, nix_cn10k_aq_enq, nix_cn10k_aq_enq_req, \ 255 nix_cn10k_aq_enq_rsp) \ 256 M(NIX_GET_HW_INFO, 0x801a, nix_get_hw_info, msg_req, nix_hw_info) 257 258 /* Messages initiated by AF (range 0xC00 - 0xDFF) */ 259 #define MBOX_UP_CGX_MESSAGES \ 260 M(CGX_LINK_EVENT, 0xC00, cgx_link_event, cgx_link_info_msg, msg_rsp) 261 262 enum { 263 #define M(_name, _id, _1, _2, _3) MBOX_MSG_ ## _name = _id, 264 MBOX_MESSAGES 265 MBOX_UP_CGX_MESSAGES 266 #undef M 267 }; 268 269 /* Mailbox message formats */ 270 271 #define RVU_DEFAULT_PF_FUNC 0xFFFF 272 273 /* Generic request msg used for those mbox messages which 274 * don't send any data in the request. 275 */ 276 struct msg_req { 277 struct mbox_msghdr hdr; 278 }; 279 280 /* Generic rsponse msg used a ack or response for those mbox 281 * messages which doesn't have a specific rsp msg format. 282 */ 283 struct msg_rsp { 284 struct mbox_msghdr hdr; 285 }; 286 287 /* RVU mailbox error codes 288 * Range 256 - 300. 289 */ 290 enum rvu_af_status { 291 RVU_INVALID_VF_ID = -256, 292 }; 293 294 struct ready_msg_rsp { 295 struct mbox_msghdr hdr; 296 u16 sclk_freq; /* SCLK frequency (in MHz) */ 297 u16 rclk_freq; /* RCLK frequency (in MHz) */ 298 }; 299 300 /* Structure for requesting resource provisioning. 301 * 'modify' flag to be used when either requesting more 302 * or to detach partial of a cetain resource type. 303 * Rest of the fields specify how many of what type to 304 * be attached. 305 * To request LFs from two blocks of same type this mailbox 306 * can be sent twice as below: 307 * struct rsrc_attach *attach; 308 * .. Allocate memory for message .. 309 * attach->cptlfs = 3; <3 LFs from CPT0> 310 * .. Send message .. 311 * .. Allocate memory for message .. 312 * attach->modify = 1; 313 * attach->cpt_blkaddr = BLKADDR_CPT1; 314 * attach->cptlfs = 2; <2 LFs from CPT1> 315 * .. Send message .. 316 */ 317 struct rsrc_attach { 318 struct mbox_msghdr hdr; 319 u8 modify:1; 320 u8 npalf:1; 321 u8 nixlf:1; 322 u16 sso; 323 u16 ssow; 324 u16 timlfs; 325 u16 cptlfs; 326 int cpt_blkaddr; /* BLKADDR_CPT0/BLKADDR_CPT1 or 0 for BLKADDR_CPT0 */ 327 }; 328 329 /* Structure for relinquishing resources. 330 * 'partial' flag to be used when relinquishing all resources 331 * but only of a certain type. If not set, all resources of all 332 * types provisioned to the RVU function will be detached. 333 */ 334 struct rsrc_detach { 335 struct mbox_msghdr hdr; 336 u8 partial:1; 337 u8 npalf:1; 338 u8 nixlf:1; 339 u8 sso:1; 340 u8 ssow:1; 341 u8 timlfs:1; 342 u8 cptlfs:1; 343 }; 344 345 #define MSIX_VECTOR_INVALID 0xFFFF 346 #define MAX_RVU_BLKLF_CNT 256 347 348 struct msix_offset_rsp { 349 struct mbox_msghdr hdr; 350 u16 npa_msixoff; 351 u16 nix_msixoff; 352 u8 sso; 353 u8 ssow; 354 u8 timlfs; 355 u8 cptlfs; 356 u16 sso_msixoff[MAX_RVU_BLKLF_CNT]; 357 u16 ssow_msixoff[MAX_RVU_BLKLF_CNT]; 358 u16 timlf_msixoff[MAX_RVU_BLKLF_CNT]; 359 u16 cptlf_msixoff[MAX_RVU_BLKLF_CNT]; 360 u8 cpt1_lfs; 361 u16 cpt1_lf_msixoff[MAX_RVU_BLKLF_CNT]; 362 }; 363 364 struct get_hw_cap_rsp { 365 struct mbox_msghdr hdr; 366 u8 nix_fixed_txschq_mapping; /* Schq mapping fixed or flexible */ 367 u8 nix_shaping; /* Is shaping and coloring supported */ 368 }; 369 370 /* CGX mbox message formats */ 371 372 struct cgx_stats_rsp { 373 struct mbox_msghdr hdr; 374 #define CGX_RX_STATS_COUNT 9 375 #define CGX_TX_STATS_COUNT 18 376 u64 rx_stats[CGX_RX_STATS_COUNT]; 377 u64 tx_stats[CGX_TX_STATS_COUNT]; 378 }; 379 380 struct cgx_fec_stats_rsp { 381 struct mbox_msghdr hdr; 382 u64 fec_corr_blks; 383 u64 fec_uncorr_blks; 384 }; 385 /* Structure for requesting the operation for 386 * setting/getting mac address in the CGX interface 387 */ 388 struct cgx_mac_addr_set_or_get { 389 struct mbox_msghdr hdr; 390 u8 mac_addr[ETH_ALEN]; 391 }; 392 393 struct cgx_link_user_info { 394 uint64_t link_up:1; 395 uint64_t full_duplex:1; 396 uint64_t lmac_type_id:4; 397 uint64_t speed:20; /* speed in Mbps */ 398 uint64_t an:1; /* AN supported or not */ 399 uint64_t fec:2; /* FEC type if enabled else 0 */ 400 #define LMACTYPE_STR_LEN 16 401 char lmac_type[LMACTYPE_STR_LEN]; 402 }; 403 404 struct cgx_link_info_msg { 405 struct mbox_msghdr hdr; 406 struct cgx_link_user_info link_info; 407 }; 408 409 struct cgx_pause_frm_cfg { 410 struct mbox_msghdr hdr; 411 u8 set; 412 /* set = 1 if the request is to config pause frames */ 413 /* set = 0 if the request is to fetch pause frames config */ 414 u8 rx_pause; 415 u8 tx_pause; 416 }; 417 418 enum fec_type { 419 OTX2_FEC_NONE, 420 OTX2_FEC_BASER, 421 OTX2_FEC_RS, 422 OTX2_FEC_STATS_CNT = 2, 423 OTX2_FEC_OFF, 424 }; 425 426 struct fec_mode { 427 struct mbox_msghdr hdr; 428 int fec; 429 }; 430 431 struct sfp_eeprom_s { 432 #define SFP_EEPROM_SIZE 256 433 u16 sff_id; 434 u8 buf[SFP_EEPROM_SIZE]; 435 u64 reserved; 436 }; 437 438 struct phy_s { 439 struct { 440 u64 can_change_mod_type:1; 441 u64 mod_type:1; 442 u64 has_fec_stats:1; 443 } misc; 444 struct fec_stats_s { 445 u32 rsfec_corr_cws; 446 u32 rsfec_uncorr_cws; 447 u32 brfec_corr_blks; 448 u32 brfec_uncorr_blks; 449 } fec_stats; 450 }; 451 452 struct cgx_lmac_fwdata_s { 453 u16 rw_valid; 454 u64 supported_fec; 455 u64 supported_an; 456 u64 supported_link_modes; 457 /* only applicable if AN is supported */ 458 u64 advertised_fec; 459 u64 advertised_link_modes; 460 /* Only applicable if SFP/QSFP slot is present */ 461 struct sfp_eeprom_s sfp_eeprom; 462 struct phy_s phy; 463 #define LMAC_FWDATA_RESERVED_MEM 1021 464 u64 reserved[LMAC_FWDATA_RESERVED_MEM]; 465 }; 466 467 struct cgx_fw_data { 468 struct mbox_msghdr hdr; 469 struct cgx_lmac_fwdata_s fwdata; 470 }; 471 472 struct cgx_set_link_mode_args { 473 u32 speed; 474 u8 duplex; 475 u8 an; 476 u8 ports; 477 u64 mode; 478 }; 479 480 struct cgx_set_link_mode_req { 481 #define AUTONEG_UNKNOWN 0xff 482 struct mbox_msghdr hdr; 483 struct cgx_set_link_mode_args args; 484 }; 485 486 struct cgx_set_link_mode_rsp { 487 struct mbox_msghdr hdr; 488 int status; 489 }; 490 491 #define RVU_LMAC_FEAT_FC BIT_ULL(0) /* pause frames */ 492 #define RVU_LMAC_FEAT_PTP BIT_ULL(1) /* precison time protocol */ 493 #define RVU_MAC_VERSION BIT_ULL(2) 494 #define RVU_MAC_CGX BIT_ULL(3) 495 #define RVU_MAC_RPM BIT_ULL(4) 496 497 struct cgx_features_info_msg { 498 struct mbox_msghdr hdr; 499 u64 lmac_features; 500 }; 501 502 struct rpm_stats_rsp { 503 struct mbox_msghdr hdr; 504 #define RPM_RX_STATS_COUNT 43 505 #define RPM_TX_STATS_COUNT 34 506 u64 rx_stats[RPM_RX_STATS_COUNT]; 507 u64 tx_stats[RPM_TX_STATS_COUNT]; 508 }; 509 510 /* NPA mbox message formats */ 511 512 /* NPA mailbox error codes 513 * Range 301 - 400. 514 */ 515 enum npa_af_status { 516 NPA_AF_ERR_PARAM = -301, 517 NPA_AF_ERR_AQ_FULL = -302, 518 NPA_AF_ERR_AQ_ENQUEUE = -303, 519 NPA_AF_ERR_AF_LF_INVALID = -304, 520 NPA_AF_ERR_AF_LF_ALLOC = -305, 521 NPA_AF_ERR_LF_RESET = -306, 522 }; 523 524 /* For NPA LF context alloc and init */ 525 struct npa_lf_alloc_req { 526 struct mbox_msghdr hdr; 527 int node; 528 int aura_sz; /* No of auras */ 529 u32 nr_pools; /* No of pools */ 530 u64 way_mask; 531 }; 532 533 struct npa_lf_alloc_rsp { 534 struct mbox_msghdr hdr; 535 u32 stack_pg_ptrs; /* No of ptrs per stack page */ 536 u32 stack_pg_bytes; /* Size of stack page */ 537 u16 qints; /* NPA_AF_CONST::QINTS */ 538 }; 539 540 /* NPA AQ enqueue msg */ 541 struct npa_aq_enq_req { 542 struct mbox_msghdr hdr; 543 u32 aura_id; 544 u8 ctype; 545 u8 op; 546 union { 547 /* Valid when op == WRITE/INIT and ctype == AURA. 548 * LF fills the pool_id in aura.pool_addr. AF will translate 549 * the pool_id to pool context pointer. 550 */ 551 struct npa_aura_s aura; 552 /* Valid when op == WRITE/INIT and ctype == POOL */ 553 struct npa_pool_s pool; 554 }; 555 /* Mask data when op == WRITE (1=write, 0=don't write) */ 556 union { 557 /* Valid when op == WRITE and ctype == AURA */ 558 struct npa_aura_s aura_mask; 559 /* Valid when op == WRITE and ctype == POOL */ 560 struct npa_pool_s pool_mask; 561 }; 562 }; 563 564 struct npa_aq_enq_rsp { 565 struct mbox_msghdr hdr; 566 union { 567 /* Valid when op == READ and ctype == AURA */ 568 struct npa_aura_s aura; 569 /* Valid when op == READ and ctype == POOL */ 570 struct npa_pool_s pool; 571 }; 572 }; 573 574 /* Disable all contexts of type 'ctype' */ 575 struct hwctx_disable_req { 576 struct mbox_msghdr hdr; 577 u8 ctype; 578 }; 579 580 /* NIX mbox message formats */ 581 582 /* NIX mailbox error codes 583 * Range 401 - 500. 584 */ 585 enum nix_af_status { 586 NIX_AF_ERR_PARAM = -401, 587 NIX_AF_ERR_AQ_FULL = -402, 588 NIX_AF_ERR_AQ_ENQUEUE = -403, 589 NIX_AF_ERR_AF_LF_INVALID = -404, 590 NIX_AF_ERR_AF_LF_ALLOC = -405, 591 NIX_AF_ERR_TLX_ALLOC_FAIL = -406, 592 NIX_AF_ERR_TLX_INVALID = -407, 593 NIX_AF_ERR_RSS_SIZE_INVALID = -408, 594 NIX_AF_ERR_RSS_GRPS_INVALID = -409, 595 NIX_AF_ERR_FRS_INVALID = -410, 596 NIX_AF_ERR_RX_LINK_INVALID = -411, 597 NIX_AF_INVAL_TXSCHQ_CFG = -412, 598 NIX_AF_SMQ_FLUSH_FAILED = -413, 599 NIX_AF_ERR_LF_RESET = -414, 600 NIX_AF_ERR_RSS_NOSPC_FIELD = -415, 601 NIX_AF_ERR_RSS_NOSPC_ALGO = -416, 602 NIX_AF_ERR_MARK_CFG_FAIL = -417, 603 NIX_AF_ERR_LSO_CFG_FAIL = -418, 604 NIX_AF_INVAL_NPA_PF_FUNC = -419, 605 NIX_AF_INVAL_SSO_PF_FUNC = -420, 606 NIX_AF_ERR_TX_VTAG_NOSPC = -421, 607 NIX_AF_ERR_RX_VTAG_INUSE = -422, 608 }; 609 610 /* For NIX RX vtag action */ 611 enum nix_rx_vtag0_type { 612 NIX_AF_LFX_RX_VTAG_TYPE0, /* reserved for rx vlan offload */ 613 NIX_AF_LFX_RX_VTAG_TYPE1, 614 NIX_AF_LFX_RX_VTAG_TYPE2, 615 NIX_AF_LFX_RX_VTAG_TYPE3, 616 NIX_AF_LFX_RX_VTAG_TYPE4, 617 NIX_AF_LFX_RX_VTAG_TYPE5, 618 NIX_AF_LFX_RX_VTAG_TYPE6, 619 NIX_AF_LFX_RX_VTAG_TYPE7, 620 }; 621 622 /* For NIX LF context alloc and init */ 623 struct nix_lf_alloc_req { 624 struct mbox_msghdr hdr; 625 int node; 626 u32 rq_cnt; /* No of receive queues */ 627 u32 sq_cnt; /* No of send queues */ 628 u32 cq_cnt; /* No of completion queues */ 629 u8 xqe_sz; 630 u16 rss_sz; 631 u8 rss_grps; 632 u16 npa_func; 633 u16 sso_func; 634 u64 rx_cfg; /* See NIX_AF_LF(0..127)_RX_CFG */ 635 u64 way_mask; 636 }; 637 638 struct nix_lf_alloc_rsp { 639 struct mbox_msghdr hdr; 640 u16 sqb_size; 641 u16 rx_chan_base; 642 u16 tx_chan_base; 643 u8 rx_chan_cnt; /* total number of RX channels */ 644 u8 tx_chan_cnt; /* total number of TX channels */ 645 u8 lso_tsov4_idx; 646 u8 lso_tsov6_idx; 647 u8 mac_addr[ETH_ALEN]; 648 u8 lf_rx_stats; /* NIX_AF_CONST1::LF_RX_STATS */ 649 u8 lf_tx_stats; /* NIX_AF_CONST1::LF_TX_STATS */ 650 u16 cints; /* NIX_AF_CONST2::CINTS */ 651 u16 qints; /* NIX_AF_CONST2::QINTS */ 652 u8 cgx_links; /* No. of CGX links present in HW */ 653 u8 lbk_links; /* No. of LBK links present in HW */ 654 u8 sdp_links; /* No. of SDP links present in HW */ 655 }; 656 657 struct nix_lf_free_req { 658 struct mbox_msghdr hdr; 659 #define NIX_LF_DISABLE_FLOWS BIT_ULL(0) 660 #define NIX_LF_DONT_FREE_TX_VTAG BIT_ULL(1) 661 u64 flags; 662 }; 663 664 /* CN10K NIX AQ enqueue msg */ 665 struct nix_cn10k_aq_enq_req { 666 struct mbox_msghdr hdr; 667 u32 qidx; 668 u8 ctype; 669 u8 op; 670 union { 671 struct nix_cn10k_rq_ctx_s rq; 672 struct nix_cn10k_sq_ctx_s sq; 673 struct nix_cq_ctx_s cq; 674 struct nix_rsse_s rss; 675 struct nix_rx_mce_s mce; 676 }; 677 union { 678 struct nix_cn10k_rq_ctx_s rq_mask; 679 struct nix_cn10k_sq_ctx_s sq_mask; 680 struct nix_cq_ctx_s cq_mask; 681 struct nix_rsse_s rss_mask; 682 struct nix_rx_mce_s mce_mask; 683 }; 684 }; 685 686 struct nix_cn10k_aq_enq_rsp { 687 struct mbox_msghdr hdr; 688 union { 689 struct nix_cn10k_rq_ctx_s rq; 690 struct nix_cn10k_sq_ctx_s sq; 691 struct nix_cq_ctx_s cq; 692 struct nix_rsse_s rss; 693 struct nix_rx_mce_s mce; 694 }; 695 }; 696 697 /* NIX AQ enqueue msg */ 698 struct nix_aq_enq_req { 699 struct mbox_msghdr hdr; 700 u32 qidx; 701 u8 ctype; 702 u8 op; 703 union { 704 struct nix_rq_ctx_s rq; 705 struct nix_sq_ctx_s sq; 706 struct nix_cq_ctx_s cq; 707 struct nix_rsse_s rss; 708 struct nix_rx_mce_s mce; 709 }; 710 union { 711 struct nix_rq_ctx_s rq_mask; 712 struct nix_sq_ctx_s sq_mask; 713 struct nix_cq_ctx_s cq_mask; 714 struct nix_rsse_s rss_mask; 715 struct nix_rx_mce_s mce_mask; 716 }; 717 }; 718 719 struct nix_aq_enq_rsp { 720 struct mbox_msghdr hdr; 721 union { 722 struct nix_rq_ctx_s rq; 723 struct nix_sq_ctx_s sq; 724 struct nix_cq_ctx_s cq; 725 struct nix_rsse_s rss; 726 struct nix_rx_mce_s mce; 727 }; 728 }; 729 730 /* Tx scheduler/shaper mailbox messages */ 731 732 #define MAX_TXSCHQ_PER_FUNC 128 733 734 struct nix_txsch_alloc_req { 735 struct mbox_msghdr hdr; 736 /* Scheduler queue count request at each level */ 737 u16 schq_contig[NIX_TXSCH_LVL_CNT]; /* No of contiguous queues */ 738 u16 schq[NIX_TXSCH_LVL_CNT]; /* No of non-contiguous queues */ 739 }; 740 741 struct nix_txsch_alloc_rsp { 742 struct mbox_msghdr hdr; 743 /* Scheduler queue count allocated at each level */ 744 u16 schq_contig[NIX_TXSCH_LVL_CNT]; 745 u16 schq[NIX_TXSCH_LVL_CNT]; 746 /* Scheduler queue list allocated at each level */ 747 u16 schq_contig_list[NIX_TXSCH_LVL_CNT][MAX_TXSCHQ_PER_FUNC]; 748 u16 schq_list[NIX_TXSCH_LVL_CNT][MAX_TXSCHQ_PER_FUNC]; 749 u8 aggr_level; /* Traffic aggregation scheduler level */ 750 u8 aggr_lvl_rr_prio; /* Aggregation lvl's RR_PRIO config */ 751 u8 link_cfg_lvl; /* LINKX_CFG CSRs mapped to TL3 or TL2's index ? */ 752 }; 753 754 struct nix_txsch_free_req { 755 struct mbox_msghdr hdr; 756 #define TXSCHQ_FREE_ALL BIT_ULL(0) 757 u16 flags; 758 /* Scheduler queue level to be freed */ 759 u16 schq_lvl; 760 /* List of scheduler queues to be freed */ 761 u16 schq; 762 }; 763 764 struct nix_txschq_config { 765 struct mbox_msghdr hdr; 766 u8 lvl; /* SMQ/MDQ/TL4/TL3/TL2/TL1 */ 767 #define TXSCHQ_IDX_SHIFT 16 768 #define TXSCHQ_IDX_MASK (BIT_ULL(10) - 1) 769 #define TXSCHQ_IDX(reg, shift) (((reg) >> (shift)) & TXSCHQ_IDX_MASK) 770 u8 num_regs; 771 #define MAX_REGS_PER_MBOX_MSG 20 772 u64 reg[MAX_REGS_PER_MBOX_MSG]; 773 u64 regval[MAX_REGS_PER_MBOX_MSG]; 774 }; 775 776 struct nix_vtag_config { 777 struct mbox_msghdr hdr; 778 /* '0' for 4 octet VTAG, '1' for 8 octet VTAG */ 779 u8 vtag_size; 780 /* cfg_type is '0' for tx vlan cfg 781 * cfg_type is '1' for rx vlan cfg 782 */ 783 u8 cfg_type; 784 union { 785 /* valid when cfg_type is '0' */ 786 struct { 787 u64 vtag0; 788 u64 vtag1; 789 790 /* cfg_vtag0 & cfg_vtag1 fields are valid 791 * when free_vtag0 & free_vtag1 are '0's. 792 */ 793 /* cfg_vtag0 = 1 to configure vtag0 */ 794 u8 cfg_vtag0 :1; 795 /* cfg_vtag1 = 1 to configure vtag1 */ 796 u8 cfg_vtag1 :1; 797 798 /* vtag0_idx & vtag1_idx are only valid when 799 * both cfg_vtag0 & cfg_vtag1 are '0's, 800 * these fields are used along with free_vtag0 801 * & free_vtag1 to free the nix lf's tx_vlan 802 * configuration. 803 * 804 * Denotes the indices of tx_vtag def registers 805 * that needs to be cleared and freed. 806 */ 807 int vtag0_idx; 808 int vtag1_idx; 809 810 /* free_vtag0 & free_vtag1 fields are valid 811 * when cfg_vtag0 & cfg_vtag1 are '0's. 812 */ 813 /* free_vtag0 = 1 clears vtag0 configuration 814 * vtag0_idx denotes the index to be cleared. 815 */ 816 u8 free_vtag0 :1; 817 /* free_vtag1 = 1 clears vtag1 configuration 818 * vtag1_idx denotes the index to be cleared. 819 */ 820 u8 free_vtag1 :1; 821 } tx; 822 823 /* valid when cfg_type is '1' */ 824 struct { 825 /* rx vtag type index, valid values are in 0..7 range */ 826 u8 vtag_type; 827 /* rx vtag strip */ 828 u8 strip_vtag :1; 829 /* rx vtag capture */ 830 u8 capture_vtag :1; 831 } rx; 832 }; 833 }; 834 835 struct nix_vtag_config_rsp { 836 struct mbox_msghdr hdr; 837 int vtag0_idx; 838 int vtag1_idx; 839 /* Indices of tx_vtag def registers used to configure 840 * tx vtag0 & vtag1 headers, these indices are valid 841 * when nix_vtag_config mbox requested for vtag0 and/ 842 * or vtag1 configuration. 843 */ 844 }; 845 846 struct nix_rss_flowkey_cfg { 847 struct mbox_msghdr hdr; 848 int mcam_index; /* MCAM entry index to modify */ 849 #define NIX_FLOW_KEY_TYPE_PORT BIT(0) 850 #define NIX_FLOW_KEY_TYPE_IPV4 BIT(1) 851 #define NIX_FLOW_KEY_TYPE_IPV6 BIT(2) 852 #define NIX_FLOW_KEY_TYPE_TCP BIT(3) 853 #define NIX_FLOW_KEY_TYPE_UDP BIT(4) 854 #define NIX_FLOW_KEY_TYPE_SCTP BIT(5) 855 #define NIX_FLOW_KEY_TYPE_NVGRE BIT(6) 856 #define NIX_FLOW_KEY_TYPE_VXLAN BIT(7) 857 #define NIX_FLOW_KEY_TYPE_GENEVE BIT(8) 858 #define NIX_FLOW_KEY_TYPE_ETH_DMAC BIT(9) 859 #define NIX_FLOW_KEY_TYPE_IPV6_EXT BIT(10) 860 #define NIX_FLOW_KEY_TYPE_GTPU BIT(11) 861 #define NIX_FLOW_KEY_TYPE_INNR_IPV4 BIT(12) 862 #define NIX_FLOW_KEY_TYPE_INNR_IPV6 BIT(13) 863 #define NIX_FLOW_KEY_TYPE_INNR_TCP BIT(14) 864 #define NIX_FLOW_KEY_TYPE_INNR_UDP BIT(15) 865 #define NIX_FLOW_KEY_TYPE_INNR_SCTP BIT(16) 866 #define NIX_FLOW_KEY_TYPE_INNR_ETH_DMAC BIT(17) 867 #define NIX_FLOW_KEY_TYPE_VLAN BIT(20) 868 #define NIX_FLOW_KEY_TYPE_IPV4_PROTO BIT(21) 869 #define NIX_FLOW_KEY_TYPE_AH BIT(22) 870 #define NIX_FLOW_KEY_TYPE_ESP BIT(23) 871 u32 flowkey_cfg; /* Flowkey types selected */ 872 u8 group; /* RSS context or group */ 873 }; 874 875 struct nix_rss_flowkey_cfg_rsp { 876 struct mbox_msghdr hdr; 877 u8 alg_idx; /* Selected algo index */ 878 }; 879 880 struct nix_set_mac_addr { 881 struct mbox_msghdr hdr; 882 u8 mac_addr[ETH_ALEN]; /* MAC address to be set for this pcifunc */ 883 }; 884 885 struct nix_get_mac_addr_rsp { 886 struct mbox_msghdr hdr; 887 u8 mac_addr[ETH_ALEN]; 888 }; 889 890 struct nix_mark_format_cfg { 891 struct mbox_msghdr hdr; 892 u8 offset; 893 u8 y_mask; 894 u8 y_val; 895 u8 r_mask; 896 u8 r_val; 897 }; 898 899 struct nix_mark_format_cfg_rsp { 900 struct mbox_msghdr hdr; 901 u8 mark_format_idx; 902 }; 903 904 struct nix_rx_mode { 905 struct mbox_msghdr hdr; 906 #define NIX_RX_MODE_UCAST BIT(0) 907 #define NIX_RX_MODE_PROMISC BIT(1) 908 #define NIX_RX_MODE_ALLMULTI BIT(2) 909 u16 mode; 910 }; 911 912 struct nix_rx_cfg { 913 struct mbox_msghdr hdr; 914 #define NIX_RX_OL3_VERIFY BIT(0) 915 #define NIX_RX_OL4_VERIFY BIT(1) 916 u8 len_verify; /* Outer L3/L4 len check */ 917 #define NIX_RX_CSUM_OL4_VERIFY BIT(0) 918 u8 csum_verify; /* Outer L4 checksum verification */ 919 }; 920 921 struct nix_frs_cfg { 922 struct mbox_msghdr hdr; 923 u8 update_smq; /* Update SMQ's min/max lens */ 924 u8 update_minlen; /* Set minlen also */ 925 u8 sdp_link; /* Set SDP RX link */ 926 u16 maxlen; 927 u16 minlen; 928 }; 929 930 struct nix_lso_format_cfg { 931 struct mbox_msghdr hdr; 932 u64 field_mask; 933 #define NIX_LSO_FIELD_MAX 8 934 u64 fields[NIX_LSO_FIELD_MAX]; 935 }; 936 937 struct nix_lso_format_cfg_rsp { 938 struct mbox_msghdr hdr; 939 u8 lso_format_idx; 940 }; 941 942 struct nix_bp_cfg_req { 943 struct mbox_msghdr hdr; 944 u16 chan_base; /* Starting channel number */ 945 u8 chan_cnt; /* Number of channels */ 946 u8 bpid_per_chan; 947 /* bpid_per_chan = 0 assigns single bp id for range of channels */ 948 /* bpid_per_chan = 1 assigns separate bp id for each channel */ 949 }; 950 951 /* PF can be mapped to either CGX or LBK interface, 952 * so maximum 64 channels are possible. 953 */ 954 #define NIX_MAX_BPID_CHAN 64 955 struct nix_bp_cfg_rsp { 956 struct mbox_msghdr hdr; 957 u16 chan_bpid[NIX_MAX_BPID_CHAN]; /* Channel and bpid mapping */ 958 u8 chan_cnt; /* Number of channel for which bpids are assigned */ 959 }; 960 961 struct nix_hw_info { 962 struct mbox_msghdr hdr; 963 u16 max_mtu; 964 u16 min_mtu; 965 }; 966 967 /* NPC mbox message structs */ 968 969 #define NPC_MCAM_ENTRY_INVALID 0xFFFF 970 #define NPC_MCAM_INVALID_MAP 0xFFFF 971 972 /* NPC mailbox error codes 973 * Range 701 - 800. 974 */ 975 enum npc_af_status { 976 NPC_MCAM_INVALID_REQ = -701, 977 NPC_MCAM_ALLOC_DENIED = -702, 978 NPC_MCAM_ALLOC_FAILED = -703, 979 NPC_MCAM_PERM_DENIED = -704, 980 }; 981 982 struct npc_mcam_alloc_entry_req { 983 struct mbox_msghdr hdr; 984 #define NPC_MAX_NONCONTIG_ENTRIES 256 985 u8 contig; /* Contiguous entries ? */ 986 #define NPC_MCAM_ANY_PRIO 0 987 #define NPC_MCAM_LOWER_PRIO 1 988 #define NPC_MCAM_HIGHER_PRIO 2 989 u8 priority; /* Lower or higher w.r.t ref_entry */ 990 u16 ref_entry; 991 u16 count; /* Number of entries requested */ 992 }; 993 994 struct npc_mcam_alloc_entry_rsp { 995 struct mbox_msghdr hdr; 996 u16 entry; /* Entry allocated or start index if contiguous. 997 * Invalid incase of non-contiguous. 998 */ 999 u16 count; /* Number of entries allocated */ 1000 u16 free_count; /* Number of entries available */ 1001 u16 entry_list[NPC_MAX_NONCONTIG_ENTRIES]; 1002 }; 1003 1004 struct npc_mcam_free_entry_req { 1005 struct mbox_msghdr hdr; 1006 u16 entry; /* Entry index to be freed */ 1007 u8 all; /* If all entries allocated to this PFVF to be freed */ 1008 }; 1009 1010 struct mcam_entry { 1011 #define NPC_MAX_KWS_IN_KEY 7 /* Number of keywords in max keywidth */ 1012 u64 kw[NPC_MAX_KWS_IN_KEY]; 1013 u64 kw_mask[NPC_MAX_KWS_IN_KEY]; 1014 u64 action; 1015 u64 vtag_action; 1016 }; 1017 1018 struct npc_mcam_write_entry_req { 1019 struct mbox_msghdr hdr; 1020 struct mcam_entry entry_data; 1021 u16 entry; /* MCAM entry to write this match key */ 1022 u16 cntr; /* Counter for this MCAM entry */ 1023 u8 intf; /* Rx or Tx interface */ 1024 u8 enable_entry;/* Enable this MCAM entry ? */ 1025 u8 set_cntr; /* Set counter for this entry ? */ 1026 }; 1027 1028 /* Enable/Disable a given entry */ 1029 struct npc_mcam_ena_dis_entry_req { 1030 struct mbox_msghdr hdr; 1031 u16 entry; 1032 }; 1033 1034 struct npc_mcam_shift_entry_req { 1035 struct mbox_msghdr hdr; 1036 #define NPC_MCAM_MAX_SHIFTS 64 1037 u16 curr_entry[NPC_MCAM_MAX_SHIFTS]; 1038 u16 new_entry[NPC_MCAM_MAX_SHIFTS]; 1039 u16 shift_count; /* Number of entries to shift */ 1040 }; 1041 1042 struct npc_mcam_shift_entry_rsp { 1043 struct mbox_msghdr hdr; 1044 u16 failed_entry_idx; /* Index in 'curr_entry', not entry itself */ 1045 }; 1046 1047 struct npc_mcam_alloc_counter_req { 1048 struct mbox_msghdr hdr; 1049 u8 contig; /* Contiguous counters ? */ 1050 #define NPC_MAX_NONCONTIG_COUNTERS 64 1051 u16 count; /* Number of counters requested */ 1052 }; 1053 1054 struct npc_mcam_alloc_counter_rsp { 1055 struct mbox_msghdr hdr; 1056 u16 cntr; /* Counter allocated or start index if contiguous. 1057 * Invalid incase of non-contiguous. 1058 */ 1059 u16 count; /* Number of counters allocated */ 1060 u16 cntr_list[NPC_MAX_NONCONTIG_COUNTERS]; 1061 }; 1062 1063 struct npc_mcam_oper_counter_req { 1064 struct mbox_msghdr hdr; 1065 u16 cntr; /* Free a counter or clear/fetch it's stats */ 1066 }; 1067 1068 struct npc_mcam_oper_counter_rsp { 1069 struct mbox_msghdr hdr; 1070 u64 stat; /* valid only while fetching counter's stats */ 1071 }; 1072 1073 struct npc_mcam_unmap_counter_req { 1074 struct mbox_msghdr hdr; 1075 u16 cntr; 1076 u16 entry; /* Entry and counter to be unmapped */ 1077 u8 all; /* Unmap all entries using this counter ? */ 1078 }; 1079 1080 struct npc_mcam_alloc_and_write_entry_req { 1081 struct mbox_msghdr hdr; 1082 struct mcam_entry entry_data; 1083 u16 ref_entry; 1084 u8 priority; /* Lower or higher w.r.t ref_entry */ 1085 u8 intf; /* Rx or Tx interface */ 1086 u8 enable_entry;/* Enable this MCAM entry ? */ 1087 u8 alloc_cntr; /* Allocate counter and map ? */ 1088 }; 1089 1090 struct npc_mcam_alloc_and_write_entry_rsp { 1091 struct mbox_msghdr hdr; 1092 u16 entry; 1093 u16 cntr; 1094 }; 1095 1096 struct npc_get_kex_cfg_rsp { 1097 struct mbox_msghdr hdr; 1098 u64 rx_keyx_cfg; /* NPC_AF_INTF(0)_KEX_CFG */ 1099 u64 tx_keyx_cfg; /* NPC_AF_INTF(1)_KEX_CFG */ 1100 #define NPC_MAX_INTF 2 1101 #define NPC_MAX_LID 8 1102 #define NPC_MAX_LT 16 1103 #define NPC_MAX_LD 2 1104 #define NPC_MAX_LFL 16 1105 /* NPC_AF_KEX_LDATA(0..1)_FLAGS_CFG */ 1106 u64 kex_ld_flags[NPC_MAX_LD]; 1107 /* NPC_AF_INTF(0..1)_LID(0..7)_LT(0..15)_LD(0..1)_CFG */ 1108 u64 intf_lid_lt_ld[NPC_MAX_INTF][NPC_MAX_LID][NPC_MAX_LT][NPC_MAX_LD]; 1109 /* NPC_AF_INTF(0..1)_LDATA(0..1)_FLAGS(0..15)_CFG */ 1110 u64 intf_ld_flags[NPC_MAX_INTF][NPC_MAX_LD][NPC_MAX_LFL]; 1111 #define MKEX_NAME_LEN 128 1112 u8 mkex_pfl_name[MKEX_NAME_LEN]; 1113 }; 1114 1115 struct flow_msg { 1116 unsigned char dmac[6]; 1117 unsigned char smac[6]; 1118 __be16 etype; 1119 __be16 vlan_etype; 1120 __be16 vlan_tci; 1121 union { 1122 __be32 ip4src; 1123 __be32 ip6src[4]; 1124 }; 1125 union { 1126 __be32 ip4dst; 1127 __be32 ip6dst[4]; 1128 }; 1129 u8 tos; 1130 u8 ip_ver; 1131 u8 ip_proto; 1132 u8 tc; 1133 __be16 sport; 1134 __be16 dport; 1135 }; 1136 1137 struct npc_install_flow_req { 1138 struct mbox_msghdr hdr; 1139 struct flow_msg packet; 1140 struct flow_msg mask; 1141 u64 features; 1142 u16 entry; 1143 u16 channel; 1144 u8 intf; 1145 u8 set_cntr; /* If counter is available set counter for this entry ? */ 1146 u8 default_rule; 1147 u8 append; /* overwrite(0) or append(1) flow to default rule? */ 1148 u16 vf; 1149 /* action */ 1150 u32 index; 1151 u16 match_id; 1152 u8 flow_key_alg; 1153 u8 op; 1154 /* vtag rx action */ 1155 u8 vtag0_type; 1156 u8 vtag0_valid; 1157 u8 vtag1_type; 1158 u8 vtag1_valid; 1159 /* vtag tx action */ 1160 u16 vtag0_def; 1161 u8 vtag0_op; 1162 u16 vtag1_def; 1163 u8 vtag1_op; 1164 }; 1165 1166 struct npc_install_flow_rsp { 1167 struct mbox_msghdr hdr; 1168 int counter; /* negative if no counter else counter number */ 1169 }; 1170 1171 struct npc_delete_flow_req { 1172 struct mbox_msghdr hdr; 1173 u16 entry; 1174 u16 start;/*Disable range of entries */ 1175 u16 end; 1176 u8 all; /* PF + VFs */ 1177 }; 1178 1179 struct npc_mcam_read_entry_req { 1180 struct mbox_msghdr hdr; 1181 u16 entry; /* MCAM entry to read */ 1182 }; 1183 1184 struct npc_mcam_read_entry_rsp { 1185 struct mbox_msghdr hdr; 1186 struct mcam_entry entry_data; 1187 u8 intf; 1188 u8 enable; 1189 }; 1190 1191 struct npc_mcam_read_base_rule_rsp { 1192 struct mbox_msghdr hdr; 1193 struct mcam_entry entry; 1194 }; 1195 1196 enum ptp_op { 1197 PTP_OP_ADJFINE = 0, 1198 PTP_OP_GET_CLOCK = 1, 1199 }; 1200 1201 struct ptp_req { 1202 struct mbox_msghdr hdr; 1203 u8 op; 1204 s64 scaled_ppm; 1205 }; 1206 1207 struct ptp_rsp { 1208 struct mbox_msghdr hdr; 1209 u64 clk; 1210 }; 1211 1212 /* CPT mailbox error codes 1213 * Range 901 - 1000. 1214 */ 1215 enum cpt_af_status { 1216 CPT_AF_ERR_PARAM = -901, 1217 CPT_AF_ERR_GRP_INVALID = -902, 1218 CPT_AF_ERR_LF_INVALID = -903, 1219 CPT_AF_ERR_ACCESS_DENIED = -904, 1220 CPT_AF_ERR_SSO_PF_FUNC_INVALID = -905, 1221 CPT_AF_ERR_NIX_PF_FUNC_INVALID = -906 1222 }; 1223 1224 /* CPT mbox message formats */ 1225 struct cpt_rd_wr_reg_msg { 1226 struct mbox_msghdr hdr; 1227 u64 reg_offset; 1228 u64 *ret_val; 1229 u64 val; 1230 u8 is_write; 1231 int blkaddr; 1232 }; 1233 1234 struct cpt_lf_alloc_req_msg { 1235 struct mbox_msghdr hdr; 1236 u16 nix_pf_func; 1237 u16 sso_pf_func; 1238 u16 eng_grpmsk; 1239 int blkaddr; 1240 }; 1241 1242 #endif /* MBOX_H */ 1243