1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Marvell OcteonTx2 RVU Admin Function driver 3 * 4 * Copyright (C) 2018 Marvell International Ltd. 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 */ 10 11 #ifndef MBOX_H 12 #define MBOX_H 13 14 #include <linux/etherdevice.h> 15 #include <linux/sizes.h> 16 17 #include "rvu_struct.h" 18 #include "common.h" 19 20 #define MBOX_SIZE SZ_64K 21 22 /* AF/PF: PF initiated, PF/VF VF initiated */ 23 #define MBOX_DOWN_RX_START 0 24 #define MBOX_DOWN_RX_SIZE (46 * SZ_1K) 25 #define MBOX_DOWN_TX_START (MBOX_DOWN_RX_START + MBOX_DOWN_RX_SIZE) 26 #define MBOX_DOWN_TX_SIZE (16 * SZ_1K) 27 /* AF/PF: AF initiated, PF/VF PF initiated */ 28 #define MBOX_UP_RX_START (MBOX_DOWN_TX_START + MBOX_DOWN_TX_SIZE) 29 #define MBOX_UP_RX_SIZE SZ_1K 30 #define MBOX_UP_TX_START (MBOX_UP_RX_START + MBOX_UP_RX_SIZE) 31 #define MBOX_UP_TX_SIZE SZ_1K 32 33 #if MBOX_UP_TX_SIZE + MBOX_UP_TX_START != MBOX_SIZE 34 # error "incorrect mailbox area sizes" 35 #endif 36 37 #define INTR_MASK(pfvfs) ((pfvfs < 64) ? (BIT_ULL(pfvfs) - 1) : (~0ull)) 38 39 #define MBOX_RSP_TIMEOUT 3000 /* Time(ms) to wait for mbox response */ 40 41 #define MBOX_MSG_ALIGN 16 /* Align mbox msg start to 16bytes */ 42 43 /* Mailbox directions */ 44 #define MBOX_DIR_AFPF 0 /* AF replies to PF */ 45 #define MBOX_DIR_PFAF 1 /* PF sends messages to AF */ 46 #define MBOX_DIR_PFVF 2 /* PF replies to VF */ 47 #define MBOX_DIR_VFPF 3 /* VF sends messages to PF */ 48 #define MBOX_DIR_AFPF_UP 4 /* AF sends messages to PF */ 49 #define MBOX_DIR_PFAF_UP 5 /* PF replies to AF */ 50 #define MBOX_DIR_PFVF_UP 6 /* PF sends messages to VF */ 51 #define MBOX_DIR_VFPF_UP 7 /* VF replies to PF */ 52 53 struct otx2_mbox_dev { 54 void *mbase; /* This dev's mbox region */ 55 void *hwbase; 56 spinlock_t mbox_lock; 57 u16 msg_size; /* Total msg size to be sent */ 58 u16 rsp_size; /* Total rsp size to be sure the reply is ok */ 59 u16 num_msgs; /* No of msgs sent or waiting for response */ 60 u16 msgs_acked; /* No of msgs for which response is received */ 61 }; 62 63 struct otx2_mbox { 64 struct pci_dev *pdev; 65 void *hwbase; /* Mbox region advertised by HW */ 66 void *reg_base;/* CSR base for this dev */ 67 u64 trigger; /* Trigger mbox notification */ 68 u16 tr_shift; /* Mbox trigger shift */ 69 u64 rx_start; /* Offset of Rx region in mbox memory */ 70 u64 tx_start; /* Offset of Tx region in mbox memory */ 71 u16 rx_size; /* Size of Rx region */ 72 u16 tx_size; /* Size of Tx region */ 73 u16 ndevs; /* The number of peers */ 74 struct otx2_mbox_dev *dev; 75 }; 76 77 /* Header which precedes all mbox messages */ 78 struct mbox_hdr { 79 u64 msg_size; /* Total msgs size embedded */ 80 u16 num_msgs; /* No of msgs embedded */ 81 }; 82 83 /* Header which precedes every msg and is also part of it */ 84 struct mbox_msghdr { 85 u16 pcifunc; /* Who's sending this msg */ 86 u16 id; /* Mbox message ID */ 87 #define OTX2_MBOX_REQ_SIG (0xdead) 88 #define OTX2_MBOX_RSP_SIG (0xbeef) 89 u16 sig; /* Signature, for validating corrupted msgs */ 90 #define OTX2_MBOX_VERSION (0x0007) 91 u16 ver; /* Version of msg's structure for this ID */ 92 u16 next_msgoff; /* Offset of next msg within mailbox region */ 93 int rc; /* Msg process'ed response code */ 94 }; 95 96 void otx2_mbox_reset(struct otx2_mbox *mbox, int devid); 97 void __otx2_mbox_reset(struct otx2_mbox *mbox, int devid); 98 void otx2_mbox_destroy(struct otx2_mbox *mbox); 99 int otx2_mbox_init(struct otx2_mbox *mbox, void __force *hwbase, 100 struct pci_dev *pdev, void __force *reg_base, 101 int direction, int ndevs); 102 int otx2_mbox_regions_init(struct otx2_mbox *mbox, void __force **hwbase, 103 struct pci_dev *pdev, void __force *reg_base, 104 int direction, int ndevs); 105 void otx2_mbox_msg_send(struct otx2_mbox *mbox, int devid); 106 int otx2_mbox_wait_for_rsp(struct otx2_mbox *mbox, int devid); 107 int otx2_mbox_busy_poll_for_rsp(struct otx2_mbox *mbox, int devid); 108 struct mbox_msghdr *otx2_mbox_alloc_msg_rsp(struct otx2_mbox *mbox, int devid, 109 int size, int size_rsp); 110 struct mbox_msghdr *otx2_mbox_get_rsp(struct otx2_mbox *mbox, int devid, 111 struct mbox_msghdr *msg); 112 int otx2_mbox_check_rsp_msgs(struct otx2_mbox *mbox, int devid); 113 int otx2_reply_invalid_msg(struct otx2_mbox *mbox, int devid, 114 u16 pcifunc, u16 id); 115 bool otx2_mbox_nonempty(struct otx2_mbox *mbox, int devid); 116 const char *otx2_mbox_id2name(u16 id); 117 static inline struct mbox_msghdr *otx2_mbox_alloc_msg(struct otx2_mbox *mbox, 118 int devid, int size) 119 { 120 return otx2_mbox_alloc_msg_rsp(mbox, devid, size, 0); 121 } 122 123 /* Mailbox message types */ 124 #define MBOX_MSG_MASK 0xFFFF 125 #define MBOX_MSG_INVALID 0xFFFE 126 #define MBOX_MSG_MAX 0xFFFF 127 128 #define MBOX_MESSAGES \ 129 /* Generic mbox IDs (range 0x000 - 0x1FF) */ \ 130 M(READY, 0x001, ready, msg_req, ready_msg_rsp) \ 131 M(ATTACH_RESOURCES, 0x002, attach_resources, rsrc_attach, msg_rsp) \ 132 M(DETACH_RESOURCES, 0x003, detach_resources, rsrc_detach, msg_rsp) \ 133 M(MSIX_OFFSET, 0x005, msix_offset, msg_req, msix_offset_rsp) \ 134 M(VF_FLR, 0x006, vf_flr, msg_req, msg_rsp) \ 135 M(PTP_OP, 0x007, ptp_op, ptp_req, ptp_rsp) \ 136 M(GET_HW_CAP, 0x008, get_hw_cap, msg_req, get_hw_cap_rsp) \ 137 M(SET_VF_PERM, 0x00b, set_vf_perm, set_vf_perm, msg_rsp) \ 138 /* CGX mbox IDs (range 0x200 - 0x3FF) */ \ 139 M(CGX_START_RXTX, 0x200, cgx_start_rxtx, msg_req, msg_rsp) \ 140 M(CGX_STOP_RXTX, 0x201, cgx_stop_rxtx, msg_req, msg_rsp) \ 141 M(CGX_STATS, 0x202, cgx_stats, msg_req, cgx_stats_rsp) \ 142 M(CGX_MAC_ADDR_SET, 0x203, cgx_mac_addr_set, cgx_mac_addr_set_or_get, \ 143 cgx_mac_addr_set_or_get) \ 144 M(CGX_MAC_ADDR_GET, 0x204, cgx_mac_addr_get, cgx_mac_addr_set_or_get, \ 145 cgx_mac_addr_set_or_get) \ 146 M(CGX_PROMISC_ENABLE, 0x205, cgx_promisc_enable, msg_req, msg_rsp) \ 147 M(CGX_PROMISC_DISABLE, 0x206, cgx_promisc_disable, msg_req, msg_rsp) \ 148 M(CGX_START_LINKEVENTS, 0x207, cgx_start_linkevents, msg_req, msg_rsp) \ 149 M(CGX_STOP_LINKEVENTS, 0x208, cgx_stop_linkevents, msg_req, msg_rsp) \ 150 M(CGX_GET_LINKINFO, 0x209, cgx_get_linkinfo, msg_req, cgx_link_info_msg) \ 151 M(CGX_INTLBK_ENABLE, 0x20A, cgx_intlbk_enable, msg_req, msg_rsp) \ 152 M(CGX_INTLBK_DISABLE, 0x20B, cgx_intlbk_disable, msg_req, msg_rsp) \ 153 M(CGX_PTP_RX_ENABLE, 0x20C, cgx_ptp_rx_enable, msg_req, msg_rsp) \ 154 M(CGX_PTP_RX_DISABLE, 0x20D, cgx_ptp_rx_disable, msg_req, msg_rsp) \ 155 M(CGX_CFG_PAUSE_FRM, 0x20E, cgx_cfg_pause_frm, cgx_pause_frm_cfg, \ 156 cgx_pause_frm_cfg) \ 157 M(CGX_FEC_SET, 0x210, cgx_set_fec_param, fec_mode, fec_mode) \ 158 M(CGX_FEC_STATS, 0x211, cgx_fec_stats, msg_req, cgx_fec_stats_rsp) \ 159 M(CGX_GET_PHY_FEC_STATS, 0x212, cgx_get_phy_fec_stats, msg_req, msg_rsp) \ 160 M(CGX_FW_DATA_GET, 0x213, cgx_get_aux_link_info, msg_req, cgx_fw_data) \ 161 M(CGX_SET_LINK_MODE, 0x214, cgx_set_link_mode, cgx_set_link_mode_req,\ 162 cgx_set_link_mode_rsp) \ 163 M(CGX_FEATURES_GET, 0x215, cgx_features_get, msg_req, \ 164 cgx_features_info_msg) \ 165 M(RPM_STATS, 0x216, rpm_stats, msg_req, rpm_stats_rsp) \ 166 /* NPA mbox IDs (range 0x400 - 0x5FF) */ \ 167 /* NPA mbox IDs (range 0x400 - 0x5FF) */ \ 168 M(NPA_LF_ALLOC, 0x400, npa_lf_alloc, \ 169 npa_lf_alloc_req, npa_lf_alloc_rsp) \ 170 M(NPA_LF_FREE, 0x401, npa_lf_free, msg_req, msg_rsp) \ 171 M(NPA_AQ_ENQ, 0x402, npa_aq_enq, npa_aq_enq_req, npa_aq_enq_rsp) \ 172 M(NPA_HWCTX_DISABLE, 0x403, npa_hwctx_disable, hwctx_disable_req, msg_rsp)\ 173 /* SSO/SSOW mbox IDs (range 0x600 - 0x7FF) */ \ 174 /* TIM mbox IDs (range 0x800 - 0x9FF) */ \ 175 /* CPT mbox IDs (range 0xA00 - 0xBFF) */ \ 176 M(CPT_LF_ALLOC, 0xA00, cpt_lf_alloc, cpt_lf_alloc_req_msg, \ 177 msg_rsp) \ 178 M(CPT_LF_FREE, 0xA01, cpt_lf_free, msg_req, msg_rsp) \ 179 M(CPT_RD_WR_REGISTER, 0xA02, cpt_rd_wr_register, cpt_rd_wr_reg_msg, \ 180 cpt_rd_wr_reg_msg) \ 181 M(CPT_STATS, 0xA05, cpt_sts, cpt_sts_req, cpt_sts_rsp) \ 182 M(CPT_RXC_TIME_CFG, 0xA06, cpt_rxc_time_cfg, cpt_rxc_time_cfg_req, \ 183 msg_rsp) \ 184 /* NPC mbox IDs (range 0x6000 - 0x7FFF) */ \ 185 M(NPC_MCAM_ALLOC_ENTRY, 0x6000, npc_mcam_alloc_entry, npc_mcam_alloc_entry_req,\ 186 npc_mcam_alloc_entry_rsp) \ 187 M(NPC_MCAM_FREE_ENTRY, 0x6001, npc_mcam_free_entry, \ 188 npc_mcam_free_entry_req, msg_rsp) \ 189 M(NPC_MCAM_WRITE_ENTRY, 0x6002, npc_mcam_write_entry, \ 190 npc_mcam_write_entry_req, msg_rsp) \ 191 M(NPC_MCAM_ENA_ENTRY, 0x6003, npc_mcam_ena_entry, \ 192 npc_mcam_ena_dis_entry_req, msg_rsp) \ 193 M(NPC_MCAM_DIS_ENTRY, 0x6004, npc_mcam_dis_entry, \ 194 npc_mcam_ena_dis_entry_req, msg_rsp) \ 195 M(NPC_MCAM_SHIFT_ENTRY, 0x6005, npc_mcam_shift_entry, npc_mcam_shift_entry_req,\ 196 npc_mcam_shift_entry_rsp) \ 197 M(NPC_MCAM_ALLOC_COUNTER, 0x6006, npc_mcam_alloc_counter, \ 198 npc_mcam_alloc_counter_req, \ 199 npc_mcam_alloc_counter_rsp) \ 200 M(NPC_MCAM_FREE_COUNTER, 0x6007, npc_mcam_free_counter, \ 201 npc_mcam_oper_counter_req, msg_rsp) \ 202 M(NPC_MCAM_UNMAP_COUNTER, 0x6008, npc_mcam_unmap_counter, \ 203 npc_mcam_unmap_counter_req, msg_rsp) \ 204 M(NPC_MCAM_CLEAR_COUNTER, 0x6009, npc_mcam_clear_counter, \ 205 npc_mcam_oper_counter_req, msg_rsp) \ 206 M(NPC_MCAM_COUNTER_STATS, 0x600a, npc_mcam_counter_stats, \ 207 npc_mcam_oper_counter_req, \ 208 npc_mcam_oper_counter_rsp) \ 209 M(NPC_MCAM_ALLOC_AND_WRITE_ENTRY, 0x600b, npc_mcam_alloc_and_write_entry, \ 210 npc_mcam_alloc_and_write_entry_req, \ 211 npc_mcam_alloc_and_write_entry_rsp) \ 212 M(NPC_GET_KEX_CFG, 0x600c, npc_get_kex_cfg, \ 213 msg_req, npc_get_kex_cfg_rsp) \ 214 M(NPC_INSTALL_FLOW, 0x600d, npc_install_flow, \ 215 npc_install_flow_req, npc_install_flow_rsp) \ 216 M(NPC_DELETE_FLOW, 0x600e, npc_delete_flow, \ 217 npc_delete_flow_req, msg_rsp) \ 218 M(NPC_MCAM_READ_ENTRY, 0x600f, npc_mcam_read_entry, \ 219 npc_mcam_read_entry_req, \ 220 npc_mcam_read_entry_rsp) \ 221 M(NPC_MCAM_READ_BASE_RULE, 0x6011, npc_read_base_steer_rule, \ 222 msg_req, npc_mcam_read_base_rule_rsp) \ 223 M(NPC_MCAM_GET_STATS, 0x6012, npc_mcam_entry_stats, \ 224 npc_mcam_get_stats_req, \ 225 npc_mcam_get_stats_rsp) \ 226 /* NIX mbox IDs (range 0x8000 - 0xFFFF) */ \ 227 M(NIX_LF_ALLOC, 0x8000, nix_lf_alloc, \ 228 nix_lf_alloc_req, nix_lf_alloc_rsp) \ 229 M(NIX_LF_FREE, 0x8001, nix_lf_free, nix_lf_free_req, msg_rsp) \ 230 M(NIX_AQ_ENQ, 0x8002, nix_aq_enq, nix_aq_enq_req, nix_aq_enq_rsp) \ 231 M(NIX_HWCTX_DISABLE, 0x8003, nix_hwctx_disable, \ 232 hwctx_disable_req, msg_rsp) \ 233 M(NIX_TXSCH_ALLOC, 0x8004, nix_txsch_alloc, \ 234 nix_txsch_alloc_req, nix_txsch_alloc_rsp) \ 235 M(NIX_TXSCH_FREE, 0x8005, nix_txsch_free, nix_txsch_free_req, msg_rsp) \ 236 M(NIX_TXSCHQ_CFG, 0x8006, nix_txschq_cfg, nix_txschq_config, msg_rsp) \ 237 M(NIX_STATS_RST, 0x8007, nix_stats_rst, msg_req, msg_rsp) \ 238 M(NIX_VTAG_CFG, 0x8008, nix_vtag_cfg, nix_vtag_config, \ 239 nix_vtag_config_rsp) \ 240 M(NIX_RSS_FLOWKEY_CFG, 0x8009, nix_rss_flowkey_cfg, \ 241 nix_rss_flowkey_cfg, \ 242 nix_rss_flowkey_cfg_rsp) \ 243 M(NIX_SET_MAC_ADDR, 0x800a, nix_set_mac_addr, nix_set_mac_addr, msg_rsp) \ 244 M(NIX_SET_RX_MODE, 0x800b, nix_set_rx_mode, nix_rx_mode, msg_rsp) \ 245 M(NIX_SET_HW_FRS, 0x800c, nix_set_hw_frs, nix_frs_cfg, msg_rsp) \ 246 M(NIX_LF_START_RX, 0x800d, nix_lf_start_rx, msg_req, msg_rsp) \ 247 M(NIX_LF_STOP_RX, 0x800e, nix_lf_stop_rx, msg_req, msg_rsp) \ 248 M(NIX_MARK_FORMAT_CFG, 0x800f, nix_mark_format_cfg, \ 249 nix_mark_format_cfg, \ 250 nix_mark_format_cfg_rsp) \ 251 M(NIX_SET_RX_CFG, 0x8010, nix_set_rx_cfg, nix_rx_cfg, msg_rsp) \ 252 M(NIX_LSO_FORMAT_CFG, 0x8011, nix_lso_format_cfg, \ 253 nix_lso_format_cfg, \ 254 nix_lso_format_cfg_rsp) \ 255 M(NIX_LF_PTP_TX_ENABLE, 0x8013, nix_lf_ptp_tx_enable, msg_req, msg_rsp) \ 256 M(NIX_LF_PTP_TX_DISABLE, 0x8014, nix_lf_ptp_tx_disable, msg_req, msg_rsp) \ 257 M(NIX_BP_ENABLE, 0x8016, nix_bp_enable, nix_bp_cfg_req, \ 258 nix_bp_cfg_rsp) \ 259 M(NIX_BP_DISABLE, 0x8017, nix_bp_disable, nix_bp_cfg_req, msg_rsp) \ 260 M(NIX_GET_MAC_ADDR, 0x8018, nix_get_mac_addr, msg_req, nix_get_mac_addr_rsp) \ 261 M(NIX_CN10K_AQ_ENQ, 0x8019, nix_cn10k_aq_enq, nix_cn10k_aq_enq_req, \ 262 nix_cn10k_aq_enq_rsp) \ 263 M(NIX_GET_HW_INFO, 0x801c, nix_get_hw_info, msg_req, nix_hw_info) \ 264 M(NIX_BANDPROF_ALLOC, 0x801d, nix_bandprof_alloc, nix_bandprof_alloc_req, \ 265 nix_bandprof_alloc_rsp) \ 266 M(NIX_BANDPROF_FREE, 0x801e, nix_bandprof_free, nix_bandprof_free_req, \ 267 msg_rsp) 268 269 /* Messages initiated by AF (range 0xC00 - 0xDFF) */ 270 #define MBOX_UP_CGX_MESSAGES \ 271 M(CGX_LINK_EVENT, 0xC00, cgx_link_event, cgx_link_info_msg, msg_rsp) 272 273 enum { 274 #define M(_name, _id, _1, _2, _3) MBOX_MSG_ ## _name = _id, 275 MBOX_MESSAGES 276 MBOX_UP_CGX_MESSAGES 277 #undef M 278 }; 279 280 /* Mailbox message formats */ 281 282 #define RVU_DEFAULT_PF_FUNC 0xFFFF 283 284 /* Generic request msg used for those mbox messages which 285 * don't send any data in the request. 286 */ 287 struct msg_req { 288 struct mbox_msghdr hdr; 289 }; 290 291 /* Generic response msg used an ack or response for those mbox 292 * messages which don't have a specific rsp msg format. 293 */ 294 struct msg_rsp { 295 struct mbox_msghdr hdr; 296 }; 297 298 /* RVU mailbox error codes 299 * Range 256 - 300. 300 */ 301 enum rvu_af_status { 302 RVU_INVALID_VF_ID = -256, 303 }; 304 305 struct ready_msg_rsp { 306 struct mbox_msghdr hdr; 307 u16 sclk_freq; /* SCLK frequency (in MHz) */ 308 u16 rclk_freq; /* RCLK frequency (in MHz) */ 309 }; 310 311 /* Structure for requesting resource provisioning. 312 * 'modify' flag to be used when either requesting more 313 * or to detach partial of a certain resource type. 314 * Rest of the fields specify how many of what type to 315 * be attached. 316 * To request LFs from two blocks of same type this mailbox 317 * can be sent twice as below: 318 * struct rsrc_attach *attach; 319 * .. Allocate memory for message .. 320 * attach->cptlfs = 3; <3 LFs from CPT0> 321 * .. Send message .. 322 * .. Allocate memory for message .. 323 * attach->modify = 1; 324 * attach->cpt_blkaddr = BLKADDR_CPT1; 325 * attach->cptlfs = 2; <2 LFs from CPT1> 326 * .. Send message .. 327 */ 328 struct rsrc_attach { 329 struct mbox_msghdr hdr; 330 u8 modify:1; 331 u8 npalf:1; 332 u8 nixlf:1; 333 u16 sso; 334 u16 ssow; 335 u16 timlfs; 336 u16 cptlfs; 337 int cpt_blkaddr; /* BLKADDR_CPT0/BLKADDR_CPT1 or 0 for BLKADDR_CPT0 */ 338 }; 339 340 /* Structure for relinquishing resources. 341 * 'partial' flag to be used when relinquishing all resources 342 * but only of a certain type. If not set, all resources of all 343 * types provisioned to the RVU function will be detached. 344 */ 345 struct rsrc_detach { 346 struct mbox_msghdr hdr; 347 u8 partial:1; 348 u8 npalf:1; 349 u8 nixlf:1; 350 u8 sso:1; 351 u8 ssow:1; 352 u8 timlfs:1; 353 u8 cptlfs:1; 354 }; 355 356 #define MSIX_VECTOR_INVALID 0xFFFF 357 #define MAX_RVU_BLKLF_CNT 256 358 359 struct msix_offset_rsp { 360 struct mbox_msghdr hdr; 361 u16 npa_msixoff; 362 u16 nix_msixoff; 363 u8 sso; 364 u8 ssow; 365 u8 timlfs; 366 u8 cptlfs; 367 u16 sso_msixoff[MAX_RVU_BLKLF_CNT]; 368 u16 ssow_msixoff[MAX_RVU_BLKLF_CNT]; 369 u16 timlf_msixoff[MAX_RVU_BLKLF_CNT]; 370 u16 cptlf_msixoff[MAX_RVU_BLKLF_CNT]; 371 u8 cpt1_lfs; 372 u16 cpt1_lf_msixoff[MAX_RVU_BLKLF_CNT]; 373 }; 374 375 struct get_hw_cap_rsp { 376 struct mbox_msghdr hdr; 377 u8 nix_fixed_txschq_mapping; /* Schq mapping fixed or flexible */ 378 u8 nix_shaping; /* Is shaping and coloring supported */ 379 }; 380 381 /* CGX mbox message formats */ 382 383 struct cgx_stats_rsp { 384 struct mbox_msghdr hdr; 385 #define CGX_RX_STATS_COUNT 9 386 #define CGX_TX_STATS_COUNT 18 387 u64 rx_stats[CGX_RX_STATS_COUNT]; 388 u64 tx_stats[CGX_TX_STATS_COUNT]; 389 }; 390 391 struct cgx_fec_stats_rsp { 392 struct mbox_msghdr hdr; 393 u64 fec_corr_blks; 394 u64 fec_uncorr_blks; 395 }; 396 /* Structure for requesting the operation for 397 * setting/getting mac address in the CGX interface 398 */ 399 struct cgx_mac_addr_set_or_get { 400 struct mbox_msghdr hdr; 401 u8 mac_addr[ETH_ALEN]; 402 }; 403 404 struct cgx_link_user_info { 405 uint64_t link_up:1; 406 uint64_t full_duplex:1; 407 uint64_t lmac_type_id:4; 408 uint64_t speed:20; /* speed in Mbps */ 409 uint64_t an:1; /* AN supported or not */ 410 uint64_t fec:2; /* FEC type if enabled else 0 */ 411 #define LMACTYPE_STR_LEN 16 412 char lmac_type[LMACTYPE_STR_LEN]; 413 }; 414 415 struct cgx_link_info_msg { 416 struct mbox_msghdr hdr; 417 struct cgx_link_user_info link_info; 418 }; 419 420 struct cgx_pause_frm_cfg { 421 struct mbox_msghdr hdr; 422 u8 set; 423 /* set = 1 if the request is to config pause frames */ 424 /* set = 0 if the request is to fetch pause frames config */ 425 u8 rx_pause; 426 u8 tx_pause; 427 }; 428 429 enum fec_type { 430 OTX2_FEC_NONE, 431 OTX2_FEC_BASER, 432 OTX2_FEC_RS, 433 OTX2_FEC_STATS_CNT = 2, 434 OTX2_FEC_OFF, 435 }; 436 437 struct fec_mode { 438 struct mbox_msghdr hdr; 439 int fec; 440 }; 441 442 struct sfp_eeprom_s { 443 #define SFP_EEPROM_SIZE 256 444 u16 sff_id; 445 u8 buf[SFP_EEPROM_SIZE]; 446 u64 reserved; 447 }; 448 449 struct phy_s { 450 struct { 451 u64 can_change_mod_type:1; 452 u64 mod_type:1; 453 u64 has_fec_stats:1; 454 } misc; 455 struct fec_stats_s { 456 u32 rsfec_corr_cws; 457 u32 rsfec_uncorr_cws; 458 u32 brfec_corr_blks; 459 u32 brfec_uncorr_blks; 460 } fec_stats; 461 }; 462 463 struct cgx_lmac_fwdata_s { 464 u16 rw_valid; 465 u64 supported_fec; 466 u64 supported_an; 467 u64 supported_link_modes; 468 /* only applicable if AN is supported */ 469 u64 advertised_fec; 470 u64 advertised_link_modes; 471 /* Only applicable if SFP/QSFP slot is present */ 472 struct sfp_eeprom_s sfp_eeprom; 473 struct phy_s phy; 474 #define LMAC_FWDATA_RESERVED_MEM 1021 475 u64 reserved[LMAC_FWDATA_RESERVED_MEM]; 476 }; 477 478 struct cgx_fw_data { 479 struct mbox_msghdr hdr; 480 struct cgx_lmac_fwdata_s fwdata; 481 }; 482 483 struct cgx_set_link_mode_args { 484 u32 speed; 485 u8 duplex; 486 u8 an; 487 u8 ports; 488 u64 mode; 489 }; 490 491 struct cgx_set_link_mode_req { 492 #define AUTONEG_UNKNOWN 0xff 493 struct mbox_msghdr hdr; 494 struct cgx_set_link_mode_args args; 495 }; 496 497 struct cgx_set_link_mode_rsp { 498 struct mbox_msghdr hdr; 499 int status; 500 }; 501 502 #define RVU_LMAC_FEAT_FC BIT_ULL(0) /* pause frames */ 503 #define RVU_LMAC_FEAT_PTP BIT_ULL(1) /* precision time protocol */ 504 #define RVU_MAC_VERSION BIT_ULL(2) 505 #define RVU_MAC_CGX BIT_ULL(3) 506 #define RVU_MAC_RPM BIT_ULL(4) 507 508 struct cgx_features_info_msg { 509 struct mbox_msghdr hdr; 510 u64 lmac_features; 511 }; 512 513 struct rpm_stats_rsp { 514 struct mbox_msghdr hdr; 515 #define RPM_RX_STATS_COUNT 43 516 #define RPM_TX_STATS_COUNT 34 517 u64 rx_stats[RPM_RX_STATS_COUNT]; 518 u64 tx_stats[RPM_TX_STATS_COUNT]; 519 }; 520 521 /* NPA mbox message formats */ 522 523 /* NPA mailbox error codes 524 * Range 301 - 400. 525 */ 526 enum npa_af_status { 527 NPA_AF_ERR_PARAM = -301, 528 NPA_AF_ERR_AQ_FULL = -302, 529 NPA_AF_ERR_AQ_ENQUEUE = -303, 530 NPA_AF_ERR_AF_LF_INVALID = -304, 531 NPA_AF_ERR_AF_LF_ALLOC = -305, 532 NPA_AF_ERR_LF_RESET = -306, 533 }; 534 535 /* For NPA LF context alloc and init */ 536 struct npa_lf_alloc_req { 537 struct mbox_msghdr hdr; 538 int node; 539 int aura_sz; /* No of auras */ 540 u32 nr_pools; /* No of pools */ 541 u64 way_mask; 542 }; 543 544 struct npa_lf_alloc_rsp { 545 struct mbox_msghdr hdr; 546 u32 stack_pg_ptrs; /* No of ptrs per stack page */ 547 u32 stack_pg_bytes; /* Size of stack page */ 548 u16 qints; /* NPA_AF_CONST::QINTS */ 549 }; 550 551 /* NPA AQ enqueue msg */ 552 struct npa_aq_enq_req { 553 struct mbox_msghdr hdr; 554 u32 aura_id; 555 u8 ctype; 556 u8 op; 557 union { 558 /* Valid when op == WRITE/INIT and ctype == AURA. 559 * LF fills the pool_id in aura.pool_addr. AF will translate 560 * the pool_id to pool context pointer. 561 */ 562 struct npa_aura_s aura; 563 /* Valid when op == WRITE/INIT and ctype == POOL */ 564 struct npa_pool_s pool; 565 }; 566 /* Mask data when op == WRITE (1=write, 0=don't write) */ 567 union { 568 /* Valid when op == WRITE and ctype == AURA */ 569 struct npa_aura_s aura_mask; 570 /* Valid when op == WRITE and ctype == POOL */ 571 struct npa_pool_s pool_mask; 572 }; 573 }; 574 575 struct npa_aq_enq_rsp { 576 struct mbox_msghdr hdr; 577 union { 578 /* Valid when op == READ and ctype == AURA */ 579 struct npa_aura_s aura; 580 /* Valid when op == READ and ctype == POOL */ 581 struct npa_pool_s pool; 582 }; 583 }; 584 585 /* Disable all contexts of type 'ctype' */ 586 struct hwctx_disable_req { 587 struct mbox_msghdr hdr; 588 u8 ctype; 589 }; 590 591 /* NIX mbox message formats */ 592 593 /* NIX mailbox error codes 594 * Range 401 - 500. 595 */ 596 enum nix_af_status { 597 NIX_AF_ERR_PARAM = -401, 598 NIX_AF_ERR_AQ_FULL = -402, 599 NIX_AF_ERR_AQ_ENQUEUE = -403, 600 NIX_AF_ERR_AF_LF_INVALID = -404, 601 NIX_AF_ERR_AF_LF_ALLOC = -405, 602 NIX_AF_ERR_TLX_ALLOC_FAIL = -406, 603 NIX_AF_ERR_TLX_INVALID = -407, 604 NIX_AF_ERR_RSS_SIZE_INVALID = -408, 605 NIX_AF_ERR_RSS_GRPS_INVALID = -409, 606 NIX_AF_ERR_FRS_INVALID = -410, 607 NIX_AF_ERR_RX_LINK_INVALID = -411, 608 NIX_AF_INVAL_TXSCHQ_CFG = -412, 609 NIX_AF_SMQ_FLUSH_FAILED = -413, 610 NIX_AF_ERR_LF_RESET = -414, 611 NIX_AF_ERR_RSS_NOSPC_FIELD = -415, 612 NIX_AF_ERR_RSS_NOSPC_ALGO = -416, 613 NIX_AF_ERR_MARK_CFG_FAIL = -417, 614 NIX_AF_ERR_LSO_CFG_FAIL = -418, 615 NIX_AF_INVAL_NPA_PF_FUNC = -419, 616 NIX_AF_INVAL_SSO_PF_FUNC = -420, 617 NIX_AF_ERR_TX_VTAG_NOSPC = -421, 618 NIX_AF_ERR_RX_VTAG_INUSE = -422, 619 NIX_AF_ERR_PTP_CONFIG_FAIL = -423, 620 NIX_AF_ERR_NPC_KEY_NOT_SUPP = -424, 621 NIX_AF_ERR_INVALID_NIXBLK = -425, 622 NIX_AF_ERR_INVALID_BANDPROF = -426, 623 NIX_AF_ERR_IPOLICER_NOTSUPP = -427, 624 NIX_AF_ERR_BANDPROF_INVAL_REQ = -428, 625 }; 626 627 /* For NIX RX vtag action */ 628 enum nix_rx_vtag0_type { 629 NIX_AF_LFX_RX_VTAG_TYPE0, /* reserved for rx vlan offload */ 630 NIX_AF_LFX_RX_VTAG_TYPE1, 631 NIX_AF_LFX_RX_VTAG_TYPE2, 632 NIX_AF_LFX_RX_VTAG_TYPE3, 633 NIX_AF_LFX_RX_VTAG_TYPE4, 634 NIX_AF_LFX_RX_VTAG_TYPE5, 635 NIX_AF_LFX_RX_VTAG_TYPE6, 636 NIX_AF_LFX_RX_VTAG_TYPE7, 637 }; 638 639 /* For NIX LF context alloc and init */ 640 struct nix_lf_alloc_req { 641 struct mbox_msghdr hdr; 642 int node; 643 u32 rq_cnt; /* No of receive queues */ 644 u32 sq_cnt; /* No of send queues */ 645 u32 cq_cnt; /* No of completion queues */ 646 u8 xqe_sz; 647 u16 rss_sz; 648 u8 rss_grps; 649 u16 npa_func; 650 u16 sso_func; 651 u64 rx_cfg; /* See NIX_AF_LF(0..127)_RX_CFG */ 652 u64 way_mask; 653 }; 654 655 struct nix_lf_alloc_rsp { 656 struct mbox_msghdr hdr; 657 u16 sqb_size; 658 u16 rx_chan_base; 659 u16 tx_chan_base; 660 u8 rx_chan_cnt; /* total number of RX channels */ 661 u8 tx_chan_cnt; /* total number of TX channels */ 662 u8 lso_tsov4_idx; 663 u8 lso_tsov6_idx; 664 u8 mac_addr[ETH_ALEN]; 665 u8 lf_rx_stats; /* NIX_AF_CONST1::LF_RX_STATS */ 666 u8 lf_tx_stats; /* NIX_AF_CONST1::LF_TX_STATS */ 667 u16 cints; /* NIX_AF_CONST2::CINTS */ 668 u16 qints; /* NIX_AF_CONST2::QINTS */ 669 u8 cgx_links; /* No. of CGX links present in HW */ 670 u8 lbk_links; /* No. of LBK links present in HW */ 671 u8 sdp_links; /* No. of SDP links present in HW */ 672 }; 673 674 struct nix_lf_free_req { 675 struct mbox_msghdr hdr; 676 #define NIX_LF_DISABLE_FLOWS BIT_ULL(0) 677 #define NIX_LF_DONT_FREE_TX_VTAG BIT_ULL(1) 678 u64 flags; 679 }; 680 681 /* CN10K NIX AQ enqueue msg */ 682 struct nix_cn10k_aq_enq_req { 683 struct mbox_msghdr hdr; 684 u32 qidx; 685 u8 ctype; 686 u8 op; 687 union { 688 struct nix_cn10k_rq_ctx_s rq; 689 struct nix_cn10k_sq_ctx_s sq; 690 struct nix_cq_ctx_s cq; 691 struct nix_rsse_s rss; 692 struct nix_rx_mce_s mce; 693 struct nix_bandprof_s prof; 694 }; 695 union { 696 struct nix_cn10k_rq_ctx_s rq_mask; 697 struct nix_cn10k_sq_ctx_s sq_mask; 698 struct nix_cq_ctx_s cq_mask; 699 struct nix_rsse_s rss_mask; 700 struct nix_rx_mce_s mce_mask; 701 struct nix_bandprof_s prof_mask; 702 }; 703 }; 704 705 struct nix_cn10k_aq_enq_rsp { 706 struct mbox_msghdr hdr; 707 union { 708 struct nix_cn10k_rq_ctx_s rq; 709 struct nix_cn10k_sq_ctx_s sq; 710 struct nix_cq_ctx_s cq; 711 struct nix_rsse_s rss; 712 struct nix_rx_mce_s mce; 713 struct nix_bandprof_s prof; 714 }; 715 }; 716 717 /* NIX AQ enqueue msg */ 718 struct nix_aq_enq_req { 719 struct mbox_msghdr hdr; 720 u32 qidx; 721 u8 ctype; 722 u8 op; 723 union { 724 struct nix_rq_ctx_s rq; 725 struct nix_sq_ctx_s sq; 726 struct nix_cq_ctx_s cq; 727 struct nix_rsse_s rss; 728 struct nix_rx_mce_s mce; 729 u64 prof; 730 }; 731 union { 732 struct nix_rq_ctx_s rq_mask; 733 struct nix_sq_ctx_s sq_mask; 734 struct nix_cq_ctx_s cq_mask; 735 struct nix_rsse_s rss_mask; 736 struct nix_rx_mce_s mce_mask; 737 u64 prof_mask; 738 }; 739 }; 740 741 struct nix_aq_enq_rsp { 742 struct mbox_msghdr hdr; 743 union { 744 struct nix_rq_ctx_s rq; 745 struct nix_sq_ctx_s sq; 746 struct nix_cq_ctx_s cq; 747 struct nix_rsse_s rss; 748 struct nix_rx_mce_s mce; 749 struct nix_bandprof_s prof; 750 }; 751 }; 752 753 /* Tx scheduler/shaper mailbox messages */ 754 755 #define MAX_TXSCHQ_PER_FUNC 128 756 757 struct nix_txsch_alloc_req { 758 struct mbox_msghdr hdr; 759 /* Scheduler queue count request at each level */ 760 u16 schq_contig[NIX_TXSCH_LVL_CNT]; /* No of contiguous queues */ 761 u16 schq[NIX_TXSCH_LVL_CNT]; /* No of non-contiguous queues */ 762 }; 763 764 struct nix_txsch_alloc_rsp { 765 struct mbox_msghdr hdr; 766 /* Scheduler queue count allocated at each level */ 767 u16 schq_contig[NIX_TXSCH_LVL_CNT]; 768 u16 schq[NIX_TXSCH_LVL_CNT]; 769 /* Scheduler queue list allocated at each level */ 770 u16 schq_contig_list[NIX_TXSCH_LVL_CNT][MAX_TXSCHQ_PER_FUNC]; 771 u16 schq_list[NIX_TXSCH_LVL_CNT][MAX_TXSCHQ_PER_FUNC]; 772 u8 aggr_level; /* Traffic aggregation scheduler level */ 773 u8 aggr_lvl_rr_prio; /* Aggregation lvl's RR_PRIO config */ 774 u8 link_cfg_lvl; /* LINKX_CFG CSRs mapped to TL3 or TL2's index ? */ 775 }; 776 777 struct nix_txsch_free_req { 778 struct mbox_msghdr hdr; 779 #define TXSCHQ_FREE_ALL BIT_ULL(0) 780 u16 flags; 781 /* Scheduler queue level to be freed */ 782 u16 schq_lvl; 783 /* List of scheduler queues to be freed */ 784 u16 schq; 785 }; 786 787 struct nix_txschq_config { 788 struct mbox_msghdr hdr; 789 u8 lvl; /* SMQ/MDQ/TL4/TL3/TL2/TL1 */ 790 #define TXSCHQ_IDX_SHIFT 16 791 #define TXSCHQ_IDX_MASK (BIT_ULL(10) - 1) 792 #define TXSCHQ_IDX(reg, shift) (((reg) >> (shift)) & TXSCHQ_IDX_MASK) 793 u8 num_regs; 794 #define MAX_REGS_PER_MBOX_MSG 20 795 u64 reg[MAX_REGS_PER_MBOX_MSG]; 796 u64 regval[MAX_REGS_PER_MBOX_MSG]; 797 }; 798 799 struct nix_vtag_config { 800 struct mbox_msghdr hdr; 801 /* '0' for 4 octet VTAG, '1' for 8 octet VTAG */ 802 u8 vtag_size; 803 /* cfg_type is '0' for tx vlan cfg 804 * cfg_type is '1' for rx vlan cfg 805 */ 806 u8 cfg_type; 807 union { 808 /* valid when cfg_type is '0' */ 809 struct { 810 u64 vtag0; 811 u64 vtag1; 812 813 /* cfg_vtag0 & cfg_vtag1 fields are valid 814 * when free_vtag0 & free_vtag1 are '0's. 815 */ 816 /* cfg_vtag0 = 1 to configure vtag0 */ 817 u8 cfg_vtag0 :1; 818 /* cfg_vtag1 = 1 to configure vtag1 */ 819 u8 cfg_vtag1 :1; 820 821 /* vtag0_idx & vtag1_idx are only valid when 822 * both cfg_vtag0 & cfg_vtag1 are '0's, 823 * these fields are used along with free_vtag0 824 * & free_vtag1 to free the nix lf's tx_vlan 825 * configuration. 826 * 827 * Denotes the indices of tx_vtag def registers 828 * that needs to be cleared and freed. 829 */ 830 int vtag0_idx; 831 int vtag1_idx; 832 833 /* free_vtag0 & free_vtag1 fields are valid 834 * when cfg_vtag0 & cfg_vtag1 are '0's. 835 */ 836 /* free_vtag0 = 1 clears vtag0 configuration 837 * vtag0_idx denotes the index to be cleared. 838 */ 839 u8 free_vtag0 :1; 840 /* free_vtag1 = 1 clears vtag1 configuration 841 * vtag1_idx denotes the index to be cleared. 842 */ 843 u8 free_vtag1 :1; 844 } tx; 845 846 /* valid when cfg_type is '1' */ 847 struct { 848 /* rx vtag type index, valid values are in 0..7 range */ 849 u8 vtag_type; 850 /* rx vtag strip */ 851 u8 strip_vtag :1; 852 /* rx vtag capture */ 853 u8 capture_vtag :1; 854 } rx; 855 }; 856 }; 857 858 struct nix_vtag_config_rsp { 859 struct mbox_msghdr hdr; 860 int vtag0_idx; 861 int vtag1_idx; 862 /* Indices of tx_vtag def registers used to configure 863 * tx vtag0 & vtag1 headers, these indices are valid 864 * when nix_vtag_config mbox requested for vtag0 and/ 865 * or vtag1 configuration. 866 */ 867 }; 868 869 struct nix_rss_flowkey_cfg { 870 struct mbox_msghdr hdr; 871 int mcam_index; /* MCAM entry index to modify */ 872 #define NIX_FLOW_KEY_TYPE_PORT BIT(0) 873 #define NIX_FLOW_KEY_TYPE_IPV4 BIT(1) 874 #define NIX_FLOW_KEY_TYPE_IPV6 BIT(2) 875 #define NIX_FLOW_KEY_TYPE_TCP BIT(3) 876 #define NIX_FLOW_KEY_TYPE_UDP BIT(4) 877 #define NIX_FLOW_KEY_TYPE_SCTP BIT(5) 878 #define NIX_FLOW_KEY_TYPE_NVGRE BIT(6) 879 #define NIX_FLOW_KEY_TYPE_VXLAN BIT(7) 880 #define NIX_FLOW_KEY_TYPE_GENEVE BIT(8) 881 #define NIX_FLOW_KEY_TYPE_ETH_DMAC BIT(9) 882 #define NIX_FLOW_KEY_TYPE_IPV6_EXT BIT(10) 883 #define NIX_FLOW_KEY_TYPE_GTPU BIT(11) 884 #define NIX_FLOW_KEY_TYPE_INNR_IPV4 BIT(12) 885 #define NIX_FLOW_KEY_TYPE_INNR_IPV6 BIT(13) 886 #define NIX_FLOW_KEY_TYPE_INNR_TCP BIT(14) 887 #define NIX_FLOW_KEY_TYPE_INNR_UDP BIT(15) 888 #define NIX_FLOW_KEY_TYPE_INNR_SCTP BIT(16) 889 #define NIX_FLOW_KEY_TYPE_INNR_ETH_DMAC BIT(17) 890 #define NIX_FLOW_KEY_TYPE_VLAN BIT(20) 891 #define NIX_FLOW_KEY_TYPE_IPV4_PROTO BIT(21) 892 #define NIX_FLOW_KEY_TYPE_AH BIT(22) 893 #define NIX_FLOW_KEY_TYPE_ESP BIT(23) 894 u32 flowkey_cfg; /* Flowkey types selected */ 895 u8 group; /* RSS context or group */ 896 }; 897 898 struct nix_rss_flowkey_cfg_rsp { 899 struct mbox_msghdr hdr; 900 u8 alg_idx; /* Selected algo index */ 901 }; 902 903 struct nix_set_mac_addr { 904 struct mbox_msghdr hdr; 905 u8 mac_addr[ETH_ALEN]; /* MAC address to be set for this pcifunc */ 906 }; 907 908 struct nix_get_mac_addr_rsp { 909 struct mbox_msghdr hdr; 910 u8 mac_addr[ETH_ALEN]; 911 }; 912 913 struct nix_mark_format_cfg { 914 struct mbox_msghdr hdr; 915 u8 offset; 916 u8 y_mask; 917 u8 y_val; 918 u8 r_mask; 919 u8 r_val; 920 }; 921 922 struct nix_mark_format_cfg_rsp { 923 struct mbox_msghdr hdr; 924 u8 mark_format_idx; 925 }; 926 927 struct nix_rx_mode { 928 struct mbox_msghdr hdr; 929 #define NIX_RX_MODE_UCAST BIT(0) 930 #define NIX_RX_MODE_PROMISC BIT(1) 931 #define NIX_RX_MODE_ALLMULTI BIT(2) 932 #define NIX_RX_MODE_USE_MCE BIT(3) 933 u16 mode; 934 }; 935 936 struct nix_rx_cfg { 937 struct mbox_msghdr hdr; 938 #define NIX_RX_OL3_VERIFY BIT(0) 939 #define NIX_RX_OL4_VERIFY BIT(1) 940 u8 len_verify; /* Outer L3/L4 len check */ 941 #define NIX_RX_CSUM_OL4_VERIFY BIT(0) 942 u8 csum_verify; /* Outer L4 checksum verification */ 943 }; 944 945 struct nix_frs_cfg { 946 struct mbox_msghdr hdr; 947 u8 update_smq; /* Update SMQ's min/max lens */ 948 u8 update_minlen; /* Set minlen also */ 949 u8 sdp_link; /* Set SDP RX link */ 950 u16 maxlen; 951 u16 minlen; 952 }; 953 954 struct nix_lso_format_cfg { 955 struct mbox_msghdr hdr; 956 u64 field_mask; 957 #define NIX_LSO_FIELD_MAX 8 958 u64 fields[NIX_LSO_FIELD_MAX]; 959 }; 960 961 struct nix_lso_format_cfg_rsp { 962 struct mbox_msghdr hdr; 963 u8 lso_format_idx; 964 }; 965 966 struct nix_bp_cfg_req { 967 struct mbox_msghdr hdr; 968 u16 chan_base; /* Starting channel number */ 969 u8 chan_cnt; /* Number of channels */ 970 u8 bpid_per_chan; 971 /* bpid_per_chan = 0 assigns single bp id for range of channels */ 972 /* bpid_per_chan = 1 assigns separate bp id for each channel */ 973 }; 974 975 /* PF can be mapped to either CGX or LBK interface, 976 * so maximum 64 channels are possible. 977 */ 978 #define NIX_MAX_BPID_CHAN 64 979 struct nix_bp_cfg_rsp { 980 struct mbox_msghdr hdr; 981 u16 chan_bpid[NIX_MAX_BPID_CHAN]; /* Channel and bpid mapping */ 982 u8 chan_cnt; /* Number of channel for which bpids are assigned */ 983 }; 984 985 struct nix_hw_info { 986 struct mbox_msghdr hdr; 987 u16 max_mtu; 988 u16 min_mtu; 989 }; 990 991 struct nix_bandprof_alloc_req { 992 struct mbox_msghdr hdr; 993 /* Count of profiles needed per layer */ 994 u16 prof_count[BAND_PROF_NUM_LAYERS]; 995 }; 996 997 struct nix_bandprof_alloc_rsp { 998 struct mbox_msghdr hdr; 999 u16 prof_count[BAND_PROF_NUM_LAYERS]; 1000 1001 /* There is no need to allocate morethan 1 bandwidth profile 1002 * per RQ of a PF_FUNC's NIXLF. So limit the maximum 1003 * profiles to 64 per PF_FUNC. 1004 */ 1005 #define MAX_BANDPROF_PER_PFFUNC 64 1006 u16 prof_idx[BAND_PROF_NUM_LAYERS][MAX_BANDPROF_PER_PFFUNC]; 1007 }; 1008 1009 struct nix_bandprof_free_req { 1010 struct mbox_msghdr hdr; 1011 u8 free_all; 1012 u16 prof_count[BAND_PROF_NUM_LAYERS]; 1013 u16 prof_idx[BAND_PROF_NUM_LAYERS][MAX_BANDPROF_PER_PFFUNC]; 1014 }; 1015 1016 /* NPC mbox message structs */ 1017 1018 #define NPC_MCAM_ENTRY_INVALID 0xFFFF 1019 #define NPC_MCAM_INVALID_MAP 0xFFFF 1020 1021 /* NPC mailbox error codes 1022 * Range 701 - 800. 1023 */ 1024 enum npc_af_status { 1025 NPC_MCAM_INVALID_REQ = -701, 1026 NPC_MCAM_ALLOC_DENIED = -702, 1027 NPC_MCAM_ALLOC_FAILED = -703, 1028 NPC_MCAM_PERM_DENIED = -704, 1029 }; 1030 1031 struct npc_mcam_alloc_entry_req { 1032 struct mbox_msghdr hdr; 1033 #define NPC_MAX_NONCONTIG_ENTRIES 256 1034 u8 contig; /* Contiguous entries ? */ 1035 #define NPC_MCAM_ANY_PRIO 0 1036 #define NPC_MCAM_LOWER_PRIO 1 1037 #define NPC_MCAM_HIGHER_PRIO 2 1038 u8 priority; /* Lower or higher w.r.t ref_entry */ 1039 u16 ref_entry; 1040 u16 count; /* Number of entries requested */ 1041 }; 1042 1043 struct npc_mcam_alloc_entry_rsp { 1044 struct mbox_msghdr hdr; 1045 u16 entry; /* Entry allocated or start index if contiguous. 1046 * Invalid incase of non-contiguous. 1047 */ 1048 u16 count; /* Number of entries allocated */ 1049 u16 free_count; /* Number of entries available */ 1050 u16 entry_list[NPC_MAX_NONCONTIG_ENTRIES]; 1051 }; 1052 1053 struct npc_mcam_free_entry_req { 1054 struct mbox_msghdr hdr; 1055 u16 entry; /* Entry index to be freed */ 1056 u8 all; /* If all entries allocated to this PFVF to be freed */ 1057 }; 1058 1059 struct mcam_entry { 1060 #define NPC_MAX_KWS_IN_KEY 7 /* Number of keywords in max keywidth */ 1061 u64 kw[NPC_MAX_KWS_IN_KEY]; 1062 u64 kw_mask[NPC_MAX_KWS_IN_KEY]; 1063 u64 action; 1064 u64 vtag_action; 1065 }; 1066 1067 struct npc_mcam_write_entry_req { 1068 struct mbox_msghdr hdr; 1069 struct mcam_entry entry_data; 1070 u16 entry; /* MCAM entry to write this match key */ 1071 u16 cntr; /* Counter for this MCAM entry */ 1072 u8 intf; /* Rx or Tx interface */ 1073 u8 enable_entry;/* Enable this MCAM entry ? */ 1074 u8 set_cntr; /* Set counter for this entry ? */ 1075 }; 1076 1077 /* Enable/Disable a given entry */ 1078 struct npc_mcam_ena_dis_entry_req { 1079 struct mbox_msghdr hdr; 1080 u16 entry; 1081 }; 1082 1083 struct npc_mcam_shift_entry_req { 1084 struct mbox_msghdr hdr; 1085 #define NPC_MCAM_MAX_SHIFTS 64 1086 u16 curr_entry[NPC_MCAM_MAX_SHIFTS]; 1087 u16 new_entry[NPC_MCAM_MAX_SHIFTS]; 1088 u16 shift_count; /* Number of entries to shift */ 1089 }; 1090 1091 struct npc_mcam_shift_entry_rsp { 1092 struct mbox_msghdr hdr; 1093 u16 failed_entry_idx; /* Index in 'curr_entry', not entry itself */ 1094 }; 1095 1096 struct npc_mcam_alloc_counter_req { 1097 struct mbox_msghdr hdr; 1098 u8 contig; /* Contiguous counters ? */ 1099 #define NPC_MAX_NONCONTIG_COUNTERS 64 1100 u16 count; /* Number of counters requested */ 1101 }; 1102 1103 struct npc_mcam_alloc_counter_rsp { 1104 struct mbox_msghdr hdr; 1105 u16 cntr; /* Counter allocated or start index if contiguous. 1106 * Invalid incase of non-contiguous. 1107 */ 1108 u16 count; /* Number of counters allocated */ 1109 u16 cntr_list[NPC_MAX_NONCONTIG_COUNTERS]; 1110 }; 1111 1112 struct npc_mcam_oper_counter_req { 1113 struct mbox_msghdr hdr; 1114 u16 cntr; /* Free a counter or clear/fetch it's stats */ 1115 }; 1116 1117 struct npc_mcam_oper_counter_rsp { 1118 struct mbox_msghdr hdr; 1119 u64 stat; /* valid only while fetching counter's stats */ 1120 }; 1121 1122 struct npc_mcam_unmap_counter_req { 1123 struct mbox_msghdr hdr; 1124 u16 cntr; 1125 u16 entry; /* Entry and counter to be unmapped */ 1126 u8 all; /* Unmap all entries using this counter ? */ 1127 }; 1128 1129 struct npc_mcam_alloc_and_write_entry_req { 1130 struct mbox_msghdr hdr; 1131 struct mcam_entry entry_data; 1132 u16 ref_entry; 1133 u8 priority; /* Lower or higher w.r.t ref_entry */ 1134 u8 intf; /* Rx or Tx interface */ 1135 u8 enable_entry;/* Enable this MCAM entry ? */ 1136 u8 alloc_cntr; /* Allocate counter and map ? */ 1137 }; 1138 1139 struct npc_mcam_alloc_and_write_entry_rsp { 1140 struct mbox_msghdr hdr; 1141 u16 entry; 1142 u16 cntr; 1143 }; 1144 1145 struct npc_get_kex_cfg_rsp { 1146 struct mbox_msghdr hdr; 1147 u64 rx_keyx_cfg; /* NPC_AF_INTF(0)_KEX_CFG */ 1148 u64 tx_keyx_cfg; /* NPC_AF_INTF(1)_KEX_CFG */ 1149 #define NPC_MAX_INTF 2 1150 #define NPC_MAX_LID 8 1151 #define NPC_MAX_LT 16 1152 #define NPC_MAX_LD 2 1153 #define NPC_MAX_LFL 16 1154 /* NPC_AF_KEX_LDATA(0..1)_FLAGS_CFG */ 1155 u64 kex_ld_flags[NPC_MAX_LD]; 1156 /* NPC_AF_INTF(0..1)_LID(0..7)_LT(0..15)_LD(0..1)_CFG */ 1157 u64 intf_lid_lt_ld[NPC_MAX_INTF][NPC_MAX_LID][NPC_MAX_LT][NPC_MAX_LD]; 1158 /* NPC_AF_INTF(0..1)_LDATA(0..1)_FLAGS(0..15)_CFG */ 1159 u64 intf_ld_flags[NPC_MAX_INTF][NPC_MAX_LD][NPC_MAX_LFL]; 1160 #define MKEX_NAME_LEN 128 1161 u8 mkex_pfl_name[MKEX_NAME_LEN]; 1162 }; 1163 1164 struct flow_msg { 1165 unsigned char dmac[6]; 1166 unsigned char smac[6]; 1167 __be16 etype; 1168 __be16 vlan_etype; 1169 __be16 vlan_tci; 1170 union { 1171 __be32 ip4src; 1172 __be32 ip6src[4]; 1173 }; 1174 union { 1175 __be32 ip4dst; 1176 __be32 ip6dst[4]; 1177 }; 1178 u8 tos; 1179 u8 ip_ver; 1180 u8 ip_proto; 1181 u8 tc; 1182 __be16 sport; 1183 __be16 dport; 1184 }; 1185 1186 struct npc_install_flow_req { 1187 struct mbox_msghdr hdr; 1188 struct flow_msg packet; 1189 struct flow_msg mask; 1190 u64 features; 1191 u16 entry; 1192 u16 channel; 1193 u16 chan_mask; 1194 u8 intf; 1195 u8 set_cntr; /* If counter is available set counter for this entry ? */ 1196 u8 default_rule; 1197 u8 append; /* overwrite(0) or append(1) flow to default rule? */ 1198 u16 vf; 1199 /* action */ 1200 u32 index; 1201 u16 match_id; 1202 u8 flow_key_alg; 1203 u8 op; 1204 /* vtag rx action */ 1205 u8 vtag0_type; 1206 u8 vtag0_valid; 1207 u8 vtag1_type; 1208 u8 vtag1_valid; 1209 /* vtag tx action */ 1210 u16 vtag0_def; 1211 u8 vtag0_op; 1212 u16 vtag1_def; 1213 u8 vtag1_op; 1214 }; 1215 1216 struct npc_install_flow_rsp { 1217 struct mbox_msghdr hdr; 1218 int counter; /* negative if no counter else counter number */ 1219 }; 1220 1221 struct npc_delete_flow_req { 1222 struct mbox_msghdr hdr; 1223 u16 entry; 1224 u16 start;/*Disable range of entries */ 1225 u16 end; 1226 u8 all; /* PF + VFs */ 1227 }; 1228 1229 struct npc_mcam_read_entry_req { 1230 struct mbox_msghdr hdr; 1231 u16 entry; /* MCAM entry to read */ 1232 }; 1233 1234 struct npc_mcam_read_entry_rsp { 1235 struct mbox_msghdr hdr; 1236 struct mcam_entry entry_data; 1237 u8 intf; 1238 u8 enable; 1239 }; 1240 1241 struct npc_mcam_read_base_rule_rsp { 1242 struct mbox_msghdr hdr; 1243 struct mcam_entry entry; 1244 }; 1245 1246 struct npc_mcam_get_stats_req { 1247 struct mbox_msghdr hdr; 1248 u16 entry; /* mcam entry */ 1249 }; 1250 1251 struct npc_mcam_get_stats_rsp { 1252 struct mbox_msghdr hdr; 1253 u64 stat; /* counter stats */ 1254 u8 stat_ena; /* enabled */ 1255 }; 1256 1257 enum ptp_op { 1258 PTP_OP_ADJFINE = 0, 1259 PTP_OP_GET_CLOCK = 1, 1260 }; 1261 1262 struct ptp_req { 1263 struct mbox_msghdr hdr; 1264 u8 op; 1265 s64 scaled_ppm; 1266 }; 1267 1268 struct ptp_rsp { 1269 struct mbox_msghdr hdr; 1270 u64 clk; 1271 }; 1272 1273 struct set_vf_perm { 1274 struct mbox_msghdr hdr; 1275 u16 vf; 1276 #define RESET_VF_PERM BIT_ULL(0) 1277 #define VF_TRUSTED BIT_ULL(1) 1278 u64 flags; 1279 }; 1280 1281 /* CPT mailbox error codes 1282 * Range 901 - 1000. 1283 */ 1284 enum cpt_af_status { 1285 CPT_AF_ERR_PARAM = -901, 1286 CPT_AF_ERR_GRP_INVALID = -902, 1287 CPT_AF_ERR_LF_INVALID = -903, 1288 CPT_AF_ERR_ACCESS_DENIED = -904, 1289 CPT_AF_ERR_SSO_PF_FUNC_INVALID = -905, 1290 CPT_AF_ERR_NIX_PF_FUNC_INVALID = -906 1291 }; 1292 1293 /* CPT mbox message formats */ 1294 struct cpt_rd_wr_reg_msg { 1295 struct mbox_msghdr hdr; 1296 u64 reg_offset; 1297 u64 *ret_val; 1298 u64 val; 1299 u8 is_write; 1300 int blkaddr; 1301 }; 1302 1303 struct cpt_lf_alloc_req_msg { 1304 struct mbox_msghdr hdr; 1305 u16 nix_pf_func; 1306 u16 sso_pf_func; 1307 u16 eng_grpmsk; 1308 int blkaddr; 1309 }; 1310 1311 /* Mailbox message request and response format for CPT stats. */ 1312 struct cpt_sts_req { 1313 struct mbox_msghdr hdr; 1314 u8 blkaddr; 1315 }; 1316 1317 struct cpt_sts_rsp { 1318 struct mbox_msghdr hdr; 1319 u64 inst_req_pc; 1320 u64 inst_lat_pc; 1321 u64 rd_req_pc; 1322 u64 rd_lat_pc; 1323 u64 rd_uc_pc; 1324 u64 active_cycles_pc; 1325 u64 ctx_mis_pc; 1326 u64 ctx_hit_pc; 1327 u64 ctx_aop_pc; 1328 u64 ctx_aop_lat_pc; 1329 u64 ctx_ifetch_pc; 1330 u64 ctx_ifetch_lat_pc; 1331 u64 ctx_ffetch_pc; 1332 u64 ctx_ffetch_lat_pc; 1333 u64 ctx_wback_pc; 1334 u64 ctx_wback_lat_pc; 1335 u64 ctx_psh_pc; 1336 u64 ctx_psh_lat_pc; 1337 u64 ctx_err; 1338 u64 ctx_enc_id; 1339 u64 ctx_flush_timer; 1340 u64 rxc_time; 1341 u64 rxc_time_cfg; 1342 u64 rxc_active_sts; 1343 u64 rxc_zombie_sts; 1344 u64 busy_sts_ae; 1345 u64 free_sts_ae; 1346 u64 busy_sts_se; 1347 u64 free_sts_se; 1348 u64 busy_sts_ie; 1349 u64 free_sts_ie; 1350 u64 exe_err_info; 1351 u64 cptclk_cnt; 1352 u64 diag; 1353 u64 rxc_dfrg; 1354 u64 x2p_link_cfg0; 1355 u64 x2p_link_cfg1; 1356 }; 1357 1358 /* Mailbox message request format to configure reassembly timeout. */ 1359 struct cpt_rxc_time_cfg_req { 1360 struct mbox_msghdr hdr; 1361 int blkaddr; 1362 u32 step; 1363 u16 zombie_thres; 1364 u16 zombie_limit; 1365 u16 active_thres; 1366 u16 active_limit; 1367 }; 1368 1369 #endif /* MBOX_H */ 1370