xref: /openbmc/linux/drivers/net/ethernet/marvell/octeontx2/af/mbox.h (revision 05cf4fe738242183f1237f1b3a28b4479348c0a1)
1 /* SPDX-License-Identifier: GPL-2.0
2  * Marvell OcteonTx2 RVU Admin Function driver
3  *
4  * Copyright (C) 2018 Marvell International Ltd.
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License version 2 as
8  * published by the Free Software Foundation.
9  */
10 
11 #ifndef MBOX_H
12 #define MBOX_H
13 
14 #include <linux/etherdevice.h>
15 #include <linux/sizes.h>
16 
17 #include "rvu_struct.h"
18 #include "common.h"
19 
20 #define MBOX_SIZE		SZ_64K
21 
22 /* AF/PF: PF initiated, PF/VF VF initiated */
23 #define MBOX_DOWN_RX_START	0
24 #define MBOX_DOWN_RX_SIZE	(46 * SZ_1K)
25 #define MBOX_DOWN_TX_START	(MBOX_DOWN_RX_START + MBOX_DOWN_RX_SIZE)
26 #define MBOX_DOWN_TX_SIZE	(16 * SZ_1K)
27 /* AF/PF: AF initiated, PF/VF PF initiated */
28 #define MBOX_UP_RX_START	(MBOX_DOWN_TX_START + MBOX_DOWN_TX_SIZE)
29 #define MBOX_UP_RX_SIZE		SZ_1K
30 #define MBOX_UP_TX_START	(MBOX_UP_RX_START + MBOX_UP_RX_SIZE)
31 #define MBOX_UP_TX_SIZE		SZ_1K
32 
33 #if MBOX_UP_TX_SIZE + MBOX_UP_TX_START != MBOX_SIZE
34 # error "incorrect mailbox area sizes"
35 #endif
36 
37 #define INTR_MASK(pfvfs) ((pfvfs < 64) ? (BIT_ULL(pfvfs) - 1) : (~0ull))
38 
39 #define MBOX_RSP_TIMEOUT	1000 /* in ms, Time to wait for mbox response */
40 
41 #define MBOX_MSG_ALIGN		16  /* Align mbox msg start to 16bytes */
42 
43 /* Mailbox directions */
44 #define MBOX_DIR_AFPF		0  /* AF replies to PF */
45 #define MBOX_DIR_PFAF		1  /* PF sends messages to AF */
46 #define MBOX_DIR_PFVF		2  /* PF replies to VF */
47 #define MBOX_DIR_VFPF		3  /* VF sends messages to PF */
48 #define MBOX_DIR_AFPF_UP	4  /* AF sends messages to PF */
49 #define MBOX_DIR_PFAF_UP	5  /* PF replies to AF */
50 #define MBOX_DIR_PFVF_UP	6  /* PF sends messages to VF */
51 #define MBOX_DIR_VFPF_UP	7  /* VF replies to PF */
52 
53 struct otx2_mbox_dev {
54 	void	    *mbase;   /* This dev's mbox region */
55 	spinlock_t  mbox_lock;
56 	u16         msg_size; /* Total msg size to be sent */
57 	u16         rsp_size; /* Total rsp size to be sure the reply is ok */
58 	u16         num_msgs; /* No of msgs sent or waiting for response */
59 	u16         msgs_acked; /* No of msgs for which response is received */
60 };
61 
62 struct otx2_mbox {
63 	struct pci_dev *pdev;
64 	void   *hwbase;  /* Mbox region advertised by HW */
65 	void   *reg_base;/* CSR base for this dev */
66 	u64    trigger;  /* Trigger mbox notification */
67 	u16    tr_shift; /* Mbox trigger shift */
68 	u64    rx_start; /* Offset of Rx region in mbox memory */
69 	u64    tx_start; /* Offset of Tx region in mbox memory */
70 	u16    rx_size;  /* Size of Rx region */
71 	u16    tx_size;  /* Size of Tx region */
72 	u16    ndevs;    /* The number of peers */
73 	struct otx2_mbox_dev *dev;
74 };
75 
76 /* Header which preceeds all mbox messages */
77 struct mbox_hdr {
78 	u16  num_msgs;   /* No of msgs embedded */
79 };
80 
81 /* Header which preceeds every msg and is also part of it */
82 struct mbox_msghdr {
83 	u16 pcifunc;     /* Who's sending this msg */
84 	u16 id;          /* Mbox message ID */
85 #define OTX2_MBOX_REQ_SIG (0xdead)
86 #define OTX2_MBOX_RSP_SIG (0xbeef)
87 	u16 sig;         /* Signature, for validating corrupted msgs */
88 #define OTX2_MBOX_VERSION (0x0001)
89 	u16 ver;         /* Version of msg's structure for this ID */
90 	u16 next_msgoff; /* Offset of next msg within mailbox region */
91 	int rc;          /* Msg process'ed response code */
92 };
93 
94 void otx2_mbox_reset(struct otx2_mbox *mbox, int devid);
95 void otx2_mbox_destroy(struct otx2_mbox *mbox);
96 int otx2_mbox_init(struct otx2_mbox *mbox, void __force *hwbase,
97 		   struct pci_dev *pdev, void __force *reg_base,
98 		   int direction, int ndevs);
99 void otx2_mbox_msg_send(struct otx2_mbox *mbox, int devid);
100 int otx2_mbox_wait_for_rsp(struct otx2_mbox *mbox, int devid);
101 int otx2_mbox_busy_poll_for_rsp(struct otx2_mbox *mbox, int devid);
102 struct mbox_msghdr *otx2_mbox_alloc_msg_rsp(struct otx2_mbox *mbox, int devid,
103 					    int size, int size_rsp);
104 struct mbox_msghdr *otx2_mbox_get_rsp(struct otx2_mbox *mbox, int devid,
105 				      struct mbox_msghdr *msg);
106 int otx2_reply_invalid_msg(struct otx2_mbox *mbox, int devid,
107 			   u16 pcifunc, u16 id);
108 bool otx2_mbox_nonempty(struct otx2_mbox *mbox, int devid);
109 const char *otx2_mbox_id2name(u16 id);
110 static inline struct mbox_msghdr *otx2_mbox_alloc_msg(struct otx2_mbox *mbox,
111 						      int devid, int size)
112 {
113 	return otx2_mbox_alloc_msg_rsp(mbox, devid, size, 0);
114 }
115 
116 /* Mailbox message types */
117 #define MBOX_MSG_MASK				0xFFFF
118 #define MBOX_MSG_INVALID			0xFFFE
119 #define MBOX_MSG_MAX				0xFFFF
120 
121 #define MBOX_MESSAGES							\
122 /* Generic mbox IDs (range 0x000 - 0x1FF) */				\
123 M(READY,		0x001, msg_req, ready_msg_rsp)			\
124 M(ATTACH_RESOURCES,	0x002, rsrc_attach, msg_rsp)			\
125 M(DETACH_RESOURCES,	0x003, rsrc_detach, msg_rsp)			\
126 M(MSIX_OFFSET,		0x004, msg_req, msix_offset_rsp)		\
127 /* CGX mbox IDs (range 0x200 - 0x3FF) */				\
128 M(CGX_START_RXTX,	0x200, msg_req, msg_rsp)			\
129 M(CGX_STOP_RXTX,	0x201, msg_req, msg_rsp)			\
130 M(CGX_STATS,		0x202, msg_req, cgx_stats_rsp)			\
131 M(CGX_MAC_ADDR_SET,	0x203, cgx_mac_addr_set_or_get,			\
132 				cgx_mac_addr_set_or_get)		\
133 M(CGX_MAC_ADDR_GET,	0x204, cgx_mac_addr_set_or_get,			\
134 				cgx_mac_addr_set_or_get)		\
135 M(CGX_PROMISC_ENABLE,	0x205, msg_req, msg_rsp)			\
136 M(CGX_PROMISC_DISABLE,	0x206, msg_req, msg_rsp)			\
137 M(CGX_START_LINKEVENTS, 0x207, msg_req, msg_rsp)			\
138 M(CGX_STOP_LINKEVENTS,	0x208, msg_req, msg_rsp)			\
139 M(CGX_GET_LINKINFO,	0x209, msg_req, cgx_link_info_msg)		\
140 M(CGX_INTLBK_ENABLE,	0x20A, msg_req, msg_rsp)			\
141 M(CGX_INTLBK_DISABLE,	0x20B, msg_req, msg_rsp)			\
142 /* NPA mbox IDs (range 0x400 - 0x5FF) */				\
143 M(NPA_LF_ALLOC,		0x400, npa_lf_alloc_req, npa_lf_alloc_rsp)	\
144 M(NPA_LF_FREE,		0x401, msg_req, msg_rsp)			\
145 M(NPA_AQ_ENQ,		0x402, npa_aq_enq_req, npa_aq_enq_rsp)		\
146 M(NPA_HWCTX_DISABLE,	0x403, hwctx_disable_req, msg_rsp)		\
147 /* SSO/SSOW mbox IDs (range 0x600 - 0x7FF) */				\
148 /* TIM mbox IDs (range 0x800 - 0x9FF) */				\
149 /* CPT mbox IDs (range 0xA00 - 0xBFF) */				\
150 /* NPC mbox IDs (range 0x6000 - 0x7FFF) */				\
151 /* NIX mbox IDs (range 0x8000 - 0xFFFF) */				\
152 M(NIX_LF_ALLOC,		0x8000, nix_lf_alloc_req, nix_lf_alloc_rsp)	\
153 M(NIX_LF_FREE,		0x8001, msg_req, msg_rsp)			\
154 M(NIX_AQ_ENQ,		0x8002, nix_aq_enq_req, nix_aq_enq_rsp)		\
155 M(NIX_HWCTX_DISABLE,	0x8003, hwctx_disable_req, msg_rsp)		\
156 M(NIX_TXSCH_ALLOC,	0x8004, nix_txsch_alloc_req, nix_txsch_alloc_rsp) \
157 M(NIX_TXSCH_FREE,	0x8005, nix_txsch_free_req, msg_rsp)		\
158 M(NIX_TXSCHQ_CFG,	0x8006, nix_txschq_config, msg_rsp)		\
159 M(NIX_STATS_RST,	0x8007, msg_req, msg_rsp)			\
160 M(NIX_VTAG_CFG,	0x8008, nix_vtag_config, msg_rsp)		\
161 M(NIX_RSS_FLOWKEY_CFG,  0x8009, nix_rss_flowkey_cfg, msg_rsp)		\
162 M(NIX_SET_MAC_ADDR,	0x800a, nix_set_mac_addr, msg_rsp)		\
163 M(NIX_SET_RX_MODE,	0x800b, nix_rx_mode, msg_rsp)
164 
165 /* Messages initiated by AF (range 0xC00 - 0xDFF) */
166 #define MBOX_UP_CGX_MESSAGES						\
167 M(CGX_LINK_EVENT,		0xC00, cgx_link_info_msg, msg_rsp)
168 
169 enum {
170 #define M(_name, _id, _1, _2) MBOX_MSG_ ## _name = _id,
171 MBOX_MESSAGES
172 MBOX_UP_CGX_MESSAGES
173 #undef M
174 };
175 
176 /* Mailbox message formats */
177 
178 #define RVU_DEFAULT_PF_FUNC     0xFFFF
179 
180 /* Generic request msg used for those mbox messages which
181  * don't send any data in the request.
182  */
183 struct msg_req {
184 	struct mbox_msghdr hdr;
185 };
186 
187 /* Generic rsponse msg used a ack or response for those mbox
188  * messages which doesn't have a specific rsp msg format.
189  */
190 struct msg_rsp {
191 	struct mbox_msghdr hdr;
192 };
193 
194 struct ready_msg_rsp {
195 	struct mbox_msghdr hdr;
196 	u16    sclk_feq;	/* SCLK frequency */
197 };
198 
199 /* Structure for requesting resource provisioning.
200  * 'modify' flag to be used when either requesting more
201  * or to detach partial of a cetain resource type.
202  * Rest of the fields specify how many of what type to
203  * be attached.
204  */
205 struct rsrc_attach {
206 	struct mbox_msghdr hdr;
207 	u8   modify:1;
208 	u8   npalf:1;
209 	u8   nixlf:1;
210 	u16  sso;
211 	u16  ssow;
212 	u16  timlfs;
213 	u16  cptlfs;
214 };
215 
216 /* Structure for relinquishing resources.
217  * 'partial' flag to be used when relinquishing all resources
218  * but only of a certain type. If not set, all resources of all
219  * types provisioned to the RVU function will be detached.
220  */
221 struct rsrc_detach {
222 	struct mbox_msghdr hdr;
223 	u8 partial:1;
224 	u8 npalf:1;
225 	u8 nixlf:1;
226 	u8 sso:1;
227 	u8 ssow:1;
228 	u8 timlfs:1;
229 	u8 cptlfs:1;
230 };
231 
232 #define MSIX_VECTOR_INVALID	0xFFFF
233 #define MAX_RVU_BLKLF_CNT	256
234 
235 struct msix_offset_rsp {
236 	struct mbox_msghdr hdr;
237 	u16  npa_msixoff;
238 	u16  nix_msixoff;
239 	u8   sso;
240 	u8   ssow;
241 	u8   timlfs;
242 	u8   cptlfs;
243 	u16  sso_msixoff[MAX_RVU_BLKLF_CNT];
244 	u16  ssow_msixoff[MAX_RVU_BLKLF_CNT];
245 	u16  timlf_msixoff[MAX_RVU_BLKLF_CNT];
246 	u16  cptlf_msixoff[MAX_RVU_BLKLF_CNT];
247 };
248 
249 /* CGX mbox message formats */
250 
251 struct cgx_stats_rsp {
252 	struct mbox_msghdr hdr;
253 #define CGX_RX_STATS_COUNT	13
254 #define CGX_TX_STATS_COUNT	18
255 	u64 rx_stats[CGX_RX_STATS_COUNT];
256 	u64 tx_stats[CGX_TX_STATS_COUNT];
257 };
258 
259 /* Structure for requesting the operation for
260  * setting/getting mac address in the CGX interface
261  */
262 struct cgx_mac_addr_set_or_get {
263 	struct mbox_msghdr hdr;
264 	u8 mac_addr[ETH_ALEN];
265 };
266 
267 struct cgx_link_user_info {
268 	uint64_t link_up:1;
269 	uint64_t full_duplex:1;
270 	uint64_t lmac_type_id:4;
271 	uint64_t speed:20; /* speed in Mbps */
272 #define LMACTYPE_STR_LEN 16
273 	char lmac_type[LMACTYPE_STR_LEN];
274 };
275 
276 struct cgx_link_info_msg {
277 	struct mbox_msghdr hdr;
278 	struct cgx_link_user_info link_info;
279 };
280 
281 /* NPA mbox message formats */
282 
283 /* NPA mailbox error codes
284  * Range 301 - 400.
285  */
286 enum npa_af_status {
287 	NPA_AF_ERR_PARAM            = -301,
288 	NPA_AF_ERR_AQ_FULL          = -302,
289 	NPA_AF_ERR_AQ_ENQUEUE       = -303,
290 	NPA_AF_ERR_AF_LF_INVALID    = -304,
291 	NPA_AF_ERR_AF_LF_ALLOC      = -305,
292 	NPA_AF_ERR_LF_RESET         = -306,
293 };
294 
295 /* For NPA LF context alloc and init */
296 struct npa_lf_alloc_req {
297 	struct mbox_msghdr hdr;
298 	int node;
299 	int aura_sz;  /* No of auras */
300 	u32 nr_pools; /* No of pools */
301 };
302 
303 struct npa_lf_alloc_rsp {
304 	struct mbox_msghdr hdr;
305 	u32 stack_pg_ptrs;  /* No of ptrs per stack page */
306 	u32 stack_pg_bytes; /* Size of stack page */
307 	u16 qints; /* NPA_AF_CONST::QINTS */
308 };
309 
310 /* NPA AQ enqueue msg */
311 struct npa_aq_enq_req {
312 	struct mbox_msghdr hdr;
313 	u32 aura_id;
314 	u8 ctype;
315 	u8 op;
316 	union {
317 		/* Valid when op == WRITE/INIT and ctype == AURA.
318 		 * LF fills the pool_id in aura.pool_addr. AF will translate
319 		 * the pool_id to pool context pointer.
320 		 */
321 		struct npa_aura_s aura;
322 		/* Valid when op == WRITE/INIT and ctype == POOL */
323 		struct npa_pool_s pool;
324 	};
325 	/* Mask data when op == WRITE (1=write, 0=don't write) */
326 	union {
327 		/* Valid when op == WRITE and ctype == AURA */
328 		struct npa_aura_s aura_mask;
329 		/* Valid when op == WRITE and ctype == POOL */
330 		struct npa_pool_s pool_mask;
331 	};
332 };
333 
334 struct npa_aq_enq_rsp {
335 	struct mbox_msghdr hdr;
336 	union {
337 		/* Valid when op == READ and ctype == AURA */
338 		struct npa_aura_s aura;
339 		/* Valid when op == READ and ctype == POOL */
340 		struct npa_pool_s pool;
341 	};
342 };
343 
344 /* Disable all contexts of type 'ctype' */
345 struct hwctx_disable_req {
346 	struct mbox_msghdr hdr;
347 	u8 ctype;
348 };
349 
350 /* NIX mailbox error codes
351  * Range 401 - 500.
352  */
353 enum nix_af_status {
354 	NIX_AF_ERR_PARAM            = -401,
355 	NIX_AF_ERR_AQ_FULL          = -402,
356 	NIX_AF_ERR_AQ_ENQUEUE       = -403,
357 	NIX_AF_ERR_AF_LF_INVALID    = -404,
358 	NIX_AF_ERR_AF_LF_ALLOC      = -405,
359 	NIX_AF_ERR_TLX_ALLOC_FAIL   = -406,
360 	NIX_AF_ERR_TLX_INVALID      = -407,
361 	NIX_AF_ERR_RSS_SIZE_INVALID = -408,
362 	NIX_AF_ERR_RSS_GRPS_INVALID = -409,
363 	NIX_AF_ERR_FRS_INVALID      = -410,
364 	NIX_AF_ERR_RX_LINK_INVALID  = -411,
365 	NIX_AF_INVAL_TXSCHQ_CFG     = -412,
366 	NIX_AF_SMQ_FLUSH_FAILED     = -413,
367 	NIX_AF_ERR_LF_RESET         = -414,
368 };
369 
370 /* For NIX LF context alloc and init */
371 struct nix_lf_alloc_req {
372 	struct mbox_msghdr hdr;
373 	int node;
374 	u32 rq_cnt;   /* No of receive queues */
375 	u32 sq_cnt;   /* No of send queues */
376 	u32 cq_cnt;   /* No of completion queues */
377 	u8  xqe_sz;
378 	u16 rss_sz;
379 	u8  rss_grps;
380 	u16 npa_func;
381 	u16 sso_func;
382 	u64 rx_cfg;   /* See NIX_AF_LF(0..127)_RX_CFG */
383 };
384 
385 struct nix_lf_alloc_rsp {
386 	struct mbox_msghdr hdr;
387 	u16	sqb_size;
388 	u16	rx_chan_base;
389 	u16	tx_chan_base;
390 	u8      rx_chan_cnt; /* total number of RX channels */
391 	u8      tx_chan_cnt; /* total number of TX channels */
392 	u8	lso_tsov4_idx;
393 	u8	lso_tsov6_idx;
394 	u8      mac_addr[ETH_ALEN];
395 };
396 
397 /* NIX AQ enqueue msg */
398 struct nix_aq_enq_req {
399 	struct mbox_msghdr hdr;
400 	u32  qidx;
401 	u8 ctype;
402 	u8 op;
403 	union {
404 		struct nix_rq_ctx_s rq;
405 		struct nix_sq_ctx_s sq;
406 		struct nix_cq_ctx_s cq;
407 		struct nix_rsse_s   rss;
408 		struct nix_rx_mce_s mce;
409 	};
410 	union {
411 		struct nix_rq_ctx_s rq_mask;
412 		struct nix_sq_ctx_s sq_mask;
413 		struct nix_cq_ctx_s cq_mask;
414 		struct nix_rsse_s   rss_mask;
415 		struct nix_rx_mce_s mce_mask;
416 	};
417 };
418 
419 struct nix_aq_enq_rsp {
420 	struct mbox_msghdr hdr;
421 	union {
422 		struct nix_rq_ctx_s rq;
423 		struct nix_sq_ctx_s sq;
424 		struct nix_cq_ctx_s cq;
425 		struct nix_rsse_s   rss;
426 		struct nix_rx_mce_s mce;
427 	};
428 };
429 
430 /* Tx scheduler/shaper mailbox messages */
431 
432 #define MAX_TXSCHQ_PER_FUNC		128
433 
434 struct nix_txsch_alloc_req {
435 	struct mbox_msghdr hdr;
436 	/* Scheduler queue count request at each level */
437 	u16 schq_contig[NIX_TXSCH_LVL_CNT]; /* No of contiguous queues */
438 	u16 schq[NIX_TXSCH_LVL_CNT]; /* No of non-contiguous queues */
439 };
440 
441 struct nix_txsch_alloc_rsp {
442 	struct mbox_msghdr hdr;
443 	/* Scheduler queue count allocated at each level */
444 	u16 schq_contig[NIX_TXSCH_LVL_CNT];
445 	u16 schq[NIX_TXSCH_LVL_CNT];
446 	/* Scheduler queue list allocated at each level */
447 	u16 schq_contig_list[NIX_TXSCH_LVL_CNT][MAX_TXSCHQ_PER_FUNC];
448 	u16 schq_list[NIX_TXSCH_LVL_CNT][MAX_TXSCHQ_PER_FUNC];
449 };
450 
451 struct nix_txsch_free_req {
452 	struct mbox_msghdr hdr;
453 #define TXSCHQ_FREE_ALL BIT_ULL(0)
454 	u16 flags;
455 	/* Scheduler queue level to be freed */
456 	u16 schq_lvl;
457 	/* List of scheduler queues to be freed */
458 	u16 schq;
459 };
460 
461 struct nix_txschq_config {
462 	struct mbox_msghdr hdr;
463 	u8 lvl;	/* SMQ/MDQ/TL4/TL3/TL2/TL1 */
464 #define TXSCHQ_IDX_SHIFT	16
465 #define TXSCHQ_IDX_MASK		(BIT_ULL(10) - 1)
466 #define TXSCHQ_IDX(reg, shift)	(((reg) >> (shift)) & TXSCHQ_IDX_MASK)
467 	u8 num_regs;
468 #define MAX_REGS_PER_MBOX_MSG	20
469 	u64 reg[MAX_REGS_PER_MBOX_MSG];
470 	u64 regval[MAX_REGS_PER_MBOX_MSG];
471 };
472 
473 struct nix_vtag_config {
474 	struct mbox_msghdr hdr;
475 	u8 vtag_size;
476 	/* cfg_type is '0' for tx vlan cfg
477 	 * cfg_type is '1' for rx vlan cfg
478 	 */
479 	u8 cfg_type;
480 	union {
481 		/* valid when cfg_type is '0' */
482 		struct {
483 			/* tx vlan0 tag(C-VLAN) */
484 			u64 vlan0;
485 			/* tx vlan1 tag(S-VLAN) */
486 			u64 vlan1;
487 			/* insert tx vlan tag */
488 			u8 insert_vlan :1;
489 			/* insert tx double vlan tag */
490 			u8 double_vlan :1;
491 		} tx;
492 
493 		/* valid when cfg_type is '1' */
494 		struct {
495 			/* rx vtag type index */
496 			u8 vtag_type;
497 			/* rx vtag strip */
498 			u8 strip_vtag :1;
499 			/* rx vtag capture */
500 			u8 capture_vtag :1;
501 		} rx;
502 	};
503 };
504 
505 struct nix_rss_flowkey_cfg {
506 	struct mbox_msghdr hdr;
507 	int	mcam_index;  /* MCAM entry index to modify */
508 	u32	flowkey_cfg; /* Flowkey types selected */
509 	u8	group;       /* RSS context or group */
510 };
511 
512 struct nix_set_mac_addr {
513 	struct mbox_msghdr hdr;
514 	u8 mac_addr[ETH_ALEN]; /* MAC address to be set for this pcifunc */
515 };
516 
517 struct nix_rx_mode {
518 	struct mbox_msghdr hdr;
519 #define NIX_RX_MODE_UCAST	BIT(0)
520 #define NIX_RX_MODE_PROMISC	BIT(1)
521 #define NIX_RX_MODE_ALLMULTI	BIT(2)
522 	u16	mode;
523 };
524 
525 #endif /* MBOX_H */
526