1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Marvell CN10K RPM driver 3 * 4 * Copyright (C) 2020 Marvell. 5 * 6 */ 7 8 #ifndef LMAC_COMMON_H 9 #define LMAC_COMMON_H 10 11 #include "rvu.h" 12 #include "cgx.h" 13 /** 14 * struct lmac - per lmac locks and properties 15 * @wq_cmd_cmplt: waitq to keep the process blocked until cmd completion 16 * @cmd_lock: Lock to serialize the command interface 17 * @resp: command response 18 * @link_info: link related information 19 * @mac_to_index_bmap: Mac address to CGX table index mapping 20 * @rx_fc_pfvf_bmap: Receive flow control enabled netdev mapping 21 * @tx_fc_pfvf_bmap: Transmit flow control enabled netdev mapping 22 * @event_cb: callback for linkchange events 23 * @event_cb_lock: lock for serializing callback with unregister 24 * @cgx: parent cgx port 25 * @mcast_filters_count: Number of multicast filters installed 26 * @lmac_id: lmac port id 27 * @cmd_pend: flag set before new command is started 28 * flag cleared after command response is received 29 * @name: lmac port name 30 */ 31 struct lmac { 32 wait_queue_head_t wq_cmd_cmplt; 33 /* Lock to serialize the command interface */ 34 struct mutex cmd_lock; 35 u64 resp; 36 struct cgx_link_user_info link_info; 37 struct rsrc_bmap mac_to_index_bmap; 38 struct rsrc_bmap rx_fc_pfvf_bmap; 39 struct rsrc_bmap tx_fc_pfvf_bmap; 40 struct cgx_event_cb event_cb; 41 /* lock for serializing callback with unregister */ 42 spinlock_t event_cb_lock; 43 struct cgx *cgx; 44 u8 mcast_filters_count; 45 u8 lmac_id; 46 bool cmd_pend; 47 char *name; 48 }; 49 50 /* CGX & RPM has different feature set 51 * update the structure fields with different one 52 */ 53 struct mac_ops { 54 char *name; 55 /* Features like RXSTAT, TXSTAT, DMAC FILTER csrs differs by fixed 56 * bar offset for example 57 * CGX DMAC_CTL0 0x1f8 58 * RPM DMAC_CTL0 0x4ff8 59 */ 60 u64 csr_offset; 61 /* For ATF to send events to kernel, there is no dedicated interrupt 62 * defined hence CGX uses OVERFLOW bit in CMR_INT. RPM block supports 63 * SW_INT so that ATF triggers this interrupt after processing of 64 * requested command 65 */ 66 u64 int_register; 67 u64 int_set_reg; 68 /* lmac offset is different is RPM */ 69 u8 lmac_offset; 70 u8 irq_offset; 71 u8 int_ena_bit; 72 u8 lmac_fwi; 73 u32 fifo_len; 74 bool non_contiguous_serdes_lane; 75 /* RPM & CGX differs in number of Receive/transmit stats */ 76 u8 rx_stats_cnt; 77 u8 tx_stats_cnt; 78 /* Unlike CN10K which shares same CSR offset with CGX 79 * CNF10KB has different csr offset 80 */ 81 u64 rxid_map_offset; 82 u8 dmac_filter_count; 83 /* Incase of RPM get number of lmacs from RPMX_CMR_RX_LMACS[LMAC_EXIST] 84 * number of setbits in lmac_exist tells number of lmacs 85 */ 86 int (*get_nr_lmacs)(void *cgx); 87 u8 (*get_lmac_type)(void *cgx, int lmac_id); 88 u32 (*lmac_fifo_len)(void *cgx, int lmac_id); 89 int (*mac_lmac_intl_lbk)(void *cgx, int lmac_id, 90 bool enable); 91 /* Register Stats related functions */ 92 int (*mac_get_rx_stats)(void *cgx, int lmac_id, 93 int idx, u64 *rx_stat); 94 int (*mac_get_tx_stats)(void *cgx, int lmac_id, 95 int idx, u64 *tx_stat); 96 97 /* Enable LMAC Pause Frame Configuration */ 98 void (*mac_enadis_rx_pause_fwding)(void *cgxd, 99 int lmac_id, 100 bool enable); 101 102 int (*mac_get_pause_frm_status)(void *cgxd, 103 int lmac_id, 104 u8 *tx_pause, 105 u8 *rx_pause); 106 107 int (*mac_enadis_pause_frm)(void *cgxd, 108 int lmac_id, 109 u8 tx_pause, 110 u8 rx_pause); 111 112 void (*mac_pause_frm_config)(void *cgxd, 113 int lmac_id, 114 bool enable); 115 116 /* Enable/Disable Inbound PTP */ 117 void (*mac_enadis_ptp_config)(void *cgxd, 118 int lmac_id, 119 bool enable); 120 121 int (*mac_rx_tx_enable)(void *cgxd, int lmac_id, bool enable); 122 int (*mac_tx_enable)(void *cgxd, int lmac_id, bool enable); 123 int (*pfc_config)(void *cgxd, int lmac_id, 124 u8 tx_pause, u8 rx_pause, u16 pfc_en); 125 126 int (*mac_get_pfc_frm_cfg)(void *cgxd, int lmac_id, 127 u8 *tx_pause, u8 *rx_pause); 128 129 /* FEC stats */ 130 int (*get_fec_stats)(void *cgxd, int lmac_id, 131 struct cgx_fec_stats_rsp *rsp); 132 }; 133 134 struct cgx { 135 void __iomem *reg_base; 136 struct pci_dev *pdev; 137 u8 cgx_id; 138 u8 lmac_count; 139 /* number of LMACs per MAC could be 4 or 8 */ 140 u8 max_lmac_per_mac; 141 #define MAX_LMAC_COUNT 8 142 struct lmac *lmac_idmap[MAX_LMAC_COUNT]; 143 struct work_struct cgx_cmd_work; 144 struct workqueue_struct *cgx_cmd_workq; 145 struct list_head cgx_list; 146 u64 hw_features; 147 struct mac_ops *mac_ops; 148 unsigned long lmac_bmap; /* bitmap of enabled lmacs */ 149 /* Lock to serialize read/write of global csrs like 150 * RPMX_MTI_STAT_DATA_HI_CDC etc 151 */ 152 struct mutex lock; 153 }; 154 155 typedef struct cgx rpm_t; 156 157 /* Function Declarations */ 158 void cgx_write(struct cgx *cgx, u64 lmac, u64 offset, u64 val); 159 u64 cgx_read(struct cgx *cgx, u64 lmac, u64 offset); 160 struct lmac *lmac_pdata(u8 lmac_id, struct cgx *cgx); 161 int cgx_fwi_cmd_send(u64 req, u64 *resp, struct lmac *lmac); 162 int cgx_fwi_cmd_generic(u64 req, u64 *resp, struct cgx *cgx, int lmac_id); 163 bool is_lmac_valid(struct cgx *cgx, int lmac_id); 164 struct mac_ops *rpm_get_mac_ops(struct cgx *cgx); 165 166 #endif /* LMAC_COMMON_H */ 167