1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Marvell OcteonTx2 RVU Admin Function driver 3 * 4 * Copyright (C) 2018 Marvell International Ltd. 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 */ 10 11 #ifndef COMMON_H 12 #define COMMON_H 13 14 #include "rvu_struct.h" 15 16 #define OTX2_ALIGN 128 /* Align to cacheline */ 17 18 #define Q_SIZE_16 0ULL /* 16 entries */ 19 #define Q_SIZE_64 1ULL /* 64 entries */ 20 #define Q_SIZE_256 2ULL 21 #define Q_SIZE_1K 3ULL 22 #define Q_SIZE_4K 4ULL 23 #define Q_SIZE_16K 5ULL 24 #define Q_SIZE_64K 6ULL 25 #define Q_SIZE_256K 7ULL 26 #define Q_SIZE_1M 8ULL /* Million entries */ 27 #define Q_SIZE_MIN Q_SIZE_16 28 #define Q_SIZE_MAX Q_SIZE_1M 29 30 #define Q_COUNT(x) (16ULL << (2 * x)) 31 #define Q_SIZE(x, n) ((ilog2(x) - (n)) / 2) 32 33 /* Admin queue info */ 34 35 /* Since we intend to add only one instruction at a time, 36 * keep queue size to it's minimum. 37 */ 38 #define AQ_SIZE Q_SIZE_16 39 /* HW head & tail pointer mask */ 40 #define AQ_PTR_MASK 0xFFFFF 41 42 struct qmem { 43 void *base; 44 dma_addr_t iova; 45 int alloc_sz; 46 u16 entry_sz; 47 u8 align; 48 u32 qsize; 49 }; 50 51 static inline int qmem_alloc(struct device *dev, struct qmem **q, 52 int qsize, int entry_sz) 53 { 54 struct qmem *qmem; 55 int aligned_addr; 56 57 if (!qsize) 58 return -EINVAL; 59 60 *q = devm_kzalloc(dev, sizeof(*qmem), GFP_KERNEL); 61 if (!*q) 62 return -ENOMEM; 63 qmem = *q; 64 65 qmem->entry_sz = entry_sz; 66 qmem->alloc_sz = (qsize * entry_sz) + OTX2_ALIGN; 67 qmem->base = dma_alloc_attrs(dev, qmem->alloc_sz, &qmem->iova, 68 GFP_KERNEL, DMA_ATTR_FORCE_CONTIGUOUS); 69 if (!qmem->base) 70 return -ENOMEM; 71 72 qmem->qsize = qsize; 73 74 aligned_addr = ALIGN((u64)qmem->iova, OTX2_ALIGN); 75 qmem->align = (aligned_addr - qmem->iova); 76 qmem->base += qmem->align; 77 qmem->iova += qmem->align; 78 return 0; 79 } 80 81 static inline void qmem_free(struct device *dev, struct qmem *qmem) 82 { 83 if (!qmem) 84 return; 85 86 if (qmem->base) 87 dma_free_attrs(dev, qmem->alloc_sz, 88 qmem->base - qmem->align, 89 qmem->iova - qmem->align, 90 DMA_ATTR_FORCE_CONTIGUOUS); 91 devm_kfree(dev, qmem); 92 } 93 94 struct admin_queue { 95 struct qmem *inst; 96 struct qmem *res; 97 spinlock_t lock; /* Serialize inst enqueue from PFs */ 98 }; 99 100 /* NPA aura count */ 101 enum npa_aura_sz { 102 NPA_AURA_SZ_0, 103 NPA_AURA_SZ_128, 104 NPA_AURA_SZ_256, 105 NPA_AURA_SZ_512, 106 NPA_AURA_SZ_1K, 107 NPA_AURA_SZ_2K, 108 NPA_AURA_SZ_4K, 109 NPA_AURA_SZ_8K, 110 NPA_AURA_SZ_16K, 111 NPA_AURA_SZ_32K, 112 NPA_AURA_SZ_64K, 113 NPA_AURA_SZ_128K, 114 NPA_AURA_SZ_256K, 115 NPA_AURA_SZ_512K, 116 NPA_AURA_SZ_1M, 117 NPA_AURA_SZ_MAX, 118 }; 119 120 #define NPA_AURA_COUNT(x) (1ULL << ((x) + 6)) 121 122 /* NPA AQ result structure for init/read/write of aura HW contexts */ 123 struct npa_aq_aura_res { 124 struct npa_aq_res_s res; 125 struct npa_aura_s aura_ctx; 126 struct npa_aura_s ctx_mask; 127 }; 128 129 /* NPA AQ result structure for init/read/write of pool HW contexts */ 130 struct npa_aq_pool_res { 131 struct npa_aq_res_s res; 132 struct npa_pool_s pool_ctx; 133 struct npa_pool_s ctx_mask; 134 }; 135 136 /* NIX Transmit schedulers */ 137 enum nix_scheduler { 138 NIX_TXSCH_LVL_SMQ = 0x0, 139 NIX_TXSCH_LVL_MDQ = 0x0, 140 NIX_TXSCH_LVL_TL4 = 0x1, 141 NIX_TXSCH_LVL_TL3 = 0x2, 142 NIX_TXSCH_LVL_TL2 = 0x3, 143 NIX_TXSCH_LVL_TL1 = 0x4, 144 NIX_TXSCH_LVL_CNT = 0x5, 145 }; 146 147 #define TXSCH_RR_QTM_MAX ((1 << 24) - 1) 148 #define TXSCH_TL1_DFLT_RR_QTM TXSCH_RR_QTM_MAX 149 #define TXSCH_TL1_DFLT_RR_PRIO (0x1ull) 150 #define CN10K_MAX_DWRR_WEIGHT 16384 /* Weight is 14bit on CN10K */ 151 152 /* Min/Max packet sizes, excluding FCS */ 153 #define NIC_HW_MIN_FRS 40 154 #define NIC_HW_MAX_FRS 9212 155 #define SDP_HW_MAX_FRS 65535 156 #define CN10K_LMAC_LINK_MAX_FRS 16380 /* 16k - FCS */ 157 #define CN10K_LBK_LINK_MAX_FRS 65535 /* 64k */ 158 159 /* NIX RX action operation*/ 160 #define NIX_RX_ACTIONOP_DROP (0x0ull) 161 #define NIX_RX_ACTIONOP_UCAST (0x1ull) 162 #define NIX_RX_ACTIONOP_UCAST_IPSEC (0x2ull) 163 #define NIX_RX_ACTIONOP_MCAST (0x3ull) 164 #define NIX_RX_ACTIONOP_RSS (0x4ull) 165 /* Use the RX action set in the default unicast entry */ 166 #define NIX_RX_ACTION_DEFAULT (0xfull) 167 168 /* NIX TX action operation*/ 169 #define NIX_TX_ACTIONOP_DROP (0x0ull) 170 #define NIX_TX_ACTIONOP_UCAST_DEFAULT (0x1ull) 171 #define NIX_TX_ACTIONOP_UCAST_CHAN (0x2ull) 172 #define NIX_TX_ACTIONOP_MCAST (0x3ull) 173 #define NIX_TX_ACTIONOP_DROP_VIOL (0x5ull) 174 175 #define NPC_MCAM_KEY_X1 0 176 #define NPC_MCAM_KEY_X2 1 177 #define NPC_MCAM_KEY_X4 2 178 179 #define NIX_INTFX_RX(a) (0x0ull | (a) << 1) 180 #define NIX_INTFX_TX(a) (0x1ull | (a) << 1) 181 182 /* Default interfaces are NIX0_RX and NIX0_TX */ 183 #define NIX_INTF_RX NIX_INTFX_RX(0) 184 #define NIX_INTF_TX NIX_INTFX_TX(0) 185 186 #define NIX_INTF_TYPE_CGX 0 187 #define NIX_INTF_TYPE_LBK 1 188 #define NIX_INTF_TYPE_SDP 2 189 190 #define MAX_LMAC_PKIND 12 191 #define NIX_LINK_CGX_LMAC(a, b) (0 + 4 * (a) + (b)) 192 #define NIX_LINK_LBK(a) (12 + (a)) 193 #define NIX_CHAN_CGX_LMAC_CHX(a, b, c) (0x800 + 0x100 * (a) + 0x10 * (b) + (c)) 194 #define NIX_CHAN_LBK_CHX(a, b) (0 + 0x100 * (a) + (b)) 195 #define NIX_CHAN_SDP_CH_START (0x700ull) 196 #define NIX_CHAN_SDP_CHX(a) (NIX_CHAN_SDP_CH_START + (a)) 197 #define NIX_CHAN_SDP_NUM_CHANS 256 198 199 /* The mask is to extract lower 10-bits of channel number 200 * which CPT will pass to X2P. 201 */ 202 #define NIX_CHAN_CPT_X2P_MASK (0x3ffull) 203 204 /* NIX LSO format indices. 205 * As of now TSO is the only one using, so statically assigning indices. 206 */ 207 #define NIX_LSO_FORMAT_IDX_TSOV4 0 208 #define NIX_LSO_FORMAT_IDX_TSOV6 1 209 210 /* RSS info */ 211 #define MAX_RSS_GROUPS 8 212 /* Group 0 has to be used in default pkt forwarding MCAM entries 213 * reserved for NIXLFs. Groups 1-7 can be used for RSS for ntuple 214 * filters. 215 */ 216 #define DEFAULT_RSS_CONTEXT_GROUP 0 217 #define MAX_RSS_INDIR_TBL_SIZE 256 /* 1 << Max adder bits */ 218 219 /* NDC info */ 220 enum ndc_idx_e { 221 NIX0_RX = 0x0, 222 NIX0_TX = 0x1, 223 NPA0_U = 0x2, 224 NIX1_RX = 0x4, 225 NIX1_TX = 0x5, 226 }; 227 228 enum ndc_ctype_e { 229 CACHING = 0x0, 230 BYPASS = 0x1, 231 }; 232 233 #define NDC_MAX_PORT 6 234 #define NDC_READ_TRANS 0 235 #define NDC_WRITE_TRANS 1 236 237 #endif /* COMMON_H */ 238