1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Marvell OcteonTx2 CGX driver
3  *
4  * Copyright (C) 2018 Marvell.
5  *
6  */
7 
8 #ifndef CGX_H
9 #define CGX_H
10 
11 #include "mbox.h"
12 #include "cgx_fw_if.h"
13 #include "rpm.h"
14 
15  /* PCI device IDs */
16 #define	PCI_DEVID_OCTEONTX2_CGX		0xA059
17 
18 /* PCI BAR nos */
19 #define PCI_CFG_REG_BAR_NUM		0
20 
21 #define CGX_ID_MASK			0x7
22 #define MAX_LMAC_PER_CGX		4
23 #define MAX_DMAC_ENTRIES_PER_CGX	32
24 #define CGX_FIFO_LEN			65536 /* 64K for both Rx & Tx */
25 #define CGX_OFFSET(x)			((x) * MAX_LMAC_PER_CGX)
26 
27 /* Registers */
28 #define CGXX_CMRX_CFG			0x00
29 #define CMR_P2X_SEL_MASK		GENMASK_ULL(61, 59)
30 #define CMR_P2X_SEL_SHIFT		59ULL
31 #define CMR_P2X_SEL_NIX0		1ULL
32 #define CMR_P2X_SEL_NIX1		2ULL
33 #define CMR_EN				BIT_ULL(55)
34 #define DATA_PKT_TX_EN			BIT_ULL(53)
35 #define DATA_PKT_RX_EN			BIT_ULL(54)
36 #define CGX_LMAC_TYPE_SHIFT		40
37 #define CGX_LMAC_TYPE_MASK		0xF
38 #define CGXX_CMRX_INT			0x040
39 #define FW_CGX_INT			BIT_ULL(1)
40 #define CGXX_CMRX_INT_ENA_W1S		0x058
41 #define CGXX_CMRX_RX_ID_MAP		0x060
42 #define CGXX_CMRX_RX_STAT0		0x070
43 #define CGXX_CMRX_RX_LMACS		0x128
44 #define CGXX_CMRX_RX_DMAC_CTL0		(0x1F8 + mac_ops->csr_offset)
45 #define CGX_DMAC_CTL0_CAM_ENABLE	BIT_ULL(3)
46 #define CGX_DMAC_CAM_ACCEPT		BIT_ULL(3)
47 #define CGX_DMAC_MCAST_MODE_CAM		BIT_ULL(2)
48 #define CGX_DMAC_MCAST_MODE		BIT_ULL(1)
49 #define CGX_DMAC_BCAST_MODE		BIT_ULL(0)
50 #define CGXX_CMRX_RX_DMAC_CAM0		(0x200 + mac_ops->csr_offset)
51 #define CGX_DMAC_CAM_ADDR_ENABLE	BIT_ULL(48)
52 #define CGX_DMAC_CAM_ENTRY_LMACID	GENMASK_ULL(50, 49)
53 #define CGXX_CMRX_RX_DMAC_CAM1		0x400
54 #define CGX_RX_DMAC_ADR_MASK		GENMASK_ULL(47, 0)
55 #define CGXX_CMRX_TX_STAT0		0x700
56 #define CGXX_SCRATCH0_REG		0x1050
57 #define CGXX_SCRATCH1_REG		0x1058
58 #define CGX_CONST			0x2000
59 #define CGX_CONST_RXFIFO_SIZE	        GENMASK_ULL(23, 0)
60 #define CGXX_SPUX_CONTROL1		0x10000
61 #define CGXX_SPUX_LNX_FEC_CORR_BLOCKS	0x10700
62 #define CGXX_SPUX_LNX_FEC_UNCORR_BLOCKS	0x10800
63 #define CGXX_SPUX_RSFEC_CORR		0x10088
64 #define CGXX_SPUX_RSFEC_UNCORR		0x10090
65 
66 #define CGXX_SPUX_CONTROL1_LBK		BIT_ULL(14)
67 #define CGXX_GMP_PCS_MRX_CTL		0x30000
68 #define CGXX_GMP_PCS_MRX_CTL_LBK	BIT_ULL(14)
69 
70 #define CGXX_SMUX_RX_FRM_CTL		0x20020
71 #define CGX_SMUX_RX_FRM_CTL_CTL_BCK	BIT_ULL(3)
72 #define CGX_SMUX_RX_FRM_CTL_PTP_MODE	BIT_ULL(12)
73 #define CGXX_GMP_GMI_RXX_FRM_CTL	0x38028
74 #define CGX_GMP_GMI_RXX_FRM_CTL_CTL_BCK	BIT_ULL(3)
75 #define CGX_GMP_GMI_RXX_FRM_CTL_PTP_MODE BIT_ULL(12)
76 #define CGXX_SMUX_TX_CTL		0x20178
77 #define CGXX_SMUX_TX_PAUSE_PKT_TIME	0x20110
78 #define CGXX_SMUX_TX_PAUSE_PKT_INTERVAL	0x20120
79 #define CGXX_SMUX_SMAC                        0x20108
80 #define CGXX_SMUX_CBFC_CTL                    0x20218
81 #define CGXX_SMUX_CBFC_CTL_RX_EN             BIT_ULL(0)
82 #define CGXX_SMUX_CBFC_CTL_TX_EN             BIT_ULL(1)
83 #define CGXX_SMUX_CBFC_CTL_DRP_EN            BIT_ULL(2)
84 #define CGXX_SMUX_CBFC_CTL_BCK_EN            BIT_ULL(3)
85 #define CGX_PFC_CLASS_MASK		     GENMASK_ULL(47, 32)
86 #define CGXX_GMP_GMI_TX_PAUSE_PKT_TIME	0x38230
87 #define CGXX_GMP_GMI_TX_PAUSE_PKT_INTERVAL	0x38248
88 #define CGX_SMUX_TX_CTL_L2P_BP_CONV	BIT_ULL(7)
89 #define CGXX_CMR_RX_OVR_BP		0x130
90 #define CGX_CMR_RX_OVR_BP_EN(X)		BIT_ULL(((X) + 8))
91 #define CGX_CMR_RX_OVR_BP_BP(X)		BIT_ULL(((X) + 4))
92 
93 #define CGX_COMMAND_REG			CGXX_SCRATCH1_REG
94 #define CGX_EVENT_REG			CGXX_SCRATCH0_REG
95 #define CGX_CMD_TIMEOUT			2200 /* msecs */
96 #define DEFAULT_PAUSE_TIME		0x7FF
97 
98 #define CGX_LMAC_FWI			0
99 
100 enum  cgx_nix_stat_type {
101 	NIX_STATS_RX,
102 	NIX_STATS_TX,
103 };
104 
105 enum LMAC_TYPE {
106 	LMAC_MODE_SGMII		= 0,
107 	LMAC_MODE_XAUI		= 1,
108 	LMAC_MODE_RXAUI		= 2,
109 	LMAC_MODE_10G_R		= 3,
110 	LMAC_MODE_40G_R		= 4,
111 	LMAC_MODE_QSGMII	= 6,
112 	LMAC_MODE_25G_R		= 7,
113 	LMAC_MODE_50G_R		= 8,
114 	LMAC_MODE_100G_R	= 9,
115 	LMAC_MODE_USXGMII	= 10,
116 	LMAC_MODE_MAX,
117 };
118 
119 struct cgx_link_event {
120 	struct cgx_link_user_info link_uinfo;
121 	u8 cgx_id;
122 	u8 lmac_id;
123 };
124 
125 /**
126  * struct cgx_event_cb
127  * @notify_link_chg:	callback for link change notification
128  * @data:	data passed to callback function
129  */
130 struct cgx_event_cb {
131 	int (*notify_link_chg)(struct cgx_link_event *event, void *data);
132 	void *data;
133 };
134 
135 extern struct pci_driver cgx_driver;
136 
137 int cgx_get_cgxcnt_max(void);
138 int cgx_get_cgxid(void *cgxd);
139 int cgx_get_lmac_cnt(void *cgxd);
140 void *cgx_get_pdata(int cgx_id);
141 int cgx_set_pkind(void *cgxd, u8 lmac_id, int pkind);
142 int cgx_lmac_evh_register(struct cgx_event_cb *cb, void *cgxd, int lmac_id);
143 int cgx_lmac_evh_unregister(void *cgxd, int lmac_id);
144 int cgx_get_tx_stats(void *cgxd, int lmac_id, int idx, u64 *tx_stat);
145 int cgx_get_rx_stats(void *cgxd, int lmac_id, int idx, u64 *rx_stat);
146 int cgx_lmac_rx_tx_enable(void *cgxd, int lmac_id, bool enable);
147 int cgx_lmac_tx_enable(void *cgxd, int lmac_id, bool enable);
148 int cgx_lmac_addr_set(u8 cgx_id, u8 lmac_id, u8 *mac_addr);
149 int cgx_lmac_addr_reset(u8 cgx_id, u8 lmac_id);
150 u64 cgx_lmac_addr_get(u8 cgx_id, u8 lmac_id);
151 int cgx_lmac_addr_add(u8 cgx_id, u8 lmac_id, u8 *mac_addr);
152 int cgx_lmac_addr_del(u8 cgx_id, u8 lmac_id, u8 index);
153 int cgx_lmac_addr_max_entries_get(u8 cgx_id, u8 lmac_id);
154 void cgx_lmac_promisc_config(int cgx_id, int lmac_id, bool enable);
155 void cgx_lmac_enadis_rx_pause_fwding(void *cgxd, int lmac_id, bool enable);
156 int cgx_lmac_internal_loopback(void *cgxd, int lmac_id, bool enable);
157 int cgx_get_link_info(void *cgxd, int lmac_id,
158 		      struct cgx_link_user_info *linfo);
159 int cgx_lmac_linkup_start(void *cgxd);
160 int cgx_get_fwdata_base(u64 *base);
161 int cgx_lmac_get_pause_frm(void *cgxd, int lmac_id,
162 			   u8 *tx_pause, u8 *rx_pause);
163 int cgx_lmac_set_pause_frm(void *cgxd, int lmac_id,
164 			   u8 tx_pause, u8 rx_pause);
165 void cgx_lmac_ptp_config(void *cgxd, int lmac_id, bool enable);
166 u8 cgx_lmac_get_p2x(int cgx_id, int lmac_id);
167 int cgx_set_fec(u64 fec, int cgx_id, int lmac_id);
168 int cgx_get_fec_stats(void *cgxd, int lmac_id, struct cgx_fec_stats_rsp *rsp);
169 int cgx_get_phy_fec_stats(void *cgxd, int lmac_id);
170 int cgx_set_link_mode(void *cgxd, struct cgx_set_link_mode_args args,
171 		      int cgx_id, int lmac_id);
172 u64 cgx_features_get(void *cgxd);
173 struct mac_ops *get_mac_ops(void *cgxd);
174 int cgx_get_nr_lmacs(void *cgxd);
175 u8 cgx_get_lmacid(void *cgxd, u8 lmac_index);
176 unsigned long cgx_get_lmac_bmap(void *cgxd);
177 void cgx_lmac_write(int cgx_id, int lmac_id, u64 offset, u64 val);
178 u64 cgx_lmac_read(int cgx_id, int lmac_id, u64 offset);
179 int cgx_lmac_addr_update(u8 cgx_id, u8 lmac_id, u8 *mac_addr, u8 index);
180 u64 cgx_read_dmac_ctrl(void *cgxd, int lmac_id);
181 u64 cgx_read_dmac_entry(void *cgxd, int index);
182 int cgx_lmac_pfc_config(void *cgxd, int lmac_id, u8 tx_pause, u8 rx_pause,
183 			u16 pfc_en);
184 int cgx_lmac_get_pfc_frm_cfg(void *cgxd, int lmac_id, u8 *tx_pause,
185 			     u8 *rx_pause);
186 int verify_lmac_fc_cfg(void *cgxd, int lmac_id, u8 tx_pause, u8 rx_pause,
187 		       int pfvf_idx);
188 #endif /* CGX_H */
189