1 /* SPDX-License-Identifier: GPL-2.0 2 * Marvell OcteonTx2 CGX driver 3 * 4 * Copyright (C) 2018 Marvell International Ltd. 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 */ 10 11 #ifndef CGX_H 12 #define CGX_H 13 14 #include "mbox.h" 15 #include "cgx_fw_if.h" 16 17 /* PCI device IDs */ 18 #define PCI_DEVID_OCTEONTX2_CGX 0xA059 19 20 /* PCI BAR nos */ 21 #define PCI_CFG_REG_BAR_NUM 0 22 23 #define CGX_ID_MASK 0x7 24 #define MAX_LMAC_PER_CGX 4 25 #define CGX_FIFO_LEN 65536 /* 64K for both Rx & Tx */ 26 #define CGX_OFFSET(x) ((x) * MAX_LMAC_PER_CGX) 27 28 /* Registers */ 29 #define CGXX_CMRX_CFG 0x00 30 #define CMR_EN BIT_ULL(55) 31 #define DATA_PKT_TX_EN BIT_ULL(53) 32 #define DATA_PKT_RX_EN BIT_ULL(54) 33 #define CGX_LMAC_TYPE_SHIFT 40 34 #define CGX_LMAC_TYPE_MASK 0xF 35 #define CGXX_CMRX_INT 0x040 36 #define FW_CGX_INT BIT_ULL(1) 37 #define CGXX_CMRX_INT_ENA_W1S 0x058 38 #define CGXX_CMRX_RX_ID_MAP 0x060 39 #define CGXX_CMRX_RX_STAT0 0x070 40 #define CGXX_CMRX_RX_LMACS 0x128 41 #define CGXX_CMRX_RX_DMAC_CTL0 0x1F8 42 #define CGX_DMAC_CTL0_CAM_ENABLE BIT_ULL(3) 43 #define CGX_DMAC_CAM_ACCEPT BIT_ULL(3) 44 #define CGX_DMAC_MCAST_MODE BIT_ULL(1) 45 #define CGX_DMAC_BCAST_MODE BIT_ULL(0) 46 #define CGXX_CMRX_RX_DMAC_CAM0 0x200 47 #define CGX_DMAC_CAM_ADDR_ENABLE BIT_ULL(48) 48 #define CGXX_CMRX_RX_DMAC_CAM1 0x400 49 #define CGX_RX_DMAC_ADR_MASK GENMASK_ULL(47, 0) 50 #define CGXX_CMRX_TX_STAT0 0x700 51 #define CGXX_SCRATCH0_REG 0x1050 52 #define CGXX_SCRATCH1_REG 0x1058 53 #define CGX_CONST 0x2000 54 #define CGXX_SPUX_CONTROL1 0x10000 55 #define CGXX_SPUX_CONTROL1_LBK BIT_ULL(14) 56 #define CGXX_GMP_PCS_MRX_CTL 0x30000 57 #define CGXX_GMP_PCS_MRX_CTL_LBK BIT_ULL(14) 58 59 #define CGX_COMMAND_REG CGXX_SCRATCH1_REG 60 #define CGX_EVENT_REG CGXX_SCRATCH0_REG 61 #define CGX_CMD_TIMEOUT 2200 /* msecs */ 62 63 #define CGX_NVEC 37 64 #define CGX_LMAC_FWI 0 65 66 enum LMAC_TYPE { 67 LMAC_MODE_SGMII = 0, 68 LMAC_MODE_XAUI = 1, 69 LMAC_MODE_RXAUI = 2, 70 LMAC_MODE_10G_R = 3, 71 LMAC_MODE_40G_R = 4, 72 LMAC_MODE_QSGMII = 6, 73 LMAC_MODE_25G_R = 7, 74 LMAC_MODE_50G_R = 8, 75 LMAC_MODE_100G_R = 9, 76 LMAC_MODE_USXGMII = 10, 77 LMAC_MODE_MAX, 78 }; 79 80 struct cgx_link_event { 81 struct cgx_link_user_info link_uinfo; 82 u8 cgx_id; 83 u8 lmac_id; 84 }; 85 86 /** 87 * struct cgx_event_cb 88 * @notify_link_chg: callback for link change notification 89 * @data: data passed to callback function 90 */ 91 struct cgx_event_cb { 92 int (*notify_link_chg)(struct cgx_link_event *event, void *data); 93 void *data; 94 }; 95 96 extern struct pci_driver cgx_driver; 97 98 int cgx_get_cgxcnt_max(void); 99 int cgx_get_lmac_cnt(void *cgxd); 100 void *cgx_get_pdata(int cgx_id); 101 int cgx_set_pkind(void *cgxd, u8 lmac_id, int pkind); 102 int cgx_lmac_evh_register(struct cgx_event_cb *cb, void *cgxd, int lmac_id); 103 int cgx_lmac_evh_unregister(void *cgxd, int lmac_id); 104 int cgx_get_tx_stats(void *cgxd, int lmac_id, int idx, u64 *tx_stat); 105 int cgx_get_rx_stats(void *cgxd, int lmac_id, int idx, u64 *rx_stat); 106 int cgx_lmac_rx_tx_enable(void *cgxd, int lmac_id, bool enable); 107 int cgx_lmac_addr_set(u8 cgx_id, u8 lmac_id, u8 *mac_addr); 108 u64 cgx_lmac_addr_get(u8 cgx_id, u8 lmac_id); 109 void cgx_lmac_promisc_config(int cgx_id, int lmac_id, bool enable); 110 int cgx_lmac_internal_loopback(void *cgxd, int lmac_id, bool enable); 111 int cgx_get_link_info(void *cgxd, int lmac_id, 112 struct cgx_link_user_info *linfo); 113 int cgx_lmac_linkup_start(void *cgxd); 114 int cgx_get_mkex_prfl_info(u64 *addr, u64 *size); 115 #endif /* CGX_H */ 116