1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*  Marvell OcteonTx2 CGX driver
3  *
4  * Copyright (C) 2018 Marvell International Ltd.
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License version 2 as
8  * published by the Free Software Foundation.
9  */
10 
11 #ifndef CGX_H
12 #define CGX_H
13 
14 #include "mbox.h"
15 #include "cgx_fw_if.h"
16 
17  /* PCI device IDs */
18 #define	PCI_DEVID_OCTEONTX2_CGX		0xA059
19 
20 /* PCI BAR nos */
21 #define PCI_CFG_REG_BAR_NUM		0
22 
23 #define CGX_ID_MASK			0x7
24 #define MAX_LMAC_PER_CGX		4
25 #define CGX_FIFO_LEN			65536 /* 64K for both Rx & Tx */
26 #define CGX_OFFSET(x)			((x) * MAX_LMAC_PER_CGX)
27 
28 /* Registers */
29 #define CGXX_CMRX_CFG			0x00
30 #define CMR_P2X_SEL_MASK		GENMASK_ULL(61, 59)
31 #define CMR_P2X_SEL_SHIFT		59ULL
32 #define CMR_P2X_SEL_NIX0		1ULL
33 #define CMR_P2X_SEL_NIX1		2ULL
34 #define CMR_EN				BIT_ULL(55)
35 #define DATA_PKT_TX_EN			BIT_ULL(53)
36 #define DATA_PKT_RX_EN			BIT_ULL(54)
37 #define CGX_LMAC_TYPE_SHIFT		40
38 #define CGX_LMAC_TYPE_MASK		0xF
39 #define CGXX_CMRX_INT			0x040
40 #define FW_CGX_INT			BIT_ULL(1)
41 #define CGXX_CMRX_INT_ENA_W1S		0x058
42 #define CGXX_CMRX_RX_ID_MAP		0x060
43 #define CGXX_CMRX_RX_STAT0		0x070
44 #define CGXX_CMRX_RX_LMACS		0x128
45 #define CGXX_CMRX_RX_DMAC_CTL0		0x1F8
46 #define CGX_DMAC_CTL0_CAM_ENABLE	BIT_ULL(3)
47 #define CGX_DMAC_CAM_ACCEPT		BIT_ULL(3)
48 #define CGX_DMAC_MCAST_MODE		BIT_ULL(1)
49 #define CGX_DMAC_BCAST_MODE		BIT_ULL(0)
50 #define CGXX_CMRX_RX_DMAC_CAM0		0x200
51 #define CGX_DMAC_CAM_ADDR_ENABLE	BIT_ULL(48)
52 #define CGXX_CMRX_RX_DMAC_CAM1		0x400
53 #define CGX_RX_DMAC_ADR_MASK		GENMASK_ULL(47, 0)
54 #define CGXX_CMRX_TX_STAT0		0x700
55 #define CGXX_SCRATCH0_REG		0x1050
56 #define CGXX_SCRATCH1_REG		0x1058
57 #define CGX_CONST			0x2000
58 #define CGXX_SPUX_CONTROL1		0x10000
59 #define CGXX_SPUX_CONTROL1_LBK		BIT_ULL(14)
60 #define CGXX_GMP_PCS_MRX_CTL		0x30000
61 #define CGXX_GMP_PCS_MRX_CTL_LBK	BIT_ULL(14)
62 
63 #define CGXX_SMUX_RX_FRM_CTL		0x20020
64 #define CGX_SMUX_RX_FRM_CTL_CTL_BCK	BIT_ULL(3)
65 #define CGX_SMUX_RX_FRM_CTL_PTP_MODE	BIT_ULL(12)
66 #define CGXX_GMP_GMI_RXX_FRM_CTL	0x38028
67 #define CGX_GMP_GMI_RXX_FRM_CTL_CTL_BCK	BIT_ULL(3)
68 #define CGX_GMP_GMI_RXX_FRM_CTL_PTP_MODE BIT_ULL(12)
69 #define CGXX_SMUX_TX_CTL		0x20178
70 #define CGXX_SMUX_TX_PAUSE_PKT_TIME	0x20110
71 #define CGXX_SMUX_TX_PAUSE_PKT_INTERVAL	0x20120
72 #define CGXX_GMP_GMI_TX_PAUSE_PKT_TIME	0x38230
73 #define CGXX_GMP_GMI_TX_PAUSE_PKT_INTERVAL	0x38248
74 #define CGX_SMUX_TX_CTL_L2P_BP_CONV	BIT_ULL(7)
75 #define CGXX_CMR_RX_OVR_BP		0x130
76 #define CGX_CMR_RX_OVR_BP_EN(X)		BIT_ULL(((X) + 8))
77 #define CGX_CMR_RX_OVR_BP_BP(X)		BIT_ULL(((X) + 4))
78 
79 #define CGX_COMMAND_REG			CGXX_SCRATCH1_REG
80 #define CGX_EVENT_REG			CGXX_SCRATCH0_REG
81 #define CGX_CMD_TIMEOUT			2200 /* msecs */
82 #define DEFAULT_PAUSE_TIME		0x7FF
83 
84 #define CGX_NVEC			37
85 #define CGX_LMAC_FWI			0
86 
87 enum  cgx_nix_stat_type {
88 	NIX_STATS_RX,
89 	NIX_STATS_TX,
90 };
91 
92 enum LMAC_TYPE {
93 	LMAC_MODE_SGMII		= 0,
94 	LMAC_MODE_XAUI		= 1,
95 	LMAC_MODE_RXAUI		= 2,
96 	LMAC_MODE_10G_R		= 3,
97 	LMAC_MODE_40G_R		= 4,
98 	LMAC_MODE_QSGMII	= 6,
99 	LMAC_MODE_25G_R		= 7,
100 	LMAC_MODE_50G_R		= 8,
101 	LMAC_MODE_100G_R	= 9,
102 	LMAC_MODE_USXGMII	= 10,
103 	LMAC_MODE_MAX,
104 };
105 
106 struct cgx_link_event {
107 	struct cgx_link_user_info link_uinfo;
108 	u8 cgx_id;
109 	u8 lmac_id;
110 };
111 
112 /**
113  * struct cgx_event_cb
114  * @notify_link_chg:	callback for link change notification
115  * @data:	data passed to callback function
116  */
117 struct cgx_event_cb {
118 	int (*notify_link_chg)(struct cgx_link_event *event, void *data);
119 	void *data;
120 };
121 
122 extern struct pci_driver cgx_driver;
123 
124 int cgx_get_cgxcnt_max(void);
125 int cgx_get_cgxid(void *cgxd);
126 int cgx_get_lmac_cnt(void *cgxd);
127 void *cgx_get_pdata(int cgx_id);
128 int cgx_set_pkind(void *cgxd, u8 lmac_id, int pkind);
129 int cgx_lmac_evh_register(struct cgx_event_cb *cb, void *cgxd, int lmac_id);
130 int cgx_lmac_evh_unregister(void *cgxd, int lmac_id);
131 int cgx_get_tx_stats(void *cgxd, int lmac_id, int idx, u64 *tx_stat);
132 int cgx_get_rx_stats(void *cgxd, int lmac_id, int idx, u64 *rx_stat);
133 int cgx_lmac_rx_tx_enable(void *cgxd, int lmac_id, bool enable);
134 int cgx_lmac_tx_enable(void *cgxd, int lmac_id, bool enable);
135 int cgx_lmac_addr_set(u8 cgx_id, u8 lmac_id, u8 *mac_addr);
136 u64 cgx_lmac_addr_get(u8 cgx_id, u8 lmac_id);
137 void cgx_lmac_promisc_config(int cgx_id, int lmac_id, bool enable);
138 void cgx_lmac_enadis_rx_pause_fwding(void *cgxd, int lmac_id, bool enable);
139 int cgx_lmac_internal_loopback(void *cgxd, int lmac_id, bool enable);
140 int cgx_get_link_info(void *cgxd, int lmac_id,
141 		      struct cgx_link_user_info *linfo);
142 int cgx_lmac_linkup_start(void *cgxd);
143 int cgx_get_fwdata_base(u64 *base);
144 int cgx_lmac_get_pause_frm(void *cgxd, int lmac_id,
145 			   u8 *tx_pause, u8 *rx_pause);
146 int cgx_lmac_set_pause_frm(void *cgxd, int lmac_id,
147 			   u8 tx_pause, u8 rx_pause);
148 void cgx_lmac_ptp_config(void *cgxd, int lmac_id, bool enable);
149 u8 cgx_lmac_get_p2x(int cgx_id, int lmac_id);
150 
151 #endif /* CGX_H */
152