18e22f040SSunil Goutham /* SPDX-License-Identifier: GPL-2.0 28e22f040SSunil Goutham * Marvell OcteonTx2 CGX driver 38e22f040SSunil Goutham * 48e22f040SSunil Goutham * Copyright (C) 2018 Marvell International Ltd. 58e22f040SSunil Goutham * 68e22f040SSunil Goutham * This program is free software; you can redistribute it and/or modify 78e22f040SSunil Goutham * it under the terms of the GNU General Public License version 2 as 88e22f040SSunil Goutham * published by the Free Software Foundation. 98e22f040SSunil Goutham */ 108e22f040SSunil Goutham 118e22f040SSunil Goutham #ifndef CGX_H 128e22f040SSunil Goutham #define CGX_H 138e22f040SSunil Goutham 1461071a87SLinu Cherian #include "mbox.h" 151463f382SLinu Cherian #include "cgx_fw_if.h" 161463f382SLinu Cherian 178e22f040SSunil Goutham /* PCI device IDs */ 188e22f040SSunil Goutham #define PCI_DEVID_OCTEONTX2_CGX 0xA059 198e22f040SSunil Goutham 208e22f040SSunil Goutham /* PCI BAR nos */ 218e22f040SSunil Goutham #define PCI_CFG_REG_BAR_NUM 0 228e22f040SSunil Goutham 233a4fa841SLinu Cherian #define MAX_CGX 3 243a4fa841SLinu Cherian #define MAX_LMAC_PER_CGX 4 253a4fa841SLinu Cherian #define CGX_OFFSET(x) ((x) * MAX_LMAC_PER_CGX) 263a4fa841SLinu Cherian 273a4fa841SLinu Cherian /* Registers */ 281435f66aSSunil Goutham #define CGXX_CMRX_CFG 0x00 291435f66aSSunil Goutham #define CMR_EN BIT_ULL(55) 301435f66aSSunil Goutham #define DATA_PKT_TX_EN BIT_ULL(53) 311435f66aSSunil Goutham #define DATA_PKT_RX_EN BIT_ULL(54) 3261071a87SLinu Cherian #define CGX_LMAC_TYPE_SHIFT 40 3361071a87SLinu Cherian #define CGX_LMAC_TYPE_MASK 0xF 341463f382SLinu Cherian #define CGXX_CMRX_INT 0x040 351463f382SLinu Cherian #define FW_CGX_INT BIT_ULL(1) 361463f382SLinu Cherian #define CGXX_CMRX_INT_ENA_W1S 0x058 373a4fa841SLinu Cherian #define CGXX_CMRX_RX_ID_MAP 0x060 3866208910SChristina Jacob #define CGXX_CMRX_RX_STAT0 0x070 393a4fa841SLinu Cherian #define CGXX_CMRX_RX_LMACS 0x128 4096be2e0dSVidhya Raman #define CGXX_CMRX_RX_DMAC_CTL0 0x1F8 4196be2e0dSVidhya Raman #define CGX_DMAC_CTL0_CAM_ENABLE BIT_ULL(3) 4296be2e0dSVidhya Raman #define CGX_DMAC_CAM_ACCEPT BIT_ULL(3) 4396be2e0dSVidhya Raman #define CGX_DMAC_MCAST_MODE BIT_ULL(1) 4496be2e0dSVidhya Raman #define CGX_DMAC_BCAST_MODE BIT_ULL(0) 4596be2e0dSVidhya Raman #define CGXX_CMRX_RX_DMAC_CAM0 0x200 4696be2e0dSVidhya Raman #define CGX_DMAC_CAM_ADDR_ENABLE BIT_ULL(48) 4796be2e0dSVidhya Raman #define CGXX_CMRX_RX_DMAC_CAM1 0x400 4896be2e0dSVidhya Raman #define CGX_RX_DMAC_ADR_MASK GENMASK_ULL(47, 0) 4966208910SChristina Jacob #define CGXX_CMRX_TX_STAT0 0x700 501463f382SLinu Cherian #define CGXX_SCRATCH0_REG 0x1050 511463f382SLinu Cherian #define CGXX_SCRATCH1_REG 0x1058 521463f382SLinu Cherian #define CGX_CONST 0x2000 531463f382SLinu Cherian 541463f382SLinu Cherian #define CGX_COMMAND_REG CGXX_SCRATCH1_REG 551463f382SLinu Cherian #define CGX_EVENT_REG CGXX_SCRATCH0_REG 561463f382SLinu Cherian #define CGX_CMD_TIMEOUT 2200 /* msecs */ 571463f382SLinu Cherian 581463f382SLinu Cherian #define CGX_NVEC 37 591463f382SLinu Cherian #define CGX_LMAC_FWI 0 601463f382SLinu Cherian 6161071a87SLinu Cherian enum LMAC_TYPE { 6261071a87SLinu Cherian LMAC_MODE_SGMII = 0, 6361071a87SLinu Cherian LMAC_MODE_XAUI = 1, 6461071a87SLinu Cherian LMAC_MODE_RXAUI = 2, 6561071a87SLinu Cherian LMAC_MODE_10G_R = 3, 6661071a87SLinu Cherian LMAC_MODE_40G_R = 4, 6761071a87SLinu Cherian LMAC_MODE_QSGMII = 6, 6861071a87SLinu Cherian LMAC_MODE_25G_R = 7, 6961071a87SLinu Cherian LMAC_MODE_50G_R = 8, 7061071a87SLinu Cherian LMAC_MODE_100G_R = 9, 7161071a87SLinu Cherian LMAC_MODE_USXGMII = 10, 7261071a87SLinu Cherian LMAC_MODE_MAX, 7361071a87SLinu Cherian }; 7461071a87SLinu Cherian 751463f382SLinu Cherian struct cgx_link_event { 7661071a87SLinu Cherian struct cgx_link_user_info link_uinfo; 771463f382SLinu Cherian u8 cgx_id; 781463f382SLinu Cherian u8 lmac_id; 791463f382SLinu Cherian }; 801463f382SLinu Cherian 811463f382SLinu Cherian /** 821463f382SLinu Cherian * struct cgx_event_cb 831463f382SLinu Cherian * @notify_link_chg: callback for link change notification 841463f382SLinu Cherian * @data: data passed to callback function 851463f382SLinu Cherian */ 861463f382SLinu Cherian struct cgx_event_cb { 871463f382SLinu Cherian int (*notify_link_chg)(struct cgx_link_event *event, void *data); 881463f382SLinu Cherian void *data; 891463f382SLinu Cherian }; 903a4fa841SLinu Cherian 918e22f040SSunil Goutham extern struct pci_driver cgx_driver; 928e22f040SSunil Goutham 933a4fa841SLinu Cherian int cgx_get_cgx_cnt(void); 943a4fa841SLinu Cherian int cgx_get_lmac_cnt(void *cgxd); 953a4fa841SLinu Cherian void *cgx_get_pdata(int cgx_id); 961463f382SLinu Cherian int cgx_lmac_evh_register(struct cgx_event_cb *cb, void *cgxd, int lmac_id); 9766208910SChristina Jacob int cgx_get_tx_stats(void *cgxd, int lmac_id, int idx, u64 *tx_stat); 9866208910SChristina Jacob int cgx_get_rx_stats(void *cgxd, int lmac_id, int idx, u64 *rx_stat); 991435f66aSSunil Goutham int cgx_lmac_rx_tx_enable(void *cgxd, int lmac_id, bool enable); 10096be2e0dSVidhya Raman int cgx_lmac_addr_set(u8 cgx_id, u8 lmac_id, u8 *mac_addr); 10196be2e0dSVidhya Raman u64 cgx_lmac_addr_get(u8 cgx_id, u8 lmac_id); 10296be2e0dSVidhya Raman void cgx_lmac_promisc_config(int cgx_id, int lmac_id, bool enable); 10361071a87SLinu Cherian int cgx_get_link_info(void *cgxd, int lmac_id, 10461071a87SLinu Cherian struct cgx_link_user_info *linfo); 1058e22f040SSunil Goutham #endif /* CGX_H */ 106