18e22f040SSunil Goutham /* SPDX-License-Identifier: GPL-2.0 28e22f040SSunil Goutham * Marvell OcteonTx2 CGX driver 38e22f040SSunil Goutham * 48e22f040SSunil Goutham * Copyright (C) 2018 Marvell International Ltd. 58e22f040SSunil Goutham * 68e22f040SSunil Goutham * This program is free software; you can redistribute it and/or modify 78e22f040SSunil Goutham * it under the terms of the GNU General Public License version 2 as 88e22f040SSunil Goutham * published by the Free Software Foundation. 98e22f040SSunil Goutham */ 108e22f040SSunil Goutham 118e22f040SSunil Goutham #ifndef CGX_H 128e22f040SSunil Goutham #define CGX_H 138e22f040SSunil Goutham 1461071a87SLinu Cherian #include "mbox.h" 151463f382SLinu Cherian #include "cgx_fw_if.h" 161463f382SLinu Cherian 178e22f040SSunil Goutham /* PCI device IDs */ 188e22f040SSunil Goutham #define PCI_DEVID_OCTEONTX2_CGX 0xA059 198e22f040SSunil Goutham 208e22f040SSunil Goutham /* PCI BAR nos */ 218e22f040SSunil Goutham #define PCI_CFG_REG_BAR_NUM 0 228e22f040SSunil Goutham 2312e4c9abSLinu Cherian #define CGX_ID_MASK 0x7 243a4fa841SLinu Cherian #define MAX_LMAC_PER_CGX 4 259b7dd87aSSunil Goutham #define CGX_FIFO_LEN 65536 /* 64K for both Rx & Tx */ 263a4fa841SLinu Cherian #define CGX_OFFSET(x) ((x) * MAX_LMAC_PER_CGX) 273a4fa841SLinu Cherian 283a4fa841SLinu Cherian /* Registers */ 291435f66aSSunil Goutham #define CGXX_CMRX_CFG 0x00 301435f66aSSunil Goutham #define CMR_EN BIT_ULL(55) 311435f66aSSunil Goutham #define DATA_PKT_TX_EN BIT_ULL(53) 321435f66aSSunil Goutham #define DATA_PKT_RX_EN BIT_ULL(54) 3361071a87SLinu Cherian #define CGX_LMAC_TYPE_SHIFT 40 3461071a87SLinu Cherian #define CGX_LMAC_TYPE_MASK 0xF 351463f382SLinu Cherian #define CGXX_CMRX_INT 0x040 361463f382SLinu Cherian #define FW_CGX_INT BIT_ULL(1) 371463f382SLinu Cherian #define CGXX_CMRX_INT_ENA_W1S 0x058 383a4fa841SLinu Cherian #define CGXX_CMRX_RX_ID_MAP 0x060 3966208910SChristina Jacob #define CGXX_CMRX_RX_STAT0 0x070 403a4fa841SLinu Cherian #define CGXX_CMRX_RX_LMACS 0x128 4196be2e0dSVidhya Raman #define CGXX_CMRX_RX_DMAC_CTL0 0x1F8 4296be2e0dSVidhya Raman #define CGX_DMAC_CTL0_CAM_ENABLE BIT_ULL(3) 4396be2e0dSVidhya Raman #define CGX_DMAC_CAM_ACCEPT BIT_ULL(3) 4496be2e0dSVidhya Raman #define CGX_DMAC_MCAST_MODE BIT_ULL(1) 4596be2e0dSVidhya Raman #define CGX_DMAC_BCAST_MODE BIT_ULL(0) 4696be2e0dSVidhya Raman #define CGXX_CMRX_RX_DMAC_CAM0 0x200 4796be2e0dSVidhya Raman #define CGX_DMAC_CAM_ADDR_ENABLE BIT_ULL(48) 4896be2e0dSVidhya Raman #define CGXX_CMRX_RX_DMAC_CAM1 0x400 4996be2e0dSVidhya Raman #define CGX_RX_DMAC_ADR_MASK GENMASK_ULL(47, 0) 5066208910SChristina Jacob #define CGXX_CMRX_TX_STAT0 0x700 511463f382SLinu Cherian #define CGXX_SCRATCH0_REG 0x1050 521463f382SLinu Cherian #define CGXX_SCRATCH1_REG 0x1058 531463f382SLinu Cherian #define CGX_CONST 0x2000 5423999b30SGeetha sowjanya #define CGXX_SPUX_CONTROL1 0x10000 5523999b30SGeetha sowjanya #define CGXX_SPUX_CONTROL1_LBK BIT_ULL(14) 5623999b30SGeetha sowjanya #define CGXX_GMP_PCS_MRX_CTL 0x30000 5723999b30SGeetha sowjanya #define CGXX_GMP_PCS_MRX_CTL_LBK BIT_ULL(14) 581463f382SLinu Cherian 595d9b976dSSunil Goutham #define CGXX_SMUX_RX_FRM_CTL 0x20020 605d9b976dSSunil Goutham #define CGX_SMUX_RX_FRM_CTL_CTL_BCK BIT_ULL(3) 615d9b976dSSunil Goutham #define CGXX_GMP_GMI_RXX_FRM_CTL 0x38028 625d9b976dSSunil Goutham #define CGX_GMP_GMI_RXX_FRM_CTL_CTL_BCK BIT_ULL(3) 635d9b976dSSunil Goutham 641463f382SLinu Cherian #define CGX_COMMAND_REG CGXX_SCRATCH1_REG 651463f382SLinu Cherian #define CGX_EVENT_REG CGXX_SCRATCH0_REG 661463f382SLinu Cherian #define CGX_CMD_TIMEOUT 2200 /* msecs */ 671463f382SLinu Cherian 681463f382SLinu Cherian #define CGX_NVEC 37 691463f382SLinu Cherian #define CGX_LMAC_FWI 0 701463f382SLinu Cherian 71f967488dSLinu Cherian enum cgx_nix_stat_type { 72f967488dSLinu Cherian NIX_STATS_RX, 73f967488dSLinu Cherian NIX_STATS_TX, 74f967488dSLinu Cherian }; 75f967488dSLinu Cherian 7661071a87SLinu Cherian enum LMAC_TYPE { 7761071a87SLinu Cherian LMAC_MODE_SGMII = 0, 7861071a87SLinu Cherian LMAC_MODE_XAUI = 1, 7961071a87SLinu Cherian LMAC_MODE_RXAUI = 2, 8061071a87SLinu Cherian LMAC_MODE_10G_R = 3, 8161071a87SLinu Cherian LMAC_MODE_40G_R = 4, 8261071a87SLinu Cherian LMAC_MODE_QSGMII = 6, 8361071a87SLinu Cherian LMAC_MODE_25G_R = 7, 8461071a87SLinu Cherian LMAC_MODE_50G_R = 8, 8561071a87SLinu Cherian LMAC_MODE_100G_R = 9, 8661071a87SLinu Cherian LMAC_MODE_USXGMII = 10, 8761071a87SLinu Cherian LMAC_MODE_MAX, 8861071a87SLinu Cherian }; 8961071a87SLinu Cherian 901463f382SLinu Cherian struct cgx_link_event { 9161071a87SLinu Cherian struct cgx_link_user_info link_uinfo; 921463f382SLinu Cherian u8 cgx_id; 931463f382SLinu Cherian u8 lmac_id; 941463f382SLinu Cherian }; 951463f382SLinu Cherian 961463f382SLinu Cherian /** 971463f382SLinu Cherian * struct cgx_event_cb 981463f382SLinu Cherian * @notify_link_chg: callback for link change notification 991463f382SLinu Cherian * @data: data passed to callback function 1001463f382SLinu Cherian */ 1011463f382SLinu Cherian struct cgx_event_cb { 1021463f382SLinu Cherian int (*notify_link_chg)(struct cgx_link_event *event, void *data); 1031463f382SLinu Cherian void *data; 1041463f382SLinu Cherian }; 1053a4fa841SLinu Cherian 1068e22f040SSunil Goutham extern struct pci_driver cgx_driver; 1078e22f040SSunil Goutham 10812e4c9abSLinu Cherian int cgx_get_cgxcnt_max(void); 109f967488dSLinu Cherian int cgx_get_cgxid(void *cgxd); 1103a4fa841SLinu Cherian int cgx_get_lmac_cnt(void *cgxd); 1113a4fa841SLinu Cherian void *cgx_get_pdata(int cgx_id); 11294d942c5SGeetha sowjanya int cgx_set_pkind(void *cgxd, u8 lmac_id, int pkind); 1131463f382SLinu Cherian int cgx_lmac_evh_register(struct cgx_event_cb *cb, void *cgxd, int lmac_id); 114c9293236SLinu Cherian int cgx_lmac_evh_unregister(void *cgxd, int lmac_id); 11566208910SChristina Jacob int cgx_get_tx_stats(void *cgxd, int lmac_id, int idx, u64 *tx_stat); 11666208910SChristina Jacob int cgx_get_rx_stats(void *cgxd, int lmac_id, int idx, u64 *rx_stat); 1171435f66aSSunil Goutham int cgx_lmac_rx_tx_enable(void *cgxd, int lmac_id, bool enable); 1185d9b976dSSunil Goutham int cgx_lmac_tx_enable(void *cgxd, int lmac_id, bool enable); 11996be2e0dSVidhya Raman int cgx_lmac_addr_set(u8 cgx_id, u8 lmac_id, u8 *mac_addr); 12096be2e0dSVidhya Raman u64 cgx_lmac_addr_get(u8 cgx_id, u8 lmac_id); 12196be2e0dSVidhya Raman void cgx_lmac_promisc_config(int cgx_id, int lmac_id, bool enable); 1225d9b976dSSunil Goutham void cgx_lmac_enadis_rx_pause_fwding(void *cgxd, int lmac_id, bool enable); 12323999b30SGeetha sowjanya int cgx_lmac_internal_loopback(void *cgxd, int lmac_id, bool enable); 12461071a87SLinu Cherian int cgx_get_link_info(void *cgxd, int lmac_id, 12561071a87SLinu Cherian struct cgx_link_user_info *linfo); 126d3b2b9abSLinu Cherian int cgx_lmac_linkup_start(void *cgxd); 12723705adbSVamsi Attunuru int cgx_get_mkex_prfl_info(u64 *addr, u64 *size); 1288e22f040SSunil Goutham #endif /* CGX_H */ 129