126b3f3ccSNishad Kamdar /* SPDX-License-Identifier: GPL-2.0 */
226b3f3ccSNishad Kamdar /* Marvell OcteonTx2 CGX driver
38e22f040SSunil Goutham  *
4c7cd6c5aSSunil Goutham  * Copyright (C) 2018 Marvell.
58e22f040SSunil Goutham  *
68e22f040SSunil Goutham  */
78e22f040SSunil Goutham 
88e22f040SSunil Goutham #ifndef CGX_H
98e22f040SSunil Goutham #define CGX_H
108e22f040SSunil Goutham 
1161071a87SLinu Cherian #include "mbox.h"
121463f382SLinu Cherian #include "cgx_fw_if.h"
1391c6945eSHariprasad Kelam #include "rpm.h"
141463f382SLinu Cherian 
158e22f040SSunil Goutham  /* PCI device IDs */
168e22f040SSunil Goutham #define	PCI_DEVID_OCTEONTX2_CGX		0xA059
178e22f040SSunil Goutham 
188e22f040SSunil Goutham /* PCI BAR nos */
198e22f040SSunil Goutham #define PCI_CFG_REG_BAR_NUM		0
208e22f040SSunil Goutham 
21f2e664adSRakesh Babu Saladi #define CGX_ID_MASK			0xF
223a4fa841SLinu Cherian 
233a4fa841SLinu Cherian /* Registers */
241435f66aSSunil Goutham #define CGXX_CMRX_CFG			0x00
25c5a73b63SSubbaraya Sundeep #define CMR_P2X_SEL_MASK		GENMASK_ULL(61, 59)
26c5a73b63SSubbaraya Sundeep #define CMR_P2X_SEL_SHIFT		59ULL
27c5a73b63SSubbaraya Sundeep #define CMR_P2X_SEL_NIX0		1ULL
28c5a73b63SSubbaraya Sundeep #define CMR_P2X_SEL_NIX1		2ULL
291435f66aSSunil Goutham #define DATA_PKT_TX_EN			BIT_ULL(53)
301435f66aSSunil Goutham #define DATA_PKT_RX_EN			BIT_ULL(54)
3161071a87SLinu Cherian #define CGX_LMAC_TYPE_SHIFT		40
3261071a87SLinu Cherian #define CGX_LMAC_TYPE_MASK		0xF
331463f382SLinu Cherian #define CGXX_CMRX_INT			0x040
341463f382SLinu Cherian #define FW_CGX_INT			BIT_ULL(1)
351463f382SLinu Cherian #define CGXX_CMRX_INT_ENA_W1S		0x058
363a4fa841SLinu Cherian #define CGXX_CMRX_RX_ID_MAP		0x060
37ce7a6c31SHariprasad Kelam #define CGXX_CMRX_RX_STAT0		0x070
382e3e94c2SHariprasad Kelam #define CGXX_CMRX_RX_LOGL_XON		0x100
393a4fa841SLinu Cherian #define CGXX_CMRX_RX_LMACS		0x128
4091c6945eSHariprasad Kelam #define CGXX_CMRX_RX_DMAC_CTL0		(0x1F8 + mac_ops->csr_offset)
4196be2e0dSVidhya Raman #define CGX_DMAC_CTL0_CAM_ENABLE	BIT_ULL(3)
4296be2e0dSVidhya Raman #define CGX_DMAC_CAM_ACCEPT		BIT_ULL(3)
436f14078eSSunil Kumar Kori #define CGX_DMAC_MCAST_MODE_CAM		BIT_ULL(2)
4496be2e0dSVidhya Raman #define CGX_DMAC_MCAST_MODE		BIT_ULL(1)
4596be2e0dSVidhya Raman #define CGX_DMAC_BCAST_MODE		BIT_ULL(0)
4691c6945eSHariprasad Kelam #define CGXX_CMRX_RX_DMAC_CAM0		(0x200 + mac_ops->csr_offset)
4796be2e0dSVidhya Raman #define CGX_DMAC_CAM_ADDR_ENABLE	BIT_ULL(48)
48dbc52debSHariprasad Kelam #define CGX_DMAC_CAM_ENTRY_LMACID	GENMASK_ULL(50, 49)
4996be2e0dSVidhya Raman #define CGXX_CMRX_RX_DMAC_CAM1		0x400
5096be2e0dSVidhya Raman #define CGX_RX_DMAC_ADR_MASK		GENMASK_ULL(47, 0)
51ce7a6c31SHariprasad Kelam #define CGXX_CMRX_TX_STAT0		0x700
521463f382SLinu Cherian #define CGXX_SCRATCH0_REG		0x1050
531463f382SLinu Cherian #define CGXX_SCRATCH1_REG		0x1058
541463f382SLinu Cherian #define CGX_CONST			0x2000
55b9d0fedcSHariprasad Kelam #define CGX_CONST_RXFIFO_SIZE	        GENMASK_ULL(55, 32)
56f2e664adSRakesh Babu Saladi #define CGX_CONST_MAX_LMACS	        GENMASK_ULL(31, 24)
5723999b30SGeetha sowjanya #define CGXX_SPUX_CONTROL1		0x10000
5884c4f9caSChristina Jacob #define CGXX_SPUX_LNX_FEC_CORR_BLOCKS	0x10700
5984c4f9caSChristina Jacob #define CGXX_SPUX_LNX_FEC_UNCORR_BLOCKS	0x10800
6084c4f9caSChristina Jacob #define CGXX_SPUX_RSFEC_CORR		0x10088
6184c4f9caSChristina Jacob #define CGXX_SPUX_RSFEC_UNCORR		0x10090
6284c4f9caSChristina Jacob 
6323999b30SGeetha sowjanya #define CGXX_SPUX_CONTROL1_LBK		BIT_ULL(14)
6423999b30SGeetha sowjanya #define CGXX_GMP_PCS_MRX_CTL		0x30000
6523999b30SGeetha sowjanya #define CGXX_GMP_PCS_MRX_CTL_LBK	BIT_ULL(14)
661463f382SLinu Cherian 
675d9b976dSSunil Goutham #define CGXX_SMUX_RX_FRM_CTL		0x20020
685d9b976dSSunil Goutham #define CGX_SMUX_RX_FRM_CTL_CTL_BCK	BIT_ULL(3)
6942157217SZyta Szpak #define CGX_SMUX_RX_FRM_CTL_PTP_MODE	BIT_ULL(12)
705d9b976dSSunil Goutham #define CGXX_GMP_GMI_RXX_FRM_CTL	0x38028
715d9b976dSSunil Goutham #define CGX_GMP_GMI_RXX_FRM_CTL_CTL_BCK	BIT_ULL(3)
7242157217SZyta Szpak #define CGX_GMP_GMI_RXX_FRM_CTL_PTP_MODE BIT_ULL(12)
73f7e086e7SGeetha sowjanya #define CGXX_SMUX_TX_CTL		0x20178
74f7e086e7SGeetha sowjanya #define CGXX_SMUX_TX_PAUSE_PKT_TIME	0x20110
75f7e086e7SGeetha sowjanya #define CGXX_SMUX_TX_PAUSE_PKT_INTERVAL	0x20120
761121f6b0SSunil Kumar Kori #define CGXX_SMUX_SMAC                        0x20108
771121f6b0SSunil Kumar Kori #define CGXX_SMUX_CBFC_CTL                    0x20218
781121f6b0SSunil Kumar Kori #define CGXX_SMUX_CBFC_CTL_RX_EN             BIT_ULL(0)
791121f6b0SSunil Kumar Kori #define CGXX_SMUX_CBFC_CTL_TX_EN             BIT_ULL(1)
801121f6b0SSunil Kumar Kori #define CGXX_SMUX_CBFC_CTL_DRP_EN            BIT_ULL(2)
811121f6b0SSunil Kumar Kori #define CGXX_SMUX_CBFC_CTL_BCK_EN            BIT_ULL(3)
821121f6b0SSunil Kumar Kori #define CGX_PFC_CLASS_MASK		     GENMASK_ULL(47, 32)
83f7e086e7SGeetha sowjanya #define CGXX_GMP_GMI_TX_PAUSE_PKT_TIME	0x38230
84f7e086e7SGeetha sowjanya #define CGXX_GMP_GMI_TX_PAUSE_PKT_INTERVAL	0x38248
85f7e086e7SGeetha sowjanya #define CGX_SMUX_TX_CTL_L2P_BP_CONV	BIT_ULL(7)
86f7e086e7SGeetha sowjanya #define CGXX_CMR_RX_OVR_BP		0x130
87f7e086e7SGeetha sowjanya #define CGX_CMR_RX_OVR_BP_EN(X)		BIT_ULL(((X) + 8))
88f7e086e7SGeetha sowjanya #define CGX_CMR_RX_OVR_BP_BP(X)		BIT_ULL(((X) + 4))
895d9b976dSSunil Goutham 
901463f382SLinu Cherian #define CGX_COMMAND_REG			CGXX_SCRATCH1_REG
911463f382SLinu Cherian #define CGX_EVENT_REG			CGXX_SCRATCH0_REG
929b633670SHariprasad Kelam #define CGX_CMD_TIMEOUT			5000 /* msecs */
93f7e086e7SGeetha sowjanya #define DEFAULT_PAUSE_TIME		0x7FF
941463f382SLinu Cherian 
951463f382SLinu Cherian #define CGX_LMAC_FWI			0
961463f382SLinu Cherian 
97f967488dSLinu Cherian enum  cgx_nix_stat_type {
98f967488dSLinu Cherian 	NIX_STATS_RX,
99f967488dSLinu Cherian 	NIX_STATS_TX,
100f967488dSLinu Cherian };
101f967488dSLinu Cherian 
10261071a87SLinu Cherian enum LMAC_TYPE {
10361071a87SLinu Cherian 	LMAC_MODE_SGMII		= 0,
10461071a87SLinu Cherian 	LMAC_MODE_XAUI		= 1,
10561071a87SLinu Cherian 	LMAC_MODE_RXAUI		= 2,
10661071a87SLinu Cherian 	LMAC_MODE_10G_R		= 3,
10761071a87SLinu Cherian 	LMAC_MODE_40G_R		= 4,
10861071a87SLinu Cherian 	LMAC_MODE_QSGMII	= 6,
10961071a87SLinu Cherian 	LMAC_MODE_25G_R		= 7,
11061071a87SLinu Cherian 	LMAC_MODE_50G_R		= 8,
11161071a87SLinu Cherian 	LMAC_MODE_100G_R	= 9,
11261071a87SLinu Cherian 	LMAC_MODE_USXGMII	= 10,
113*5266733cSHariprasad Kelam 	LMAC_MODE_USGMII	= 11,
11461071a87SLinu Cherian 	LMAC_MODE_MAX,
11561071a87SLinu Cherian };
11661071a87SLinu Cherian 
1171463f382SLinu Cherian struct cgx_link_event {
11861071a87SLinu Cherian 	struct cgx_link_user_info link_uinfo;
1191463f382SLinu Cherian 	u8 cgx_id;
1201463f382SLinu Cherian 	u8 lmac_id;
1211463f382SLinu Cherian };
1221463f382SLinu Cherian 
1231463f382SLinu Cherian /**
1241463f382SLinu Cherian  * struct cgx_event_cb
1251463f382SLinu Cherian  * @notify_link_chg:	callback for link change notification
1261463f382SLinu Cherian  * @data:	data passed to callback function
1271463f382SLinu Cherian  */
1281463f382SLinu Cherian struct cgx_event_cb {
1291463f382SLinu Cherian 	int (*notify_link_chg)(struct cgx_link_event *event, void *data);
1301463f382SLinu Cherian 	void *data;
1311463f382SLinu Cherian };
1323a4fa841SLinu Cherian 
1338e22f040SSunil Goutham extern struct pci_driver cgx_driver;
1348e22f040SSunil Goutham 
13512e4c9abSLinu Cherian int cgx_get_cgxcnt_max(void);
136f967488dSLinu Cherian int cgx_get_cgxid(void *cgxd);
1373a4fa841SLinu Cherian int cgx_get_lmac_cnt(void *cgxd);
1383a4fa841SLinu Cherian void *cgx_get_pdata(int cgx_id);
13994d942c5SGeetha sowjanya int cgx_set_pkind(void *cgxd, u8 lmac_id, int pkind);
1401463f382SLinu Cherian int cgx_lmac_evh_register(struct cgx_event_cb *cb, void *cgxd, int lmac_id);
141c9293236SLinu Cherian int cgx_lmac_evh_unregister(void *cgxd, int lmac_id);
14266208910SChristina Jacob int cgx_get_tx_stats(void *cgxd, int lmac_id, int idx, u64 *tx_stat);
14366208910SChristina Jacob int cgx_get_rx_stats(void *cgxd, int lmac_id, int idx, u64 *rx_stat);
1441435f66aSSunil Goutham int cgx_lmac_rx_tx_enable(void *cgxd, int lmac_id, bool enable);
1455d9b976dSSunil Goutham int cgx_lmac_tx_enable(void *cgxd, int lmac_id, bool enable);
14696be2e0dSVidhya Raman int cgx_lmac_addr_set(u8 cgx_id, u8 lmac_id, u8 *mac_addr);
1476f14078eSSunil Kumar Kori int cgx_lmac_addr_reset(u8 cgx_id, u8 lmac_id);
14896be2e0dSVidhya Raman u64 cgx_lmac_addr_get(u8 cgx_id, u8 lmac_id);
1496f14078eSSunil Kumar Kori int cgx_lmac_addr_add(u8 cgx_id, u8 lmac_id, u8 *mac_addr);
1506f14078eSSunil Kumar Kori int cgx_lmac_addr_del(u8 cgx_id, u8 lmac_id, u8 index);
1516f14078eSSunil Kumar Kori int cgx_lmac_addr_max_entries_get(u8 cgx_id, u8 lmac_id);
15296be2e0dSVidhya Raman void cgx_lmac_promisc_config(int cgx_id, int lmac_id, bool enable);
1535d9b976dSSunil Goutham void cgx_lmac_enadis_rx_pause_fwding(void *cgxd, int lmac_id, bool enable);
15423999b30SGeetha sowjanya int cgx_lmac_internal_loopback(void *cgxd, int lmac_id, bool enable);
15561071a87SLinu Cherian int cgx_get_link_info(void *cgxd, int lmac_id,
15661071a87SLinu Cherian 		      struct cgx_link_user_info *linfo);
157d3b2b9abSLinu Cherian int cgx_lmac_linkup_start(void *cgxd);
1584f4eebf2SLinu Cherian int cgx_get_fwdata_base(u64 *base);
159f7e086e7SGeetha sowjanya int cgx_lmac_get_pause_frm(void *cgxd, int lmac_id,
160f7e086e7SGeetha sowjanya 			   u8 *tx_pause, u8 *rx_pause);
161f7e086e7SGeetha sowjanya int cgx_lmac_set_pause_frm(void *cgxd, int lmac_id,
162f7e086e7SGeetha sowjanya 			   u8 tx_pause, u8 rx_pause);
16342157217SZyta Szpak void cgx_lmac_ptp_config(void *cgxd, int lmac_id, bool enable);
164c5a73b63SSubbaraya Sundeep u8 cgx_lmac_get_p2x(int cgx_id, int lmac_id);
16584c4f9caSChristina Jacob int cgx_set_fec(u64 fec, int cgx_id, int lmac_id);
16684c4f9caSChristina Jacob int cgx_get_fec_stats(void *cgxd, int lmac_id, struct cgx_fec_stats_rsp *rsp);
167bd74d4eaSFelix Manlunas int cgx_get_phy_fec_stats(void *cgxd, int lmac_id);
16856b6d539SChristina Jacob int cgx_set_link_mode(void *cgxd, struct cgx_set_link_mode_args args,
16956b6d539SChristina Jacob 		      int cgx_id, int lmac_id);
17091c6945eSHariprasad Kelam u64 cgx_features_get(void *cgxd);
17191c6945eSHariprasad Kelam struct mac_ops *get_mac_ops(void *cgxd);
17291c6945eSHariprasad Kelam int cgx_get_nr_lmacs(void *cgxd);
17391c6945eSHariprasad Kelam u8 cgx_get_lmacid(void *cgxd, u8 lmac_index);
17491c6945eSHariprasad Kelam unsigned long cgx_get_lmac_bmap(void *cgxd);
175242da439SSubbaraya Sundeep void cgx_lmac_write(int cgx_id, int lmac_id, u64 offset, u64 val);
176242da439SSubbaraya Sundeep u64 cgx_lmac_read(int cgx_id, int lmac_id, u64 offset);
1776f14078eSSunil Kumar Kori int cgx_lmac_addr_update(u8 cgx_id, u8 lmac_id, u8 *mac_addr, u8 index);
178dbc52debSHariprasad Kelam u64 cgx_read_dmac_ctrl(void *cgxd, int lmac_id);
179dbc52debSHariprasad Kelam u64 cgx_read_dmac_entry(void *cgxd, int index);
1801121f6b0SSunil Kumar Kori int cgx_lmac_pfc_config(void *cgxd, int lmac_id, u8 tx_pause, u8 rx_pause,
1811121f6b0SSunil Kumar Kori 			u16 pfc_en);
182e7400038SHariprasad Kelam int cgx_lmac_get_pfc_frm_cfg(void *cgxd, int lmac_id, u8 *tx_pause,
183e7400038SHariprasad Kelam 			     u8 *rx_pause);
184e7400038SHariprasad Kelam int verify_lmac_fc_cfg(void *cgxd, int lmac_id, u8 tx_pause, u8 rx_pause,
185e7400038SHariprasad Kelam 		       int pfvf_idx);
1862e3e94c2SHariprasad Kelam int cgx_lmac_reset(void *cgxd, int lmac_id, u8 pf_req_flr);
1878e22f040SSunil Goutham #endif /* CGX_H */
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