1 // SPDX-License-Identifier: GPL-2.0 2 /* Marvell OcteonTx2 CGX driver 3 * 4 * Copyright (C) 2018 Marvell International Ltd. 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 */ 10 11 #include <linux/acpi.h> 12 #include <linux/module.h> 13 #include <linux/interrupt.h> 14 #include <linux/pci.h> 15 #include <linux/netdevice.h> 16 #include <linux/etherdevice.h> 17 #include <linux/ethtool.h> 18 #include <linux/phy.h> 19 #include <linux/of.h> 20 #include <linux/of_mdio.h> 21 #include <linux/of_net.h> 22 23 #include "cgx.h" 24 #include "rvu.h" 25 #include "lmac_common.h" 26 27 #define DRV_NAME "Marvell-CGX/RPM" 28 #define DRV_STRING "Marvell CGX/RPM Driver" 29 30 static LIST_HEAD(cgx_list); 31 32 /* Convert firmware speed encoding to user format(Mbps) */ 33 static u32 cgx_speed_mbps[CGX_LINK_SPEED_MAX]; 34 35 /* Convert firmware lmac type encoding to string */ 36 static char *cgx_lmactype_string[LMAC_MODE_MAX]; 37 38 /* CGX PHY management internal APIs */ 39 static int cgx_fwi_link_change(struct cgx *cgx, int lmac_id, bool en); 40 41 /* Supported devices */ 42 static const struct pci_device_id cgx_id_table[] = { 43 { PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_OCTEONTX2_CGX) }, 44 { PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_CN10K_RPM) }, 45 { 0, } /* end of table */ 46 }; 47 48 MODULE_DEVICE_TABLE(pci, cgx_id_table); 49 50 static bool is_dev_rpm(void *cgxd) 51 { 52 struct cgx *cgx = cgxd; 53 54 return (cgx->pdev->device == PCI_DEVID_CN10K_RPM); 55 } 56 57 bool is_lmac_valid(struct cgx *cgx, int lmac_id) 58 { 59 if (!cgx || lmac_id < 0 || lmac_id >= MAX_LMAC_PER_CGX) 60 return false; 61 return test_bit(lmac_id, &cgx->lmac_bmap); 62 } 63 64 struct mac_ops *get_mac_ops(void *cgxd) 65 { 66 if (!cgxd) 67 return cgxd; 68 69 return ((struct cgx *)cgxd)->mac_ops; 70 } 71 72 void cgx_write(struct cgx *cgx, u64 lmac, u64 offset, u64 val) 73 { 74 writeq(val, cgx->reg_base + (lmac << cgx->mac_ops->lmac_offset) + 75 offset); 76 } 77 78 u64 cgx_read(struct cgx *cgx, u64 lmac, u64 offset) 79 { 80 return readq(cgx->reg_base + (lmac << cgx->mac_ops->lmac_offset) + 81 offset); 82 } 83 84 struct lmac *lmac_pdata(u8 lmac_id, struct cgx *cgx) 85 { 86 if (!cgx || lmac_id >= MAX_LMAC_PER_CGX) 87 return NULL; 88 89 return cgx->lmac_idmap[lmac_id]; 90 } 91 92 int cgx_get_cgxcnt_max(void) 93 { 94 struct cgx *cgx_dev; 95 int idmax = -ENODEV; 96 97 list_for_each_entry(cgx_dev, &cgx_list, cgx_list) 98 if (cgx_dev->cgx_id > idmax) 99 idmax = cgx_dev->cgx_id; 100 101 if (idmax < 0) 102 return 0; 103 104 return idmax + 1; 105 } 106 107 int cgx_get_lmac_cnt(void *cgxd) 108 { 109 struct cgx *cgx = cgxd; 110 111 if (!cgx) 112 return -ENODEV; 113 114 return cgx->lmac_count; 115 } 116 117 void *cgx_get_pdata(int cgx_id) 118 { 119 struct cgx *cgx_dev; 120 121 list_for_each_entry(cgx_dev, &cgx_list, cgx_list) { 122 if (cgx_dev->cgx_id == cgx_id) 123 return cgx_dev; 124 } 125 return NULL; 126 } 127 128 void cgx_lmac_write(int cgx_id, int lmac_id, u64 offset, u64 val) 129 { 130 struct cgx *cgx_dev = cgx_get_pdata(cgx_id); 131 132 cgx_write(cgx_dev, lmac_id, offset, val); 133 } 134 135 u64 cgx_lmac_read(int cgx_id, int lmac_id, u64 offset) 136 { 137 struct cgx *cgx_dev = cgx_get_pdata(cgx_id); 138 139 return cgx_read(cgx_dev, lmac_id, offset); 140 } 141 142 int cgx_get_cgxid(void *cgxd) 143 { 144 struct cgx *cgx = cgxd; 145 146 if (!cgx) 147 return -EINVAL; 148 149 return cgx->cgx_id; 150 } 151 152 u8 cgx_lmac_get_p2x(int cgx_id, int lmac_id) 153 { 154 struct cgx *cgx_dev = cgx_get_pdata(cgx_id); 155 u64 cfg; 156 157 cfg = cgx_read(cgx_dev, lmac_id, CGXX_CMRX_CFG); 158 159 return (cfg & CMR_P2X_SEL_MASK) >> CMR_P2X_SEL_SHIFT; 160 } 161 162 /* Ensure the required lock for event queue(where asynchronous events are 163 * posted) is acquired before calling this API. Else an asynchronous event(with 164 * latest link status) can reach the destination before this function returns 165 * and could make the link status appear wrong. 166 */ 167 int cgx_get_link_info(void *cgxd, int lmac_id, 168 struct cgx_link_user_info *linfo) 169 { 170 struct lmac *lmac = lmac_pdata(lmac_id, cgxd); 171 172 if (!lmac) 173 return -ENODEV; 174 175 *linfo = lmac->link_info; 176 return 0; 177 } 178 179 static u64 mac2u64 (u8 *mac_addr) 180 { 181 u64 mac = 0; 182 int index; 183 184 for (index = ETH_ALEN - 1; index >= 0; index--) 185 mac |= ((u64)*mac_addr++) << (8 * index); 186 return mac; 187 } 188 189 int cgx_lmac_addr_set(u8 cgx_id, u8 lmac_id, u8 *mac_addr) 190 { 191 struct cgx *cgx_dev = cgx_get_pdata(cgx_id); 192 struct mac_ops *mac_ops; 193 u64 cfg; 194 195 mac_ops = cgx_dev->mac_ops; 196 /* copy 6bytes from macaddr */ 197 /* memcpy(&cfg, mac_addr, 6); */ 198 199 cfg = mac2u64 (mac_addr); 200 201 cgx_write(cgx_dev, 0, (CGXX_CMRX_RX_DMAC_CAM0 + (lmac_id * 0x8)), 202 cfg | CGX_DMAC_CAM_ADDR_ENABLE | ((u64)lmac_id << 49)); 203 204 cfg = cgx_read(cgx_dev, lmac_id, CGXX_CMRX_RX_DMAC_CTL0); 205 cfg |= CGX_DMAC_CTL0_CAM_ENABLE; 206 cgx_write(cgx_dev, lmac_id, CGXX_CMRX_RX_DMAC_CTL0, cfg); 207 208 return 0; 209 } 210 211 u64 cgx_lmac_addr_get(u8 cgx_id, u8 lmac_id) 212 { 213 struct cgx *cgx_dev = cgx_get_pdata(cgx_id); 214 struct mac_ops *mac_ops; 215 u64 cfg; 216 217 mac_ops = cgx_dev->mac_ops; 218 219 cfg = cgx_read(cgx_dev, 0, CGXX_CMRX_RX_DMAC_CAM0 + lmac_id * 0x8); 220 return cfg & CGX_RX_DMAC_ADR_MASK; 221 } 222 223 int cgx_set_pkind(void *cgxd, u8 lmac_id, int pkind) 224 { 225 struct cgx *cgx = cgxd; 226 227 if (!is_lmac_valid(cgx, lmac_id)) 228 return -ENODEV; 229 230 cgx_write(cgx, lmac_id, CGXX_CMRX_RX_ID_MAP, (pkind & 0x3F)); 231 return 0; 232 } 233 234 static u8 cgx_get_lmac_type(void *cgxd, int lmac_id) 235 { 236 struct cgx *cgx = cgxd; 237 u64 cfg; 238 239 cfg = cgx_read(cgx, lmac_id, CGXX_CMRX_CFG); 240 return (cfg >> CGX_LMAC_TYPE_SHIFT) & CGX_LMAC_TYPE_MASK; 241 } 242 243 /* Configure CGX LMAC in internal loopback mode */ 244 int cgx_lmac_internal_loopback(void *cgxd, int lmac_id, bool enable) 245 { 246 struct cgx *cgx = cgxd; 247 u8 lmac_type; 248 u64 cfg; 249 250 if (!is_lmac_valid(cgx, lmac_id)) 251 return -ENODEV; 252 253 lmac_type = cgx->mac_ops->get_lmac_type(cgx, lmac_id); 254 if (lmac_type == LMAC_MODE_SGMII || lmac_type == LMAC_MODE_QSGMII) { 255 cfg = cgx_read(cgx, lmac_id, CGXX_GMP_PCS_MRX_CTL); 256 if (enable) 257 cfg |= CGXX_GMP_PCS_MRX_CTL_LBK; 258 else 259 cfg &= ~CGXX_GMP_PCS_MRX_CTL_LBK; 260 cgx_write(cgx, lmac_id, CGXX_GMP_PCS_MRX_CTL, cfg); 261 } else { 262 cfg = cgx_read(cgx, lmac_id, CGXX_SPUX_CONTROL1); 263 if (enable) 264 cfg |= CGXX_SPUX_CONTROL1_LBK; 265 else 266 cfg &= ~CGXX_SPUX_CONTROL1_LBK; 267 cgx_write(cgx, lmac_id, CGXX_SPUX_CONTROL1, cfg); 268 } 269 return 0; 270 } 271 272 void cgx_lmac_promisc_config(int cgx_id, int lmac_id, bool enable) 273 { 274 struct cgx *cgx = cgx_get_pdata(cgx_id); 275 struct mac_ops *mac_ops; 276 u64 cfg = 0; 277 278 if (!cgx) 279 return; 280 281 mac_ops = cgx->mac_ops; 282 if (enable) { 283 /* Enable promiscuous mode on LMAC */ 284 cfg = cgx_read(cgx, lmac_id, CGXX_CMRX_RX_DMAC_CTL0); 285 cfg &= ~(CGX_DMAC_CAM_ACCEPT | CGX_DMAC_MCAST_MODE); 286 cfg |= CGX_DMAC_BCAST_MODE; 287 cgx_write(cgx, lmac_id, CGXX_CMRX_RX_DMAC_CTL0, cfg); 288 289 cfg = cgx_read(cgx, 0, 290 (CGXX_CMRX_RX_DMAC_CAM0 + lmac_id * 0x8)); 291 cfg &= ~CGX_DMAC_CAM_ADDR_ENABLE; 292 cgx_write(cgx, 0, 293 (CGXX_CMRX_RX_DMAC_CAM0 + lmac_id * 0x8), cfg); 294 } else { 295 /* Disable promiscuous mode */ 296 cfg = cgx_read(cgx, lmac_id, CGXX_CMRX_RX_DMAC_CTL0); 297 cfg |= CGX_DMAC_CAM_ACCEPT | CGX_DMAC_MCAST_MODE; 298 cgx_write(cgx, lmac_id, CGXX_CMRX_RX_DMAC_CTL0, cfg); 299 cfg = cgx_read(cgx, 0, 300 (CGXX_CMRX_RX_DMAC_CAM0 + lmac_id * 0x8)); 301 cfg |= CGX_DMAC_CAM_ADDR_ENABLE; 302 cgx_write(cgx, 0, 303 (CGXX_CMRX_RX_DMAC_CAM0 + lmac_id * 0x8), cfg); 304 } 305 } 306 307 /* Enable or disable forwarding received pause frames to Tx block */ 308 void cgx_lmac_enadis_rx_pause_fwding(void *cgxd, int lmac_id, bool enable) 309 { 310 struct cgx *cgx = cgxd; 311 u64 cfg; 312 313 if (!cgx) 314 return; 315 316 if (enable) { 317 cfg = cgx_read(cgx, lmac_id, CGXX_GMP_GMI_RXX_FRM_CTL); 318 cfg |= CGX_GMP_GMI_RXX_FRM_CTL_CTL_BCK; 319 cgx_write(cgx, lmac_id, CGXX_GMP_GMI_RXX_FRM_CTL, cfg); 320 321 cfg = cgx_read(cgx, lmac_id, CGXX_SMUX_RX_FRM_CTL); 322 cfg |= CGX_SMUX_RX_FRM_CTL_CTL_BCK; 323 cgx_write(cgx, lmac_id, CGXX_SMUX_RX_FRM_CTL, cfg); 324 } else { 325 cfg = cgx_read(cgx, lmac_id, CGXX_GMP_GMI_RXX_FRM_CTL); 326 cfg &= ~CGX_GMP_GMI_RXX_FRM_CTL_CTL_BCK; 327 cgx_write(cgx, lmac_id, CGXX_GMP_GMI_RXX_FRM_CTL, cfg); 328 329 cfg = cgx_read(cgx, lmac_id, CGXX_SMUX_RX_FRM_CTL); 330 cfg &= ~CGX_SMUX_RX_FRM_CTL_CTL_BCK; 331 cgx_write(cgx, lmac_id, CGXX_SMUX_RX_FRM_CTL, cfg); 332 } 333 } 334 335 int cgx_get_rx_stats(void *cgxd, int lmac_id, int idx, u64 *rx_stat) 336 { 337 struct cgx *cgx = cgxd; 338 339 if (!is_lmac_valid(cgx, lmac_id)) 340 return -ENODEV; 341 *rx_stat = cgx_read(cgx, lmac_id, CGXX_CMRX_RX_STAT0 + (idx * 8)); 342 return 0; 343 } 344 345 int cgx_get_tx_stats(void *cgxd, int lmac_id, int idx, u64 *tx_stat) 346 { 347 struct cgx *cgx = cgxd; 348 349 if (!is_lmac_valid(cgx, lmac_id)) 350 return -ENODEV; 351 *tx_stat = cgx_read(cgx, lmac_id, CGXX_CMRX_TX_STAT0 + (idx * 8)); 352 return 0; 353 } 354 355 u64 cgx_features_get(void *cgxd) 356 { 357 return ((struct cgx *)cgxd)->hw_features; 358 } 359 360 static int cgx_set_fec_stats_count(struct cgx_link_user_info *linfo) 361 { 362 if (!linfo->fec) 363 return 0; 364 365 switch (linfo->lmac_type_id) { 366 case LMAC_MODE_SGMII: 367 case LMAC_MODE_XAUI: 368 case LMAC_MODE_RXAUI: 369 case LMAC_MODE_QSGMII: 370 return 0; 371 case LMAC_MODE_10G_R: 372 case LMAC_MODE_25G_R: 373 case LMAC_MODE_100G_R: 374 case LMAC_MODE_USXGMII: 375 return 1; 376 case LMAC_MODE_40G_R: 377 return 4; 378 case LMAC_MODE_50G_R: 379 if (linfo->fec == OTX2_FEC_BASER) 380 return 2; 381 else 382 return 1; 383 default: 384 return 0; 385 } 386 } 387 388 int cgx_get_fec_stats(void *cgxd, int lmac_id, struct cgx_fec_stats_rsp *rsp) 389 { 390 int stats, fec_stats_count = 0; 391 int corr_reg, uncorr_reg; 392 struct cgx *cgx = cgxd; 393 394 if (!cgx || lmac_id >= cgx->lmac_count) 395 return -ENODEV; 396 fec_stats_count = 397 cgx_set_fec_stats_count(&cgx->lmac_idmap[lmac_id]->link_info); 398 if (cgx->lmac_idmap[lmac_id]->link_info.fec == OTX2_FEC_BASER) { 399 corr_reg = CGXX_SPUX_LNX_FEC_CORR_BLOCKS; 400 uncorr_reg = CGXX_SPUX_LNX_FEC_UNCORR_BLOCKS; 401 } else { 402 corr_reg = CGXX_SPUX_RSFEC_CORR; 403 uncorr_reg = CGXX_SPUX_RSFEC_UNCORR; 404 } 405 for (stats = 0; stats < fec_stats_count; stats++) { 406 rsp->fec_corr_blks += 407 cgx_read(cgx, lmac_id, corr_reg + (stats * 8)); 408 rsp->fec_uncorr_blks += 409 cgx_read(cgx, lmac_id, uncorr_reg + (stats * 8)); 410 } 411 return 0; 412 } 413 414 int cgx_lmac_rx_tx_enable(void *cgxd, int lmac_id, bool enable) 415 { 416 struct cgx *cgx = cgxd; 417 u64 cfg; 418 419 if (!is_lmac_valid(cgx, lmac_id)) 420 return -ENODEV; 421 422 cfg = cgx_read(cgx, lmac_id, CGXX_CMRX_CFG); 423 if (enable) 424 cfg |= CMR_EN | DATA_PKT_RX_EN | DATA_PKT_TX_EN; 425 else 426 cfg &= ~(CMR_EN | DATA_PKT_RX_EN | DATA_PKT_TX_EN); 427 cgx_write(cgx, lmac_id, CGXX_CMRX_CFG, cfg); 428 return 0; 429 } 430 431 int cgx_lmac_tx_enable(void *cgxd, int lmac_id, bool enable) 432 { 433 struct cgx *cgx = cgxd; 434 u64 cfg, last; 435 436 if (!is_lmac_valid(cgx, lmac_id)) 437 return -ENODEV; 438 439 cfg = cgx_read(cgx, lmac_id, CGXX_CMRX_CFG); 440 last = cfg; 441 if (enable) 442 cfg |= DATA_PKT_TX_EN; 443 else 444 cfg &= ~DATA_PKT_TX_EN; 445 446 if (cfg != last) 447 cgx_write(cgx, lmac_id, CGXX_CMRX_CFG, cfg); 448 return !!(last & DATA_PKT_TX_EN); 449 } 450 451 static int cgx_lmac_get_pause_frm_status(void *cgxd, int lmac_id, 452 u8 *tx_pause, u8 *rx_pause) 453 { 454 struct cgx *cgx = cgxd; 455 u64 cfg; 456 457 if (is_dev_rpm(cgx)) 458 return 0; 459 460 if (!is_lmac_valid(cgx, lmac_id)) 461 return -ENODEV; 462 463 cfg = cgx_read(cgx, lmac_id, CGXX_SMUX_RX_FRM_CTL); 464 *rx_pause = !!(cfg & CGX_SMUX_RX_FRM_CTL_CTL_BCK); 465 466 cfg = cgx_read(cgx, lmac_id, CGXX_SMUX_TX_CTL); 467 *tx_pause = !!(cfg & CGX_SMUX_TX_CTL_L2P_BP_CONV); 468 return 0; 469 } 470 471 static int cgx_lmac_enadis_pause_frm(void *cgxd, int lmac_id, 472 u8 tx_pause, u8 rx_pause) 473 { 474 struct cgx *cgx = cgxd; 475 u64 cfg; 476 477 if (is_dev_rpm(cgx)) 478 return 0; 479 480 if (!is_lmac_valid(cgx, lmac_id)) 481 return -ENODEV; 482 483 cfg = cgx_read(cgx, lmac_id, CGXX_SMUX_RX_FRM_CTL); 484 cfg &= ~CGX_SMUX_RX_FRM_CTL_CTL_BCK; 485 cfg |= rx_pause ? CGX_SMUX_RX_FRM_CTL_CTL_BCK : 0x0; 486 cgx_write(cgx, lmac_id, CGXX_SMUX_RX_FRM_CTL, cfg); 487 488 cfg = cgx_read(cgx, lmac_id, CGXX_SMUX_TX_CTL); 489 cfg &= ~CGX_SMUX_TX_CTL_L2P_BP_CONV; 490 cfg |= tx_pause ? CGX_SMUX_TX_CTL_L2P_BP_CONV : 0x0; 491 cgx_write(cgx, lmac_id, CGXX_SMUX_TX_CTL, cfg); 492 493 cfg = cgx_read(cgx, 0, CGXX_CMR_RX_OVR_BP); 494 if (tx_pause) { 495 cfg &= ~CGX_CMR_RX_OVR_BP_EN(lmac_id); 496 } else { 497 cfg |= CGX_CMR_RX_OVR_BP_EN(lmac_id); 498 cfg &= ~CGX_CMR_RX_OVR_BP_BP(lmac_id); 499 } 500 cgx_write(cgx, 0, CGXX_CMR_RX_OVR_BP, cfg); 501 return 0; 502 } 503 504 static void cgx_lmac_pause_frm_config(void *cgxd, int lmac_id, bool enable) 505 { 506 struct cgx *cgx = cgxd; 507 u64 cfg; 508 509 if (!is_lmac_valid(cgx, lmac_id)) 510 return; 511 if (enable) { 512 /* Enable receive pause frames */ 513 cfg = cgx_read(cgx, lmac_id, CGXX_SMUX_RX_FRM_CTL); 514 cfg |= CGX_SMUX_RX_FRM_CTL_CTL_BCK; 515 cgx_write(cgx, lmac_id, CGXX_SMUX_RX_FRM_CTL, cfg); 516 517 cfg = cgx_read(cgx, lmac_id, CGXX_GMP_GMI_RXX_FRM_CTL); 518 cfg |= CGX_GMP_GMI_RXX_FRM_CTL_CTL_BCK; 519 cgx_write(cgx, lmac_id, CGXX_GMP_GMI_RXX_FRM_CTL, cfg); 520 521 /* Enable pause frames transmission */ 522 cfg = cgx_read(cgx, lmac_id, CGXX_SMUX_TX_CTL); 523 cfg |= CGX_SMUX_TX_CTL_L2P_BP_CONV; 524 cgx_write(cgx, lmac_id, CGXX_SMUX_TX_CTL, cfg); 525 526 /* Set pause time and interval */ 527 cgx_write(cgx, lmac_id, CGXX_SMUX_TX_PAUSE_PKT_TIME, 528 DEFAULT_PAUSE_TIME); 529 cfg = cgx_read(cgx, lmac_id, CGXX_SMUX_TX_PAUSE_PKT_INTERVAL); 530 cfg &= ~0xFFFFULL; 531 cgx_write(cgx, lmac_id, CGXX_SMUX_TX_PAUSE_PKT_INTERVAL, 532 cfg | (DEFAULT_PAUSE_TIME / 2)); 533 534 cgx_write(cgx, lmac_id, CGXX_GMP_GMI_TX_PAUSE_PKT_TIME, 535 DEFAULT_PAUSE_TIME); 536 537 cfg = cgx_read(cgx, lmac_id, 538 CGXX_GMP_GMI_TX_PAUSE_PKT_INTERVAL); 539 cfg &= ~0xFFFFULL; 540 cgx_write(cgx, lmac_id, CGXX_GMP_GMI_TX_PAUSE_PKT_INTERVAL, 541 cfg | (DEFAULT_PAUSE_TIME / 2)); 542 } else { 543 /* ALL pause frames received are completely ignored */ 544 cfg = cgx_read(cgx, lmac_id, CGXX_SMUX_RX_FRM_CTL); 545 cfg &= ~CGX_SMUX_RX_FRM_CTL_CTL_BCK; 546 cgx_write(cgx, lmac_id, CGXX_SMUX_RX_FRM_CTL, cfg); 547 548 cfg = cgx_read(cgx, lmac_id, CGXX_GMP_GMI_RXX_FRM_CTL); 549 cfg &= ~CGX_GMP_GMI_RXX_FRM_CTL_CTL_BCK; 550 cgx_write(cgx, lmac_id, CGXX_GMP_GMI_RXX_FRM_CTL, cfg); 551 552 /* Disable pause frames transmission */ 553 cfg = cgx_read(cgx, lmac_id, CGXX_SMUX_TX_CTL); 554 cfg &= ~CGX_SMUX_TX_CTL_L2P_BP_CONV; 555 cgx_write(cgx, lmac_id, CGXX_SMUX_TX_CTL, cfg); 556 } 557 } 558 559 void cgx_lmac_ptp_config(void *cgxd, int lmac_id, bool enable) 560 { 561 struct cgx *cgx = cgxd; 562 u64 cfg; 563 564 if (!cgx) 565 return; 566 567 if (is_dev_rpm(cgx)) 568 return; 569 570 if (enable) { 571 /* Enable inbound PTP timestamping */ 572 cfg = cgx_read(cgx, lmac_id, CGXX_GMP_GMI_RXX_FRM_CTL); 573 cfg |= CGX_GMP_GMI_RXX_FRM_CTL_PTP_MODE; 574 cgx_write(cgx, lmac_id, CGXX_GMP_GMI_RXX_FRM_CTL, cfg); 575 576 cfg = cgx_read(cgx, lmac_id, CGXX_SMUX_RX_FRM_CTL); 577 cfg |= CGX_SMUX_RX_FRM_CTL_PTP_MODE; 578 cgx_write(cgx, lmac_id, CGXX_SMUX_RX_FRM_CTL, cfg); 579 } else { 580 /* Disable inbound PTP stamping */ 581 cfg = cgx_read(cgx, lmac_id, CGXX_GMP_GMI_RXX_FRM_CTL); 582 cfg &= ~CGX_GMP_GMI_RXX_FRM_CTL_PTP_MODE; 583 cgx_write(cgx, lmac_id, CGXX_GMP_GMI_RXX_FRM_CTL, cfg); 584 585 cfg = cgx_read(cgx, lmac_id, CGXX_SMUX_RX_FRM_CTL); 586 cfg &= ~CGX_SMUX_RX_FRM_CTL_PTP_MODE; 587 cgx_write(cgx, lmac_id, CGXX_SMUX_RX_FRM_CTL, cfg); 588 } 589 } 590 591 /* CGX Firmware interface low level support */ 592 int cgx_fwi_cmd_send(u64 req, u64 *resp, struct lmac *lmac) 593 { 594 struct cgx *cgx = lmac->cgx; 595 struct device *dev; 596 int err = 0; 597 u64 cmd; 598 599 /* Ensure no other command is in progress */ 600 err = mutex_lock_interruptible(&lmac->cmd_lock); 601 if (err) 602 return err; 603 604 /* Ensure command register is free */ 605 cmd = cgx_read(cgx, lmac->lmac_id, CGX_COMMAND_REG); 606 if (FIELD_GET(CMDREG_OWN, cmd) != CGX_CMD_OWN_NS) { 607 err = -EBUSY; 608 goto unlock; 609 } 610 611 /* Update ownership in command request */ 612 req = FIELD_SET(CMDREG_OWN, CGX_CMD_OWN_FIRMWARE, req); 613 614 /* Mark this lmac as pending, before we start */ 615 lmac->cmd_pend = true; 616 617 /* Start command in hardware */ 618 cgx_write(cgx, lmac->lmac_id, CGX_COMMAND_REG, req); 619 620 /* Ensure command is completed without errors */ 621 if (!wait_event_timeout(lmac->wq_cmd_cmplt, !lmac->cmd_pend, 622 msecs_to_jiffies(CGX_CMD_TIMEOUT))) { 623 dev = &cgx->pdev->dev; 624 dev_err(dev, "cgx port %d:%d cmd timeout\n", 625 cgx->cgx_id, lmac->lmac_id); 626 err = -EIO; 627 goto unlock; 628 } 629 630 /* we have a valid command response */ 631 smp_rmb(); /* Ensure the latest updates are visible */ 632 *resp = lmac->resp; 633 634 unlock: 635 mutex_unlock(&lmac->cmd_lock); 636 637 return err; 638 } 639 640 int cgx_fwi_cmd_generic(u64 req, u64 *resp, struct cgx *cgx, int lmac_id) 641 { 642 struct lmac *lmac; 643 int err; 644 645 lmac = lmac_pdata(lmac_id, cgx); 646 if (!lmac) 647 return -ENODEV; 648 649 err = cgx_fwi_cmd_send(req, resp, lmac); 650 651 /* Check for valid response */ 652 if (!err) { 653 if (FIELD_GET(EVTREG_STAT, *resp) == CGX_STAT_FAIL) 654 return -EIO; 655 else 656 return 0; 657 } 658 659 return err; 660 } 661 662 static inline void cgx_link_usertable_init(void) 663 { 664 cgx_speed_mbps[CGX_LINK_NONE] = 0; 665 cgx_speed_mbps[CGX_LINK_10M] = 10; 666 cgx_speed_mbps[CGX_LINK_100M] = 100; 667 cgx_speed_mbps[CGX_LINK_1G] = 1000; 668 cgx_speed_mbps[CGX_LINK_2HG] = 2500; 669 cgx_speed_mbps[CGX_LINK_5G] = 5000; 670 cgx_speed_mbps[CGX_LINK_10G] = 10000; 671 cgx_speed_mbps[CGX_LINK_20G] = 20000; 672 cgx_speed_mbps[CGX_LINK_25G] = 25000; 673 cgx_speed_mbps[CGX_LINK_40G] = 40000; 674 cgx_speed_mbps[CGX_LINK_50G] = 50000; 675 cgx_speed_mbps[CGX_LINK_80G] = 80000; 676 cgx_speed_mbps[CGX_LINK_100G] = 100000; 677 678 cgx_lmactype_string[LMAC_MODE_SGMII] = "SGMII"; 679 cgx_lmactype_string[LMAC_MODE_XAUI] = "XAUI"; 680 cgx_lmactype_string[LMAC_MODE_RXAUI] = "RXAUI"; 681 cgx_lmactype_string[LMAC_MODE_10G_R] = "10G_R"; 682 cgx_lmactype_string[LMAC_MODE_40G_R] = "40G_R"; 683 cgx_lmactype_string[LMAC_MODE_QSGMII] = "QSGMII"; 684 cgx_lmactype_string[LMAC_MODE_25G_R] = "25G_R"; 685 cgx_lmactype_string[LMAC_MODE_50G_R] = "50G_R"; 686 cgx_lmactype_string[LMAC_MODE_100G_R] = "100G_R"; 687 cgx_lmactype_string[LMAC_MODE_USXGMII] = "USXGMII"; 688 } 689 690 static int cgx_link_usertable_index_map(int speed) 691 { 692 switch (speed) { 693 case SPEED_10: 694 return CGX_LINK_10M; 695 case SPEED_100: 696 return CGX_LINK_100M; 697 case SPEED_1000: 698 return CGX_LINK_1G; 699 case SPEED_2500: 700 return CGX_LINK_2HG; 701 case SPEED_5000: 702 return CGX_LINK_5G; 703 case SPEED_10000: 704 return CGX_LINK_10G; 705 case SPEED_20000: 706 return CGX_LINK_20G; 707 case SPEED_25000: 708 return CGX_LINK_25G; 709 case SPEED_40000: 710 return CGX_LINK_40G; 711 case SPEED_50000: 712 return CGX_LINK_50G; 713 case 80000: 714 return CGX_LINK_80G; 715 case SPEED_100000: 716 return CGX_LINK_100G; 717 case SPEED_UNKNOWN: 718 return CGX_LINK_NONE; 719 } 720 return CGX_LINK_NONE; 721 } 722 723 static void set_mod_args(struct cgx_set_link_mode_args *args, 724 u32 speed, u8 duplex, u8 autoneg, u64 mode) 725 { 726 /* Fill default values incase of user did not pass 727 * valid parameters 728 */ 729 if (args->duplex == DUPLEX_UNKNOWN) 730 args->duplex = duplex; 731 if (args->speed == SPEED_UNKNOWN) 732 args->speed = speed; 733 if (args->an == AUTONEG_UNKNOWN) 734 args->an = autoneg; 735 args->mode = mode; 736 args->ports = 0; 737 } 738 739 static void otx2_map_ethtool_link_modes(u64 bitmask, 740 struct cgx_set_link_mode_args *args) 741 { 742 switch (bitmask) { 743 case ETHTOOL_LINK_MODE_10baseT_Half_BIT: 744 set_mod_args(args, 10, 1, 1, BIT_ULL(CGX_MODE_SGMII)); 745 break; 746 case ETHTOOL_LINK_MODE_10baseT_Full_BIT: 747 set_mod_args(args, 10, 0, 1, BIT_ULL(CGX_MODE_SGMII)); 748 break; 749 case ETHTOOL_LINK_MODE_100baseT_Half_BIT: 750 set_mod_args(args, 100, 1, 1, BIT_ULL(CGX_MODE_SGMII)); 751 break; 752 case ETHTOOL_LINK_MODE_100baseT_Full_BIT: 753 set_mod_args(args, 100, 0, 1, BIT_ULL(CGX_MODE_SGMII)); 754 break; 755 case ETHTOOL_LINK_MODE_1000baseT_Half_BIT: 756 set_mod_args(args, 1000, 1, 1, BIT_ULL(CGX_MODE_SGMII)); 757 break; 758 case ETHTOOL_LINK_MODE_1000baseT_Full_BIT: 759 set_mod_args(args, 1000, 0, 1, BIT_ULL(CGX_MODE_SGMII)); 760 break; 761 case ETHTOOL_LINK_MODE_1000baseX_Full_BIT: 762 set_mod_args(args, 1000, 0, 0, BIT_ULL(CGX_MODE_1000_BASEX)); 763 break; 764 case ETHTOOL_LINK_MODE_10000baseT_Full_BIT: 765 set_mod_args(args, 1000, 0, 1, BIT_ULL(CGX_MODE_QSGMII)); 766 break; 767 case ETHTOOL_LINK_MODE_10000baseSR_Full_BIT: 768 set_mod_args(args, 10000, 0, 0, BIT_ULL(CGX_MODE_10G_C2C)); 769 break; 770 case ETHTOOL_LINK_MODE_10000baseLR_Full_BIT: 771 set_mod_args(args, 10000, 0, 0, BIT_ULL(CGX_MODE_10G_C2M)); 772 break; 773 case ETHTOOL_LINK_MODE_10000baseKR_Full_BIT: 774 set_mod_args(args, 10000, 0, 1, BIT_ULL(CGX_MODE_10G_KR)); 775 break; 776 case ETHTOOL_LINK_MODE_25000baseSR_Full_BIT: 777 set_mod_args(args, 25000, 0, 0, BIT_ULL(CGX_MODE_25G_C2C)); 778 break; 779 case ETHTOOL_LINK_MODE_25000baseCR_Full_BIT: 780 set_mod_args(args, 25000, 0, 1, BIT_ULL(CGX_MODE_25G_CR)); 781 break; 782 case ETHTOOL_LINK_MODE_25000baseKR_Full_BIT: 783 set_mod_args(args, 25000, 0, 1, BIT_ULL(CGX_MODE_25G_KR)); 784 break; 785 case ETHTOOL_LINK_MODE_40000baseSR4_Full_BIT: 786 set_mod_args(args, 40000, 0, 0, BIT_ULL(CGX_MODE_40G_C2C)); 787 break; 788 case ETHTOOL_LINK_MODE_40000baseLR4_Full_BIT: 789 set_mod_args(args, 40000, 0, 0, BIT_ULL(CGX_MODE_40G_C2M)); 790 break; 791 case ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT: 792 set_mod_args(args, 40000, 0, 1, BIT_ULL(CGX_MODE_40G_CR4)); 793 break; 794 case ETHTOOL_LINK_MODE_40000baseKR4_Full_BIT: 795 set_mod_args(args, 40000, 0, 1, BIT_ULL(CGX_MODE_40G_KR4)); 796 break; 797 case ETHTOOL_LINK_MODE_50000baseSR_Full_BIT: 798 set_mod_args(args, 50000, 0, 0, BIT_ULL(CGX_MODE_50G_C2C)); 799 break; 800 case ETHTOOL_LINK_MODE_50000baseLR_ER_FR_Full_BIT: 801 set_mod_args(args, 50000, 0, 0, BIT_ULL(CGX_MODE_50G_C2M)); 802 break; 803 case ETHTOOL_LINK_MODE_50000baseCR_Full_BIT: 804 set_mod_args(args, 50000, 0, 1, BIT_ULL(CGX_MODE_50G_CR)); 805 break; 806 case ETHTOOL_LINK_MODE_50000baseKR_Full_BIT: 807 set_mod_args(args, 50000, 0, 1, BIT_ULL(CGX_MODE_50G_KR)); 808 break; 809 case ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT: 810 set_mod_args(args, 100000, 0, 0, BIT_ULL(CGX_MODE_100G_C2C)); 811 break; 812 case ETHTOOL_LINK_MODE_100000baseLR4_ER4_Full_BIT: 813 set_mod_args(args, 100000, 0, 0, BIT_ULL(CGX_MODE_100G_C2M)); 814 break; 815 case ETHTOOL_LINK_MODE_100000baseCR4_Full_BIT: 816 set_mod_args(args, 100000, 0, 1, BIT_ULL(CGX_MODE_100G_CR4)); 817 break; 818 case ETHTOOL_LINK_MODE_100000baseKR4_Full_BIT: 819 set_mod_args(args, 100000, 0, 1, BIT_ULL(CGX_MODE_100G_KR4)); 820 break; 821 default: 822 set_mod_args(args, 0, 1, 0, BIT_ULL(CGX_MODE_MAX)); 823 break; 824 } 825 } 826 827 static inline void link_status_user_format(u64 lstat, 828 struct cgx_link_user_info *linfo, 829 struct cgx *cgx, u8 lmac_id) 830 { 831 char *lmac_string; 832 833 linfo->link_up = FIELD_GET(RESP_LINKSTAT_UP, lstat); 834 linfo->full_duplex = FIELD_GET(RESP_LINKSTAT_FDUPLEX, lstat); 835 linfo->speed = cgx_speed_mbps[FIELD_GET(RESP_LINKSTAT_SPEED, lstat)]; 836 linfo->an = FIELD_GET(RESP_LINKSTAT_AN, lstat); 837 linfo->fec = FIELD_GET(RESP_LINKSTAT_FEC, lstat); 838 linfo->lmac_type_id = cgx_get_lmac_type(cgx, lmac_id); 839 lmac_string = cgx_lmactype_string[linfo->lmac_type_id]; 840 strncpy(linfo->lmac_type, lmac_string, LMACTYPE_STR_LEN - 1); 841 } 842 843 /* Hardware event handlers */ 844 static inline void cgx_link_change_handler(u64 lstat, 845 struct lmac *lmac) 846 { 847 struct cgx_link_user_info *linfo; 848 struct cgx *cgx = lmac->cgx; 849 struct cgx_link_event event; 850 struct device *dev; 851 int err_type; 852 853 dev = &cgx->pdev->dev; 854 855 link_status_user_format(lstat, &event.link_uinfo, cgx, lmac->lmac_id); 856 err_type = FIELD_GET(RESP_LINKSTAT_ERRTYPE, lstat); 857 858 event.cgx_id = cgx->cgx_id; 859 event.lmac_id = lmac->lmac_id; 860 861 /* update the local copy of link status */ 862 lmac->link_info = event.link_uinfo; 863 linfo = &lmac->link_info; 864 865 if (err_type == CGX_ERR_SPEED_CHANGE_INVALID) 866 return; 867 868 /* Ensure callback doesn't get unregistered until we finish it */ 869 spin_lock(&lmac->event_cb_lock); 870 871 if (!lmac->event_cb.notify_link_chg) { 872 dev_dbg(dev, "cgx port %d:%d Link change handler null", 873 cgx->cgx_id, lmac->lmac_id); 874 if (err_type != CGX_ERR_NONE) { 875 dev_err(dev, "cgx port %d:%d Link error %d\n", 876 cgx->cgx_id, lmac->lmac_id, err_type); 877 } 878 dev_info(dev, "cgx port %d:%d Link is %s %d Mbps\n", 879 cgx->cgx_id, lmac->lmac_id, 880 linfo->link_up ? "UP" : "DOWN", linfo->speed); 881 goto err; 882 } 883 884 if (lmac->event_cb.notify_link_chg(&event, lmac->event_cb.data)) 885 dev_err(dev, "event notification failure\n"); 886 err: 887 spin_unlock(&lmac->event_cb_lock); 888 } 889 890 static inline bool cgx_cmdresp_is_linkevent(u64 event) 891 { 892 u8 id; 893 894 id = FIELD_GET(EVTREG_ID, event); 895 if (id == CGX_CMD_LINK_BRING_UP || 896 id == CGX_CMD_LINK_BRING_DOWN || 897 id == CGX_CMD_MODE_CHANGE) 898 return true; 899 else 900 return false; 901 } 902 903 static inline bool cgx_event_is_linkevent(u64 event) 904 { 905 if (FIELD_GET(EVTREG_ID, event) == CGX_EVT_LINK_CHANGE) 906 return true; 907 else 908 return false; 909 } 910 911 static irqreturn_t cgx_fwi_event_handler(int irq, void *data) 912 { 913 u64 event, offset, clear_bit; 914 struct lmac *lmac = data; 915 struct cgx *cgx; 916 917 cgx = lmac->cgx; 918 919 /* Clear SW_INT for RPM and CMR_INT for CGX */ 920 offset = cgx->mac_ops->int_register; 921 clear_bit = cgx->mac_ops->int_ena_bit; 922 923 event = cgx_read(cgx, lmac->lmac_id, CGX_EVENT_REG); 924 925 if (!FIELD_GET(EVTREG_ACK, event)) 926 return IRQ_NONE; 927 928 switch (FIELD_GET(EVTREG_EVT_TYPE, event)) { 929 case CGX_EVT_CMD_RESP: 930 /* Copy the response. Since only one command is active at a 931 * time, there is no way a response can get overwritten 932 */ 933 lmac->resp = event; 934 /* Ensure response is updated before thread context starts */ 935 smp_wmb(); 936 937 /* There wont be separate events for link change initiated from 938 * software; Hence report the command responses as events 939 */ 940 if (cgx_cmdresp_is_linkevent(event)) 941 cgx_link_change_handler(event, lmac); 942 943 /* Release thread waiting for completion */ 944 lmac->cmd_pend = false; 945 wake_up_interruptible(&lmac->wq_cmd_cmplt); 946 break; 947 case CGX_EVT_ASYNC: 948 if (cgx_event_is_linkevent(event)) 949 cgx_link_change_handler(event, lmac); 950 break; 951 } 952 953 /* Any new event or command response will be posted by firmware 954 * only after the current status is acked. 955 * Ack the interrupt register as well. 956 */ 957 cgx_write(lmac->cgx, lmac->lmac_id, CGX_EVENT_REG, 0); 958 cgx_write(lmac->cgx, lmac->lmac_id, offset, clear_bit); 959 960 return IRQ_HANDLED; 961 } 962 963 /* APIs for PHY management using CGX firmware interface */ 964 965 /* callback registration for hardware events like link change */ 966 int cgx_lmac_evh_register(struct cgx_event_cb *cb, void *cgxd, int lmac_id) 967 { 968 struct cgx *cgx = cgxd; 969 struct lmac *lmac; 970 971 lmac = lmac_pdata(lmac_id, cgx); 972 if (!lmac) 973 return -ENODEV; 974 975 lmac->event_cb = *cb; 976 977 return 0; 978 } 979 980 int cgx_lmac_evh_unregister(void *cgxd, int lmac_id) 981 { 982 struct lmac *lmac; 983 unsigned long flags; 984 struct cgx *cgx = cgxd; 985 986 lmac = lmac_pdata(lmac_id, cgx); 987 if (!lmac) 988 return -ENODEV; 989 990 spin_lock_irqsave(&lmac->event_cb_lock, flags); 991 lmac->event_cb.notify_link_chg = NULL; 992 lmac->event_cb.data = NULL; 993 spin_unlock_irqrestore(&lmac->event_cb_lock, flags); 994 995 return 0; 996 } 997 998 int cgx_get_fwdata_base(u64 *base) 999 { 1000 u64 req = 0, resp; 1001 struct cgx *cgx; 1002 int first_lmac; 1003 int err; 1004 1005 cgx = list_first_entry_or_null(&cgx_list, struct cgx, cgx_list); 1006 if (!cgx) 1007 return -ENXIO; 1008 1009 first_lmac = find_first_bit(&cgx->lmac_bmap, MAX_LMAC_PER_CGX); 1010 req = FIELD_SET(CMDREG_ID, CGX_CMD_GET_FWD_BASE, req); 1011 err = cgx_fwi_cmd_generic(req, &resp, cgx, first_lmac); 1012 if (!err) 1013 *base = FIELD_GET(RESP_FWD_BASE, resp); 1014 1015 return err; 1016 } 1017 1018 int cgx_set_link_mode(void *cgxd, struct cgx_set_link_mode_args args, 1019 int cgx_id, int lmac_id) 1020 { 1021 struct cgx *cgx = cgxd; 1022 u64 req = 0, resp; 1023 1024 if (!cgx) 1025 return -ENODEV; 1026 1027 if (args.mode) 1028 otx2_map_ethtool_link_modes(args.mode, &args); 1029 if (!args.speed && args.duplex && !args.an) 1030 return -EINVAL; 1031 1032 req = FIELD_SET(CMDREG_ID, CGX_CMD_MODE_CHANGE, req); 1033 req = FIELD_SET(CMDMODECHANGE_SPEED, 1034 cgx_link_usertable_index_map(args.speed), req); 1035 req = FIELD_SET(CMDMODECHANGE_DUPLEX, args.duplex, req); 1036 req = FIELD_SET(CMDMODECHANGE_AN, args.an, req); 1037 req = FIELD_SET(CMDMODECHANGE_PORT, args.ports, req); 1038 req = FIELD_SET(CMDMODECHANGE_FLAGS, args.mode, req); 1039 1040 return cgx_fwi_cmd_generic(req, &resp, cgx, lmac_id); 1041 } 1042 int cgx_set_fec(u64 fec, int cgx_id, int lmac_id) 1043 { 1044 u64 req = 0, resp; 1045 struct cgx *cgx; 1046 int err = 0; 1047 1048 cgx = cgx_get_pdata(cgx_id); 1049 if (!cgx) 1050 return -ENXIO; 1051 1052 req = FIELD_SET(CMDREG_ID, CGX_CMD_SET_FEC, req); 1053 req = FIELD_SET(CMDSETFEC, fec, req); 1054 err = cgx_fwi_cmd_generic(req, &resp, cgx, lmac_id); 1055 if (err) 1056 return err; 1057 1058 cgx->lmac_idmap[lmac_id]->link_info.fec = 1059 FIELD_GET(RESP_LINKSTAT_FEC, resp); 1060 return cgx->lmac_idmap[lmac_id]->link_info.fec; 1061 } 1062 1063 int cgx_get_phy_fec_stats(void *cgxd, int lmac_id) 1064 { 1065 struct cgx *cgx = cgxd; 1066 u64 req = 0, resp; 1067 1068 if (!cgx) 1069 return -ENODEV; 1070 1071 req = FIELD_SET(CMDREG_ID, CGX_CMD_GET_PHY_FEC_STATS, req); 1072 return cgx_fwi_cmd_generic(req, &resp, cgx, lmac_id); 1073 } 1074 1075 static int cgx_fwi_link_change(struct cgx *cgx, int lmac_id, bool enable) 1076 { 1077 u64 req = 0; 1078 u64 resp; 1079 1080 if (enable) 1081 req = FIELD_SET(CMDREG_ID, CGX_CMD_LINK_BRING_UP, req); 1082 else 1083 req = FIELD_SET(CMDREG_ID, CGX_CMD_LINK_BRING_DOWN, req); 1084 1085 return cgx_fwi_cmd_generic(req, &resp, cgx, lmac_id); 1086 } 1087 1088 static inline int cgx_fwi_read_version(u64 *resp, struct cgx *cgx) 1089 { 1090 int first_lmac = find_first_bit(&cgx->lmac_bmap, MAX_LMAC_PER_CGX); 1091 u64 req = 0; 1092 1093 req = FIELD_SET(CMDREG_ID, CGX_CMD_GET_FW_VER, req); 1094 return cgx_fwi_cmd_generic(req, resp, cgx, first_lmac); 1095 } 1096 1097 static int cgx_lmac_verify_fwi_version(struct cgx *cgx) 1098 { 1099 struct device *dev = &cgx->pdev->dev; 1100 int major_ver, minor_ver; 1101 u64 resp; 1102 int err; 1103 1104 if (!cgx->lmac_count) 1105 return 0; 1106 1107 err = cgx_fwi_read_version(&resp, cgx); 1108 if (err) 1109 return err; 1110 1111 major_ver = FIELD_GET(RESP_MAJOR_VER, resp); 1112 minor_ver = FIELD_GET(RESP_MINOR_VER, resp); 1113 dev_dbg(dev, "Firmware command interface version = %d.%d\n", 1114 major_ver, minor_ver); 1115 if (major_ver != CGX_FIRMWARE_MAJOR_VER) 1116 return -EIO; 1117 else 1118 return 0; 1119 } 1120 1121 static void cgx_lmac_linkup_work(struct work_struct *work) 1122 { 1123 struct cgx *cgx = container_of(work, struct cgx, cgx_cmd_work); 1124 struct device *dev = &cgx->pdev->dev; 1125 int i, err; 1126 1127 /* Do Link up for all the enabled lmacs */ 1128 for_each_set_bit(i, &cgx->lmac_bmap, MAX_LMAC_PER_CGX) { 1129 err = cgx_fwi_link_change(cgx, i, true); 1130 if (err) 1131 dev_info(dev, "cgx port %d:%d Link up command failed\n", 1132 cgx->cgx_id, i); 1133 } 1134 } 1135 1136 int cgx_lmac_linkup_start(void *cgxd) 1137 { 1138 struct cgx *cgx = cgxd; 1139 1140 if (!cgx) 1141 return -ENODEV; 1142 1143 queue_work(cgx->cgx_cmd_workq, &cgx->cgx_cmd_work); 1144 1145 return 0; 1146 } 1147 1148 static void cgx_lmac_get_fifolen(struct cgx *cgx) 1149 { 1150 u64 cfg; 1151 1152 cfg = cgx_read(cgx, 0, CGX_CONST); 1153 cgx->mac_ops->fifo_len = FIELD_GET(CGX_CONST_RXFIFO_SIZE, cfg); 1154 } 1155 1156 static int cgx_configure_interrupt(struct cgx *cgx, struct lmac *lmac, 1157 int cnt, bool req_free) 1158 { 1159 struct mac_ops *mac_ops = cgx->mac_ops; 1160 u64 offset, ena_bit; 1161 unsigned int irq; 1162 int err; 1163 1164 irq = pci_irq_vector(cgx->pdev, mac_ops->lmac_fwi + 1165 cnt * mac_ops->irq_offset); 1166 offset = mac_ops->int_set_reg; 1167 ena_bit = mac_ops->int_ena_bit; 1168 1169 if (req_free) { 1170 free_irq(irq, lmac); 1171 return 0; 1172 } 1173 1174 err = request_irq(irq, cgx_fwi_event_handler, 0, lmac->name, lmac); 1175 if (err) 1176 return err; 1177 1178 /* Enable interrupt */ 1179 cgx_write(cgx, lmac->lmac_id, offset, ena_bit); 1180 return 0; 1181 } 1182 1183 int cgx_get_nr_lmacs(void *cgxd) 1184 { 1185 struct cgx *cgx = cgxd; 1186 1187 return cgx_read(cgx, 0, CGXX_CMRX_RX_LMACS) & 0x7ULL; 1188 } 1189 1190 u8 cgx_get_lmacid(void *cgxd, u8 lmac_index) 1191 { 1192 struct cgx *cgx = cgxd; 1193 1194 return cgx->lmac_idmap[lmac_index]->lmac_id; 1195 } 1196 1197 unsigned long cgx_get_lmac_bmap(void *cgxd) 1198 { 1199 struct cgx *cgx = cgxd; 1200 1201 return cgx->lmac_bmap; 1202 } 1203 1204 static int cgx_lmac_init(struct cgx *cgx) 1205 { 1206 struct lmac *lmac; 1207 u64 lmac_list; 1208 int i, err; 1209 1210 cgx_lmac_get_fifolen(cgx); 1211 1212 cgx->lmac_count = cgx->mac_ops->get_nr_lmacs(cgx); 1213 /* lmac_list specifies which lmacs are enabled 1214 * when bit n is set to 1, LMAC[n] is enabled 1215 */ 1216 if (cgx->mac_ops->non_contiguous_serdes_lane) 1217 lmac_list = cgx_read(cgx, 0, CGXX_CMRX_RX_LMACS) & 0xFULL; 1218 1219 if (cgx->lmac_count > MAX_LMAC_PER_CGX) 1220 cgx->lmac_count = MAX_LMAC_PER_CGX; 1221 1222 for (i = 0; i < cgx->lmac_count; i++) { 1223 lmac = kzalloc(sizeof(struct lmac), GFP_KERNEL); 1224 if (!lmac) 1225 return -ENOMEM; 1226 lmac->name = kcalloc(1, sizeof("cgx_fwi_xxx_yyy"), GFP_KERNEL); 1227 if (!lmac->name) { 1228 err = -ENOMEM; 1229 goto err_lmac_free; 1230 } 1231 sprintf(lmac->name, "cgx_fwi_%d_%d", cgx->cgx_id, i); 1232 if (cgx->mac_ops->non_contiguous_serdes_lane) { 1233 lmac->lmac_id = __ffs64(lmac_list); 1234 lmac_list &= ~BIT_ULL(lmac->lmac_id); 1235 } else { 1236 lmac->lmac_id = i; 1237 } 1238 1239 lmac->cgx = cgx; 1240 init_waitqueue_head(&lmac->wq_cmd_cmplt); 1241 mutex_init(&lmac->cmd_lock); 1242 spin_lock_init(&lmac->event_cb_lock); 1243 err = cgx_configure_interrupt(cgx, lmac, lmac->lmac_id, false); 1244 if (err) 1245 goto err_irq; 1246 1247 /* Add reference */ 1248 cgx->lmac_idmap[lmac->lmac_id] = lmac; 1249 cgx->mac_ops->mac_pause_frm_config(cgx, lmac->lmac_id, true); 1250 set_bit(lmac->lmac_id, &cgx->lmac_bmap); 1251 } 1252 1253 return cgx_lmac_verify_fwi_version(cgx); 1254 1255 err_irq: 1256 kfree(lmac->name); 1257 err_lmac_free: 1258 kfree(lmac); 1259 return err; 1260 } 1261 1262 static int cgx_lmac_exit(struct cgx *cgx) 1263 { 1264 struct lmac *lmac; 1265 int i; 1266 1267 if (cgx->cgx_cmd_workq) { 1268 flush_workqueue(cgx->cgx_cmd_workq); 1269 destroy_workqueue(cgx->cgx_cmd_workq); 1270 cgx->cgx_cmd_workq = NULL; 1271 } 1272 1273 /* Free all lmac related resources */ 1274 for_each_set_bit(i, &cgx->lmac_bmap, MAX_LMAC_PER_CGX) { 1275 lmac = cgx->lmac_idmap[i]; 1276 if (!lmac) 1277 continue; 1278 cgx->mac_ops->mac_pause_frm_config(cgx, lmac->lmac_id, false); 1279 cgx_configure_interrupt(cgx, lmac, lmac->lmac_id, true); 1280 kfree(lmac->name); 1281 kfree(lmac); 1282 } 1283 1284 return 0; 1285 } 1286 1287 static void cgx_populate_features(struct cgx *cgx) 1288 { 1289 if (is_dev_rpm(cgx)) 1290 cgx->hw_features = (RVU_MAC_RPM | RVU_LMAC_FEAT_FC); 1291 else 1292 cgx->hw_features = (RVU_LMAC_FEAT_FC | RVU_LMAC_FEAT_PTP); 1293 } 1294 1295 static struct mac_ops cgx_mac_ops = { 1296 .name = "cgx", 1297 .csr_offset = 0, 1298 .lmac_offset = 18, 1299 .int_register = CGXX_CMRX_INT, 1300 .int_set_reg = CGXX_CMRX_INT_ENA_W1S, 1301 .irq_offset = 9, 1302 .int_ena_bit = FW_CGX_INT, 1303 .lmac_fwi = CGX_LMAC_FWI, 1304 .non_contiguous_serdes_lane = false, 1305 .rx_stats_cnt = 9, 1306 .tx_stats_cnt = 18, 1307 .get_nr_lmacs = cgx_get_nr_lmacs, 1308 .get_lmac_type = cgx_get_lmac_type, 1309 .mac_lmac_intl_lbk = cgx_lmac_internal_loopback, 1310 .mac_get_rx_stats = cgx_get_rx_stats, 1311 .mac_get_tx_stats = cgx_get_tx_stats, 1312 .mac_enadis_rx_pause_fwding = cgx_lmac_enadis_rx_pause_fwding, 1313 .mac_get_pause_frm_status = cgx_lmac_get_pause_frm_status, 1314 .mac_enadis_pause_frm = cgx_lmac_enadis_pause_frm, 1315 .mac_pause_frm_config = cgx_lmac_pause_frm_config, 1316 }; 1317 1318 static int cgx_probe(struct pci_dev *pdev, const struct pci_device_id *id) 1319 { 1320 struct device *dev = &pdev->dev; 1321 struct cgx *cgx; 1322 int err, nvec; 1323 1324 cgx = devm_kzalloc(dev, sizeof(*cgx), GFP_KERNEL); 1325 if (!cgx) 1326 return -ENOMEM; 1327 cgx->pdev = pdev; 1328 1329 pci_set_drvdata(pdev, cgx); 1330 1331 /* Use mac_ops to get MAC specific features */ 1332 if (pdev->device == PCI_DEVID_CN10K_RPM) 1333 cgx->mac_ops = rpm_get_mac_ops(); 1334 else 1335 cgx->mac_ops = &cgx_mac_ops; 1336 1337 err = pci_enable_device(pdev); 1338 if (err) { 1339 dev_err(dev, "Failed to enable PCI device\n"); 1340 pci_set_drvdata(pdev, NULL); 1341 return err; 1342 } 1343 1344 err = pci_request_regions(pdev, DRV_NAME); 1345 if (err) { 1346 dev_err(dev, "PCI request regions failed 0x%x\n", err); 1347 goto err_disable_device; 1348 } 1349 1350 /* MAP configuration registers */ 1351 cgx->reg_base = pcim_iomap(pdev, PCI_CFG_REG_BAR_NUM, 0); 1352 if (!cgx->reg_base) { 1353 dev_err(dev, "CGX: Cannot map CSR memory space, aborting\n"); 1354 err = -ENOMEM; 1355 goto err_release_regions; 1356 } 1357 1358 nvec = pci_msix_vec_count(cgx->pdev); 1359 err = pci_alloc_irq_vectors(pdev, nvec, nvec, PCI_IRQ_MSIX); 1360 if (err < 0 || err != nvec) { 1361 dev_err(dev, "Request for %d msix vectors failed, err %d\n", 1362 nvec, err); 1363 goto err_release_regions; 1364 } 1365 1366 cgx->cgx_id = (pci_resource_start(pdev, PCI_CFG_REG_BAR_NUM) >> 24) 1367 & CGX_ID_MASK; 1368 1369 /* init wq for processing linkup requests */ 1370 INIT_WORK(&cgx->cgx_cmd_work, cgx_lmac_linkup_work); 1371 cgx->cgx_cmd_workq = alloc_workqueue("cgx_cmd_workq", 0, 0); 1372 if (!cgx->cgx_cmd_workq) { 1373 dev_err(dev, "alloc workqueue failed for cgx cmd"); 1374 err = -ENOMEM; 1375 goto err_free_irq_vectors; 1376 } 1377 1378 list_add(&cgx->cgx_list, &cgx_list); 1379 1380 cgx_link_usertable_init(); 1381 1382 cgx_populate_features(cgx); 1383 1384 mutex_init(&cgx->lock); 1385 1386 err = cgx_lmac_init(cgx); 1387 if (err) 1388 goto err_release_lmac; 1389 1390 return 0; 1391 1392 err_release_lmac: 1393 cgx_lmac_exit(cgx); 1394 list_del(&cgx->cgx_list); 1395 err_free_irq_vectors: 1396 pci_free_irq_vectors(pdev); 1397 err_release_regions: 1398 pci_release_regions(pdev); 1399 err_disable_device: 1400 pci_disable_device(pdev); 1401 pci_set_drvdata(pdev, NULL); 1402 return err; 1403 } 1404 1405 static void cgx_remove(struct pci_dev *pdev) 1406 { 1407 struct cgx *cgx = pci_get_drvdata(pdev); 1408 1409 if (cgx) { 1410 cgx_lmac_exit(cgx); 1411 list_del(&cgx->cgx_list); 1412 } 1413 pci_free_irq_vectors(pdev); 1414 pci_release_regions(pdev); 1415 pci_disable_device(pdev); 1416 pci_set_drvdata(pdev, NULL); 1417 } 1418 1419 struct pci_driver cgx_driver = { 1420 .name = DRV_NAME, 1421 .id_table = cgx_id_table, 1422 .probe = cgx_probe, 1423 .remove = cgx_remove, 1424 }; 1425