1 // SPDX-License-Identifier: GPL-2.0 2 /* Marvell OcteonTx2 CGX driver 3 * 4 * Copyright (C) 2018 Marvell. 5 * 6 */ 7 8 #include <linux/acpi.h> 9 #include <linux/module.h> 10 #include <linux/interrupt.h> 11 #include <linux/pci.h> 12 #include <linux/netdevice.h> 13 #include <linux/etherdevice.h> 14 #include <linux/ethtool.h> 15 #include <linux/phy.h> 16 #include <linux/of.h> 17 #include <linux/of_mdio.h> 18 #include <linux/of_net.h> 19 20 #include "cgx.h" 21 #include "rvu.h" 22 #include "lmac_common.h" 23 24 #define DRV_NAME "Marvell-CGX/RPM" 25 #define DRV_STRING "Marvell CGX/RPM Driver" 26 27 static LIST_HEAD(cgx_list); 28 29 /* Convert firmware speed encoding to user format(Mbps) */ 30 static const u32 cgx_speed_mbps[CGX_LINK_SPEED_MAX] = { 31 [CGX_LINK_NONE] = 0, 32 [CGX_LINK_10M] = 10, 33 [CGX_LINK_100M] = 100, 34 [CGX_LINK_1G] = 1000, 35 [CGX_LINK_2HG] = 2500, 36 [CGX_LINK_5G] = 5000, 37 [CGX_LINK_10G] = 10000, 38 [CGX_LINK_20G] = 20000, 39 [CGX_LINK_25G] = 25000, 40 [CGX_LINK_40G] = 40000, 41 [CGX_LINK_50G] = 50000, 42 [CGX_LINK_80G] = 80000, 43 [CGX_LINK_100G] = 100000, 44 }; 45 46 /* Convert firmware lmac type encoding to string */ 47 static const char *cgx_lmactype_string[LMAC_MODE_MAX] = { 48 [LMAC_MODE_SGMII] = "SGMII", 49 [LMAC_MODE_XAUI] = "XAUI", 50 [LMAC_MODE_RXAUI] = "RXAUI", 51 [LMAC_MODE_10G_R] = "10G_R", 52 [LMAC_MODE_40G_R] = "40G_R", 53 [LMAC_MODE_QSGMII] = "QSGMII", 54 [LMAC_MODE_25G_R] = "25G_R", 55 [LMAC_MODE_50G_R] = "50G_R", 56 [LMAC_MODE_100G_R] = "100G_R", 57 [LMAC_MODE_USXGMII] = "USXGMII", 58 }; 59 60 /* CGX PHY management internal APIs */ 61 static int cgx_fwi_link_change(struct cgx *cgx, int lmac_id, bool en); 62 63 /* Supported devices */ 64 static const struct pci_device_id cgx_id_table[] = { 65 { PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_OCTEONTX2_CGX) }, 66 { PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_CN10K_RPM) }, 67 { PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_CN10KB_RPM) }, 68 { 0, } /* end of table */ 69 }; 70 71 MODULE_DEVICE_TABLE(pci, cgx_id_table); 72 73 static bool is_dev_rpm(void *cgxd) 74 { 75 struct cgx *cgx = cgxd; 76 77 return (cgx->pdev->device == PCI_DEVID_CN10K_RPM) || 78 (cgx->pdev->device == PCI_DEVID_CN10KB_RPM); 79 } 80 81 bool is_lmac_valid(struct cgx *cgx, int lmac_id) 82 { 83 if (!cgx || lmac_id < 0 || lmac_id >= cgx->max_lmac_per_mac) 84 return false; 85 return test_bit(lmac_id, &cgx->lmac_bmap); 86 } 87 88 /* Helper function to get sequential index 89 * given the enabled LMAC of a CGX 90 */ 91 static int get_sequence_id_of_lmac(struct cgx *cgx, int lmac_id) 92 { 93 int tmp, id = 0; 94 95 for_each_set_bit(tmp, &cgx->lmac_bmap, cgx->max_lmac_per_mac) { 96 if (tmp == lmac_id) 97 break; 98 id++; 99 } 100 101 return id; 102 } 103 104 struct mac_ops *get_mac_ops(void *cgxd) 105 { 106 if (!cgxd) 107 return cgxd; 108 109 return ((struct cgx *)cgxd)->mac_ops; 110 } 111 112 void cgx_write(struct cgx *cgx, u64 lmac, u64 offset, u64 val) 113 { 114 writeq(val, cgx->reg_base + (lmac << cgx->mac_ops->lmac_offset) + 115 offset); 116 } 117 118 u64 cgx_read(struct cgx *cgx, u64 lmac, u64 offset) 119 { 120 return readq(cgx->reg_base + (lmac << cgx->mac_ops->lmac_offset) + 121 offset); 122 } 123 124 struct lmac *lmac_pdata(u8 lmac_id, struct cgx *cgx) 125 { 126 if (!cgx || lmac_id >= cgx->max_lmac_per_mac) 127 return NULL; 128 129 return cgx->lmac_idmap[lmac_id]; 130 } 131 132 int cgx_get_cgxcnt_max(void) 133 { 134 struct cgx *cgx_dev; 135 int idmax = -ENODEV; 136 137 list_for_each_entry(cgx_dev, &cgx_list, cgx_list) 138 if (cgx_dev->cgx_id > idmax) 139 idmax = cgx_dev->cgx_id; 140 141 if (idmax < 0) 142 return 0; 143 144 return idmax + 1; 145 } 146 147 int cgx_get_lmac_cnt(void *cgxd) 148 { 149 struct cgx *cgx = cgxd; 150 151 if (!cgx) 152 return -ENODEV; 153 154 return cgx->lmac_count; 155 } 156 157 void *cgx_get_pdata(int cgx_id) 158 { 159 struct cgx *cgx_dev; 160 161 list_for_each_entry(cgx_dev, &cgx_list, cgx_list) { 162 if (cgx_dev->cgx_id == cgx_id) 163 return cgx_dev; 164 } 165 return NULL; 166 } 167 168 void cgx_lmac_write(int cgx_id, int lmac_id, u64 offset, u64 val) 169 { 170 struct cgx *cgx_dev = cgx_get_pdata(cgx_id); 171 172 /* Software must not access disabled LMAC registers */ 173 if (!is_lmac_valid(cgx_dev, lmac_id)) 174 return; 175 cgx_write(cgx_dev, lmac_id, offset, val); 176 } 177 178 u64 cgx_lmac_read(int cgx_id, int lmac_id, u64 offset) 179 { 180 struct cgx *cgx_dev = cgx_get_pdata(cgx_id); 181 182 /* Software must not access disabled LMAC registers */ 183 if (!is_lmac_valid(cgx_dev, lmac_id)) 184 return 0; 185 186 return cgx_read(cgx_dev, lmac_id, offset); 187 } 188 189 int cgx_get_cgxid(void *cgxd) 190 { 191 struct cgx *cgx = cgxd; 192 193 if (!cgx) 194 return -EINVAL; 195 196 return cgx->cgx_id; 197 } 198 199 u8 cgx_lmac_get_p2x(int cgx_id, int lmac_id) 200 { 201 struct cgx *cgx_dev = cgx_get_pdata(cgx_id); 202 u64 cfg; 203 204 cfg = cgx_read(cgx_dev, lmac_id, CGXX_CMRX_CFG); 205 206 return (cfg & CMR_P2X_SEL_MASK) >> CMR_P2X_SEL_SHIFT; 207 } 208 209 /* Ensure the required lock for event queue(where asynchronous events are 210 * posted) is acquired before calling this API. Else an asynchronous event(with 211 * latest link status) can reach the destination before this function returns 212 * and could make the link status appear wrong. 213 */ 214 int cgx_get_link_info(void *cgxd, int lmac_id, 215 struct cgx_link_user_info *linfo) 216 { 217 struct lmac *lmac = lmac_pdata(lmac_id, cgxd); 218 219 if (!lmac) 220 return -ENODEV; 221 222 *linfo = lmac->link_info; 223 return 0; 224 } 225 226 int cgx_lmac_addr_set(u8 cgx_id, u8 lmac_id, u8 *mac_addr) 227 { 228 struct cgx *cgx_dev = cgx_get_pdata(cgx_id); 229 struct lmac *lmac = lmac_pdata(lmac_id, cgx_dev); 230 struct mac_ops *mac_ops; 231 int index, id; 232 u64 cfg; 233 234 /* access mac_ops to know csr_offset */ 235 mac_ops = cgx_dev->mac_ops; 236 237 /* copy 6bytes from macaddr */ 238 /* memcpy(&cfg, mac_addr, 6); */ 239 240 cfg = ether_addr_to_u64(mac_addr); 241 242 id = get_sequence_id_of_lmac(cgx_dev, lmac_id); 243 244 index = id * lmac->mac_to_index_bmap.max; 245 246 cgx_write(cgx_dev, 0, (CGXX_CMRX_RX_DMAC_CAM0 + (index * 0x8)), 247 cfg | CGX_DMAC_CAM_ADDR_ENABLE | ((u64)lmac_id << 49)); 248 249 cfg = cgx_read(cgx_dev, lmac_id, CGXX_CMRX_RX_DMAC_CTL0); 250 cfg |= (CGX_DMAC_CTL0_CAM_ENABLE | CGX_DMAC_BCAST_MODE | 251 CGX_DMAC_MCAST_MODE); 252 cgx_write(cgx_dev, lmac_id, CGXX_CMRX_RX_DMAC_CTL0, cfg); 253 254 return 0; 255 } 256 257 u64 cgx_read_dmac_ctrl(void *cgxd, int lmac_id) 258 { 259 struct mac_ops *mac_ops; 260 struct cgx *cgx = cgxd; 261 262 if (!cgxd || !is_lmac_valid(cgxd, lmac_id)) 263 return 0; 264 265 cgx = cgxd; 266 /* Get mac_ops to know csr offset */ 267 mac_ops = cgx->mac_ops; 268 269 return cgx_read(cgxd, lmac_id, CGXX_CMRX_RX_DMAC_CTL0); 270 } 271 272 u64 cgx_read_dmac_entry(void *cgxd, int index) 273 { 274 struct mac_ops *mac_ops; 275 struct cgx *cgx; 276 277 if (!cgxd) 278 return 0; 279 280 cgx = cgxd; 281 mac_ops = cgx->mac_ops; 282 return cgx_read(cgx, 0, (CGXX_CMRX_RX_DMAC_CAM0 + (index * 8))); 283 } 284 285 int cgx_lmac_addr_add(u8 cgx_id, u8 lmac_id, u8 *mac_addr) 286 { 287 struct cgx *cgx_dev = cgx_get_pdata(cgx_id); 288 struct lmac *lmac = lmac_pdata(lmac_id, cgx_dev); 289 struct mac_ops *mac_ops; 290 int index, idx; 291 u64 cfg = 0; 292 int id; 293 294 if (!lmac) 295 return -ENODEV; 296 297 mac_ops = cgx_dev->mac_ops; 298 /* Get available index where entry is to be installed */ 299 idx = rvu_alloc_rsrc(&lmac->mac_to_index_bmap); 300 if (idx < 0) 301 return idx; 302 303 id = get_sequence_id_of_lmac(cgx_dev, lmac_id); 304 305 index = id * lmac->mac_to_index_bmap.max + idx; 306 307 cfg = ether_addr_to_u64(mac_addr); 308 cfg |= CGX_DMAC_CAM_ADDR_ENABLE; 309 cfg |= ((u64)lmac_id << 49); 310 cgx_write(cgx_dev, 0, (CGXX_CMRX_RX_DMAC_CAM0 + (index * 0x8)), cfg); 311 312 cfg = cgx_read(cgx_dev, lmac_id, CGXX_CMRX_RX_DMAC_CTL0); 313 cfg |= (CGX_DMAC_BCAST_MODE | CGX_DMAC_CAM_ACCEPT); 314 315 if (is_multicast_ether_addr(mac_addr)) { 316 cfg &= ~GENMASK_ULL(2, 1); 317 cfg |= CGX_DMAC_MCAST_MODE_CAM; 318 lmac->mcast_filters_count++; 319 } else if (!lmac->mcast_filters_count) { 320 cfg |= CGX_DMAC_MCAST_MODE; 321 } 322 323 cgx_write(cgx_dev, lmac_id, CGXX_CMRX_RX_DMAC_CTL0, cfg); 324 325 return idx; 326 } 327 328 int cgx_lmac_addr_reset(u8 cgx_id, u8 lmac_id) 329 { 330 struct cgx *cgx_dev = cgx_get_pdata(cgx_id); 331 struct lmac *lmac = lmac_pdata(lmac_id, cgx_dev); 332 struct mac_ops *mac_ops; 333 u8 index = 0, id; 334 u64 cfg; 335 336 if (!lmac) 337 return -ENODEV; 338 339 mac_ops = cgx_dev->mac_ops; 340 /* Restore index 0 to its default init value as done during 341 * cgx_lmac_init 342 */ 343 set_bit(0, lmac->mac_to_index_bmap.bmap); 344 345 id = get_sequence_id_of_lmac(cgx_dev, lmac_id); 346 347 index = id * lmac->mac_to_index_bmap.max + index; 348 cgx_write(cgx_dev, 0, (CGXX_CMRX_RX_DMAC_CAM0 + (index * 0x8)), 0); 349 350 /* Reset CGXX_CMRX_RX_DMAC_CTL0 register to default state */ 351 cfg = cgx_read(cgx_dev, lmac_id, CGXX_CMRX_RX_DMAC_CTL0); 352 cfg &= ~CGX_DMAC_CAM_ACCEPT; 353 cfg |= (CGX_DMAC_BCAST_MODE | CGX_DMAC_MCAST_MODE); 354 cgx_write(cgx_dev, lmac_id, CGXX_CMRX_RX_DMAC_CTL0, cfg); 355 356 return 0; 357 } 358 359 /* Allows caller to change macaddress associated with index 360 * in dmac filter table including index 0 reserved for 361 * interface mac address 362 */ 363 int cgx_lmac_addr_update(u8 cgx_id, u8 lmac_id, u8 *mac_addr, u8 index) 364 { 365 struct cgx *cgx_dev = cgx_get_pdata(cgx_id); 366 struct mac_ops *mac_ops; 367 struct lmac *lmac; 368 u64 cfg; 369 int id; 370 371 lmac = lmac_pdata(lmac_id, cgx_dev); 372 if (!lmac) 373 return -ENODEV; 374 375 mac_ops = cgx_dev->mac_ops; 376 /* Validate the index */ 377 if (index >= lmac->mac_to_index_bmap.max) 378 return -EINVAL; 379 380 /* ensure index is already set */ 381 if (!test_bit(index, lmac->mac_to_index_bmap.bmap)) 382 return -EINVAL; 383 384 id = get_sequence_id_of_lmac(cgx_dev, lmac_id); 385 386 index = id * lmac->mac_to_index_bmap.max + index; 387 388 cfg = cgx_read(cgx_dev, 0, (CGXX_CMRX_RX_DMAC_CAM0 + (index * 0x8))); 389 cfg &= ~CGX_RX_DMAC_ADR_MASK; 390 cfg |= ether_addr_to_u64(mac_addr); 391 392 cgx_write(cgx_dev, 0, (CGXX_CMRX_RX_DMAC_CAM0 + (index * 0x8)), cfg); 393 return 0; 394 } 395 396 int cgx_lmac_addr_del(u8 cgx_id, u8 lmac_id, u8 index) 397 { 398 struct cgx *cgx_dev = cgx_get_pdata(cgx_id); 399 struct lmac *lmac = lmac_pdata(lmac_id, cgx_dev); 400 struct mac_ops *mac_ops; 401 u8 mac[ETH_ALEN]; 402 u64 cfg; 403 int id; 404 405 if (!lmac) 406 return -ENODEV; 407 408 mac_ops = cgx_dev->mac_ops; 409 /* Validate the index */ 410 if (index >= lmac->mac_to_index_bmap.max) 411 return -EINVAL; 412 413 /* Skip deletion for reserved index i.e. index 0 */ 414 if (index == 0) 415 return 0; 416 417 rvu_free_rsrc(&lmac->mac_to_index_bmap, index); 418 419 id = get_sequence_id_of_lmac(cgx_dev, lmac_id); 420 421 index = id * lmac->mac_to_index_bmap.max + index; 422 423 /* Read MAC address to check whether it is ucast or mcast */ 424 cfg = cgx_read(cgx_dev, 0, (CGXX_CMRX_RX_DMAC_CAM0 + (index * 0x8))); 425 426 u64_to_ether_addr(cfg, mac); 427 if (is_multicast_ether_addr(mac)) 428 lmac->mcast_filters_count--; 429 430 if (!lmac->mcast_filters_count) { 431 cfg = cgx_read(cgx_dev, lmac_id, CGXX_CMRX_RX_DMAC_CTL0); 432 cfg &= ~GENMASK_ULL(2, 1); 433 cfg |= CGX_DMAC_MCAST_MODE; 434 cgx_write(cgx_dev, lmac_id, CGXX_CMRX_RX_DMAC_CTL0, cfg); 435 } 436 437 cgx_write(cgx_dev, 0, (CGXX_CMRX_RX_DMAC_CAM0 + (index * 0x8)), 0); 438 439 return 0; 440 } 441 442 int cgx_lmac_addr_max_entries_get(u8 cgx_id, u8 lmac_id) 443 { 444 struct cgx *cgx_dev = cgx_get_pdata(cgx_id); 445 struct lmac *lmac = lmac_pdata(lmac_id, cgx_dev); 446 447 if (lmac) 448 return lmac->mac_to_index_bmap.max; 449 450 return 0; 451 } 452 453 u64 cgx_lmac_addr_get(u8 cgx_id, u8 lmac_id) 454 { 455 struct cgx *cgx_dev = cgx_get_pdata(cgx_id); 456 struct lmac *lmac = lmac_pdata(lmac_id, cgx_dev); 457 struct mac_ops *mac_ops; 458 int index; 459 u64 cfg; 460 int id; 461 462 mac_ops = cgx_dev->mac_ops; 463 464 id = get_sequence_id_of_lmac(cgx_dev, lmac_id); 465 466 index = id * lmac->mac_to_index_bmap.max; 467 468 cfg = cgx_read(cgx_dev, 0, CGXX_CMRX_RX_DMAC_CAM0 + index * 0x8); 469 return cfg & CGX_RX_DMAC_ADR_MASK; 470 } 471 472 int cgx_set_pkind(void *cgxd, u8 lmac_id, int pkind) 473 { 474 struct cgx *cgx = cgxd; 475 476 if (!is_lmac_valid(cgx, lmac_id)) 477 return -ENODEV; 478 479 cgx_write(cgx, lmac_id, cgx->mac_ops->rxid_map_offset, (pkind & 0x3F)); 480 return 0; 481 } 482 483 static u8 cgx_get_lmac_type(void *cgxd, int lmac_id) 484 { 485 struct cgx *cgx = cgxd; 486 u64 cfg; 487 488 cfg = cgx_read(cgx, lmac_id, CGXX_CMRX_CFG); 489 return (cfg >> CGX_LMAC_TYPE_SHIFT) & CGX_LMAC_TYPE_MASK; 490 } 491 492 static u32 cgx_get_lmac_fifo_len(void *cgxd, int lmac_id) 493 { 494 struct cgx *cgx = cgxd; 495 u8 num_lmacs; 496 u32 fifo_len; 497 498 fifo_len = cgx->mac_ops->fifo_len; 499 num_lmacs = cgx->mac_ops->get_nr_lmacs(cgx); 500 501 switch (num_lmacs) { 502 case 1: 503 return fifo_len; 504 case 2: 505 return fifo_len / 2; 506 case 3: 507 /* LMAC0 gets half of the FIFO, reset 1/4th */ 508 if (lmac_id == 0) 509 return fifo_len / 2; 510 return fifo_len / 4; 511 case 4: 512 default: 513 return fifo_len / 4; 514 } 515 return 0; 516 } 517 518 /* Configure CGX LMAC in internal loopback mode */ 519 int cgx_lmac_internal_loopback(void *cgxd, int lmac_id, bool enable) 520 { 521 struct cgx *cgx = cgxd; 522 struct lmac *lmac; 523 u64 cfg; 524 525 if (!is_lmac_valid(cgx, lmac_id)) 526 return -ENODEV; 527 528 lmac = lmac_pdata(lmac_id, cgx); 529 if (lmac->lmac_type == LMAC_MODE_SGMII || 530 lmac->lmac_type == LMAC_MODE_QSGMII) { 531 cfg = cgx_read(cgx, lmac_id, CGXX_GMP_PCS_MRX_CTL); 532 if (enable) 533 cfg |= CGXX_GMP_PCS_MRX_CTL_LBK; 534 else 535 cfg &= ~CGXX_GMP_PCS_MRX_CTL_LBK; 536 cgx_write(cgx, lmac_id, CGXX_GMP_PCS_MRX_CTL, cfg); 537 } else { 538 cfg = cgx_read(cgx, lmac_id, CGXX_SPUX_CONTROL1); 539 if (enable) 540 cfg |= CGXX_SPUX_CONTROL1_LBK; 541 else 542 cfg &= ~CGXX_SPUX_CONTROL1_LBK; 543 cgx_write(cgx, lmac_id, CGXX_SPUX_CONTROL1, cfg); 544 } 545 return 0; 546 } 547 548 void cgx_lmac_promisc_config(int cgx_id, int lmac_id, bool enable) 549 { 550 struct cgx *cgx = cgx_get_pdata(cgx_id); 551 struct lmac *lmac = lmac_pdata(lmac_id, cgx); 552 u16 max_dmac = lmac->mac_to_index_bmap.max; 553 struct mac_ops *mac_ops; 554 int index, i; 555 u64 cfg = 0; 556 int id; 557 558 if (!cgx) 559 return; 560 561 id = get_sequence_id_of_lmac(cgx, lmac_id); 562 563 mac_ops = cgx->mac_ops; 564 if (enable) { 565 /* Enable promiscuous mode on LMAC */ 566 cfg = cgx_read(cgx, lmac_id, CGXX_CMRX_RX_DMAC_CTL0); 567 cfg &= ~CGX_DMAC_CAM_ACCEPT; 568 cfg |= (CGX_DMAC_BCAST_MODE | CGX_DMAC_MCAST_MODE); 569 cgx_write(cgx, lmac_id, CGXX_CMRX_RX_DMAC_CTL0, cfg); 570 571 for (i = 0; i < max_dmac; i++) { 572 index = id * max_dmac + i; 573 cfg = cgx_read(cgx, 0, 574 (CGXX_CMRX_RX_DMAC_CAM0 + index * 0x8)); 575 cfg &= ~CGX_DMAC_CAM_ADDR_ENABLE; 576 cgx_write(cgx, 0, 577 (CGXX_CMRX_RX_DMAC_CAM0 + index * 0x8), cfg); 578 } 579 } else { 580 /* Disable promiscuous mode */ 581 cfg = cgx_read(cgx, lmac_id, CGXX_CMRX_RX_DMAC_CTL0); 582 cfg |= CGX_DMAC_CAM_ACCEPT | CGX_DMAC_MCAST_MODE; 583 cgx_write(cgx, lmac_id, CGXX_CMRX_RX_DMAC_CTL0, cfg); 584 for (i = 0; i < max_dmac; i++) { 585 index = id * max_dmac + i; 586 cfg = cgx_read(cgx, 0, 587 (CGXX_CMRX_RX_DMAC_CAM0 + index * 0x8)); 588 if ((cfg & CGX_RX_DMAC_ADR_MASK) != 0) { 589 cfg |= CGX_DMAC_CAM_ADDR_ENABLE; 590 cgx_write(cgx, 0, 591 (CGXX_CMRX_RX_DMAC_CAM0 + 592 index * 0x8), 593 cfg); 594 } 595 } 596 } 597 } 598 599 static int cgx_lmac_get_pause_frm_status(void *cgxd, int lmac_id, 600 u8 *tx_pause, u8 *rx_pause) 601 { 602 struct cgx *cgx = cgxd; 603 u64 cfg; 604 605 if (is_dev_rpm(cgx)) 606 return 0; 607 608 if (!is_lmac_valid(cgx, lmac_id)) 609 return -ENODEV; 610 611 cfg = cgx_read(cgx, lmac_id, CGXX_SMUX_RX_FRM_CTL); 612 *rx_pause = !!(cfg & CGX_SMUX_RX_FRM_CTL_CTL_BCK); 613 614 cfg = cgx_read(cgx, lmac_id, CGXX_SMUX_TX_CTL); 615 *tx_pause = !!(cfg & CGX_SMUX_TX_CTL_L2P_BP_CONV); 616 return 0; 617 } 618 619 /* Enable or disable forwarding received pause frames to Tx block */ 620 void cgx_lmac_enadis_rx_pause_fwding(void *cgxd, int lmac_id, bool enable) 621 { 622 struct cgx *cgx = cgxd; 623 u8 rx_pause, tx_pause; 624 bool is_pfc_enabled; 625 struct lmac *lmac; 626 u64 cfg; 627 628 if (!cgx) 629 return; 630 631 lmac = lmac_pdata(lmac_id, cgx); 632 if (!lmac) 633 return; 634 635 /* Pause frames are not enabled just return */ 636 if (!bitmap_weight(lmac->rx_fc_pfvf_bmap.bmap, lmac->rx_fc_pfvf_bmap.max)) 637 return; 638 639 cgx_lmac_get_pause_frm_status(cgx, lmac_id, &rx_pause, &tx_pause); 640 is_pfc_enabled = rx_pause ? false : true; 641 642 if (enable) { 643 if (!is_pfc_enabled) { 644 cfg = cgx_read(cgx, lmac_id, CGXX_GMP_GMI_RXX_FRM_CTL); 645 cfg |= CGX_GMP_GMI_RXX_FRM_CTL_CTL_BCK; 646 cgx_write(cgx, lmac_id, CGXX_GMP_GMI_RXX_FRM_CTL, cfg); 647 648 cfg = cgx_read(cgx, lmac_id, CGXX_SMUX_RX_FRM_CTL); 649 cfg |= CGX_SMUX_RX_FRM_CTL_CTL_BCK; 650 cgx_write(cgx, lmac_id, CGXX_SMUX_RX_FRM_CTL, cfg); 651 } else { 652 cfg = cgx_read(cgx, lmac_id, CGXX_SMUX_CBFC_CTL); 653 cfg |= CGXX_SMUX_CBFC_CTL_BCK_EN; 654 cgx_write(cgx, lmac_id, CGXX_SMUX_CBFC_CTL, cfg); 655 } 656 } else { 657 658 if (!is_pfc_enabled) { 659 cfg = cgx_read(cgx, lmac_id, CGXX_GMP_GMI_RXX_FRM_CTL); 660 cfg &= ~CGX_GMP_GMI_RXX_FRM_CTL_CTL_BCK; 661 cgx_write(cgx, lmac_id, CGXX_GMP_GMI_RXX_FRM_CTL, cfg); 662 663 cfg = cgx_read(cgx, lmac_id, CGXX_SMUX_RX_FRM_CTL); 664 cfg &= ~CGX_SMUX_RX_FRM_CTL_CTL_BCK; 665 cgx_write(cgx, lmac_id, CGXX_SMUX_RX_FRM_CTL, cfg); 666 } else { 667 cfg = cgx_read(cgx, lmac_id, CGXX_SMUX_CBFC_CTL); 668 cfg &= ~CGXX_SMUX_CBFC_CTL_BCK_EN; 669 cgx_write(cgx, lmac_id, CGXX_SMUX_CBFC_CTL, cfg); 670 } 671 } 672 } 673 674 int cgx_get_rx_stats(void *cgxd, int lmac_id, int idx, u64 *rx_stat) 675 { 676 struct cgx *cgx = cgxd; 677 678 if (!is_lmac_valid(cgx, lmac_id)) 679 return -ENODEV; 680 *rx_stat = cgx_read(cgx, lmac_id, CGXX_CMRX_RX_STAT0 + (idx * 8)); 681 return 0; 682 } 683 684 int cgx_get_tx_stats(void *cgxd, int lmac_id, int idx, u64 *tx_stat) 685 { 686 struct cgx *cgx = cgxd; 687 688 if (!is_lmac_valid(cgx, lmac_id)) 689 return -ENODEV; 690 *tx_stat = cgx_read(cgx, lmac_id, CGXX_CMRX_TX_STAT0 + (idx * 8)); 691 return 0; 692 } 693 694 u64 cgx_features_get(void *cgxd) 695 { 696 return ((struct cgx *)cgxd)->hw_features; 697 } 698 699 static int cgx_set_fec_stats_count(struct cgx_link_user_info *linfo) 700 { 701 if (!linfo->fec) 702 return 0; 703 704 switch (linfo->lmac_type_id) { 705 case LMAC_MODE_SGMII: 706 case LMAC_MODE_XAUI: 707 case LMAC_MODE_RXAUI: 708 case LMAC_MODE_QSGMII: 709 return 0; 710 case LMAC_MODE_10G_R: 711 case LMAC_MODE_25G_R: 712 case LMAC_MODE_100G_R: 713 case LMAC_MODE_USXGMII: 714 return 1; 715 case LMAC_MODE_40G_R: 716 return 4; 717 case LMAC_MODE_50G_R: 718 if (linfo->fec == OTX2_FEC_BASER) 719 return 2; 720 else 721 return 1; 722 default: 723 return 0; 724 } 725 } 726 727 int cgx_get_fec_stats(void *cgxd, int lmac_id, struct cgx_fec_stats_rsp *rsp) 728 { 729 int stats, fec_stats_count = 0; 730 int corr_reg, uncorr_reg; 731 struct cgx *cgx = cgxd; 732 733 if (!cgx || lmac_id >= cgx->lmac_count) 734 return -ENODEV; 735 736 if (cgx->lmac_idmap[lmac_id]->link_info.fec == OTX2_FEC_NONE) 737 return 0; 738 739 fec_stats_count = 740 cgx_set_fec_stats_count(&cgx->lmac_idmap[lmac_id]->link_info); 741 if (cgx->lmac_idmap[lmac_id]->link_info.fec == OTX2_FEC_BASER) { 742 corr_reg = CGXX_SPUX_LNX_FEC_CORR_BLOCKS; 743 uncorr_reg = CGXX_SPUX_LNX_FEC_UNCORR_BLOCKS; 744 } else { 745 corr_reg = CGXX_SPUX_RSFEC_CORR; 746 uncorr_reg = CGXX_SPUX_RSFEC_UNCORR; 747 } 748 for (stats = 0; stats < fec_stats_count; stats++) { 749 rsp->fec_corr_blks += 750 cgx_read(cgx, lmac_id, corr_reg + (stats * 8)); 751 rsp->fec_uncorr_blks += 752 cgx_read(cgx, lmac_id, uncorr_reg + (stats * 8)); 753 } 754 return 0; 755 } 756 757 int cgx_lmac_rx_tx_enable(void *cgxd, int lmac_id, bool enable) 758 { 759 struct cgx *cgx = cgxd; 760 u64 cfg; 761 762 if (!is_lmac_valid(cgx, lmac_id)) 763 return -ENODEV; 764 765 cfg = cgx_read(cgx, lmac_id, CGXX_CMRX_CFG); 766 if (enable) 767 cfg |= DATA_PKT_RX_EN | DATA_PKT_TX_EN; 768 else 769 cfg &= ~(DATA_PKT_RX_EN | DATA_PKT_TX_EN); 770 cgx_write(cgx, lmac_id, CGXX_CMRX_CFG, cfg); 771 return 0; 772 } 773 774 int cgx_lmac_tx_enable(void *cgxd, int lmac_id, bool enable) 775 { 776 struct cgx *cgx = cgxd; 777 u64 cfg, last; 778 779 if (!is_lmac_valid(cgx, lmac_id)) 780 return -ENODEV; 781 782 cfg = cgx_read(cgx, lmac_id, CGXX_CMRX_CFG); 783 last = cfg; 784 if (enable) 785 cfg |= DATA_PKT_TX_EN; 786 else 787 cfg &= ~DATA_PKT_TX_EN; 788 789 if (cfg != last) 790 cgx_write(cgx, lmac_id, CGXX_CMRX_CFG, cfg); 791 return !!(last & DATA_PKT_TX_EN); 792 } 793 794 static int cgx_lmac_enadis_pause_frm(void *cgxd, int lmac_id, 795 u8 tx_pause, u8 rx_pause) 796 { 797 struct cgx *cgx = cgxd; 798 u64 cfg; 799 800 if (is_dev_rpm(cgx)) 801 return 0; 802 803 if (!is_lmac_valid(cgx, lmac_id)) 804 return -ENODEV; 805 806 cfg = cgx_read(cgx, lmac_id, CGXX_SMUX_RX_FRM_CTL); 807 cfg &= ~CGX_SMUX_RX_FRM_CTL_CTL_BCK; 808 cfg |= rx_pause ? CGX_SMUX_RX_FRM_CTL_CTL_BCK : 0x0; 809 cgx_write(cgx, lmac_id, CGXX_SMUX_RX_FRM_CTL, cfg); 810 811 cfg = cgx_read(cgx, lmac_id, CGXX_SMUX_TX_CTL); 812 cfg &= ~CGX_SMUX_TX_CTL_L2P_BP_CONV; 813 cfg |= tx_pause ? CGX_SMUX_TX_CTL_L2P_BP_CONV : 0x0; 814 cgx_write(cgx, lmac_id, CGXX_SMUX_TX_CTL, cfg); 815 816 cfg = cgx_read(cgx, 0, CGXX_CMR_RX_OVR_BP); 817 if (tx_pause) { 818 cfg &= ~CGX_CMR_RX_OVR_BP_EN(lmac_id); 819 } else { 820 cfg |= CGX_CMR_RX_OVR_BP_EN(lmac_id); 821 cfg &= ~CGX_CMR_RX_OVR_BP_BP(lmac_id); 822 } 823 cgx_write(cgx, 0, CGXX_CMR_RX_OVR_BP, cfg); 824 return 0; 825 } 826 827 static void cgx_lmac_pause_frm_config(void *cgxd, int lmac_id, bool enable) 828 { 829 struct cgx *cgx = cgxd; 830 u64 cfg; 831 832 if (!is_lmac_valid(cgx, lmac_id)) 833 return; 834 835 if (enable) { 836 /* Set pause time and interval */ 837 cgx_write(cgx, lmac_id, CGXX_SMUX_TX_PAUSE_PKT_TIME, 838 DEFAULT_PAUSE_TIME); 839 cfg = cgx_read(cgx, lmac_id, CGXX_SMUX_TX_PAUSE_PKT_INTERVAL); 840 cfg &= ~0xFFFFULL; 841 cgx_write(cgx, lmac_id, CGXX_SMUX_TX_PAUSE_PKT_INTERVAL, 842 cfg | (DEFAULT_PAUSE_TIME / 2)); 843 844 cgx_write(cgx, lmac_id, CGXX_GMP_GMI_TX_PAUSE_PKT_TIME, 845 DEFAULT_PAUSE_TIME); 846 847 cfg = cgx_read(cgx, lmac_id, 848 CGXX_GMP_GMI_TX_PAUSE_PKT_INTERVAL); 849 cfg &= ~0xFFFFULL; 850 cgx_write(cgx, lmac_id, CGXX_GMP_GMI_TX_PAUSE_PKT_INTERVAL, 851 cfg | (DEFAULT_PAUSE_TIME / 2)); 852 } 853 854 /* ALL pause frames received are completely ignored */ 855 cfg = cgx_read(cgx, lmac_id, CGXX_SMUX_RX_FRM_CTL); 856 cfg &= ~CGX_SMUX_RX_FRM_CTL_CTL_BCK; 857 cgx_write(cgx, lmac_id, CGXX_SMUX_RX_FRM_CTL, cfg); 858 859 cfg = cgx_read(cgx, lmac_id, CGXX_GMP_GMI_RXX_FRM_CTL); 860 cfg &= ~CGX_GMP_GMI_RXX_FRM_CTL_CTL_BCK; 861 cgx_write(cgx, lmac_id, CGXX_GMP_GMI_RXX_FRM_CTL, cfg); 862 863 /* Disable pause frames transmission */ 864 cfg = cgx_read(cgx, lmac_id, CGXX_SMUX_TX_CTL); 865 cfg &= ~CGX_SMUX_TX_CTL_L2P_BP_CONV; 866 cgx_write(cgx, lmac_id, CGXX_SMUX_TX_CTL, cfg); 867 868 cfg = cgx_read(cgx, 0, CGXX_CMR_RX_OVR_BP); 869 cfg |= CGX_CMR_RX_OVR_BP_EN(lmac_id); 870 cfg &= ~CGX_CMR_RX_OVR_BP_BP(lmac_id); 871 cgx_write(cgx, 0, CGXX_CMR_RX_OVR_BP, cfg); 872 873 /* Disable all PFC classes by default */ 874 cfg = cgx_read(cgx, lmac_id, CGXX_SMUX_CBFC_CTL); 875 cfg = FIELD_SET(CGX_PFC_CLASS_MASK, 0, cfg); 876 cgx_write(cgx, lmac_id, CGXX_SMUX_CBFC_CTL, cfg); 877 } 878 879 int verify_lmac_fc_cfg(void *cgxd, int lmac_id, u8 tx_pause, u8 rx_pause, 880 int pfvf_idx) 881 { 882 struct cgx *cgx = cgxd; 883 struct lmac *lmac; 884 885 lmac = lmac_pdata(lmac_id, cgx); 886 if (!lmac) 887 return -ENODEV; 888 889 if (!rx_pause) 890 clear_bit(pfvf_idx, lmac->rx_fc_pfvf_bmap.bmap); 891 else 892 set_bit(pfvf_idx, lmac->rx_fc_pfvf_bmap.bmap); 893 894 if (!tx_pause) 895 clear_bit(pfvf_idx, lmac->tx_fc_pfvf_bmap.bmap); 896 else 897 set_bit(pfvf_idx, lmac->tx_fc_pfvf_bmap.bmap); 898 899 /* check if other pfvfs are using flow control */ 900 if (!rx_pause && bitmap_weight(lmac->rx_fc_pfvf_bmap.bmap, lmac->rx_fc_pfvf_bmap.max)) { 901 dev_warn(&cgx->pdev->dev, 902 "Receive Flow control disable not permitted as its used by other PFVFs\n"); 903 return -EPERM; 904 } 905 906 if (!tx_pause && bitmap_weight(lmac->tx_fc_pfvf_bmap.bmap, lmac->tx_fc_pfvf_bmap.max)) { 907 dev_warn(&cgx->pdev->dev, 908 "Transmit Flow control disable not permitted as its used by other PFVFs\n"); 909 return -EPERM; 910 } 911 912 return 0; 913 } 914 915 int cgx_lmac_pfc_config(void *cgxd, int lmac_id, u8 tx_pause, 916 u8 rx_pause, u16 pfc_en) 917 { 918 struct cgx *cgx = cgxd; 919 u64 cfg; 920 921 if (!is_lmac_valid(cgx, lmac_id)) 922 return -ENODEV; 923 924 /* Return as no traffic classes are requested */ 925 if (tx_pause && !pfc_en) 926 return 0; 927 928 cfg = cgx_read(cgx, lmac_id, CGXX_SMUX_CBFC_CTL); 929 pfc_en |= FIELD_GET(CGX_PFC_CLASS_MASK, cfg); 930 931 if (rx_pause) { 932 cfg |= (CGXX_SMUX_CBFC_CTL_RX_EN | 933 CGXX_SMUX_CBFC_CTL_BCK_EN | 934 CGXX_SMUX_CBFC_CTL_DRP_EN); 935 } else { 936 cfg &= ~(CGXX_SMUX_CBFC_CTL_RX_EN | 937 CGXX_SMUX_CBFC_CTL_BCK_EN | 938 CGXX_SMUX_CBFC_CTL_DRP_EN); 939 } 940 941 if (tx_pause) { 942 cfg |= CGXX_SMUX_CBFC_CTL_TX_EN; 943 cfg = FIELD_SET(CGX_PFC_CLASS_MASK, pfc_en, cfg); 944 } else { 945 cfg &= ~CGXX_SMUX_CBFC_CTL_TX_EN; 946 cfg = FIELD_SET(CGX_PFC_CLASS_MASK, 0, cfg); 947 } 948 949 cgx_write(cgx, lmac_id, CGXX_SMUX_CBFC_CTL, cfg); 950 951 /* Write source MAC address which will be filled into PFC packet */ 952 cfg = cgx_lmac_addr_get(cgx->cgx_id, lmac_id); 953 cgx_write(cgx, lmac_id, CGXX_SMUX_SMAC, cfg); 954 955 return 0; 956 } 957 958 int cgx_lmac_get_pfc_frm_cfg(void *cgxd, int lmac_id, u8 *tx_pause, 959 u8 *rx_pause) 960 { 961 struct cgx *cgx = cgxd; 962 u64 cfg; 963 964 if (!is_lmac_valid(cgx, lmac_id)) 965 return -ENODEV; 966 967 cfg = cgx_read(cgx, lmac_id, CGXX_SMUX_CBFC_CTL); 968 969 *rx_pause = !!(cfg & CGXX_SMUX_CBFC_CTL_RX_EN); 970 *tx_pause = !!(cfg & CGXX_SMUX_CBFC_CTL_TX_EN); 971 972 return 0; 973 } 974 975 void cgx_lmac_ptp_config(void *cgxd, int lmac_id, bool enable) 976 { 977 struct cgx *cgx = cgxd; 978 u64 cfg; 979 980 if (!cgx) 981 return; 982 983 if (enable) { 984 /* Enable inbound PTP timestamping */ 985 cfg = cgx_read(cgx, lmac_id, CGXX_GMP_GMI_RXX_FRM_CTL); 986 cfg |= CGX_GMP_GMI_RXX_FRM_CTL_PTP_MODE; 987 cgx_write(cgx, lmac_id, CGXX_GMP_GMI_RXX_FRM_CTL, cfg); 988 989 cfg = cgx_read(cgx, lmac_id, CGXX_SMUX_RX_FRM_CTL); 990 cfg |= CGX_SMUX_RX_FRM_CTL_PTP_MODE; 991 cgx_write(cgx, lmac_id, CGXX_SMUX_RX_FRM_CTL, cfg); 992 } else { 993 /* Disable inbound PTP stamping */ 994 cfg = cgx_read(cgx, lmac_id, CGXX_GMP_GMI_RXX_FRM_CTL); 995 cfg &= ~CGX_GMP_GMI_RXX_FRM_CTL_PTP_MODE; 996 cgx_write(cgx, lmac_id, CGXX_GMP_GMI_RXX_FRM_CTL, cfg); 997 998 cfg = cgx_read(cgx, lmac_id, CGXX_SMUX_RX_FRM_CTL); 999 cfg &= ~CGX_SMUX_RX_FRM_CTL_PTP_MODE; 1000 cgx_write(cgx, lmac_id, CGXX_SMUX_RX_FRM_CTL, cfg); 1001 } 1002 } 1003 1004 /* CGX Firmware interface low level support */ 1005 int cgx_fwi_cmd_send(u64 req, u64 *resp, struct lmac *lmac) 1006 { 1007 struct cgx *cgx = lmac->cgx; 1008 struct device *dev; 1009 int err = 0; 1010 u64 cmd; 1011 1012 /* Ensure no other command is in progress */ 1013 err = mutex_lock_interruptible(&lmac->cmd_lock); 1014 if (err) 1015 return err; 1016 1017 /* Ensure command register is free */ 1018 cmd = cgx_read(cgx, lmac->lmac_id, CGX_COMMAND_REG); 1019 if (FIELD_GET(CMDREG_OWN, cmd) != CGX_CMD_OWN_NS) { 1020 err = -EBUSY; 1021 goto unlock; 1022 } 1023 1024 /* Update ownership in command request */ 1025 req = FIELD_SET(CMDREG_OWN, CGX_CMD_OWN_FIRMWARE, req); 1026 1027 /* Mark this lmac as pending, before we start */ 1028 lmac->cmd_pend = true; 1029 1030 /* Start command in hardware */ 1031 cgx_write(cgx, lmac->lmac_id, CGX_COMMAND_REG, req); 1032 1033 /* Ensure command is completed without errors */ 1034 if (!wait_event_timeout(lmac->wq_cmd_cmplt, !lmac->cmd_pend, 1035 msecs_to_jiffies(CGX_CMD_TIMEOUT))) { 1036 dev = &cgx->pdev->dev; 1037 dev_err(dev, "cgx port %d:%d cmd %lld timeout\n", 1038 cgx->cgx_id, lmac->lmac_id, FIELD_GET(CMDREG_ID, req)); 1039 err = LMAC_AF_ERR_CMD_TIMEOUT; 1040 goto unlock; 1041 } 1042 1043 /* we have a valid command response */ 1044 smp_rmb(); /* Ensure the latest updates are visible */ 1045 *resp = lmac->resp; 1046 1047 unlock: 1048 mutex_unlock(&lmac->cmd_lock); 1049 1050 return err; 1051 } 1052 1053 int cgx_fwi_cmd_generic(u64 req, u64 *resp, struct cgx *cgx, int lmac_id) 1054 { 1055 struct lmac *lmac; 1056 int err; 1057 1058 lmac = lmac_pdata(lmac_id, cgx); 1059 if (!lmac) 1060 return -ENODEV; 1061 1062 err = cgx_fwi_cmd_send(req, resp, lmac); 1063 1064 /* Check for valid response */ 1065 if (!err) { 1066 if (FIELD_GET(EVTREG_STAT, *resp) == CGX_STAT_FAIL) 1067 return -EIO; 1068 else 1069 return 0; 1070 } 1071 1072 return err; 1073 } 1074 1075 static int cgx_link_usertable_index_map(int speed) 1076 { 1077 switch (speed) { 1078 case SPEED_10: 1079 return CGX_LINK_10M; 1080 case SPEED_100: 1081 return CGX_LINK_100M; 1082 case SPEED_1000: 1083 return CGX_LINK_1G; 1084 case SPEED_2500: 1085 return CGX_LINK_2HG; 1086 case SPEED_5000: 1087 return CGX_LINK_5G; 1088 case SPEED_10000: 1089 return CGX_LINK_10G; 1090 case SPEED_20000: 1091 return CGX_LINK_20G; 1092 case SPEED_25000: 1093 return CGX_LINK_25G; 1094 case SPEED_40000: 1095 return CGX_LINK_40G; 1096 case SPEED_50000: 1097 return CGX_LINK_50G; 1098 case 80000: 1099 return CGX_LINK_80G; 1100 case SPEED_100000: 1101 return CGX_LINK_100G; 1102 case SPEED_UNKNOWN: 1103 return CGX_LINK_NONE; 1104 } 1105 return CGX_LINK_NONE; 1106 } 1107 1108 static void set_mod_args(struct cgx_set_link_mode_args *args, 1109 u32 speed, u8 duplex, u8 autoneg, u64 mode) 1110 { 1111 /* Fill default values incase of user did not pass 1112 * valid parameters 1113 */ 1114 if (args->duplex == DUPLEX_UNKNOWN) 1115 args->duplex = duplex; 1116 if (args->speed == SPEED_UNKNOWN) 1117 args->speed = speed; 1118 if (args->an == AUTONEG_UNKNOWN) 1119 args->an = autoneg; 1120 args->mode = mode; 1121 args->ports = 0; 1122 } 1123 1124 static void otx2_map_ethtool_link_modes(u64 bitmask, 1125 struct cgx_set_link_mode_args *args) 1126 { 1127 switch (bitmask) { 1128 case ETHTOOL_LINK_MODE_10baseT_Half_BIT: 1129 set_mod_args(args, 10, 1, 1, BIT_ULL(CGX_MODE_SGMII)); 1130 break; 1131 case ETHTOOL_LINK_MODE_10baseT_Full_BIT: 1132 set_mod_args(args, 10, 0, 1, BIT_ULL(CGX_MODE_SGMII)); 1133 break; 1134 case ETHTOOL_LINK_MODE_100baseT_Half_BIT: 1135 set_mod_args(args, 100, 1, 1, BIT_ULL(CGX_MODE_SGMII)); 1136 break; 1137 case ETHTOOL_LINK_MODE_100baseT_Full_BIT: 1138 set_mod_args(args, 100, 0, 1, BIT_ULL(CGX_MODE_SGMII)); 1139 break; 1140 case ETHTOOL_LINK_MODE_1000baseT_Half_BIT: 1141 set_mod_args(args, 1000, 1, 1, BIT_ULL(CGX_MODE_SGMII)); 1142 break; 1143 case ETHTOOL_LINK_MODE_1000baseT_Full_BIT: 1144 set_mod_args(args, 1000, 0, 1, BIT_ULL(CGX_MODE_SGMII)); 1145 break; 1146 case ETHTOOL_LINK_MODE_1000baseX_Full_BIT: 1147 set_mod_args(args, 1000, 0, 0, BIT_ULL(CGX_MODE_1000_BASEX)); 1148 break; 1149 case ETHTOOL_LINK_MODE_10000baseT_Full_BIT: 1150 set_mod_args(args, 1000, 0, 1, BIT_ULL(CGX_MODE_QSGMII)); 1151 break; 1152 case ETHTOOL_LINK_MODE_10000baseSR_Full_BIT: 1153 set_mod_args(args, 10000, 0, 0, BIT_ULL(CGX_MODE_10G_C2C)); 1154 break; 1155 case ETHTOOL_LINK_MODE_10000baseLR_Full_BIT: 1156 set_mod_args(args, 10000, 0, 0, BIT_ULL(CGX_MODE_10G_C2M)); 1157 break; 1158 case ETHTOOL_LINK_MODE_10000baseKR_Full_BIT: 1159 set_mod_args(args, 10000, 0, 1, BIT_ULL(CGX_MODE_10G_KR)); 1160 break; 1161 case ETHTOOL_LINK_MODE_25000baseSR_Full_BIT: 1162 set_mod_args(args, 25000, 0, 0, BIT_ULL(CGX_MODE_25G_C2C)); 1163 break; 1164 case ETHTOOL_LINK_MODE_25000baseCR_Full_BIT: 1165 set_mod_args(args, 25000, 0, 1, BIT_ULL(CGX_MODE_25G_CR)); 1166 break; 1167 case ETHTOOL_LINK_MODE_25000baseKR_Full_BIT: 1168 set_mod_args(args, 25000, 0, 1, BIT_ULL(CGX_MODE_25G_KR)); 1169 break; 1170 case ETHTOOL_LINK_MODE_40000baseSR4_Full_BIT: 1171 set_mod_args(args, 40000, 0, 0, BIT_ULL(CGX_MODE_40G_C2C)); 1172 break; 1173 case ETHTOOL_LINK_MODE_40000baseLR4_Full_BIT: 1174 set_mod_args(args, 40000, 0, 0, BIT_ULL(CGX_MODE_40G_C2M)); 1175 break; 1176 case ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT: 1177 set_mod_args(args, 40000, 0, 1, BIT_ULL(CGX_MODE_40G_CR4)); 1178 break; 1179 case ETHTOOL_LINK_MODE_40000baseKR4_Full_BIT: 1180 set_mod_args(args, 40000, 0, 1, BIT_ULL(CGX_MODE_40G_KR4)); 1181 break; 1182 case ETHTOOL_LINK_MODE_50000baseSR_Full_BIT: 1183 set_mod_args(args, 50000, 0, 0, BIT_ULL(CGX_MODE_50G_C2C)); 1184 break; 1185 case ETHTOOL_LINK_MODE_50000baseLR_ER_FR_Full_BIT: 1186 set_mod_args(args, 50000, 0, 0, BIT_ULL(CGX_MODE_50G_C2M)); 1187 break; 1188 case ETHTOOL_LINK_MODE_50000baseCR_Full_BIT: 1189 set_mod_args(args, 50000, 0, 1, BIT_ULL(CGX_MODE_50G_CR)); 1190 break; 1191 case ETHTOOL_LINK_MODE_50000baseKR_Full_BIT: 1192 set_mod_args(args, 50000, 0, 1, BIT_ULL(CGX_MODE_50G_KR)); 1193 break; 1194 case ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT: 1195 set_mod_args(args, 100000, 0, 0, BIT_ULL(CGX_MODE_100G_C2C)); 1196 break; 1197 case ETHTOOL_LINK_MODE_100000baseLR4_ER4_Full_BIT: 1198 set_mod_args(args, 100000, 0, 0, BIT_ULL(CGX_MODE_100G_C2M)); 1199 break; 1200 case ETHTOOL_LINK_MODE_100000baseCR4_Full_BIT: 1201 set_mod_args(args, 100000, 0, 1, BIT_ULL(CGX_MODE_100G_CR4)); 1202 break; 1203 case ETHTOOL_LINK_MODE_100000baseKR4_Full_BIT: 1204 set_mod_args(args, 100000, 0, 1, BIT_ULL(CGX_MODE_100G_KR4)); 1205 break; 1206 default: 1207 set_mod_args(args, 0, 1, 0, BIT_ULL(CGX_MODE_MAX)); 1208 break; 1209 } 1210 } 1211 1212 static inline void link_status_user_format(u64 lstat, 1213 struct cgx_link_user_info *linfo, 1214 struct cgx *cgx, u8 lmac_id) 1215 { 1216 const char *lmac_string; 1217 1218 linfo->link_up = FIELD_GET(RESP_LINKSTAT_UP, lstat); 1219 linfo->full_duplex = FIELD_GET(RESP_LINKSTAT_FDUPLEX, lstat); 1220 linfo->speed = cgx_speed_mbps[FIELD_GET(RESP_LINKSTAT_SPEED, lstat)]; 1221 linfo->an = FIELD_GET(RESP_LINKSTAT_AN, lstat); 1222 linfo->fec = FIELD_GET(RESP_LINKSTAT_FEC, lstat); 1223 linfo->lmac_type_id = FIELD_GET(RESP_LINKSTAT_LMAC_TYPE, lstat); 1224 1225 if (linfo->lmac_type_id >= LMAC_MODE_MAX) { 1226 dev_err(&cgx->pdev->dev, "Unknown lmac_type_id %d reported by firmware on cgx port%d:%d", 1227 linfo->lmac_type_id, cgx->cgx_id, lmac_id); 1228 strncpy(linfo->lmac_type, "Unknown", LMACTYPE_STR_LEN - 1); 1229 return; 1230 } 1231 1232 lmac_string = cgx_lmactype_string[linfo->lmac_type_id]; 1233 strncpy(linfo->lmac_type, lmac_string, LMACTYPE_STR_LEN - 1); 1234 } 1235 1236 /* Hardware event handlers */ 1237 static inline void cgx_link_change_handler(u64 lstat, 1238 struct lmac *lmac) 1239 { 1240 struct cgx_link_user_info *linfo; 1241 struct cgx *cgx = lmac->cgx; 1242 struct cgx_link_event event; 1243 struct device *dev; 1244 int err_type; 1245 1246 dev = &cgx->pdev->dev; 1247 1248 link_status_user_format(lstat, &event.link_uinfo, cgx, lmac->lmac_id); 1249 err_type = FIELD_GET(RESP_LINKSTAT_ERRTYPE, lstat); 1250 1251 event.cgx_id = cgx->cgx_id; 1252 event.lmac_id = lmac->lmac_id; 1253 1254 /* update the local copy of link status */ 1255 lmac->link_info = event.link_uinfo; 1256 linfo = &lmac->link_info; 1257 1258 if (err_type == CGX_ERR_SPEED_CHANGE_INVALID) 1259 return; 1260 1261 /* Ensure callback doesn't get unregistered until we finish it */ 1262 spin_lock(&lmac->event_cb_lock); 1263 1264 if (!lmac->event_cb.notify_link_chg) { 1265 dev_dbg(dev, "cgx port %d:%d Link change handler null", 1266 cgx->cgx_id, lmac->lmac_id); 1267 if (err_type != CGX_ERR_NONE) { 1268 dev_err(dev, "cgx port %d:%d Link error %d\n", 1269 cgx->cgx_id, lmac->lmac_id, err_type); 1270 } 1271 dev_info(dev, "cgx port %d:%d Link is %s %d Mbps\n", 1272 cgx->cgx_id, lmac->lmac_id, 1273 linfo->link_up ? "UP" : "DOWN", linfo->speed); 1274 goto err; 1275 } 1276 1277 if (lmac->event_cb.notify_link_chg(&event, lmac->event_cb.data)) 1278 dev_err(dev, "event notification failure\n"); 1279 err: 1280 spin_unlock(&lmac->event_cb_lock); 1281 } 1282 1283 static inline bool cgx_cmdresp_is_linkevent(u64 event) 1284 { 1285 u8 id; 1286 1287 id = FIELD_GET(EVTREG_ID, event); 1288 if (id == CGX_CMD_LINK_BRING_UP || 1289 id == CGX_CMD_LINK_BRING_DOWN || 1290 id == CGX_CMD_MODE_CHANGE) 1291 return true; 1292 else 1293 return false; 1294 } 1295 1296 static inline bool cgx_event_is_linkevent(u64 event) 1297 { 1298 if (FIELD_GET(EVTREG_ID, event) == CGX_EVT_LINK_CHANGE) 1299 return true; 1300 else 1301 return false; 1302 } 1303 1304 static irqreturn_t cgx_fwi_event_handler(int irq, void *data) 1305 { 1306 u64 event, offset, clear_bit; 1307 struct lmac *lmac = data; 1308 struct cgx *cgx; 1309 1310 cgx = lmac->cgx; 1311 1312 /* Clear SW_INT for RPM and CMR_INT for CGX */ 1313 offset = cgx->mac_ops->int_register; 1314 clear_bit = cgx->mac_ops->int_ena_bit; 1315 1316 event = cgx_read(cgx, lmac->lmac_id, CGX_EVENT_REG); 1317 1318 if (!FIELD_GET(EVTREG_ACK, event)) 1319 return IRQ_NONE; 1320 1321 switch (FIELD_GET(EVTREG_EVT_TYPE, event)) { 1322 case CGX_EVT_CMD_RESP: 1323 /* Copy the response. Since only one command is active at a 1324 * time, there is no way a response can get overwritten 1325 */ 1326 lmac->resp = event; 1327 /* Ensure response is updated before thread context starts */ 1328 smp_wmb(); 1329 1330 /* There wont be separate events for link change initiated from 1331 * software; Hence report the command responses as events 1332 */ 1333 if (cgx_cmdresp_is_linkevent(event)) 1334 cgx_link_change_handler(event, lmac); 1335 1336 /* Release thread waiting for completion */ 1337 lmac->cmd_pend = false; 1338 wake_up_interruptible(&lmac->wq_cmd_cmplt); 1339 break; 1340 case CGX_EVT_ASYNC: 1341 if (cgx_event_is_linkevent(event)) 1342 cgx_link_change_handler(event, lmac); 1343 break; 1344 } 1345 1346 /* Any new event or command response will be posted by firmware 1347 * only after the current status is acked. 1348 * Ack the interrupt register as well. 1349 */ 1350 cgx_write(lmac->cgx, lmac->lmac_id, CGX_EVENT_REG, 0); 1351 cgx_write(lmac->cgx, lmac->lmac_id, offset, clear_bit); 1352 1353 return IRQ_HANDLED; 1354 } 1355 1356 /* APIs for PHY management using CGX firmware interface */ 1357 1358 /* callback registration for hardware events like link change */ 1359 int cgx_lmac_evh_register(struct cgx_event_cb *cb, void *cgxd, int lmac_id) 1360 { 1361 struct cgx *cgx = cgxd; 1362 struct lmac *lmac; 1363 1364 lmac = lmac_pdata(lmac_id, cgx); 1365 if (!lmac) 1366 return -ENODEV; 1367 1368 lmac->event_cb = *cb; 1369 1370 return 0; 1371 } 1372 1373 int cgx_lmac_evh_unregister(void *cgxd, int lmac_id) 1374 { 1375 struct lmac *lmac; 1376 unsigned long flags; 1377 struct cgx *cgx = cgxd; 1378 1379 lmac = lmac_pdata(lmac_id, cgx); 1380 if (!lmac) 1381 return -ENODEV; 1382 1383 spin_lock_irqsave(&lmac->event_cb_lock, flags); 1384 lmac->event_cb.notify_link_chg = NULL; 1385 lmac->event_cb.data = NULL; 1386 spin_unlock_irqrestore(&lmac->event_cb_lock, flags); 1387 1388 return 0; 1389 } 1390 1391 int cgx_get_fwdata_base(u64 *base) 1392 { 1393 u64 req = 0, resp; 1394 struct cgx *cgx; 1395 int first_lmac; 1396 int err; 1397 1398 cgx = list_first_entry_or_null(&cgx_list, struct cgx, cgx_list); 1399 if (!cgx) 1400 return -ENXIO; 1401 1402 first_lmac = find_first_bit(&cgx->lmac_bmap, cgx->max_lmac_per_mac); 1403 req = FIELD_SET(CMDREG_ID, CGX_CMD_GET_FWD_BASE, req); 1404 err = cgx_fwi_cmd_generic(req, &resp, cgx, first_lmac); 1405 if (!err) 1406 *base = FIELD_GET(RESP_FWD_BASE, resp); 1407 1408 return err; 1409 } 1410 1411 int cgx_set_link_mode(void *cgxd, struct cgx_set_link_mode_args args, 1412 int cgx_id, int lmac_id) 1413 { 1414 struct cgx *cgx = cgxd; 1415 u64 req = 0, resp; 1416 1417 if (!cgx) 1418 return -ENODEV; 1419 1420 if (args.mode) 1421 otx2_map_ethtool_link_modes(args.mode, &args); 1422 if (!args.speed && args.duplex && !args.an) 1423 return -EINVAL; 1424 1425 req = FIELD_SET(CMDREG_ID, CGX_CMD_MODE_CHANGE, req); 1426 req = FIELD_SET(CMDMODECHANGE_SPEED, 1427 cgx_link_usertable_index_map(args.speed), req); 1428 req = FIELD_SET(CMDMODECHANGE_DUPLEX, args.duplex, req); 1429 req = FIELD_SET(CMDMODECHANGE_AN, args.an, req); 1430 req = FIELD_SET(CMDMODECHANGE_PORT, args.ports, req); 1431 req = FIELD_SET(CMDMODECHANGE_FLAGS, args.mode, req); 1432 1433 return cgx_fwi_cmd_generic(req, &resp, cgx, lmac_id); 1434 } 1435 int cgx_set_fec(u64 fec, int cgx_id, int lmac_id) 1436 { 1437 u64 req = 0, resp; 1438 struct cgx *cgx; 1439 int err = 0; 1440 1441 cgx = cgx_get_pdata(cgx_id); 1442 if (!cgx) 1443 return -ENXIO; 1444 1445 req = FIELD_SET(CMDREG_ID, CGX_CMD_SET_FEC, req); 1446 req = FIELD_SET(CMDSETFEC, fec, req); 1447 err = cgx_fwi_cmd_generic(req, &resp, cgx, lmac_id); 1448 if (err) 1449 return err; 1450 1451 cgx->lmac_idmap[lmac_id]->link_info.fec = 1452 FIELD_GET(RESP_LINKSTAT_FEC, resp); 1453 return cgx->lmac_idmap[lmac_id]->link_info.fec; 1454 } 1455 1456 int cgx_get_phy_fec_stats(void *cgxd, int lmac_id) 1457 { 1458 struct cgx *cgx = cgxd; 1459 u64 req = 0, resp; 1460 1461 if (!cgx) 1462 return -ENODEV; 1463 1464 req = FIELD_SET(CMDREG_ID, CGX_CMD_GET_PHY_FEC_STATS, req); 1465 return cgx_fwi_cmd_generic(req, &resp, cgx, lmac_id); 1466 } 1467 1468 static int cgx_fwi_link_change(struct cgx *cgx, int lmac_id, bool enable) 1469 { 1470 u64 req = 0; 1471 u64 resp; 1472 1473 if (enable) { 1474 req = FIELD_SET(CMDREG_ID, CGX_CMD_LINK_BRING_UP, req); 1475 /* On CN10K firmware offloads link bring up/down operations to ECP 1476 * On Octeontx2 link operations are handled by firmware itself 1477 * which can cause mbox errors so configure maximum time firmware 1478 * poll for Link as 1000 ms 1479 */ 1480 if (!is_dev_rpm(cgx)) 1481 req = FIELD_SET(LINKCFG_TIMEOUT, 1000, req); 1482 1483 } else { 1484 req = FIELD_SET(CMDREG_ID, CGX_CMD_LINK_BRING_DOWN, req); 1485 } 1486 return cgx_fwi_cmd_generic(req, &resp, cgx, lmac_id); 1487 } 1488 1489 static inline int cgx_fwi_read_version(u64 *resp, struct cgx *cgx) 1490 { 1491 int first_lmac = find_first_bit(&cgx->lmac_bmap, cgx->max_lmac_per_mac); 1492 u64 req = 0; 1493 1494 req = FIELD_SET(CMDREG_ID, CGX_CMD_GET_FW_VER, req); 1495 return cgx_fwi_cmd_generic(req, resp, cgx, first_lmac); 1496 } 1497 1498 static int cgx_lmac_verify_fwi_version(struct cgx *cgx) 1499 { 1500 struct device *dev = &cgx->pdev->dev; 1501 int major_ver, minor_ver; 1502 u64 resp; 1503 int err; 1504 1505 if (!cgx->lmac_count) 1506 return 0; 1507 1508 err = cgx_fwi_read_version(&resp, cgx); 1509 if (err) 1510 return err; 1511 1512 major_ver = FIELD_GET(RESP_MAJOR_VER, resp); 1513 minor_ver = FIELD_GET(RESP_MINOR_VER, resp); 1514 dev_dbg(dev, "Firmware command interface version = %d.%d\n", 1515 major_ver, minor_ver); 1516 if (major_ver != CGX_FIRMWARE_MAJOR_VER) 1517 return -EIO; 1518 else 1519 return 0; 1520 } 1521 1522 static void cgx_lmac_linkup_work(struct work_struct *work) 1523 { 1524 struct cgx *cgx = container_of(work, struct cgx, cgx_cmd_work); 1525 struct device *dev = &cgx->pdev->dev; 1526 int i, err; 1527 1528 /* Do Link up for all the enabled lmacs */ 1529 for_each_set_bit(i, &cgx->lmac_bmap, cgx->max_lmac_per_mac) { 1530 err = cgx_fwi_link_change(cgx, i, true); 1531 if (err) 1532 dev_info(dev, "cgx port %d:%d Link up command failed\n", 1533 cgx->cgx_id, i); 1534 } 1535 } 1536 1537 int cgx_lmac_linkup_start(void *cgxd) 1538 { 1539 struct cgx *cgx = cgxd; 1540 1541 if (!cgx) 1542 return -ENODEV; 1543 1544 queue_work(cgx->cgx_cmd_workq, &cgx->cgx_cmd_work); 1545 1546 return 0; 1547 } 1548 1549 int cgx_lmac_reset(void *cgxd, int lmac_id, u8 pf_req_flr) 1550 { 1551 struct cgx *cgx = cgxd; 1552 u64 cfg; 1553 1554 if (!is_lmac_valid(cgx, lmac_id)) 1555 return -ENODEV; 1556 1557 /* Resetting PFC related CSRs */ 1558 cfg = 0xff; 1559 cgx_write(cgxd, lmac_id, CGXX_CMRX_RX_LOGL_XON, cfg); 1560 1561 if (pf_req_flr) 1562 cgx_lmac_internal_loopback(cgxd, lmac_id, false); 1563 return 0; 1564 } 1565 1566 static int cgx_configure_interrupt(struct cgx *cgx, struct lmac *lmac, 1567 int cnt, bool req_free) 1568 { 1569 struct mac_ops *mac_ops = cgx->mac_ops; 1570 u64 offset, ena_bit; 1571 unsigned int irq; 1572 int err; 1573 1574 irq = pci_irq_vector(cgx->pdev, mac_ops->lmac_fwi + 1575 cnt * mac_ops->irq_offset); 1576 offset = mac_ops->int_set_reg; 1577 ena_bit = mac_ops->int_ena_bit; 1578 1579 if (req_free) { 1580 free_irq(irq, lmac); 1581 return 0; 1582 } 1583 1584 err = request_irq(irq, cgx_fwi_event_handler, 0, lmac->name, lmac); 1585 if (err) 1586 return err; 1587 1588 /* Enable interrupt */ 1589 cgx_write(cgx, lmac->lmac_id, offset, ena_bit); 1590 return 0; 1591 } 1592 1593 int cgx_get_nr_lmacs(void *cgxd) 1594 { 1595 struct cgx *cgx = cgxd; 1596 1597 return cgx_read(cgx, 0, CGXX_CMRX_RX_LMACS) & 0x7ULL; 1598 } 1599 1600 u8 cgx_get_lmacid(void *cgxd, u8 lmac_index) 1601 { 1602 struct cgx *cgx = cgxd; 1603 1604 return cgx->lmac_idmap[lmac_index]->lmac_id; 1605 } 1606 1607 unsigned long cgx_get_lmac_bmap(void *cgxd) 1608 { 1609 struct cgx *cgx = cgxd; 1610 1611 return cgx->lmac_bmap; 1612 } 1613 1614 static int cgx_lmac_init(struct cgx *cgx) 1615 { 1616 struct lmac *lmac; 1617 u64 lmac_list; 1618 int i, err; 1619 1620 /* lmac_list specifies which lmacs are enabled 1621 * when bit n is set to 1, LMAC[n] is enabled 1622 */ 1623 if (cgx->mac_ops->non_contiguous_serdes_lane) { 1624 if (is_dev_rpm2(cgx)) 1625 lmac_list = 1626 cgx_read(cgx, 0, RPM2_CMRX_RX_LMACS) & 0xFFULL; 1627 else 1628 lmac_list = 1629 cgx_read(cgx, 0, CGXX_CMRX_RX_LMACS) & 0xFULL; 1630 } 1631 1632 if (cgx->lmac_count > cgx->max_lmac_per_mac) 1633 cgx->lmac_count = cgx->max_lmac_per_mac; 1634 1635 for (i = 0; i < cgx->lmac_count; i++) { 1636 lmac = kzalloc(sizeof(struct lmac), GFP_KERNEL); 1637 if (!lmac) 1638 return -ENOMEM; 1639 lmac->name = kcalloc(1, sizeof("cgx_fwi_xxx_yyy"), GFP_KERNEL); 1640 if (!lmac->name) { 1641 err = -ENOMEM; 1642 goto err_lmac_free; 1643 } 1644 sprintf(lmac->name, "cgx_fwi_%d_%d", cgx->cgx_id, i); 1645 if (cgx->mac_ops->non_contiguous_serdes_lane) { 1646 lmac->lmac_id = __ffs64(lmac_list); 1647 lmac_list &= ~BIT_ULL(lmac->lmac_id); 1648 } else { 1649 lmac->lmac_id = i; 1650 } 1651 1652 lmac->cgx = cgx; 1653 lmac->mac_to_index_bmap.max = 1654 cgx->mac_ops->dmac_filter_count / 1655 cgx->lmac_count; 1656 1657 err = rvu_alloc_bitmap(&lmac->mac_to_index_bmap); 1658 if (err) 1659 goto err_name_free; 1660 1661 /* Reserve first entry for default MAC address */ 1662 set_bit(0, lmac->mac_to_index_bmap.bmap); 1663 1664 lmac->rx_fc_pfvf_bmap.max = 128; 1665 err = rvu_alloc_bitmap(&lmac->rx_fc_pfvf_bmap); 1666 if (err) 1667 goto err_dmac_bmap_free; 1668 1669 lmac->tx_fc_pfvf_bmap.max = 128; 1670 err = rvu_alloc_bitmap(&lmac->tx_fc_pfvf_bmap); 1671 if (err) 1672 goto err_rx_fc_bmap_free; 1673 1674 init_waitqueue_head(&lmac->wq_cmd_cmplt); 1675 mutex_init(&lmac->cmd_lock); 1676 spin_lock_init(&lmac->event_cb_lock); 1677 err = cgx_configure_interrupt(cgx, lmac, lmac->lmac_id, false); 1678 if (err) 1679 goto err_bitmap_free; 1680 1681 /* Add reference */ 1682 cgx->lmac_idmap[lmac->lmac_id] = lmac; 1683 set_bit(lmac->lmac_id, &cgx->lmac_bmap); 1684 cgx->mac_ops->mac_pause_frm_config(cgx, lmac->lmac_id, true); 1685 lmac->lmac_type = cgx->mac_ops->get_lmac_type(cgx, lmac->lmac_id); 1686 } 1687 1688 return cgx_lmac_verify_fwi_version(cgx); 1689 1690 err_bitmap_free: 1691 rvu_free_bitmap(&lmac->tx_fc_pfvf_bmap); 1692 err_rx_fc_bmap_free: 1693 rvu_free_bitmap(&lmac->rx_fc_pfvf_bmap); 1694 err_dmac_bmap_free: 1695 rvu_free_bitmap(&lmac->mac_to_index_bmap); 1696 err_name_free: 1697 kfree(lmac->name); 1698 err_lmac_free: 1699 kfree(lmac); 1700 return err; 1701 } 1702 1703 static int cgx_lmac_exit(struct cgx *cgx) 1704 { 1705 struct lmac *lmac; 1706 int i; 1707 1708 if (cgx->cgx_cmd_workq) { 1709 destroy_workqueue(cgx->cgx_cmd_workq); 1710 cgx->cgx_cmd_workq = NULL; 1711 } 1712 1713 /* Free all lmac related resources */ 1714 for_each_set_bit(i, &cgx->lmac_bmap, cgx->max_lmac_per_mac) { 1715 lmac = cgx->lmac_idmap[i]; 1716 if (!lmac) 1717 continue; 1718 cgx->mac_ops->mac_pause_frm_config(cgx, lmac->lmac_id, false); 1719 cgx_configure_interrupt(cgx, lmac, lmac->lmac_id, true); 1720 kfree(lmac->mac_to_index_bmap.bmap); 1721 kfree(lmac->name); 1722 kfree(lmac); 1723 } 1724 1725 return 0; 1726 } 1727 1728 static void cgx_populate_features(struct cgx *cgx) 1729 { 1730 u64 cfg; 1731 1732 cfg = cgx_read(cgx, 0, CGX_CONST); 1733 cgx->mac_ops->fifo_len = FIELD_GET(CGX_CONST_RXFIFO_SIZE, cfg); 1734 cgx->max_lmac_per_mac = FIELD_GET(CGX_CONST_MAX_LMACS, cfg); 1735 1736 if (is_dev_rpm(cgx)) 1737 cgx->hw_features = (RVU_LMAC_FEAT_DMACF | RVU_MAC_RPM | 1738 RVU_LMAC_FEAT_FC | RVU_LMAC_FEAT_PTP); 1739 else 1740 cgx->hw_features = (RVU_LMAC_FEAT_FC | RVU_LMAC_FEAT_HIGIG2 | 1741 RVU_LMAC_FEAT_PTP | RVU_LMAC_FEAT_DMACF); 1742 } 1743 1744 static u8 cgx_get_rxid_mapoffset(struct cgx *cgx) 1745 { 1746 if (cgx->pdev->subsystem_device == PCI_SUBSYS_DEVID_CNF10KB_RPM || 1747 is_dev_rpm2(cgx)) 1748 return 0x80; 1749 else 1750 return 0x60; 1751 } 1752 1753 static struct mac_ops cgx_mac_ops = { 1754 .name = "cgx", 1755 .csr_offset = 0, 1756 .lmac_offset = 18, 1757 .int_register = CGXX_CMRX_INT, 1758 .int_set_reg = CGXX_CMRX_INT_ENA_W1S, 1759 .irq_offset = 9, 1760 .int_ena_bit = FW_CGX_INT, 1761 .lmac_fwi = CGX_LMAC_FWI, 1762 .non_contiguous_serdes_lane = false, 1763 .rx_stats_cnt = 9, 1764 .tx_stats_cnt = 18, 1765 .dmac_filter_count = 32, 1766 .get_nr_lmacs = cgx_get_nr_lmacs, 1767 .get_lmac_type = cgx_get_lmac_type, 1768 .lmac_fifo_len = cgx_get_lmac_fifo_len, 1769 .mac_lmac_intl_lbk = cgx_lmac_internal_loopback, 1770 .mac_get_rx_stats = cgx_get_rx_stats, 1771 .mac_get_tx_stats = cgx_get_tx_stats, 1772 .get_fec_stats = cgx_get_fec_stats, 1773 .mac_enadis_rx_pause_fwding = cgx_lmac_enadis_rx_pause_fwding, 1774 .mac_get_pause_frm_status = cgx_lmac_get_pause_frm_status, 1775 .mac_enadis_pause_frm = cgx_lmac_enadis_pause_frm, 1776 .mac_pause_frm_config = cgx_lmac_pause_frm_config, 1777 .mac_enadis_ptp_config = cgx_lmac_ptp_config, 1778 .mac_rx_tx_enable = cgx_lmac_rx_tx_enable, 1779 .mac_tx_enable = cgx_lmac_tx_enable, 1780 .pfc_config = cgx_lmac_pfc_config, 1781 .mac_get_pfc_frm_cfg = cgx_lmac_get_pfc_frm_cfg, 1782 .mac_reset = cgx_lmac_reset, 1783 }; 1784 1785 static int cgx_probe(struct pci_dev *pdev, const struct pci_device_id *id) 1786 { 1787 struct device *dev = &pdev->dev; 1788 struct cgx *cgx; 1789 int err, nvec; 1790 1791 cgx = devm_kzalloc(dev, sizeof(*cgx), GFP_KERNEL); 1792 if (!cgx) 1793 return -ENOMEM; 1794 cgx->pdev = pdev; 1795 1796 pci_set_drvdata(pdev, cgx); 1797 1798 /* Use mac_ops to get MAC specific features */ 1799 if (is_dev_rpm(cgx)) 1800 cgx->mac_ops = rpm_get_mac_ops(cgx); 1801 else 1802 cgx->mac_ops = &cgx_mac_ops; 1803 1804 cgx->mac_ops->rxid_map_offset = cgx_get_rxid_mapoffset(cgx); 1805 1806 err = pci_enable_device(pdev); 1807 if (err) { 1808 dev_err(dev, "Failed to enable PCI device\n"); 1809 pci_set_drvdata(pdev, NULL); 1810 return err; 1811 } 1812 1813 err = pci_request_regions(pdev, DRV_NAME); 1814 if (err) { 1815 dev_err(dev, "PCI request regions failed 0x%x\n", err); 1816 goto err_disable_device; 1817 } 1818 1819 /* MAP configuration registers */ 1820 cgx->reg_base = pcim_iomap(pdev, PCI_CFG_REG_BAR_NUM, 0); 1821 if (!cgx->reg_base) { 1822 dev_err(dev, "CGX: Cannot map CSR memory space, aborting\n"); 1823 err = -ENOMEM; 1824 goto err_release_regions; 1825 } 1826 1827 cgx->lmac_count = cgx->mac_ops->get_nr_lmacs(cgx); 1828 if (!cgx->lmac_count) { 1829 dev_notice(dev, "CGX %d LMAC count is zero, skipping probe\n", cgx->cgx_id); 1830 err = -EOPNOTSUPP; 1831 goto err_release_regions; 1832 } 1833 1834 nvec = pci_msix_vec_count(cgx->pdev); 1835 err = pci_alloc_irq_vectors(pdev, nvec, nvec, PCI_IRQ_MSIX); 1836 if (err < 0 || err != nvec) { 1837 dev_err(dev, "Request for %d msix vectors failed, err %d\n", 1838 nvec, err); 1839 goto err_release_regions; 1840 } 1841 1842 cgx->cgx_id = (pci_resource_start(pdev, PCI_CFG_REG_BAR_NUM) >> 24) 1843 & CGX_ID_MASK; 1844 1845 /* init wq for processing linkup requests */ 1846 INIT_WORK(&cgx->cgx_cmd_work, cgx_lmac_linkup_work); 1847 cgx->cgx_cmd_workq = alloc_workqueue("cgx_cmd_workq", 0, 0); 1848 if (!cgx->cgx_cmd_workq) { 1849 dev_err(dev, "alloc workqueue failed for cgx cmd"); 1850 err = -ENOMEM; 1851 goto err_free_irq_vectors; 1852 } 1853 1854 list_add(&cgx->cgx_list, &cgx_list); 1855 1856 1857 cgx_populate_features(cgx); 1858 1859 mutex_init(&cgx->lock); 1860 1861 err = cgx_lmac_init(cgx); 1862 if (err) 1863 goto err_release_lmac; 1864 1865 return 0; 1866 1867 err_release_lmac: 1868 cgx_lmac_exit(cgx); 1869 list_del(&cgx->cgx_list); 1870 err_free_irq_vectors: 1871 pci_free_irq_vectors(pdev); 1872 err_release_regions: 1873 pci_release_regions(pdev); 1874 err_disable_device: 1875 pci_disable_device(pdev); 1876 pci_set_drvdata(pdev, NULL); 1877 return err; 1878 } 1879 1880 static void cgx_remove(struct pci_dev *pdev) 1881 { 1882 struct cgx *cgx = pci_get_drvdata(pdev); 1883 1884 if (cgx) { 1885 cgx_lmac_exit(cgx); 1886 list_del(&cgx->cgx_list); 1887 } 1888 pci_free_irq_vectors(pdev); 1889 pci_release_regions(pdev); 1890 pci_disable_device(pdev); 1891 pci_set_drvdata(pdev, NULL); 1892 } 1893 1894 struct pci_driver cgx_driver = { 1895 .name = DRV_NAME, 1896 .id_table = cgx_id_table, 1897 .probe = cgx_probe, 1898 .remove = cgx_remove, 1899 }; 1900