1 // SPDX-License-Identifier: GPL-2.0 2 /* Marvell OcteonTx2 CGX driver 3 * 4 * Copyright (C) 2018 Marvell. 5 * 6 */ 7 8 #include <linux/acpi.h> 9 #include <linux/module.h> 10 #include <linux/interrupt.h> 11 #include <linux/pci.h> 12 #include <linux/netdevice.h> 13 #include <linux/etherdevice.h> 14 #include <linux/ethtool.h> 15 #include <linux/phy.h> 16 #include <linux/of.h> 17 #include <linux/of_mdio.h> 18 #include <linux/of_net.h> 19 20 #include "cgx.h" 21 #include "rvu.h" 22 #include "lmac_common.h" 23 24 #define DRV_NAME "Marvell-CGX/RPM" 25 #define DRV_STRING "Marvell CGX/RPM Driver" 26 27 static LIST_HEAD(cgx_list); 28 29 /* Convert firmware speed encoding to user format(Mbps) */ 30 static const u32 cgx_speed_mbps[CGX_LINK_SPEED_MAX] = { 31 [CGX_LINK_NONE] = 0, 32 [CGX_LINK_10M] = 10, 33 [CGX_LINK_100M] = 100, 34 [CGX_LINK_1G] = 1000, 35 [CGX_LINK_2HG] = 2500, 36 [CGX_LINK_5G] = 5000, 37 [CGX_LINK_10G] = 10000, 38 [CGX_LINK_20G] = 20000, 39 [CGX_LINK_25G] = 25000, 40 [CGX_LINK_40G] = 40000, 41 [CGX_LINK_50G] = 50000, 42 [CGX_LINK_80G] = 80000, 43 [CGX_LINK_100G] = 100000, 44 }; 45 46 /* Convert firmware lmac type encoding to string */ 47 static const char *cgx_lmactype_string[LMAC_MODE_MAX] = { 48 [LMAC_MODE_SGMII] = "SGMII", 49 [LMAC_MODE_XAUI] = "XAUI", 50 [LMAC_MODE_RXAUI] = "RXAUI", 51 [LMAC_MODE_10G_R] = "10G_R", 52 [LMAC_MODE_40G_R] = "40G_R", 53 [LMAC_MODE_QSGMII] = "QSGMII", 54 [LMAC_MODE_25G_R] = "25G_R", 55 [LMAC_MODE_50G_R] = "50G_R", 56 [LMAC_MODE_100G_R] = "100G_R", 57 [LMAC_MODE_USXGMII] = "USXGMII", 58 }; 59 60 /* CGX PHY management internal APIs */ 61 static int cgx_fwi_link_change(struct cgx *cgx, int lmac_id, bool en); 62 63 /* Supported devices */ 64 static const struct pci_device_id cgx_id_table[] = { 65 { PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_OCTEONTX2_CGX) }, 66 { PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_CN10K_RPM) }, 67 { PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_CN10KB_RPM) }, 68 { 0, } /* end of table */ 69 }; 70 71 MODULE_DEVICE_TABLE(pci, cgx_id_table); 72 73 static bool is_dev_rpm(void *cgxd) 74 { 75 struct cgx *cgx = cgxd; 76 77 return (cgx->pdev->device == PCI_DEVID_CN10K_RPM) || 78 (cgx->pdev->device == PCI_DEVID_CN10KB_RPM); 79 } 80 81 bool is_lmac_valid(struct cgx *cgx, int lmac_id) 82 { 83 if (!cgx || lmac_id < 0 || lmac_id >= cgx->max_lmac_per_mac) 84 return false; 85 return test_bit(lmac_id, &cgx->lmac_bmap); 86 } 87 88 /* Helper function to get sequential index 89 * given the enabled LMAC of a CGX 90 */ 91 static int get_sequence_id_of_lmac(struct cgx *cgx, int lmac_id) 92 { 93 int tmp, id = 0; 94 95 for_each_set_bit(tmp, &cgx->lmac_bmap, cgx->max_lmac_per_mac) { 96 if (tmp == lmac_id) 97 break; 98 id++; 99 } 100 101 return id; 102 } 103 104 struct mac_ops *get_mac_ops(void *cgxd) 105 { 106 if (!cgxd) 107 return cgxd; 108 109 return ((struct cgx *)cgxd)->mac_ops; 110 } 111 112 void cgx_write(struct cgx *cgx, u64 lmac, u64 offset, u64 val) 113 { 114 writeq(val, cgx->reg_base + (lmac << cgx->mac_ops->lmac_offset) + 115 offset); 116 } 117 118 u64 cgx_read(struct cgx *cgx, u64 lmac, u64 offset) 119 { 120 return readq(cgx->reg_base + (lmac << cgx->mac_ops->lmac_offset) + 121 offset); 122 } 123 124 struct lmac *lmac_pdata(u8 lmac_id, struct cgx *cgx) 125 { 126 if (!cgx || lmac_id >= cgx->max_lmac_per_mac) 127 return NULL; 128 129 return cgx->lmac_idmap[lmac_id]; 130 } 131 132 int cgx_get_cgxcnt_max(void) 133 { 134 struct cgx *cgx_dev; 135 int idmax = -ENODEV; 136 137 list_for_each_entry(cgx_dev, &cgx_list, cgx_list) 138 if (cgx_dev->cgx_id > idmax) 139 idmax = cgx_dev->cgx_id; 140 141 if (idmax < 0) 142 return 0; 143 144 return idmax + 1; 145 } 146 147 int cgx_get_lmac_cnt(void *cgxd) 148 { 149 struct cgx *cgx = cgxd; 150 151 if (!cgx) 152 return -ENODEV; 153 154 return cgx->lmac_count; 155 } 156 157 void *cgx_get_pdata(int cgx_id) 158 { 159 struct cgx *cgx_dev; 160 161 list_for_each_entry(cgx_dev, &cgx_list, cgx_list) { 162 if (cgx_dev->cgx_id == cgx_id) 163 return cgx_dev; 164 } 165 return NULL; 166 } 167 168 void cgx_lmac_write(int cgx_id, int lmac_id, u64 offset, u64 val) 169 { 170 struct cgx *cgx_dev = cgx_get_pdata(cgx_id); 171 172 cgx_write(cgx_dev, lmac_id, offset, val); 173 } 174 175 u64 cgx_lmac_read(int cgx_id, int lmac_id, u64 offset) 176 { 177 struct cgx *cgx_dev = cgx_get_pdata(cgx_id); 178 179 return cgx_read(cgx_dev, lmac_id, offset); 180 } 181 182 int cgx_get_cgxid(void *cgxd) 183 { 184 struct cgx *cgx = cgxd; 185 186 if (!cgx) 187 return -EINVAL; 188 189 return cgx->cgx_id; 190 } 191 192 u8 cgx_lmac_get_p2x(int cgx_id, int lmac_id) 193 { 194 struct cgx *cgx_dev = cgx_get_pdata(cgx_id); 195 u64 cfg; 196 197 cfg = cgx_read(cgx_dev, lmac_id, CGXX_CMRX_CFG); 198 199 return (cfg & CMR_P2X_SEL_MASK) >> CMR_P2X_SEL_SHIFT; 200 } 201 202 /* Ensure the required lock for event queue(where asynchronous events are 203 * posted) is acquired before calling this API. Else an asynchronous event(with 204 * latest link status) can reach the destination before this function returns 205 * and could make the link status appear wrong. 206 */ 207 int cgx_get_link_info(void *cgxd, int lmac_id, 208 struct cgx_link_user_info *linfo) 209 { 210 struct lmac *lmac = lmac_pdata(lmac_id, cgxd); 211 212 if (!lmac) 213 return -ENODEV; 214 215 *linfo = lmac->link_info; 216 return 0; 217 } 218 219 static u64 mac2u64 (u8 *mac_addr) 220 { 221 u64 mac = 0; 222 int index; 223 224 for (index = ETH_ALEN - 1; index >= 0; index--) 225 mac |= ((u64)*mac_addr++) << (8 * index); 226 return mac; 227 } 228 229 static void cfg2mac(u64 cfg, u8 *mac_addr) 230 { 231 int i, index = 0; 232 233 for (i = ETH_ALEN - 1; i >= 0; i--, index++) 234 mac_addr[i] = (cfg >> (8 * index)) & 0xFF; 235 } 236 237 int cgx_lmac_addr_set(u8 cgx_id, u8 lmac_id, u8 *mac_addr) 238 { 239 struct cgx *cgx_dev = cgx_get_pdata(cgx_id); 240 struct lmac *lmac = lmac_pdata(lmac_id, cgx_dev); 241 struct mac_ops *mac_ops; 242 int index, id; 243 u64 cfg; 244 245 /* access mac_ops to know csr_offset */ 246 mac_ops = cgx_dev->mac_ops; 247 248 /* copy 6bytes from macaddr */ 249 /* memcpy(&cfg, mac_addr, 6); */ 250 251 cfg = mac2u64 (mac_addr); 252 253 id = get_sequence_id_of_lmac(cgx_dev, lmac_id); 254 255 index = id * lmac->mac_to_index_bmap.max; 256 257 cgx_write(cgx_dev, 0, (CGXX_CMRX_RX_DMAC_CAM0 + (index * 0x8)), 258 cfg | CGX_DMAC_CAM_ADDR_ENABLE | ((u64)lmac_id << 49)); 259 260 cfg = cgx_read(cgx_dev, lmac_id, CGXX_CMRX_RX_DMAC_CTL0); 261 cfg |= (CGX_DMAC_CTL0_CAM_ENABLE | CGX_DMAC_BCAST_MODE | 262 CGX_DMAC_MCAST_MODE); 263 cgx_write(cgx_dev, lmac_id, CGXX_CMRX_RX_DMAC_CTL0, cfg); 264 265 return 0; 266 } 267 268 u64 cgx_read_dmac_ctrl(void *cgxd, int lmac_id) 269 { 270 struct mac_ops *mac_ops; 271 struct cgx *cgx = cgxd; 272 273 if (!cgxd || !is_lmac_valid(cgxd, lmac_id)) 274 return 0; 275 276 cgx = cgxd; 277 /* Get mac_ops to know csr offset */ 278 mac_ops = cgx->mac_ops; 279 280 return cgx_read(cgxd, lmac_id, CGXX_CMRX_RX_DMAC_CTL0); 281 } 282 283 u64 cgx_read_dmac_entry(void *cgxd, int index) 284 { 285 struct mac_ops *mac_ops; 286 struct cgx *cgx; 287 288 if (!cgxd) 289 return 0; 290 291 cgx = cgxd; 292 mac_ops = cgx->mac_ops; 293 return cgx_read(cgx, 0, (CGXX_CMRX_RX_DMAC_CAM0 + (index * 8))); 294 } 295 296 int cgx_lmac_addr_add(u8 cgx_id, u8 lmac_id, u8 *mac_addr) 297 { 298 struct cgx *cgx_dev = cgx_get_pdata(cgx_id); 299 struct lmac *lmac = lmac_pdata(lmac_id, cgx_dev); 300 struct mac_ops *mac_ops; 301 int index, idx; 302 u64 cfg = 0; 303 int id; 304 305 if (!lmac) 306 return -ENODEV; 307 308 mac_ops = cgx_dev->mac_ops; 309 /* Get available index where entry is to be installed */ 310 idx = rvu_alloc_rsrc(&lmac->mac_to_index_bmap); 311 if (idx < 0) 312 return idx; 313 314 id = get_sequence_id_of_lmac(cgx_dev, lmac_id); 315 316 index = id * lmac->mac_to_index_bmap.max + idx; 317 318 cfg = mac2u64 (mac_addr); 319 cfg |= CGX_DMAC_CAM_ADDR_ENABLE; 320 cfg |= ((u64)lmac_id << 49); 321 cgx_write(cgx_dev, 0, (CGXX_CMRX_RX_DMAC_CAM0 + (index * 0x8)), cfg); 322 323 cfg = cgx_read(cgx_dev, lmac_id, CGXX_CMRX_RX_DMAC_CTL0); 324 cfg |= (CGX_DMAC_BCAST_MODE | CGX_DMAC_CAM_ACCEPT); 325 326 if (is_multicast_ether_addr(mac_addr)) { 327 cfg &= ~GENMASK_ULL(2, 1); 328 cfg |= CGX_DMAC_MCAST_MODE_CAM; 329 lmac->mcast_filters_count++; 330 } else if (!lmac->mcast_filters_count) { 331 cfg |= CGX_DMAC_MCAST_MODE; 332 } 333 334 cgx_write(cgx_dev, lmac_id, CGXX_CMRX_RX_DMAC_CTL0, cfg); 335 336 return idx; 337 } 338 339 int cgx_lmac_addr_reset(u8 cgx_id, u8 lmac_id) 340 { 341 struct cgx *cgx_dev = cgx_get_pdata(cgx_id); 342 struct lmac *lmac = lmac_pdata(lmac_id, cgx_dev); 343 struct mac_ops *mac_ops; 344 u8 index = 0, id; 345 u64 cfg; 346 347 if (!lmac) 348 return -ENODEV; 349 350 mac_ops = cgx_dev->mac_ops; 351 /* Restore index 0 to its default init value as done during 352 * cgx_lmac_init 353 */ 354 set_bit(0, lmac->mac_to_index_bmap.bmap); 355 356 id = get_sequence_id_of_lmac(cgx_dev, lmac_id); 357 358 index = id * lmac->mac_to_index_bmap.max + index; 359 cgx_write(cgx_dev, 0, (CGXX_CMRX_RX_DMAC_CAM0 + (index * 0x8)), 0); 360 361 /* Reset CGXX_CMRX_RX_DMAC_CTL0 register to default state */ 362 cfg = cgx_read(cgx_dev, lmac_id, CGXX_CMRX_RX_DMAC_CTL0); 363 cfg &= ~CGX_DMAC_CAM_ACCEPT; 364 cfg |= (CGX_DMAC_BCAST_MODE | CGX_DMAC_MCAST_MODE); 365 cgx_write(cgx_dev, lmac_id, CGXX_CMRX_RX_DMAC_CTL0, cfg); 366 367 return 0; 368 } 369 370 /* Allows caller to change macaddress associated with index 371 * in dmac filter table including index 0 reserved for 372 * interface mac address 373 */ 374 int cgx_lmac_addr_update(u8 cgx_id, u8 lmac_id, u8 *mac_addr, u8 index) 375 { 376 struct cgx *cgx_dev = cgx_get_pdata(cgx_id); 377 struct mac_ops *mac_ops; 378 struct lmac *lmac; 379 u64 cfg; 380 int id; 381 382 lmac = lmac_pdata(lmac_id, cgx_dev); 383 if (!lmac) 384 return -ENODEV; 385 386 mac_ops = cgx_dev->mac_ops; 387 /* Validate the index */ 388 if (index >= lmac->mac_to_index_bmap.max) 389 return -EINVAL; 390 391 /* ensure index is already set */ 392 if (!test_bit(index, lmac->mac_to_index_bmap.bmap)) 393 return -EINVAL; 394 395 id = get_sequence_id_of_lmac(cgx_dev, lmac_id); 396 397 index = id * lmac->mac_to_index_bmap.max + index; 398 399 cfg = cgx_read(cgx_dev, 0, (CGXX_CMRX_RX_DMAC_CAM0 + (index * 0x8))); 400 cfg &= ~CGX_RX_DMAC_ADR_MASK; 401 cfg |= mac2u64 (mac_addr); 402 403 cgx_write(cgx_dev, 0, (CGXX_CMRX_RX_DMAC_CAM0 + (index * 0x8)), cfg); 404 return 0; 405 } 406 407 int cgx_lmac_addr_del(u8 cgx_id, u8 lmac_id, u8 index) 408 { 409 struct cgx *cgx_dev = cgx_get_pdata(cgx_id); 410 struct lmac *lmac = lmac_pdata(lmac_id, cgx_dev); 411 struct mac_ops *mac_ops; 412 u8 mac[ETH_ALEN]; 413 u64 cfg; 414 int id; 415 416 if (!lmac) 417 return -ENODEV; 418 419 mac_ops = cgx_dev->mac_ops; 420 /* Validate the index */ 421 if (index >= lmac->mac_to_index_bmap.max) 422 return -EINVAL; 423 424 /* Skip deletion for reserved index i.e. index 0 */ 425 if (index == 0) 426 return 0; 427 428 rvu_free_rsrc(&lmac->mac_to_index_bmap, index); 429 430 id = get_sequence_id_of_lmac(cgx_dev, lmac_id); 431 432 index = id * lmac->mac_to_index_bmap.max + index; 433 434 /* Read MAC address to check whether it is ucast or mcast */ 435 cfg = cgx_read(cgx_dev, 0, (CGXX_CMRX_RX_DMAC_CAM0 + (index * 0x8))); 436 437 cfg2mac(cfg, mac); 438 if (is_multicast_ether_addr(mac)) 439 lmac->mcast_filters_count--; 440 441 if (!lmac->mcast_filters_count) { 442 cfg = cgx_read(cgx_dev, lmac_id, CGXX_CMRX_RX_DMAC_CTL0); 443 cfg &= ~GENMASK_ULL(2, 1); 444 cfg |= CGX_DMAC_MCAST_MODE; 445 cgx_write(cgx_dev, lmac_id, CGXX_CMRX_RX_DMAC_CTL0, cfg); 446 } 447 448 cgx_write(cgx_dev, 0, (CGXX_CMRX_RX_DMAC_CAM0 + (index * 0x8)), 0); 449 450 return 0; 451 } 452 453 int cgx_lmac_addr_max_entries_get(u8 cgx_id, u8 lmac_id) 454 { 455 struct cgx *cgx_dev = cgx_get_pdata(cgx_id); 456 struct lmac *lmac = lmac_pdata(lmac_id, cgx_dev); 457 458 if (lmac) 459 return lmac->mac_to_index_bmap.max; 460 461 return 0; 462 } 463 464 u64 cgx_lmac_addr_get(u8 cgx_id, u8 lmac_id) 465 { 466 struct cgx *cgx_dev = cgx_get_pdata(cgx_id); 467 struct lmac *lmac = lmac_pdata(lmac_id, cgx_dev); 468 struct mac_ops *mac_ops; 469 int index; 470 u64 cfg; 471 int id; 472 473 mac_ops = cgx_dev->mac_ops; 474 475 id = get_sequence_id_of_lmac(cgx_dev, lmac_id); 476 477 index = id * lmac->mac_to_index_bmap.max; 478 479 cfg = cgx_read(cgx_dev, 0, CGXX_CMRX_RX_DMAC_CAM0 + index * 0x8); 480 return cfg & CGX_RX_DMAC_ADR_MASK; 481 } 482 483 int cgx_set_pkind(void *cgxd, u8 lmac_id, int pkind) 484 { 485 struct cgx *cgx = cgxd; 486 487 if (!is_lmac_valid(cgx, lmac_id)) 488 return -ENODEV; 489 490 cgx_write(cgx, lmac_id, cgx->mac_ops->rxid_map_offset, (pkind & 0x3F)); 491 return 0; 492 } 493 494 static u8 cgx_get_lmac_type(void *cgxd, int lmac_id) 495 { 496 struct cgx *cgx = cgxd; 497 u64 cfg; 498 499 cfg = cgx_read(cgx, lmac_id, CGXX_CMRX_CFG); 500 return (cfg >> CGX_LMAC_TYPE_SHIFT) & CGX_LMAC_TYPE_MASK; 501 } 502 503 static u32 cgx_get_lmac_fifo_len(void *cgxd, int lmac_id) 504 { 505 struct cgx *cgx = cgxd; 506 u8 num_lmacs; 507 u32 fifo_len; 508 509 fifo_len = cgx->mac_ops->fifo_len; 510 num_lmacs = cgx->mac_ops->get_nr_lmacs(cgx); 511 512 switch (num_lmacs) { 513 case 1: 514 return fifo_len; 515 case 2: 516 return fifo_len / 2; 517 case 3: 518 /* LMAC0 gets half of the FIFO, reset 1/4th */ 519 if (lmac_id == 0) 520 return fifo_len / 2; 521 return fifo_len / 4; 522 case 4: 523 default: 524 return fifo_len / 4; 525 } 526 return 0; 527 } 528 529 /* Configure CGX LMAC in internal loopback mode */ 530 int cgx_lmac_internal_loopback(void *cgxd, int lmac_id, bool enable) 531 { 532 struct cgx *cgx = cgxd; 533 u8 lmac_type; 534 u64 cfg; 535 536 if (!is_lmac_valid(cgx, lmac_id)) 537 return -ENODEV; 538 539 lmac_type = cgx->mac_ops->get_lmac_type(cgx, lmac_id); 540 if (lmac_type == LMAC_MODE_SGMII || lmac_type == LMAC_MODE_QSGMII) { 541 cfg = cgx_read(cgx, lmac_id, CGXX_GMP_PCS_MRX_CTL); 542 if (enable) 543 cfg |= CGXX_GMP_PCS_MRX_CTL_LBK; 544 else 545 cfg &= ~CGXX_GMP_PCS_MRX_CTL_LBK; 546 cgx_write(cgx, lmac_id, CGXX_GMP_PCS_MRX_CTL, cfg); 547 } else { 548 cfg = cgx_read(cgx, lmac_id, CGXX_SPUX_CONTROL1); 549 if (enable) 550 cfg |= CGXX_SPUX_CONTROL1_LBK; 551 else 552 cfg &= ~CGXX_SPUX_CONTROL1_LBK; 553 cgx_write(cgx, lmac_id, CGXX_SPUX_CONTROL1, cfg); 554 } 555 return 0; 556 } 557 558 void cgx_lmac_promisc_config(int cgx_id, int lmac_id, bool enable) 559 { 560 struct cgx *cgx = cgx_get_pdata(cgx_id); 561 struct lmac *lmac = lmac_pdata(lmac_id, cgx); 562 u16 max_dmac = lmac->mac_to_index_bmap.max; 563 struct mac_ops *mac_ops; 564 int index, i; 565 u64 cfg = 0; 566 int id; 567 568 if (!cgx) 569 return; 570 571 id = get_sequence_id_of_lmac(cgx, lmac_id); 572 573 mac_ops = cgx->mac_ops; 574 if (enable) { 575 /* Enable promiscuous mode on LMAC */ 576 cfg = cgx_read(cgx, lmac_id, CGXX_CMRX_RX_DMAC_CTL0); 577 cfg &= ~CGX_DMAC_CAM_ACCEPT; 578 cfg |= (CGX_DMAC_BCAST_MODE | CGX_DMAC_MCAST_MODE); 579 cgx_write(cgx, lmac_id, CGXX_CMRX_RX_DMAC_CTL0, cfg); 580 581 for (i = 0; i < max_dmac; i++) { 582 index = id * max_dmac + i; 583 cfg = cgx_read(cgx, 0, 584 (CGXX_CMRX_RX_DMAC_CAM0 + index * 0x8)); 585 cfg &= ~CGX_DMAC_CAM_ADDR_ENABLE; 586 cgx_write(cgx, 0, 587 (CGXX_CMRX_RX_DMAC_CAM0 + index * 0x8), cfg); 588 } 589 } else { 590 /* Disable promiscuous mode */ 591 cfg = cgx_read(cgx, lmac_id, CGXX_CMRX_RX_DMAC_CTL0); 592 cfg |= CGX_DMAC_CAM_ACCEPT | CGX_DMAC_MCAST_MODE; 593 cgx_write(cgx, lmac_id, CGXX_CMRX_RX_DMAC_CTL0, cfg); 594 for (i = 0; i < max_dmac; i++) { 595 index = id * max_dmac + i; 596 cfg = cgx_read(cgx, 0, 597 (CGXX_CMRX_RX_DMAC_CAM0 + index * 0x8)); 598 if ((cfg & CGX_RX_DMAC_ADR_MASK) != 0) { 599 cfg |= CGX_DMAC_CAM_ADDR_ENABLE; 600 cgx_write(cgx, 0, 601 (CGXX_CMRX_RX_DMAC_CAM0 + 602 index * 0x8), 603 cfg); 604 } 605 } 606 } 607 } 608 609 static int cgx_lmac_get_pause_frm_status(void *cgxd, int lmac_id, 610 u8 *tx_pause, u8 *rx_pause) 611 { 612 struct cgx *cgx = cgxd; 613 u64 cfg; 614 615 if (is_dev_rpm(cgx)) 616 return 0; 617 618 if (!is_lmac_valid(cgx, lmac_id)) 619 return -ENODEV; 620 621 cfg = cgx_read(cgx, lmac_id, CGXX_SMUX_RX_FRM_CTL); 622 *rx_pause = !!(cfg & CGX_SMUX_RX_FRM_CTL_CTL_BCK); 623 624 cfg = cgx_read(cgx, lmac_id, CGXX_SMUX_TX_CTL); 625 *tx_pause = !!(cfg & CGX_SMUX_TX_CTL_L2P_BP_CONV); 626 return 0; 627 } 628 629 /* Enable or disable forwarding received pause frames to Tx block */ 630 void cgx_lmac_enadis_rx_pause_fwding(void *cgxd, int lmac_id, bool enable) 631 { 632 struct cgx *cgx = cgxd; 633 u8 rx_pause, tx_pause; 634 bool is_pfc_enabled; 635 struct lmac *lmac; 636 u64 cfg; 637 638 if (!cgx) 639 return; 640 641 lmac = lmac_pdata(lmac_id, cgx); 642 if (!lmac) 643 return; 644 645 /* Pause frames are not enabled just return */ 646 if (!bitmap_weight(lmac->rx_fc_pfvf_bmap.bmap, lmac->rx_fc_pfvf_bmap.max)) 647 return; 648 649 cgx_lmac_get_pause_frm_status(cgx, lmac_id, &rx_pause, &tx_pause); 650 is_pfc_enabled = rx_pause ? false : true; 651 652 if (enable) { 653 if (!is_pfc_enabled) { 654 cfg = cgx_read(cgx, lmac_id, CGXX_GMP_GMI_RXX_FRM_CTL); 655 cfg |= CGX_GMP_GMI_RXX_FRM_CTL_CTL_BCK; 656 cgx_write(cgx, lmac_id, CGXX_GMP_GMI_RXX_FRM_CTL, cfg); 657 658 cfg = cgx_read(cgx, lmac_id, CGXX_SMUX_RX_FRM_CTL); 659 cfg |= CGX_SMUX_RX_FRM_CTL_CTL_BCK; 660 cgx_write(cgx, lmac_id, CGXX_SMUX_RX_FRM_CTL, cfg); 661 } else { 662 cfg = cgx_read(cgx, lmac_id, CGXX_SMUX_CBFC_CTL); 663 cfg |= CGXX_SMUX_CBFC_CTL_BCK_EN; 664 cgx_write(cgx, lmac_id, CGXX_SMUX_CBFC_CTL, cfg); 665 } 666 } else { 667 668 if (!is_pfc_enabled) { 669 cfg = cgx_read(cgx, lmac_id, CGXX_GMP_GMI_RXX_FRM_CTL); 670 cfg &= ~CGX_GMP_GMI_RXX_FRM_CTL_CTL_BCK; 671 cgx_write(cgx, lmac_id, CGXX_GMP_GMI_RXX_FRM_CTL, cfg); 672 673 cfg = cgx_read(cgx, lmac_id, CGXX_SMUX_RX_FRM_CTL); 674 cfg &= ~CGX_SMUX_RX_FRM_CTL_CTL_BCK; 675 cgx_write(cgx, lmac_id, CGXX_SMUX_RX_FRM_CTL, cfg); 676 } else { 677 cfg = cgx_read(cgx, lmac_id, CGXX_SMUX_CBFC_CTL); 678 cfg &= ~CGXX_SMUX_CBFC_CTL_BCK_EN; 679 cgx_write(cgx, lmac_id, CGXX_SMUX_CBFC_CTL, cfg); 680 } 681 } 682 } 683 684 int cgx_get_rx_stats(void *cgxd, int lmac_id, int idx, u64 *rx_stat) 685 { 686 struct cgx *cgx = cgxd; 687 688 if (!is_lmac_valid(cgx, lmac_id)) 689 return -ENODEV; 690 *rx_stat = cgx_read(cgx, lmac_id, CGXX_CMRX_RX_STAT0 + (idx * 8)); 691 return 0; 692 } 693 694 int cgx_get_tx_stats(void *cgxd, int lmac_id, int idx, u64 *tx_stat) 695 { 696 struct cgx *cgx = cgxd; 697 698 if (!is_lmac_valid(cgx, lmac_id)) 699 return -ENODEV; 700 *tx_stat = cgx_read(cgx, lmac_id, CGXX_CMRX_TX_STAT0 + (idx * 8)); 701 return 0; 702 } 703 704 u64 cgx_features_get(void *cgxd) 705 { 706 return ((struct cgx *)cgxd)->hw_features; 707 } 708 709 static int cgx_set_fec_stats_count(struct cgx_link_user_info *linfo) 710 { 711 if (!linfo->fec) 712 return 0; 713 714 switch (linfo->lmac_type_id) { 715 case LMAC_MODE_SGMII: 716 case LMAC_MODE_XAUI: 717 case LMAC_MODE_RXAUI: 718 case LMAC_MODE_QSGMII: 719 return 0; 720 case LMAC_MODE_10G_R: 721 case LMAC_MODE_25G_R: 722 case LMAC_MODE_100G_R: 723 case LMAC_MODE_USXGMII: 724 return 1; 725 case LMAC_MODE_40G_R: 726 return 4; 727 case LMAC_MODE_50G_R: 728 if (linfo->fec == OTX2_FEC_BASER) 729 return 2; 730 else 731 return 1; 732 default: 733 return 0; 734 } 735 } 736 737 int cgx_get_fec_stats(void *cgxd, int lmac_id, struct cgx_fec_stats_rsp *rsp) 738 { 739 int stats, fec_stats_count = 0; 740 int corr_reg, uncorr_reg; 741 struct cgx *cgx = cgxd; 742 743 if (!cgx || lmac_id >= cgx->lmac_count) 744 return -ENODEV; 745 746 if (cgx->lmac_idmap[lmac_id]->link_info.fec == OTX2_FEC_NONE) 747 return 0; 748 749 fec_stats_count = 750 cgx_set_fec_stats_count(&cgx->lmac_idmap[lmac_id]->link_info); 751 if (cgx->lmac_idmap[lmac_id]->link_info.fec == OTX2_FEC_BASER) { 752 corr_reg = CGXX_SPUX_LNX_FEC_CORR_BLOCKS; 753 uncorr_reg = CGXX_SPUX_LNX_FEC_UNCORR_BLOCKS; 754 } else { 755 corr_reg = CGXX_SPUX_RSFEC_CORR; 756 uncorr_reg = CGXX_SPUX_RSFEC_UNCORR; 757 } 758 for (stats = 0; stats < fec_stats_count; stats++) { 759 rsp->fec_corr_blks += 760 cgx_read(cgx, lmac_id, corr_reg + (stats * 8)); 761 rsp->fec_uncorr_blks += 762 cgx_read(cgx, lmac_id, uncorr_reg + (stats * 8)); 763 } 764 return 0; 765 } 766 767 int cgx_lmac_rx_tx_enable(void *cgxd, int lmac_id, bool enable) 768 { 769 struct cgx *cgx = cgxd; 770 u64 cfg; 771 772 if (!is_lmac_valid(cgx, lmac_id)) 773 return -ENODEV; 774 775 cfg = cgx_read(cgx, lmac_id, CGXX_CMRX_CFG); 776 if (enable) 777 cfg |= DATA_PKT_RX_EN | DATA_PKT_TX_EN; 778 else 779 cfg &= ~(DATA_PKT_RX_EN | DATA_PKT_TX_EN); 780 cgx_write(cgx, lmac_id, CGXX_CMRX_CFG, cfg); 781 return 0; 782 } 783 784 int cgx_lmac_tx_enable(void *cgxd, int lmac_id, bool enable) 785 { 786 struct cgx *cgx = cgxd; 787 u64 cfg, last; 788 789 if (!is_lmac_valid(cgx, lmac_id)) 790 return -ENODEV; 791 792 cfg = cgx_read(cgx, lmac_id, CGXX_CMRX_CFG); 793 last = cfg; 794 if (enable) 795 cfg |= DATA_PKT_TX_EN; 796 else 797 cfg &= ~DATA_PKT_TX_EN; 798 799 if (cfg != last) 800 cgx_write(cgx, lmac_id, CGXX_CMRX_CFG, cfg); 801 return !!(last & DATA_PKT_TX_EN); 802 } 803 804 static int cgx_lmac_enadis_pause_frm(void *cgxd, int lmac_id, 805 u8 tx_pause, u8 rx_pause) 806 { 807 struct cgx *cgx = cgxd; 808 u64 cfg; 809 810 if (is_dev_rpm(cgx)) 811 return 0; 812 813 if (!is_lmac_valid(cgx, lmac_id)) 814 return -ENODEV; 815 816 cfg = cgx_read(cgx, lmac_id, CGXX_SMUX_RX_FRM_CTL); 817 cfg &= ~CGX_SMUX_RX_FRM_CTL_CTL_BCK; 818 cfg |= rx_pause ? CGX_SMUX_RX_FRM_CTL_CTL_BCK : 0x0; 819 cgx_write(cgx, lmac_id, CGXX_SMUX_RX_FRM_CTL, cfg); 820 821 cfg = cgx_read(cgx, lmac_id, CGXX_SMUX_TX_CTL); 822 cfg &= ~CGX_SMUX_TX_CTL_L2P_BP_CONV; 823 cfg |= tx_pause ? CGX_SMUX_TX_CTL_L2P_BP_CONV : 0x0; 824 cgx_write(cgx, lmac_id, CGXX_SMUX_TX_CTL, cfg); 825 826 cfg = cgx_read(cgx, 0, CGXX_CMR_RX_OVR_BP); 827 if (tx_pause) { 828 cfg &= ~CGX_CMR_RX_OVR_BP_EN(lmac_id); 829 } else { 830 cfg |= CGX_CMR_RX_OVR_BP_EN(lmac_id); 831 cfg &= ~CGX_CMR_RX_OVR_BP_BP(lmac_id); 832 } 833 cgx_write(cgx, 0, CGXX_CMR_RX_OVR_BP, cfg); 834 return 0; 835 } 836 837 static void cgx_lmac_pause_frm_config(void *cgxd, int lmac_id, bool enable) 838 { 839 struct cgx *cgx = cgxd; 840 u64 cfg; 841 842 if (!is_lmac_valid(cgx, lmac_id)) 843 return; 844 845 if (enable) { 846 /* Set pause time and interval */ 847 cgx_write(cgx, lmac_id, CGXX_SMUX_TX_PAUSE_PKT_TIME, 848 DEFAULT_PAUSE_TIME); 849 cfg = cgx_read(cgx, lmac_id, CGXX_SMUX_TX_PAUSE_PKT_INTERVAL); 850 cfg &= ~0xFFFFULL; 851 cgx_write(cgx, lmac_id, CGXX_SMUX_TX_PAUSE_PKT_INTERVAL, 852 cfg | (DEFAULT_PAUSE_TIME / 2)); 853 854 cgx_write(cgx, lmac_id, CGXX_GMP_GMI_TX_PAUSE_PKT_TIME, 855 DEFAULT_PAUSE_TIME); 856 857 cfg = cgx_read(cgx, lmac_id, 858 CGXX_GMP_GMI_TX_PAUSE_PKT_INTERVAL); 859 cfg &= ~0xFFFFULL; 860 cgx_write(cgx, lmac_id, CGXX_GMP_GMI_TX_PAUSE_PKT_INTERVAL, 861 cfg | (DEFAULT_PAUSE_TIME / 2)); 862 } 863 864 /* ALL pause frames received are completely ignored */ 865 cfg = cgx_read(cgx, lmac_id, CGXX_SMUX_RX_FRM_CTL); 866 cfg &= ~CGX_SMUX_RX_FRM_CTL_CTL_BCK; 867 cgx_write(cgx, lmac_id, CGXX_SMUX_RX_FRM_CTL, cfg); 868 869 cfg = cgx_read(cgx, lmac_id, CGXX_GMP_GMI_RXX_FRM_CTL); 870 cfg &= ~CGX_GMP_GMI_RXX_FRM_CTL_CTL_BCK; 871 cgx_write(cgx, lmac_id, CGXX_GMP_GMI_RXX_FRM_CTL, cfg); 872 873 /* Disable pause frames transmission */ 874 cfg = cgx_read(cgx, lmac_id, CGXX_SMUX_TX_CTL); 875 cfg &= ~CGX_SMUX_TX_CTL_L2P_BP_CONV; 876 cgx_write(cgx, lmac_id, CGXX_SMUX_TX_CTL, cfg); 877 878 cfg = cgx_read(cgx, 0, CGXX_CMR_RX_OVR_BP); 879 cfg |= CGX_CMR_RX_OVR_BP_EN(lmac_id); 880 cfg &= ~CGX_CMR_RX_OVR_BP_BP(lmac_id); 881 cgx_write(cgx, 0, CGXX_CMR_RX_OVR_BP, cfg); 882 883 /* Disable all PFC classes by default */ 884 cfg = cgx_read(cgx, lmac_id, CGXX_SMUX_CBFC_CTL); 885 cfg = FIELD_SET(CGX_PFC_CLASS_MASK, 0, cfg); 886 cgx_write(cgx, lmac_id, CGXX_SMUX_CBFC_CTL, cfg); 887 } 888 889 int verify_lmac_fc_cfg(void *cgxd, int lmac_id, u8 tx_pause, u8 rx_pause, 890 int pfvf_idx) 891 { 892 struct cgx *cgx = cgxd; 893 struct lmac *lmac; 894 895 lmac = lmac_pdata(lmac_id, cgx); 896 if (!lmac) 897 return -ENODEV; 898 899 if (!rx_pause) 900 clear_bit(pfvf_idx, lmac->rx_fc_pfvf_bmap.bmap); 901 else 902 set_bit(pfvf_idx, lmac->rx_fc_pfvf_bmap.bmap); 903 904 if (!tx_pause) 905 clear_bit(pfvf_idx, lmac->tx_fc_pfvf_bmap.bmap); 906 else 907 set_bit(pfvf_idx, lmac->tx_fc_pfvf_bmap.bmap); 908 909 /* check if other pfvfs are using flow control */ 910 if (!rx_pause && bitmap_weight(lmac->rx_fc_pfvf_bmap.bmap, lmac->rx_fc_pfvf_bmap.max)) { 911 dev_warn(&cgx->pdev->dev, 912 "Receive Flow control disable not permitted as its used by other PFVFs\n"); 913 return -EPERM; 914 } 915 916 if (!tx_pause && bitmap_weight(lmac->tx_fc_pfvf_bmap.bmap, lmac->tx_fc_pfvf_bmap.max)) { 917 dev_warn(&cgx->pdev->dev, 918 "Transmit Flow control disable not permitted as its used by other PFVFs\n"); 919 return -EPERM; 920 } 921 922 return 0; 923 } 924 925 int cgx_lmac_pfc_config(void *cgxd, int lmac_id, u8 tx_pause, 926 u8 rx_pause, u16 pfc_en) 927 { 928 struct cgx *cgx = cgxd; 929 u64 cfg; 930 931 if (!is_lmac_valid(cgx, lmac_id)) 932 return -ENODEV; 933 934 /* Return as no traffic classes are requested */ 935 if (tx_pause && !pfc_en) 936 return 0; 937 938 cfg = cgx_read(cgx, lmac_id, CGXX_SMUX_CBFC_CTL); 939 pfc_en |= FIELD_GET(CGX_PFC_CLASS_MASK, cfg); 940 941 if (rx_pause) { 942 cfg |= (CGXX_SMUX_CBFC_CTL_RX_EN | 943 CGXX_SMUX_CBFC_CTL_BCK_EN | 944 CGXX_SMUX_CBFC_CTL_DRP_EN); 945 } else { 946 cfg &= ~(CGXX_SMUX_CBFC_CTL_RX_EN | 947 CGXX_SMUX_CBFC_CTL_BCK_EN | 948 CGXX_SMUX_CBFC_CTL_DRP_EN); 949 } 950 951 if (tx_pause) { 952 cfg |= CGXX_SMUX_CBFC_CTL_TX_EN; 953 cfg = FIELD_SET(CGX_PFC_CLASS_MASK, pfc_en, cfg); 954 } else { 955 cfg &= ~CGXX_SMUX_CBFC_CTL_TX_EN; 956 cfg = FIELD_SET(CGX_PFC_CLASS_MASK, 0, cfg); 957 } 958 959 cgx_write(cgx, lmac_id, CGXX_SMUX_CBFC_CTL, cfg); 960 961 /* Write source MAC address which will be filled into PFC packet */ 962 cfg = cgx_lmac_addr_get(cgx->cgx_id, lmac_id); 963 cgx_write(cgx, lmac_id, CGXX_SMUX_SMAC, cfg); 964 965 return 0; 966 } 967 968 int cgx_lmac_get_pfc_frm_cfg(void *cgxd, int lmac_id, u8 *tx_pause, 969 u8 *rx_pause) 970 { 971 struct cgx *cgx = cgxd; 972 u64 cfg; 973 974 if (!is_lmac_valid(cgx, lmac_id)) 975 return -ENODEV; 976 977 cfg = cgx_read(cgx, lmac_id, CGXX_SMUX_CBFC_CTL); 978 979 *rx_pause = !!(cfg & CGXX_SMUX_CBFC_CTL_RX_EN); 980 *tx_pause = !!(cfg & CGXX_SMUX_CBFC_CTL_TX_EN); 981 982 return 0; 983 } 984 985 void cgx_lmac_ptp_config(void *cgxd, int lmac_id, bool enable) 986 { 987 struct cgx *cgx = cgxd; 988 u64 cfg; 989 990 if (!cgx) 991 return; 992 993 if (enable) { 994 /* Enable inbound PTP timestamping */ 995 cfg = cgx_read(cgx, lmac_id, CGXX_GMP_GMI_RXX_FRM_CTL); 996 cfg |= CGX_GMP_GMI_RXX_FRM_CTL_PTP_MODE; 997 cgx_write(cgx, lmac_id, CGXX_GMP_GMI_RXX_FRM_CTL, cfg); 998 999 cfg = cgx_read(cgx, lmac_id, CGXX_SMUX_RX_FRM_CTL); 1000 cfg |= CGX_SMUX_RX_FRM_CTL_PTP_MODE; 1001 cgx_write(cgx, lmac_id, CGXX_SMUX_RX_FRM_CTL, cfg); 1002 } else { 1003 /* Disable inbound PTP stamping */ 1004 cfg = cgx_read(cgx, lmac_id, CGXX_GMP_GMI_RXX_FRM_CTL); 1005 cfg &= ~CGX_GMP_GMI_RXX_FRM_CTL_PTP_MODE; 1006 cgx_write(cgx, lmac_id, CGXX_GMP_GMI_RXX_FRM_CTL, cfg); 1007 1008 cfg = cgx_read(cgx, lmac_id, CGXX_SMUX_RX_FRM_CTL); 1009 cfg &= ~CGX_SMUX_RX_FRM_CTL_PTP_MODE; 1010 cgx_write(cgx, lmac_id, CGXX_SMUX_RX_FRM_CTL, cfg); 1011 } 1012 } 1013 1014 /* CGX Firmware interface low level support */ 1015 int cgx_fwi_cmd_send(u64 req, u64 *resp, struct lmac *lmac) 1016 { 1017 struct cgx *cgx = lmac->cgx; 1018 struct device *dev; 1019 int err = 0; 1020 u64 cmd; 1021 1022 /* Ensure no other command is in progress */ 1023 err = mutex_lock_interruptible(&lmac->cmd_lock); 1024 if (err) 1025 return err; 1026 1027 /* Ensure command register is free */ 1028 cmd = cgx_read(cgx, lmac->lmac_id, CGX_COMMAND_REG); 1029 if (FIELD_GET(CMDREG_OWN, cmd) != CGX_CMD_OWN_NS) { 1030 err = -EBUSY; 1031 goto unlock; 1032 } 1033 1034 /* Update ownership in command request */ 1035 req = FIELD_SET(CMDREG_OWN, CGX_CMD_OWN_FIRMWARE, req); 1036 1037 /* Mark this lmac as pending, before we start */ 1038 lmac->cmd_pend = true; 1039 1040 /* Start command in hardware */ 1041 cgx_write(cgx, lmac->lmac_id, CGX_COMMAND_REG, req); 1042 1043 /* Ensure command is completed without errors */ 1044 if (!wait_event_timeout(lmac->wq_cmd_cmplt, !lmac->cmd_pend, 1045 msecs_to_jiffies(CGX_CMD_TIMEOUT))) { 1046 dev = &cgx->pdev->dev; 1047 dev_err(dev, "cgx port %d:%d cmd %lld timeout\n", 1048 cgx->cgx_id, lmac->lmac_id, FIELD_GET(CMDREG_ID, req)); 1049 err = LMAC_AF_ERR_CMD_TIMEOUT; 1050 goto unlock; 1051 } 1052 1053 /* we have a valid command response */ 1054 smp_rmb(); /* Ensure the latest updates are visible */ 1055 *resp = lmac->resp; 1056 1057 unlock: 1058 mutex_unlock(&lmac->cmd_lock); 1059 1060 return err; 1061 } 1062 1063 int cgx_fwi_cmd_generic(u64 req, u64 *resp, struct cgx *cgx, int lmac_id) 1064 { 1065 struct lmac *lmac; 1066 int err; 1067 1068 lmac = lmac_pdata(lmac_id, cgx); 1069 if (!lmac) 1070 return -ENODEV; 1071 1072 err = cgx_fwi_cmd_send(req, resp, lmac); 1073 1074 /* Check for valid response */ 1075 if (!err) { 1076 if (FIELD_GET(EVTREG_STAT, *resp) == CGX_STAT_FAIL) 1077 return -EIO; 1078 else 1079 return 0; 1080 } 1081 1082 return err; 1083 } 1084 1085 static int cgx_link_usertable_index_map(int speed) 1086 { 1087 switch (speed) { 1088 case SPEED_10: 1089 return CGX_LINK_10M; 1090 case SPEED_100: 1091 return CGX_LINK_100M; 1092 case SPEED_1000: 1093 return CGX_LINK_1G; 1094 case SPEED_2500: 1095 return CGX_LINK_2HG; 1096 case SPEED_5000: 1097 return CGX_LINK_5G; 1098 case SPEED_10000: 1099 return CGX_LINK_10G; 1100 case SPEED_20000: 1101 return CGX_LINK_20G; 1102 case SPEED_25000: 1103 return CGX_LINK_25G; 1104 case SPEED_40000: 1105 return CGX_LINK_40G; 1106 case SPEED_50000: 1107 return CGX_LINK_50G; 1108 case 80000: 1109 return CGX_LINK_80G; 1110 case SPEED_100000: 1111 return CGX_LINK_100G; 1112 case SPEED_UNKNOWN: 1113 return CGX_LINK_NONE; 1114 } 1115 return CGX_LINK_NONE; 1116 } 1117 1118 static void set_mod_args(struct cgx_set_link_mode_args *args, 1119 u32 speed, u8 duplex, u8 autoneg, u64 mode) 1120 { 1121 /* Fill default values incase of user did not pass 1122 * valid parameters 1123 */ 1124 if (args->duplex == DUPLEX_UNKNOWN) 1125 args->duplex = duplex; 1126 if (args->speed == SPEED_UNKNOWN) 1127 args->speed = speed; 1128 if (args->an == AUTONEG_UNKNOWN) 1129 args->an = autoneg; 1130 args->mode = mode; 1131 args->ports = 0; 1132 } 1133 1134 static void otx2_map_ethtool_link_modes(u64 bitmask, 1135 struct cgx_set_link_mode_args *args) 1136 { 1137 switch (bitmask) { 1138 case ETHTOOL_LINK_MODE_10baseT_Half_BIT: 1139 set_mod_args(args, 10, 1, 1, BIT_ULL(CGX_MODE_SGMII)); 1140 break; 1141 case ETHTOOL_LINK_MODE_10baseT_Full_BIT: 1142 set_mod_args(args, 10, 0, 1, BIT_ULL(CGX_MODE_SGMII)); 1143 break; 1144 case ETHTOOL_LINK_MODE_100baseT_Half_BIT: 1145 set_mod_args(args, 100, 1, 1, BIT_ULL(CGX_MODE_SGMII)); 1146 break; 1147 case ETHTOOL_LINK_MODE_100baseT_Full_BIT: 1148 set_mod_args(args, 100, 0, 1, BIT_ULL(CGX_MODE_SGMII)); 1149 break; 1150 case ETHTOOL_LINK_MODE_1000baseT_Half_BIT: 1151 set_mod_args(args, 1000, 1, 1, BIT_ULL(CGX_MODE_SGMII)); 1152 break; 1153 case ETHTOOL_LINK_MODE_1000baseT_Full_BIT: 1154 set_mod_args(args, 1000, 0, 1, BIT_ULL(CGX_MODE_SGMII)); 1155 break; 1156 case ETHTOOL_LINK_MODE_1000baseX_Full_BIT: 1157 set_mod_args(args, 1000, 0, 0, BIT_ULL(CGX_MODE_1000_BASEX)); 1158 break; 1159 case ETHTOOL_LINK_MODE_10000baseT_Full_BIT: 1160 set_mod_args(args, 1000, 0, 1, BIT_ULL(CGX_MODE_QSGMII)); 1161 break; 1162 case ETHTOOL_LINK_MODE_10000baseSR_Full_BIT: 1163 set_mod_args(args, 10000, 0, 0, BIT_ULL(CGX_MODE_10G_C2C)); 1164 break; 1165 case ETHTOOL_LINK_MODE_10000baseLR_Full_BIT: 1166 set_mod_args(args, 10000, 0, 0, BIT_ULL(CGX_MODE_10G_C2M)); 1167 break; 1168 case ETHTOOL_LINK_MODE_10000baseKR_Full_BIT: 1169 set_mod_args(args, 10000, 0, 1, BIT_ULL(CGX_MODE_10G_KR)); 1170 break; 1171 case ETHTOOL_LINK_MODE_25000baseSR_Full_BIT: 1172 set_mod_args(args, 25000, 0, 0, BIT_ULL(CGX_MODE_25G_C2C)); 1173 break; 1174 case ETHTOOL_LINK_MODE_25000baseCR_Full_BIT: 1175 set_mod_args(args, 25000, 0, 1, BIT_ULL(CGX_MODE_25G_CR)); 1176 break; 1177 case ETHTOOL_LINK_MODE_25000baseKR_Full_BIT: 1178 set_mod_args(args, 25000, 0, 1, BIT_ULL(CGX_MODE_25G_KR)); 1179 break; 1180 case ETHTOOL_LINK_MODE_40000baseSR4_Full_BIT: 1181 set_mod_args(args, 40000, 0, 0, BIT_ULL(CGX_MODE_40G_C2C)); 1182 break; 1183 case ETHTOOL_LINK_MODE_40000baseLR4_Full_BIT: 1184 set_mod_args(args, 40000, 0, 0, BIT_ULL(CGX_MODE_40G_C2M)); 1185 break; 1186 case ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT: 1187 set_mod_args(args, 40000, 0, 1, BIT_ULL(CGX_MODE_40G_CR4)); 1188 break; 1189 case ETHTOOL_LINK_MODE_40000baseKR4_Full_BIT: 1190 set_mod_args(args, 40000, 0, 1, BIT_ULL(CGX_MODE_40G_KR4)); 1191 break; 1192 case ETHTOOL_LINK_MODE_50000baseSR_Full_BIT: 1193 set_mod_args(args, 50000, 0, 0, BIT_ULL(CGX_MODE_50G_C2C)); 1194 break; 1195 case ETHTOOL_LINK_MODE_50000baseLR_ER_FR_Full_BIT: 1196 set_mod_args(args, 50000, 0, 0, BIT_ULL(CGX_MODE_50G_C2M)); 1197 break; 1198 case ETHTOOL_LINK_MODE_50000baseCR_Full_BIT: 1199 set_mod_args(args, 50000, 0, 1, BIT_ULL(CGX_MODE_50G_CR)); 1200 break; 1201 case ETHTOOL_LINK_MODE_50000baseKR_Full_BIT: 1202 set_mod_args(args, 50000, 0, 1, BIT_ULL(CGX_MODE_50G_KR)); 1203 break; 1204 case ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT: 1205 set_mod_args(args, 100000, 0, 0, BIT_ULL(CGX_MODE_100G_C2C)); 1206 break; 1207 case ETHTOOL_LINK_MODE_100000baseLR4_ER4_Full_BIT: 1208 set_mod_args(args, 100000, 0, 0, BIT_ULL(CGX_MODE_100G_C2M)); 1209 break; 1210 case ETHTOOL_LINK_MODE_100000baseCR4_Full_BIT: 1211 set_mod_args(args, 100000, 0, 1, BIT_ULL(CGX_MODE_100G_CR4)); 1212 break; 1213 case ETHTOOL_LINK_MODE_100000baseKR4_Full_BIT: 1214 set_mod_args(args, 100000, 0, 1, BIT_ULL(CGX_MODE_100G_KR4)); 1215 break; 1216 default: 1217 set_mod_args(args, 0, 1, 0, BIT_ULL(CGX_MODE_MAX)); 1218 break; 1219 } 1220 } 1221 1222 static inline void link_status_user_format(u64 lstat, 1223 struct cgx_link_user_info *linfo, 1224 struct cgx *cgx, u8 lmac_id) 1225 { 1226 const char *lmac_string; 1227 1228 linfo->link_up = FIELD_GET(RESP_LINKSTAT_UP, lstat); 1229 linfo->full_duplex = FIELD_GET(RESP_LINKSTAT_FDUPLEX, lstat); 1230 linfo->speed = cgx_speed_mbps[FIELD_GET(RESP_LINKSTAT_SPEED, lstat)]; 1231 linfo->an = FIELD_GET(RESP_LINKSTAT_AN, lstat); 1232 linfo->fec = FIELD_GET(RESP_LINKSTAT_FEC, lstat); 1233 linfo->lmac_type_id = FIELD_GET(RESP_LINKSTAT_LMAC_TYPE, lstat); 1234 1235 if (linfo->lmac_type_id >= LMAC_MODE_MAX) { 1236 dev_err(&cgx->pdev->dev, "Unknown lmac_type_id %d reported by firmware on cgx port%d:%d", 1237 linfo->lmac_type_id, cgx->cgx_id, lmac_id); 1238 strncpy(linfo->lmac_type, "Unknown", LMACTYPE_STR_LEN - 1); 1239 return; 1240 } 1241 1242 lmac_string = cgx_lmactype_string[linfo->lmac_type_id]; 1243 strncpy(linfo->lmac_type, lmac_string, LMACTYPE_STR_LEN - 1); 1244 } 1245 1246 /* Hardware event handlers */ 1247 static inline void cgx_link_change_handler(u64 lstat, 1248 struct lmac *lmac) 1249 { 1250 struct cgx_link_user_info *linfo; 1251 struct cgx *cgx = lmac->cgx; 1252 struct cgx_link_event event; 1253 struct device *dev; 1254 int err_type; 1255 1256 dev = &cgx->pdev->dev; 1257 1258 link_status_user_format(lstat, &event.link_uinfo, cgx, lmac->lmac_id); 1259 err_type = FIELD_GET(RESP_LINKSTAT_ERRTYPE, lstat); 1260 1261 event.cgx_id = cgx->cgx_id; 1262 event.lmac_id = lmac->lmac_id; 1263 1264 /* update the local copy of link status */ 1265 lmac->link_info = event.link_uinfo; 1266 linfo = &lmac->link_info; 1267 1268 if (err_type == CGX_ERR_SPEED_CHANGE_INVALID) 1269 return; 1270 1271 /* Ensure callback doesn't get unregistered until we finish it */ 1272 spin_lock(&lmac->event_cb_lock); 1273 1274 if (!lmac->event_cb.notify_link_chg) { 1275 dev_dbg(dev, "cgx port %d:%d Link change handler null", 1276 cgx->cgx_id, lmac->lmac_id); 1277 if (err_type != CGX_ERR_NONE) { 1278 dev_err(dev, "cgx port %d:%d Link error %d\n", 1279 cgx->cgx_id, lmac->lmac_id, err_type); 1280 } 1281 dev_info(dev, "cgx port %d:%d Link is %s %d Mbps\n", 1282 cgx->cgx_id, lmac->lmac_id, 1283 linfo->link_up ? "UP" : "DOWN", linfo->speed); 1284 goto err; 1285 } 1286 1287 if (lmac->event_cb.notify_link_chg(&event, lmac->event_cb.data)) 1288 dev_err(dev, "event notification failure\n"); 1289 err: 1290 spin_unlock(&lmac->event_cb_lock); 1291 } 1292 1293 static inline bool cgx_cmdresp_is_linkevent(u64 event) 1294 { 1295 u8 id; 1296 1297 id = FIELD_GET(EVTREG_ID, event); 1298 if (id == CGX_CMD_LINK_BRING_UP || 1299 id == CGX_CMD_LINK_BRING_DOWN || 1300 id == CGX_CMD_MODE_CHANGE) 1301 return true; 1302 else 1303 return false; 1304 } 1305 1306 static inline bool cgx_event_is_linkevent(u64 event) 1307 { 1308 if (FIELD_GET(EVTREG_ID, event) == CGX_EVT_LINK_CHANGE) 1309 return true; 1310 else 1311 return false; 1312 } 1313 1314 static irqreturn_t cgx_fwi_event_handler(int irq, void *data) 1315 { 1316 u64 event, offset, clear_bit; 1317 struct lmac *lmac = data; 1318 struct cgx *cgx; 1319 1320 cgx = lmac->cgx; 1321 1322 /* Clear SW_INT for RPM and CMR_INT for CGX */ 1323 offset = cgx->mac_ops->int_register; 1324 clear_bit = cgx->mac_ops->int_ena_bit; 1325 1326 event = cgx_read(cgx, lmac->lmac_id, CGX_EVENT_REG); 1327 1328 if (!FIELD_GET(EVTREG_ACK, event)) 1329 return IRQ_NONE; 1330 1331 switch (FIELD_GET(EVTREG_EVT_TYPE, event)) { 1332 case CGX_EVT_CMD_RESP: 1333 /* Copy the response. Since only one command is active at a 1334 * time, there is no way a response can get overwritten 1335 */ 1336 lmac->resp = event; 1337 /* Ensure response is updated before thread context starts */ 1338 smp_wmb(); 1339 1340 /* There wont be separate events for link change initiated from 1341 * software; Hence report the command responses as events 1342 */ 1343 if (cgx_cmdresp_is_linkevent(event)) 1344 cgx_link_change_handler(event, lmac); 1345 1346 /* Release thread waiting for completion */ 1347 lmac->cmd_pend = false; 1348 wake_up_interruptible(&lmac->wq_cmd_cmplt); 1349 break; 1350 case CGX_EVT_ASYNC: 1351 if (cgx_event_is_linkevent(event)) 1352 cgx_link_change_handler(event, lmac); 1353 break; 1354 } 1355 1356 /* Any new event or command response will be posted by firmware 1357 * only after the current status is acked. 1358 * Ack the interrupt register as well. 1359 */ 1360 cgx_write(lmac->cgx, lmac->lmac_id, CGX_EVENT_REG, 0); 1361 cgx_write(lmac->cgx, lmac->lmac_id, offset, clear_bit); 1362 1363 return IRQ_HANDLED; 1364 } 1365 1366 /* APIs for PHY management using CGX firmware interface */ 1367 1368 /* callback registration for hardware events like link change */ 1369 int cgx_lmac_evh_register(struct cgx_event_cb *cb, void *cgxd, int lmac_id) 1370 { 1371 struct cgx *cgx = cgxd; 1372 struct lmac *lmac; 1373 1374 lmac = lmac_pdata(lmac_id, cgx); 1375 if (!lmac) 1376 return -ENODEV; 1377 1378 lmac->event_cb = *cb; 1379 1380 return 0; 1381 } 1382 1383 int cgx_lmac_evh_unregister(void *cgxd, int lmac_id) 1384 { 1385 struct lmac *lmac; 1386 unsigned long flags; 1387 struct cgx *cgx = cgxd; 1388 1389 lmac = lmac_pdata(lmac_id, cgx); 1390 if (!lmac) 1391 return -ENODEV; 1392 1393 spin_lock_irqsave(&lmac->event_cb_lock, flags); 1394 lmac->event_cb.notify_link_chg = NULL; 1395 lmac->event_cb.data = NULL; 1396 spin_unlock_irqrestore(&lmac->event_cb_lock, flags); 1397 1398 return 0; 1399 } 1400 1401 int cgx_get_fwdata_base(u64 *base) 1402 { 1403 u64 req = 0, resp; 1404 struct cgx *cgx; 1405 int first_lmac; 1406 int err; 1407 1408 cgx = list_first_entry_or_null(&cgx_list, struct cgx, cgx_list); 1409 if (!cgx) 1410 return -ENXIO; 1411 1412 first_lmac = find_first_bit(&cgx->lmac_bmap, cgx->max_lmac_per_mac); 1413 req = FIELD_SET(CMDREG_ID, CGX_CMD_GET_FWD_BASE, req); 1414 err = cgx_fwi_cmd_generic(req, &resp, cgx, first_lmac); 1415 if (!err) 1416 *base = FIELD_GET(RESP_FWD_BASE, resp); 1417 1418 return err; 1419 } 1420 1421 int cgx_set_link_mode(void *cgxd, struct cgx_set_link_mode_args args, 1422 int cgx_id, int lmac_id) 1423 { 1424 struct cgx *cgx = cgxd; 1425 u64 req = 0, resp; 1426 1427 if (!cgx) 1428 return -ENODEV; 1429 1430 if (args.mode) 1431 otx2_map_ethtool_link_modes(args.mode, &args); 1432 if (!args.speed && args.duplex && !args.an) 1433 return -EINVAL; 1434 1435 req = FIELD_SET(CMDREG_ID, CGX_CMD_MODE_CHANGE, req); 1436 req = FIELD_SET(CMDMODECHANGE_SPEED, 1437 cgx_link_usertable_index_map(args.speed), req); 1438 req = FIELD_SET(CMDMODECHANGE_DUPLEX, args.duplex, req); 1439 req = FIELD_SET(CMDMODECHANGE_AN, args.an, req); 1440 req = FIELD_SET(CMDMODECHANGE_PORT, args.ports, req); 1441 req = FIELD_SET(CMDMODECHANGE_FLAGS, args.mode, req); 1442 1443 return cgx_fwi_cmd_generic(req, &resp, cgx, lmac_id); 1444 } 1445 int cgx_set_fec(u64 fec, int cgx_id, int lmac_id) 1446 { 1447 u64 req = 0, resp; 1448 struct cgx *cgx; 1449 int err = 0; 1450 1451 cgx = cgx_get_pdata(cgx_id); 1452 if (!cgx) 1453 return -ENXIO; 1454 1455 req = FIELD_SET(CMDREG_ID, CGX_CMD_SET_FEC, req); 1456 req = FIELD_SET(CMDSETFEC, fec, req); 1457 err = cgx_fwi_cmd_generic(req, &resp, cgx, lmac_id); 1458 if (err) 1459 return err; 1460 1461 cgx->lmac_idmap[lmac_id]->link_info.fec = 1462 FIELD_GET(RESP_LINKSTAT_FEC, resp); 1463 return cgx->lmac_idmap[lmac_id]->link_info.fec; 1464 } 1465 1466 int cgx_get_phy_fec_stats(void *cgxd, int lmac_id) 1467 { 1468 struct cgx *cgx = cgxd; 1469 u64 req = 0, resp; 1470 1471 if (!cgx) 1472 return -ENODEV; 1473 1474 req = FIELD_SET(CMDREG_ID, CGX_CMD_GET_PHY_FEC_STATS, req); 1475 return cgx_fwi_cmd_generic(req, &resp, cgx, lmac_id); 1476 } 1477 1478 static int cgx_fwi_link_change(struct cgx *cgx, int lmac_id, bool enable) 1479 { 1480 u64 req = 0; 1481 u64 resp; 1482 1483 if (enable) { 1484 req = FIELD_SET(CMDREG_ID, CGX_CMD_LINK_BRING_UP, req); 1485 /* On CN10K firmware offloads link bring up/down operations to ECP 1486 * On Octeontx2 link operations are handled by firmware itself 1487 * which can cause mbox errors so configure maximum time firmware 1488 * poll for Link as 1000 ms 1489 */ 1490 if (!is_dev_rpm(cgx)) 1491 req = FIELD_SET(LINKCFG_TIMEOUT, 1000, req); 1492 1493 } else { 1494 req = FIELD_SET(CMDREG_ID, CGX_CMD_LINK_BRING_DOWN, req); 1495 } 1496 return cgx_fwi_cmd_generic(req, &resp, cgx, lmac_id); 1497 } 1498 1499 static inline int cgx_fwi_read_version(u64 *resp, struct cgx *cgx) 1500 { 1501 int first_lmac = find_first_bit(&cgx->lmac_bmap, cgx->max_lmac_per_mac); 1502 u64 req = 0; 1503 1504 req = FIELD_SET(CMDREG_ID, CGX_CMD_GET_FW_VER, req); 1505 return cgx_fwi_cmd_generic(req, resp, cgx, first_lmac); 1506 } 1507 1508 static int cgx_lmac_verify_fwi_version(struct cgx *cgx) 1509 { 1510 struct device *dev = &cgx->pdev->dev; 1511 int major_ver, minor_ver; 1512 u64 resp; 1513 int err; 1514 1515 if (!cgx->lmac_count) 1516 return 0; 1517 1518 err = cgx_fwi_read_version(&resp, cgx); 1519 if (err) 1520 return err; 1521 1522 major_ver = FIELD_GET(RESP_MAJOR_VER, resp); 1523 minor_ver = FIELD_GET(RESP_MINOR_VER, resp); 1524 dev_dbg(dev, "Firmware command interface version = %d.%d\n", 1525 major_ver, minor_ver); 1526 if (major_ver != CGX_FIRMWARE_MAJOR_VER) 1527 return -EIO; 1528 else 1529 return 0; 1530 } 1531 1532 static void cgx_lmac_linkup_work(struct work_struct *work) 1533 { 1534 struct cgx *cgx = container_of(work, struct cgx, cgx_cmd_work); 1535 struct device *dev = &cgx->pdev->dev; 1536 int i, err; 1537 1538 /* Do Link up for all the enabled lmacs */ 1539 for_each_set_bit(i, &cgx->lmac_bmap, cgx->max_lmac_per_mac) { 1540 err = cgx_fwi_link_change(cgx, i, true); 1541 if (err) 1542 dev_info(dev, "cgx port %d:%d Link up command failed\n", 1543 cgx->cgx_id, i); 1544 } 1545 } 1546 1547 int cgx_lmac_linkup_start(void *cgxd) 1548 { 1549 struct cgx *cgx = cgxd; 1550 1551 if (!cgx) 1552 return -ENODEV; 1553 1554 queue_work(cgx->cgx_cmd_workq, &cgx->cgx_cmd_work); 1555 1556 return 0; 1557 } 1558 1559 static int cgx_configure_interrupt(struct cgx *cgx, struct lmac *lmac, 1560 int cnt, bool req_free) 1561 { 1562 struct mac_ops *mac_ops = cgx->mac_ops; 1563 u64 offset, ena_bit; 1564 unsigned int irq; 1565 int err; 1566 1567 irq = pci_irq_vector(cgx->pdev, mac_ops->lmac_fwi + 1568 cnt * mac_ops->irq_offset); 1569 offset = mac_ops->int_set_reg; 1570 ena_bit = mac_ops->int_ena_bit; 1571 1572 if (req_free) { 1573 free_irq(irq, lmac); 1574 return 0; 1575 } 1576 1577 err = request_irq(irq, cgx_fwi_event_handler, 0, lmac->name, lmac); 1578 if (err) 1579 return err; 1580 1581 /* Enable interrupt */ 1582 cgx_write(cgx, lmac->lmac_id, offset, ena_bit); 1583 return 0; 1584 } 1585 1586 int cgx_get_nr_lmacs(void *cgxd) 1587 { 1588 struct cgx *cgx = cgxd; 1589 1590 return cgx_read(cgx, 0, CGXX_CMRX_RX_LMACS) & 0x7ULL; 1591 } 1592 1593 u8 cgx_get_lmacid(void *cgxd, u8 lmac_index) 1594 { 1595 struct cgx *cgx = cgxd; 1596 1597 return cgx->lmac_idmap[lmac_index]->lmac_id; 1598 } 1599 1600 unsigned long cgx_get_lmac_bmap(void *cgxd) 1601 { 1602 struct cgx *cgx = cgxd; 1603 1604 return cgx->lmac_bmap; 1605 } 1606 1607 static int cgx_lmac_init(struct cgx *cgx) 1608 { 1609 struct lmac *lmac; 1610 u64 lmac_list; 1611 int i, err; 1612 1613 /* lmac_list specifies which lmacs are enabled 1614 * when bit n is set to 1, LMAC[n] is enabled 1615 */ 1616 if (cgx->mac_ops->non_contiguous_serdes_lane) { 1617 if (is_dev_rpm2(cgx)) 1618 lmac_list = 1619 cgx_read(cgx, 0, RPM2_CMRX_RX_LMACS) & 0xFFULL; 1620 else 1621 lmac_list = 1622 cgx_read(cgx, 0, CGXX_CMRX_RX_LMACS) & 0xFULL; 1623 } 1624 1625 if (cgx->lmac_count > cgx->max_lmac_per_mac) 1626 cgx->lmac_count = cgx->max_lmac_per_mac; 1627 1628 for (i = 0; i < cgx->lmac_count; i++) { 1629 lmac = kzalloc(sizeof(struct lmac), GFP_KERNEL); 1630 if (!lmac) 1631 return -ENOMEM; 1632 lmac->name = kcalloc(1, sizeof("cgx_fwi_xxx_yyy"), GFP_KERNEL); 1633 if (!lmac->name) { 1634 err = -ENOMEM; 1635 goto err_lmac_free; 1636 } 1637 sprintf(lmac->name, "cgx_fwi_%d_%d", cgx->cgx_id, i); 1638 if (cgx->mac_ops->non_contiguous_serdes_lane) { 1639 lmac->lmac_id = __ffs64(lmac_list); 1640 lmac_list &= ~BIT_ULL(lmac->lmac_id); 1641 } else { 1642 lmac->lmac_id = i; 1643 } 1644 1645 lmac->cgx = cgx; 1646 lmac->mac_to_index_bmap.max = 1647 cgx->mac_ops->dmac_filter_count / 1648 cgx->lmac_count; 1649 1650 err = rvu_alloc_bitmap(&lmac->mac_to_index_bmap); 1651 if (err) 1652 goto err_name_free; 1653 1654 /* Reserve first entry for default MAC address */ 1655 set_bit(0, lmac->mac_to_index_bmap.bmap); 1656 1657 lmac->rx_fc_pfvf_bmap.max = 128; 1658 err = rvu_alloc_bitmap(&lmac->rx_fc_pfvf_bmap); 1659 if (err) 1660 goto err_dmac_bmap_free; 1661 1662 lmac->tx_fc_pfvf_bmap.max = 128; 1663 err = rvu_alloc_bitmap(&lmac->tx_fc_pfvf_bmap); 1664 if (err) 1665 goto err_rx_fc_bmap_free; 1666 1667 init_waitqueue_head(&lmac->wq_cmd_cmplt); 1668 mutex_init(&lmac->cmd_lock); 1669 spin_lock_init(&lmac->event_cb_lock); 1670 err = cgx_configure_interrupt(cgx, lmac, lmac->lmac_id, false); 1671 if (err) 1672 goto err_bitmap_free; 1673 1674 /* Add reference */ 1675 cgx->lmac_idmap[lmac->lmac_id] = lmac; 1676 set_bit(lmac->lmac_id, &cgx->lmac_bmap); 1677 cgx->mac_ops->mac_pause_frm_config(cgx, lmac->lmac_id, true); 1678 } 1679 1680 return cgx_lmac_verify_fwi_version(cgx); 1681 1682 err_bitmap_free: 1683 rvu_free_bitmap(&lmac->tx_fc_pfvf_bmap); 1684 err_rx_fc_bmap_free: 1685 rvu_free_bitmap(&lmac->rx_fc_pfvf_bmap); 1686 err_dmac_bmap_free: 1687 rvu_free_bitmap(&lmac->mac_to_index_bmap); 1688 err_name_free: 1689 kfree(lmac->name); 1690 err_lmac_free: 1691 kfree(lmac); 1692 return err; 1693 } 1694 1695 static int cgx_lmac_exit(struct cgx *cgx) 1696 { 1697 struct lmac *lmac; 1698 int i; 1699 1700 if (cgx->cgx_cmd_workq) { 1701 destroy_workqueue(cgx->cgx_cmd_workq); 1702 cgx->cgx_cmd_workq = NULL; 1703 } 1704 1705 /* Free all lmac related resources */ 1706 for_each_set_bit(i, &cgx->lmac_bmap, cgx->max_lmac_per_mac) { 1707 lmac = cgx->lmac_idmap[i]; 1708 if (!lmac) 1709 continue; 1710 cgx->mac_ops->mac_pause_frm_config(cgx, lmac->lmac_id, false); 1711 cgx_configure_interrupt(cgx, lmac, lmac->lmac_id, true); 1712 kfree(lmac->mac_to_index_bmap.bmap); 1713 kfree(lmac->name); 1714 kfree(lmac); 1715 } 1716 1717 return 0; 1718 } 1719 1720 static void cgx_populate_features(struct cgx *cgx) 1721 { 1722 u64 cfg; 1723 1724 cfg = cgx_read(cgx, 0, CGX_CONST); 1725 cgx->mac_ops->fifo_len = FIELD_GET(CGX_CONST_RXFIFO_SIZE, cfg); 1726 cgx->max_lmac_per_mac = FIELD_GET(CGX_CONST_MAX_LMACS, cfg); 1727 1728 if (is_dev_rpm(cgx)) 1729 cgx->hw_features = (RVU_LMAC_FEAT_DMACF | RVU_MAC_RPM | 1730 RVU_LMAC_FEAT_FC | RVU_LMAC_FEAT_PTP); 1731 else 1732 cgx->hw_features = (RVU_LMAC_FEAT_FC | RVU_LMAC_FEAT_HIGIG2 | 1733 RVU_LMAC_FEAT_PTP | RVU_LMAC_FEAT_DMACF); 1734 } 1735 1736 static u8 cgx_get_rxid_mapoffset(struct cgx *cgx) 1737 { 1738 if (cgx->pdev->subsystem_device == PCI_SUBSYS_DEVID_CNF10KB_RPM || 1739 is_dev_rpm2(cgx)) 1740 return 0x80; 1741 else 1742 return 0x60; 1743 } 1744 1745 static struct mac_ops cgx_mac_ops = { 1746 .name = "cgx", 1747 .csr_offset = 0, 1748 .lmac_offset = 18, 1749 .int_register = CGXX_CMRX_INT, 1750 .int_set_reg = CGXX_CMRX_INT_ENA_W1S, 1751 .irq_offset = 9, 1752 .int_ena_bit = FW_CGX_INT, 1753 .lmac_fwi = CGX_LMAC_FWI, 1754 .non_contiguous_serdes_lane = false, 1755 .rx_stats_cnt = 9, 1756 .tx_stats_cnt = 18, 1757 .dmac_filter_count = 32, 1758 .get_nr_lmacs = cgx_get_nr_lmacs, 1759 .get_lmac_type = cgx_get_lmac_type, 1760 .lmac_fifo_len = cgx_get_lmac_fifo_len, 1761 .mac_lmac_intl_lbk = cgx_lmac_internal_loopback, 1762 .mac_get_rx_stats = cgx_get_rx_stats, 1763 .mac_get_tx_stats = cgx_get_tx_stats, 1764 .get_fec_stats = cgx_get_fec_stats, 1765 .mac_enadis_rx_pause_fwding = cgx_lmac_enadis_rx_pause_fwding, 1766 .mac_get_pause_frm_status = cgx_lmac_get_pause_frm_status, 1767 .mac_enadis_pause_frm = cgx_lmac_enadis_pause_frm, 1768 .mac_pause_frm_config = cgx_lmac_pause_frm_config, 1769 .mac_enadis_ptp_config = cgx_lmac_ptp_config, 1770 .mac_rx_tx_enable = cgx_lmac_rx_tx_enable, 1771 .mac_tx_enable = cgx_lmac_tx_enable, 1772 .pfc_config = cgx_lmac_pfc_config, 1773 .mac_get_pfc_frm_cfg = cgx_lmac_get_pfc_frm_cfg, 1774 }; 1775 1776 static int cgx_probe(struct pci_dev *pdev, const struct pci_device_id *id) 1777 { 1778 struct device *dev = &pdev->dev; 1779 struct cgx *cgx; 1780 int err, nvec; 1781 1782 cgx = devm_kzalloc(dev, sizeof(*cgx), GFP_KERNEL); 1783 if (!cgx) 1784 return -ENOMEM; 1785 cgx->pdev = pdev; 1786 1787 pci_set_drvdata(pdev, cgx); 1788 1789 /* Use mac_ops to get MAC specific features */ 1790 if (is_dev_rpm(cgx)) 1791 cgx->mac_ops = rpm_get_mac_ops(cgx); 1792 else 1793 cgx->mac_ops = &cgx_mac_ops; 1794 1795 cgx->mac_ops->rxid_map_offset = cgx_get_rxid_mapoffset(cgx); 1796 1797 err = pci_enable_device(pdev); 1798 if (err) { 1799 dev_err(dev, "Failed to enable PCI device\n"); 1800 pci_set_drvdata(pdev, NULL); 1801 return err; 1802 } 1803 1804 err = pci_request_regions(pdev, DRV_NAME); 1805 if (err) { 1806 dev_err(dev, "PCI request regions failed 0x%x\n", err); 1807 goto err_disable_device; 1808 } 1809 1810 /* MAP configuration registers */ 1811 cgx->reg_base = pcim_iomap(pdev, PCI_CFG_REG_BAR_NUM, 0); 1812 if (!cgx->reg_base) { 1813 dev_err(dev, "CGX: Cannot map CSR memory space, aborting\n"); 1814 err = -ENOMEM; 1815 goto err_release_regions; 1816 } 1817 1818 cgx->lmac_count = cgx->mac_ops->get_nr_lmacs(cgx); 1819 if (!cgx->lmac_count) { 1820 dev_notice(dev, "CGX %d LMAC count is zero, skipping probe\n", cgx->cgx_id); 1821 err = -EOPNOTSUPP; 1822 goto err_release_regions; 1823 } 1824 1825 nvec = pci_msix_vec_count(cgx->pdev); 1826 err = pci_alloc_irq_vectors(pdev, nvec, nvec, PCI_IRQ_MSIX); 1827 if (err < 0 || err != nvec) { 1828 dev_err(dev, "Request for %d msix vectors failed, err %d\n", 1829 nvec, err); 1830 goto err_release_regions; 1831 } 1832 1833 cgx->cgx_id = (pci_resource_start(pdev, PCI_CFG_REG_BAR_NUM) >> 24) 1834 & CGX_ID_MASK; 1835 1836 /* init wq for processing linkup requests */ 1837 INIT_WORK(&cgx->cgx_cmd_work, cgx_lmac_linkup_work); 1838 cgx->cgx_cmd_workq = alloc_workqueue("cgx_cmd_workq", 0, 0); 1839 if (!cgx->cgx_cmd_workq) { 1840 dev_err(dev, "alloc workqueue failed for cgx cmd"); 1841 err = -ENOMEM; 1842 goto err_free_irq_vectors; 1843 } 1844 1845 list_add(&cgx->cgx_list, &cgx_list); 1846 1847 1848 cgx_populate_features(cgx); 1849 1850 mutex_init(&cgx->lock); 1851 1852 err = cgx_lmac_init(cgx); 1853 if (err) 1854 goto err_release_lmac; 1855 1856 return 0; 1857 1858 err_release_lmac: 1859 cgx_lmac_exit(cgx); 1860 list_del(&cgx->cgx_list); 1861 err_free_irq_vectors: 1862 pci_free_irq_vectors(pdev); 1863 err_release_regions: 1864 pci_release_regions(pdev); 1865 err_disable_device: 1866 pci_disable_device(pdev); 1867 pci_set_drvdata(pdev, NULL); 1868 return err; 1869 } 1870 1871 static void cgx_remove(struct pci_dev *pdev) 1872 { 1873 struct cgx *cgx = pci_get_drvdata(pdev); 1874 1875 if (cgx) { 1876 cgx_lmac_exit(cgx); 1877 list_del(&cgx->cgx_list); 1878 } 1879 pci_free_irq_vectors(pdev); 1880 pci_release_regions(pdev); 1881 pci_disable_device(pdev); 1882 pci_set_drvdata(pdev, NULL); 1883 } 1884 1885 struct pci_driver cgx_driver = { 1886 .name = DRV_NAME, 1887 .id_table = cgx_id_table, 1888 .probe = cgx_probe, 1889 .remove = cgx_remove, 1890 }; 1891