1862cd659SVeerasenareddy Burru /* SPDX-License-Identifier: GPL-2.0 */ 2862cd659SVeerasenareddy Burru /* Marvell Octeon EP (EndPoint) Ethernet Driver 3862cd659SVeerasenareddy Burru * 4862cd659SVeerasenareddy Burru * Copyright (C) 2020 Marvell. 5862cd659SVeerasenareddy Burru * 6862cd659SVeerasenareddy Burru */ 7862cd659SVeerasenareddy Burru 8862cd659SVeerasenareddy Burru #ifndef _OCTEP_TX_H_ 9862cd659SVeerasenareddy Burru #define _OCTEP_TX_H_ 10862cd659SVeerasenareddy Burru 11862cd659SVeerasenareddy Burru #define IQ_SEND_OK 0 12862cd659SVeerasenareddy Burru #define IQ_SEND_STOP 1 13862cd659SVeerasenareddy Burru #define IQ_SEND_FAILED -1 14862cd659SVeerasenareddy Burru 15862cd659SVeerasenareddy Burru #define TX_BUFTYPE_NONE 0 16862cd659SVeerasenareddy Burru #define TX_BUFTYPE_NET 1 17862cd659SVeerasenareddy Burru #define TX_BUFTYPE_NET_SG 2 18862cd659SVeerasenareddy Burru #define NUM_TX_BUFTYPES 3 19862cd659SVeerasenareddy Burru 20*350db8a5SShinas Rasheed /* Hardware format for Scatter/Gather list 21*350db8a5SShinas Rasheed * 22*350db8a5SShinas Rasheed * 63 48|47 32|31 16|15 0 23*350db8a5SShinas Rasheed * ----------------------------------------- 24*350db8a5SShinas Rasheed * | Len 0 | Len 1 | Len 2 | Len 3 | 25*350db8a5SShinas Rasheed * ----------------------------------------- 26*350db8a5SShinas Rasheed * | Ptr 0 | 27*350db8a5SShinas Rasheed * ----------------------------------------- 28*350db8a5SShinas Rasheed * | Ptr 1 | 29*350db8a5SShinas Rasheed * ----------------------------------------- 30*350db8a5SShinas Rasheed * | Ptr 2 | 31*350db8a5SShinas Rasheed * ----------------------------------------- 32*350db8a5SShinas Rasheed * | Ptr 3 | 33*350db8a5SShinas Rasheed * ----------------------------------------- 34*350db8a5SShinas Rasheed */ 35862cd659SVeerasenareddy Burru struct octep_tx_sglist_desc { 36862cd659SVeerasenareddy Burru u16 len[4]; 37862cd659SVeerasenareddy Burru dma_addr_t dma_ptr[4]; 38862cd659SVeerasenareddy Burru }; 39862cd659SVeerasenareddy Burru 40862cd659SVeerasenareddy Burru /* Each Scatter/Gather entry sent to hardwar hold four pointers. 41862cd659SVeerasenareddy Burru * So, number of entries required is (MAX_SKB_FRAGS + 1)/4, where '+1' 42862cd659SVeerasenareddy Burru * is for main skb which also goes as a gather buffer to Octeon hardware. 43862cd659SVeerasenareddy Burru * To allocate sufficient SGLIST entries for a packet with max fragments, 44862cd659SVeerasenareddy Burru * align by adding 3 before calcuating max SGLIST entries per packet. 45862cd659SVeerasenareddy Burru */ 46862cd659SVeerasenareddy Burru #define OCTEP_SGLIST_ENTRIES_PER_PKT ((MAX_SKB_FRAGS + 1 + 3) / 4) 47862cd659SVeerasenareddy Burru #define OCTEP_SGLIST_SIZE_PER_PKT \ 48862cd659SVeerasenareddy Burru (OCTEP_SGLIST_ENTRIES_PER_PKT * sizeof(struct octep_tx_sglist_desc)) 49862cd659SVeerasenareddy Burru 50862cd659SVeerasenareddy Burru struct octep_tx_buffer { 51862cd659SVeerasenareddy Burru struct sk_buff *skb; 52862cd659SVeerasenareddy Burru dma_addr_t dma; 53862cd659SVeerasenareddy Burru struct octep_tx_sglist_desc *sglist; 54862cd659SVeerasenareddy Burru dma_addr_t sglist_dma; 55862cd659SVeerasenareddy Burru u8 gather; 56862cd659SVeerasenareddy Burru }; 57862cd659SVeerasenareddy Burru 58862cd659SVeerasenareddy Burru #define OCTEP_IQ_TXBUFF_INFO_SIZE (sizeof(struct octep_tx_buffer)) 59862cd659SVeerasenareddy Burru 60862cd659SVeerasenareddy Burru /* Hardware interface Tx statistics */ 61862cd659SVeerasenareddy Burru struct octep_iface_tx_stats { 62862cd659SVeerasenareddy Burru /* Packets dropped due to excessive collisions */ 63862cd659SVeerasenareddy Burru u64 xscol; 64862cd659SVeerasenareddy Burru 65862cd659SVeerasenareddy Burru /* Packets dropped due to excessive deferral */ 66862cd659SVeerasenareddy Burru u64 xsdef; 67862cd659SVeerasenareddy Burru 68862cd659SVeerasenareddy Burru /* Packets sent that experienced multiple collisions before successful 69862cd659SVeerasenareddy Burru * transmission 70862cd659SVeerasenareddy Burru */ 71862cd659SVeerasenareddy Burru u64 mcol; 72862cd659SVeerasenareddy Burru 73862cd659SVeerasenareddy Burru /* Packets sent that experienced a single collision before successful 74862cd659SVeerasenareddy Burru * transmission 75862cd659SVeerasenareddy Burru */ 76862cd659SVeerasenareddy Burru u64 scol; 77862cd659SVeerasenareddy Burru 78862cd659SVeerasenareddy Burru /* Total octets sent on the interface */ 79862cd659SVeerasenareddy Burru u64 octs; 80862cd659SVeerasenareddy Burru 81862cd659SVeerasenareddy Burru /* Total frames sent on the interface */ 82862cd659SVeerasenareddy Burru u64 pkts; 83862cd659SVeerasenareddy Burru 84862cd659SVeerasenareddy Burru /* Packets sent with an octet count < 64 */ 85862cd659SVeerasenareddy Burru u64 hist_lt64; 86862cd659SVeerasenareddy Burru 87862cd659SVeerasenareddy Burru /* Packets sent with an octet count == 64 */ 88862cd659SVeerasenareddy Burru u64 hist_eq64; 89862cd659SVeerasenareddy Burru 90862cd659SVeerasenareddy Burru /* Packets sent with an octet count of 65–127 */ 91862cd659SVeerasenareddy Burru u64 hist_65to127; 92862cd659SVeerasenareddy Burru 93862cd659SVeerasenareddy Burru /* Packets sent with an octet count of 128–255 */ 94862cd659SVeerasenareddy Burru u64 hist_128to255; 95862cd659SVeerasenareddy Burru 96862cd659SVeerasenareddy Burru /* Packets sent with an octet count of 256–511 */ 97862cd659SVeerasenareddy Burru u64 hist_256to511; 98862cd659SVeerasenareddy Burru 99862cd659SVeerasenareddy Burru /* Packets sent with an octet count of 512–1023 */ 100862cd659SVeerasenareddy Burru u64 hist_512to1023; 101862cd659SVeerasenareddy Burru 102862cd659SVeerasenareddy Burru /* Packets sent with an octet count of 1024-1518 */ 103862cd659SVeerasenareddy Burru u64 hist_1024to1518; 104862cd659SVeerasenareddy Burru 105862cd659SVeerasenareddy Burru /* Packets sent with an octet count of > 1518 */ 106862cd659SVeerasenareddy Burru u64 hist_gt1518; 107862cd659SVeerasenareddy Burru 108862cd659SVeerasenareddy Burru /* Packets sent to a broadcast DMAC */ 109862cd659SVeerasenareddy Burru u64 bcst; 110862cd659SVeerasenareddy Burru 111862cd659SVeerasenareddy Burru /* Packets sent to the multicast DMAC */ 112862cd659SVeerasenareddy Burru u64 mcst; 113862cd659SVeerasenareddy Burru 114862cd659SVeerasenareddy Burru /* Packets sent that experienced a transmit underflow and were 115862cd659SVeerasenareddy Burru * truncated 116862cd659SVeerasenareddy Burru */ 117862cd659SVeerasenareddy Burru u64 undflw; 118862cd659SVeerasenareddy Burru 119862cd659SVeerasenareddy Burru /* Control/PAUSE packets sent */ 120862cd659SVeerasenareddy Burru u64 ctl; 121862cd659SVeerasenareddy Burru }; 122862cd659SVeerasenareddy Burru 123862cd659SVeerasenareddy Burru /* Input Queue statistics. Each input queue has four stats fields. */ 124862cd659SVeerasenareddy Burru struct octep_iq_stats { 125862cd659SVeerasenareddy Burru /* Instructions posted to this queue. */ 126862cd659SVeerasenareddy Burru u64 instr_posted; 127862cd659SVeerasenareddy Burru 128862cd659SVeerasenareddy Burru /* Instructions copied by hardware for processing. */ 129862cd659SVeerasenareddy Burru u64 instr_completed; 130862cd659SVeerasenareddy Burru 131862cd659SVeerasenareddy Burru /* Instructions that could not be processed. */ 132862cd659SVeerasenareddy Burru u64 instr_dropped; 133862cd659SVeerasenareddy Burru 134862cd659SVeerasenareddy Burru /* Bytes sent through this queue. */ 135862cd659SVeerasenareddy Burru u64 bytes_sent; 136862cd659SVeerasenareddy Burru 137862cd659SVeerasenareddy Burru /* Gather entries sent through this queue. */ 138862cd659SVeerasenareddy Burru u64 sgentry_sent; 139862cd659SVeerasenareddy Burru 140862cd659SVeerasenareddy Burru /* Number of transmit failures due to TX_BUSY */ 141862cd659SVeerasenareddy Burru u64 tx_busy; 142862cd659SVeerasenareddy Burru 143862cd659SVeerasenareddy Burru /* Number of times the queue is restarted */ 144862cd659SVeerasenareddy Burru u64 restart_cnt; 145862cd659SVeerasenareddy Burru }; 146862cd659SVeerasenareddy Burru 147862cd659SVeerasenareddy Burru /* The instruction (input) queue. 148862cd659SVeerasenareddy Burru * The input queue is used to post raw (instruction) mode data or packet 149862cd659SVeerasenareddy Burru * data to Octeon device from the host. Each input queue (up to 4) for 150862cd659SVeerasenareddy Burru * a Octeon device has one such structure to represent it. 151862cd659SVeerasenareddy Burru */ 152862cd659SVeerasenareddy Burru struct octep_iq { 153862cd659SVeerasenareddy Burru u32 q_no; 154862cd659SVeerasenareddy Burru 155862cd659SVeerasenareddy Burru struct octep_device *octep_dev; 156862cd659SVeerasenareddy Burru struct net_device *netdev; 157862cd659SVeerasenareddy Burru struct device *dev; 158862cd659SVeerasenareddy Burru struct netdev_queue *netdev_q; 159862cd659SVeerasenareddy Burru 160862cd659SVeerasenareddy Burru /* Index in input ring where driver should write the next packet */ 161862cd659SVeerasenareddy Burru u16 host_write_index; 162862cd659SVeerasenareddy Burru 163862cd659SVeerasenareddy Burru /* Index in input ring where Octeon is expected to read next packet */ 164862cd659SVeerasenareddy Burru u16 octep_read_index; 165862cd659SVeerasenareddy Burru 166862cd659SVeerasenareddy Burru /* This index aids in finding the window in the queue where Octeon 167862cd659SVeerasenareddy Burru * has read the commands. 168862cd659SVeerasenareddy Burru */ 169862cd659SVeerasenareddy Burru u16 flush_index; 170862cd659SVeerasenareddy Burru 171862cd659SVeerasenareddy Burru /* Statistics for this input queue. */ 172862cd659SVeerasenareddy Burru struct octep_iq_stats stats; 173862cd659SVeerasenareddy Burru 174862cd659SVeerasenareddy Burru /* This field keeps track of the instructions pending in this queue. */ 175862cd659SVeerasenareddy Burru atomic_t instr_pending; 176862cd659SVeerasenareddy Burru 177862cd659SVeerasenareddy Burru /* Pointer to the Virtual Base addr of the input ring. */ 178862cd659SVeerasenareddy Burru struct octep_tx_desc_hw *desc_ring; 179862cd659SVeerasenareddy Burru 180862cd659SVeerasenareddy Burru /* DMA mapped base address of the input descriptor ring. */ 181862cd659SVeerasenareddy Burru dma_addr_t desc_ring_dma; 182862cd659SVeerasenareddy Burru 183862cd659SVeerasenareddy Burru /* Info of Tx buffers pending completion. */ 184862cd659SVeerasenareddy Burru struct octep_tx_buffer *buff_info; 185862cd659SVeerasenareddy Burru 186862cd659SVeerasenareddy Burru /* Base pointer to Scatter/Gather lists for all ring descriptors. */ 187862cd659SVeerasenareddy Burru struct octep_tx_sglist_desc *sglist; 188862cd659SVeerasenareddy Burru 189862cd659SVeerasenareddy Burru /* DMA mapped addr of Scatter Gather Lists */ 190862cd659SVeerasenareddy Burru dma_addr_t sglist_dma; 191862cd659SVeerasenareddy Burru 192862cd659SVeerasenareddy Burru /* Octeon doorbell register for the ring. */ 193862cd659SVeerasenareddy Burru u8 __iomem *doorbell_reg; 194862cd659SVeerasenareddy Burru 195862cd659SVeerasenareddy Burru /* Octeon instruction count register for this ring. */ 196862cd659SVeerasenareddy Burru u8 __iomem *inst_cnt_reg; 197862cd659SVeerasenareddy Burru 198862cd659SVeerasenareddy Burru /* interrupt level register for this ring */ 199862cd659SVeerasenareddy Burru u8 __iomem *intr_lvl_reg; 200862cd659SVeerasenareddy Burru 201862cd659SVeerasenareddy Burru /* Maximum no. of instructions in this queue. */ 202862cd659SVeerasenareddy Burru u32 max_count; 203862cd659SVeerasenareddy Burru u32 ring_size_mask; 204862cd659SVeerasenareddy Burru 205862cd659SVeerasenareddy Burru u32 pkt_in_done; 206862cd659SVeerasenareddy Burru u32 pkts_processed; 207862cd659SVeerasenareddy Burru 208862cd659SVeerasenareddy Burru u32 status; 209862cd659SVeerasenareddy Burru 210862cd659SVeerasenareddy Burru /* Number of instructions pending to be posted to Octeon. */ 211862cd659SVeerasenareddy Burru u32 fill_cnt; 212862cd659SVeerasenareddy Burru 213862cd659SVeerasenareddy Burru /* The max. number of instructions that can be held pending by the 214862cd659SVeerasenareddy Burru * driver before ringing doorbell. 215862cd659SVeerasenareddy Burru */ 216862cd659SVeerasenareddy Burru u32 fill_threshold; 217862cd659SVeerasenareddy Burru }; 218862cd659SVeerasenareddy Burru 219862cd659SVeerasenareddy Burru /* Hardware Tx Instruction Header */ 220862cd659SVeerasenareddy Burru struct octep_instr_hdr { 221862cd659SVeerasenareddy Burru /* Data Len */ 222862cd659SVeerasenareddy Burru u64 tlen:16; 223862cd659SVeerasenareddy Burru 224862cd659SVeerasenareddy Burru /* Reserved */ 225862cd659SVeerasenareddy Burru u64 rsvd:20; 226862cd659SVeerasenareddy Burru 227862cd659SVeerasenareddy Burru /* PKIND for SDP */ 228862cd659SVeerasenareddy Burru u64 pkind:6; 229862cd659SVeerasenareddy Burru 230862cd659SVeerasenareddy Burru /* Front Data size */ 231862cd659SVeerasenareddy Burru u64 fsz:6; 232862cd659SVeerasenareddy Burru 233862cd659SVeerasenareddy Burru /* No. of entries in gather list */ 234862cd659SVeerasenareddy Burru u64 gsz:14; 235862cd659SVeerasenareddy Burru 236862cd659SVeerasenareddy Burru /* Gather indicator 1=gather*/ 237862cd659SVeerasenareddy Burru u64 gather:1; 238862cd659SVeerasenareddy Burru 239862cd659SVeerasenareddy Burru /* Reserved3 */ 240862cd659SVeerasenareddy Burru u64 reserved3:1; 241862cd659SVeerasenareddy Burru }; 242862cd659SVeerasenareddy Burru 243862cd659SVeerasenareddy Burru /* Hardware Tx completion response header */ 244862cd659SVeerasenareddy Burru struct octep_instr_resp_hdr { 245862cd659SVeerasenareddy Burru /* Request ID */ 246862cd659SVeerasenareddy Burru u64 rid:16; 247862cd659SVeerasenareddy Burru 248862cd659SVeerasenareddy Burru /* PCIe port to use for response */ 249862cd659SVeerasenareddy Burru u64 pcie_port:3; 250862cd659SVeerasenareddy Burru 251862cd659SVeerasenareddy Burru /* Scatter indicator 1=scatter */ 252862cd659SVeerasenareddy Burru u64 scatter:1; 253862cd659SVeerasenareddy Burru 254862cd659SVeerasenareddy Burru /* Size of Expected result OR no. of entries in scatter list */ 255862cd659SVeerasenareddy Burru u64 rlenssz:14; 256862cd659SVeerasenareddy Burru 257862cd659SVeerasenareddy Burru /* Desired destination port for result */ 258862cd659SVeerasenareddy Burru u64 dport:6; 259862cd659SVeerasenareddy Burru 260862cd659SVeerasenareddy Burru /* Opcode Specific parameters */ 261862cd659SVeerasenareddy Burru u64 param:8; 262862cd659SVeerasenareddy Burru 263862cd659SVeerasenareddy Burru /* Opcode for the return packet */ 264862cd659SVeerasenareddy Burru u64 opcode:16; 265862cd659SVeerasenareddy Burru }; 266862cd659SVeerasenareddy Burru 267862cd659SVeerasenareddy Burru /* 64-byte Tx instruction format. 268862cd659SVeerasenareddy Burru * Format of instruction for a 64-byte mode input queue. 269862cd659SVeerasenareddy Burru * 270862cd659SVeerasenareddy Burru * only first 16-bytes (dptr and ih) are mandatory; rest are optional 271862cd659SVeerasenareddy Burru * and filled by the driver based on firmware/hardware capabilities. 272862cd659SVeerasenareddy Burru * These optional headers together called Front Data and its size is 273862cd659SVeerasenareddy Burru * described by ih->fsz. 274862cd659SVeerasenareddy Burru */ 275862cd659SVeerasenareddy Burru struct octep_tx_desc_hw { 276862cd659SVeerasenareddy Burru /* Pointer where the input data is available. */ 277862cd659SVeerasenareddy Burru u64 dptr; 278862cd659SVeerasenareddy Burru 279862cd659SVeerasenareddy Burru /* Instruction Header. */ 280862cd659SVeerasenareddy Burru union { 281862cd659SVeerasenareddy Burru struct octep_instr_hdr ih; 282862cd659SVeerasenareddy Burru u64 ih64; 283862cd659SVeerasenareddy Burru }; 284862cd659SVeerasenareddy Burru 285862cd659SVeerasenareddy Burru /* Pointer where the response for a RAW mode packet will be written 286862cd659SVeerasenareddy Burru * by Octeon. 287862cd659SVeerasenareddy Burru */ 288862cd659SVeerasenareddy Burru u64 rptr; 289862cd659SVeerasenareddy Burru 290862cd659SVeerasenareddy Burru /* Input Instruction Response Header. */ 291862cd659SVeerasenareddy Burru struct octep_instr_resp_hdr irh; 292862cd659SVeerasenareddy Burru 293862cd659SVeerasenareddy Burru /* Additional headers available in a 64-byte instruction. */ 294862cd659SVeerasenareddy Burru u64 exhdr[4]; 295862cd659SVeerasenareddy Burru }; 296862cd659SVeerasenareddy Burru 297862cd659SVeerasenareddy Burru #define OCTEP_IQ_DESC_SIZE (sizeof(struct octep_tx_desc_hw)) 298862cd659SVeerasenareddy Burru #endif /* _OCTEP_TX_H_ */ 299