1862cd659SVeerasenareddy Burru /* SPDX-License-Identifier: GPL-2.0 */ 2862cd659SVeerasenareddy Burru /* Marvell Octeon EP (EndPoint) Ethernet Driver 3862cd659SVeerasenareddy Burru * 4862cd659SVeerasenareddy Burru * Copyright (C) 2020 Marvell. 5862cd659SVeerasenareddy Burru * 6862cd659SVeerasenareddy Burru */ 7862cd659SVeerasenareddy Burru 8862cd659SVeerasenareddy Burru #ifndef _OCTEP_REGS_CN9K_PF_H_ 9862cd659SVeerasenareddy Burru #define _OCTEP_REGS_CN9K_PF_H_ 10862cd659SVeerasenareddy Burru 11862cd659SVeerasenareddy Burru /* ############################ RST ######################### */ 12862cd659SVeerasenareddy Burru #define CN93_RST_BOOT 0x000087E006001600ULL 13862cd659SVeerasenareddy Burru #define CN93_RST_CORE_DOMAIN_W1S 0x000087E006001820ULL 14862cd659SVeerasenareddy Burru #define CN93_RST_CORE_DOMAIN_W1C 0x000087E006001828ULL 15862cd659SVeerasenareddy Burru 16862cd659SVeerasenareddy Burru #define CN93_CONFIG_XPANSION_BAR 0x38 17862cd659SVeerasenareddy Burru #define CN93_CONFIG_PCIE_CAP 0x70 18862cd659SVeerasenareddy Burru #define CN93_CONFIG_PCIE_DEVCAP 0x74 19862cd659SVeerasenareddy Burru #define CN93_CONFIG_PCIE_DEVCTL 0x78 20862cd659SVeerasenareddy Burru #define CN93_CONFIG_PCIE_LINKCAP 0x7C 21862cd659SVeerasenareddy Burru #define CN93_CONFIG_PCIE_LINKCTL 0x80 22862cd659SVeerasenareddy Burru #define CN93_CONFIG_PCIE_SLOTCAP 0x84 23862cd659SVeerasenareddy Burru #define CN93_CONFIG_PCIE_SLOTCTL 0x88 24862cd659SVeerasenareddy Burru 25862cd659SVeerasenareddy Burru #define CN93_PCIE_SRIOV_FDL 0x188 /* 0x98 */ 26862cd659SVeerasenareddy Burru #define CN93_PCIE_SRIOV_FDL_BIT_POS 0x10 27862cd659SVeerasenareddy Burru #define CN93_PCIE_SRIOV_FDL_MASK 0xFF 28862cd659SVeerasenareddy Burru 29862cd659SVeerasenareddy Burru #define CN93_CONFIG_PCIE_FLTMSK 0x720 30862cd659SVeerasenareddy Burru 31862cd659SVeerasenareddy Burru /* ################# Offsets of RING, EPF, MAC ######################### */ 32862cd659SVeerasenareddy Burru #define CN93_RING_OFFSET (0x1ULL << 17) 33862cd659SVeerasenareddy Burru #define CN93_EPF_OFFSET (0x1ULL << 25) 34862cd659SVeerasenareddy Burru #define CN93_MAC_OFFSET (0x1ULL << 4) 35862cd659SVeerasenareddy Burru #define CN93_BIT_ARRAY_OFFSET (0x1ULL << 4) 36862cd659SVeerasenareddy Burru #define CN93_EPVF_RING_OFFSET (0x1ULL << 4) 37862cd659SVeerasenareddy Burru 38862cd659SVeerasenareddy Burru /* ################# Scratch Registers ######################### */ 39862cd659SVeerasenareddy Burru #define CN93_SDP_EPF_SCRATCH 0x205E0 40862cd659SVeerasenareddy Burru 41862cd659SVeerasenareddy Burru /* ################# Window Registers ######################### */ 42862cd659SVeerasenareddy Burru #define CN93_SDP_WIN_WR_ADDR64 0x20000 43862cd659SVeerasenareddy Burru #define CN93_SDP_WIN_RD_ADDR64 0x20010 44862cd659SVeerasenareddy Burru #define CN93_SDP_WIN_WR_DATA64 0x20020 45862cd659SVeerasenareddy Burru #define CN93_SDP_WIN_WR_MASK_REG 0x20030 46862cd659SVeerasenareddy Burru #define CN93_SDP_WIN_RD_DATA64 0x20040 47862cd659SVeerasenareddy Burru 48862cd659SVeerasenareddy Burru #define CN93_SDP_MAC_NUMBER 0x2C100 49862cd659SVeerasenareddy Burru 50862cd659SVeerasenareddy Burru /* ################# Global Previliged registers ######################### */ 51862cd659SVeerasenareddy Burru #define CN93_SDP_EPF_RINFO 0x205F0 52862cd659SVeerasenareddy Burru 53862cd659SVeerasenareddy Burru #define CN93_SDP_EPF_RINFO_SRN(val) ((val) & 0xFF) 54862cd659SVeerasenareddy Burru #define CN93_SDP_EPF_RINFO_RPVF(val) (((val) >> 32) & 0xF) 554bbfed91SShreenidhi Shedi #define CN93_SDP_EPF_RINFO_NVFS(val) (((val) >> 48) & 0xFF) 56862cd659SVeerasenareddy Burru 57862cd659SVeerasenareddy Burru /* SDP Function select */ 58862cd659SVeerasenareddy Burru #define CN93_SDP_FUNC_SEL_EPF_BIT_POS 8 59862cd659SVeerasenareddy Burru #define CN93_SDP_FUNC_SEL_FUNC_BIT_POS 0 60862cd659SVeerasenareddy Burru 61862cd659SVeerasenareddy Burru /* ##### RING IN (Into device from PCI: Tx Ring) REGISTERS #### */ 62862cd659SVeerasenareddy Burru #define CN93_SDP_R_IN_CONTROL_START 0x10000 63862cd659SVeerasenareddy Burru #define CN93_SDP_R_IN_ENABLE_START 0x10010 64862cd659SVeerasenareddy Burru #define CN93_SDP_R_IN_INSTR_BADDR_START 0x10020 65862cd659SVeerasenareddy Burru #define CN93_SDP_R_IN_INSTR_RSIZE_START 0x10030 66862cd659SVeerasenareddy Burru #define CN93_SDP_R_IN_INSTR_DBELL_START 0x10040 67862cd659SVeerasenareddy Burru #define CN93_SDP_R_IN_CNTS_START 0x10050 68862cd659SVeerasenareddy Burru #define CN93_SDP_R_IN_INT_LEVELS_START 0x10060 69862cd659SVeerasenareddy Burru #define CN93_SDP_R_IN_PKT_CNT_START 0x10080 70862cd659SVeerasenareddy Burru #define CN93_SDP_R_IN_BYTE_CNT_START 0x10090 71862cd659SVeerasenareddy Burru 72862cd659SVeerasenareddy Burru #define CN93_SDP_R_IN_CONTROL(ring) \ 73862cd659SVeerasenareddy Burru (CN93_SDP_R_IN_CONTROL_START + ((ring) * CN93_RING_OFFSET)) 74862cd659SVeerasenareddy Burru 75862cd659SVeerasenareddy Burru #define CN93_SDP_R_IN_ENABLE(ring) \ 76862cd659SVeerasenareddy Burru (CN93_SDP_R_IN_ENABLE_START + ((ring) * CN93_RING_OFFSET)) 77862cd659SVeerasenareddy Burru 78862cd659SVeerasenareddy Burru #define CN93_SDP_R_IN_INSTR_BADDR(ring) \ 79862cd659SVeerasenareddy Burru (CN93_SDP_R_IN_INSTR_BADDR_START + ((ring) * CN93_RING_OFFSET)) 80862cd659SVeerasenareddy Burru 81862cd659SVeerasenareddy Burru #define CN93_SDP_R_IN_INSTR_RSIZE(ring) \ 82862cd659SVeerasenareddy Burru (CN93_SDP_R_IN_INSTR_RSIZE_START + ((ring) * CN93_RING_OFFSET)) 83862cd659SVeerasenareddy Burru 84862cd659SVeerasenareddy Burru #define CN93_SDP_R_IN_INSTR_DBELL(ring) \ 85862cd659SVeerasenareddy Burru (CN93_SDP_R_IN_INSTR_DBELL_START + ((ring) * CN93_RING_OFFSET)) 86862cd659SVeerasenareddy Burru 87862cd659SVeerasenareddy Burru #define CN93_SDP_R_IN_CNTS(ring) \ 88862cd659SVeerasenareddy Burru (CN93_SDP_R_IN_CNTS_START + ((ring) * CN93_RING_OFFSET)) 89862cd659SVeerasenareddy Burru 90862cd659SVeerasenareddy Burru #define CN93_SDP_R_IN_INT_LEVELS(ring) \ 91862cd659SVeerasenareddy Burru (CN93_SDP_R_IN_INT_LEVELS_START + ((ring) * CN93_RING_OFFSET)) 92862cd659SVeerasenareddy Burru 93862cd659SVeerasenareddy Burru #define CN93_SDP_R_IN_PKT_CNT(ring) \ 94862cd659SVeerasenareddy Burru (CN93_SDP_R_IN_PKT_CNT_START + ((ring) * CN93_RING_OFFSET)) 95862cd659SVeerasenareddy Burru 96862cd659SVeerasenareddy Burru #define CN93_SDP_R_IN_BYTE_CNT(ring) \ 97862cd659SVeerasenareddy Burru (CN93_SDP_R_IN_BYTE_CNT_START + ((ring) * CN93_RING_OFFSET)) 98862cd659SVeerasenareddy Burru 99862cd659SVeerasenareddy Burru /* Rings per Virtual Function */ 100862cd659SVeerasenareddy Burru #define CN93_R_IN_CTL_RPVF_MASK (0xF) 101862cd659SVeerasenareddy Burru #define CN93_R_IN_CTL_RPVF_POS (48) 102862cd659SVeerasenareddy Burru 103862cd659SVeerasenareddy Burru /* Number of instructions to be read in one MAC read request. 104862cd659SVeerasenareddy Burru * setting to Max value(4) 105862cd659SVeerasenareddy Burru */ 106862cd659SVeerasenareddy Burru #define CN93_R_IN_CTL_IDLE (0x1ULL << 28) 107862cd659SVeerasenareddy Burru #define CN93_R_IN_CTL_RDSIZE (0x3ULL << 25) 108862cd659SVeerasenareddy Burru #define CN93_R_IN_CTL_IS_64B (0x1ULL << 24) 109862cd659SVeerasenareddy Burru #define CN93_R_IN_CTL_D_NSR (0x1ULL << 8) 110862cd659SVeerasenareddy Burru #define CN93_R_IN_CTL_D_ESR (0x1ULL << 6) 111862cd659SVeerasenareddy Burru #define CN93_R_IN_CTL_D_ROR (0x1ULL << 5) 112862cd659SVeerasenareddy Burru #define CN93_R_IN_CTL_NSR (0x1ULL << 3) 113862cd659SVeerasenareddy Burru #define CN93_R_IN_CTL_ESR (0x1ULL << 1) 114862cd659SVeerasenareddy Burru #define CN93_R_IN_CTL_ROR (0x1ULL << 0) 115862cd659SVeerasenareddy Burru 116862cd659SVeerasenareddy Burru #define CN93_R_IN_CTL_MASK (CN93_R_IN_CTL_RDSIZE | CN93_R_IN_CTL_IS_64B) 117862cd659SVeerasenareddy Burru 118862cd659SVeerasenareddy Burru /* ##### RING OUT (out from device to PCI host: Rx Ring) REGISTERS #### */ 119862cd659SVeerasenareddy Burru #define CN93_SDP_R_OUT_CNTS_START 0x10100 120862cd659SVeerasenareddy Burru #define CN93_SDP_R_OUT_INT_LEVELS_START 0x10110 121862cd659SVeerasenareddy Burru #define CN93_SDP_R_OUT_SLIST_BADDR_START 0x10120 122862cd659SVeerasenareddy Burru #define CN93_SDP_R_OUT_SLIST_RSIZE_START 0x10130 123862cd659SVeerasenareddy Burru #define CN93_SDP_R_OUT_SLIST_DBELL_START 0x10140 124862cd659SVeerasenareddy Burru #define CN93_SDP_R_OUT_CONTROL_START 0x10150 125862cd659SVeerasenareddy Burru #define CN93_SDP_R_OUT_ENABLE_START 0x10160 126862cd659SVeerasenareddy Burru #define CN93_SDP_R_OUT_PKT_CNT_START 0x10180 127862cd659SVeerasenareddy Burru #define CN93_SDP_R_OUT_BYTE_CNT_START 0x10190 128862cd659SVeerasenareddy Burru 129862cd659SVeerasenareddy Burru #define CN93_SDP_R_OUT_CONTROL(ring) \ 130862cd659SVeerasenareddy Burru (CN93_SDP_R_OUT_CONTROL_START + ((ring) * CN93_RING_OFFSET)) 131862cd659SVeerasenareddy Burru 132862cd659SVeerasenareddy Burru #define CN93_SDP_R_OUT_ENABLE(ring) \ 133862cd659SVeerasenareddy Burru (CN93_SDP_R_OUT_ENABLE_START + ((ring) * CN93_RING_OFFSET)) 134862cd659SVeerasenareddy Burru 135862cd659SVeerasenareddy Burru #define CN93_SDP_R_OUT_SLIST_BADDR(ring) \ 136862cd659SVeerasenareddy Burru (CN93_SDP_R_OUT_SLIST_BADDR_START + ((ring) * CN93_RING_OFFSET)) 137862cd659SVeerasenareddy Burru 138862cd659SVeerasenareddy Burru #define CN93_SDP_R_OUT_SLIST_RSIZE(ring) \ 139862cd659SVeerasenareddy Burru (CN93_SDP_R_OUT_SLIST_RSIZE_START + ((ring) * CN93_RING_OFFSET)) 140862cd659SVeerasenareddy Burru 141862cd659SVeerasenareddy Burru #define CN93_SDP_R_OUT_SLIST_DBELL(ring) \ 142862cd659SVeerasenareddy Burru (CN93_SDP_R_OUT_SLIST_DBELL_START + ((ring) * CN93_RING_OFFSET)) 143862cd659SVeerasenareddy Burru 144862cd659SVeerasenareddy Burru #define CN93_SDP_R_OUT_CNTS(ring) \ 145862cd659SVeerasenareddy Burru (CN93_SDP_R_OUT_CNTS_START + ((ring) * CN93_RING_OFFSET)) 146862cd659SVeerasenareddy Burru 147862cd659SVeerasenareddy Burru #define CN93_SDP_R_OUT_INT_LEVELS(ring) \ 148862cd659SVeerasenareddy Burru (CN93_SDP_R_OUT_INT_LEVELS_START + ((ring) * CN93_RING_OFFSET)) 149862cd659SVeerasenareddy Burru 150862cd659SVeerasenareddy Burru #define CN93_SDP_R_OUT_PKT_CNT(ring) \ 151862cd659SVeerasenareddy Burru (CN93_SDP_R_OUT_PKT_CNT_START + ((ring) * CN93_RING_OFFSET)) 152862cd659SVeerasenareddy Burru 153862cd659SVeerasenareddy Burru #define CN93_SDP_R_OUT_BYTE_CNT(ring) \ 154862cd659SVeerasenareddy Burru (CN93_SDP_R_OUT_BYTE_CNT_START + ((ring) * CN93_RING_OFFSET)) 155862cd659SVeerasenareddy Burru 156862cd659SVeerasenareddy Burru /*------------------ R_OUT Masks ----------------*/ 157862cd659SVeerasenareddy Burru #define CN93_R_OUT_INT_LEVELS_BMODE BIT_ULL(63) 158862cd659SVeerasenareddy Burru #define CN93_R_OUT_INT_LEVELS_TIMET (32) 159862cd659SVeerasenareddy Burru 160862cd659SVeerasenareddy Burru #define CN93_R_OUT_CTL_IDLE BIT_ULL(40) 161862cd659SVeerasenareddy Burru #define CN93_R_OUT_CTL_ES_I BIT_ULL(34) 162862cd659SVeerasenareddy Burru #define CN93_R_OUT_CTL_NSR_I BIT_ULL(33) 163862cd659SVeerasenareddy Burru #define CN93_R_OUT_CTL_ROR_I BIT_ULL(32) 164862cd659SVeerasenareddy Burru #define CN93_R_OUT_CTL_ES_D BIT_ULL(30) 165862cd659SVeerasenareddy Burru #define CN93_R_OUT_CTL_NSR_D BIT_ULL(29) 166862cd659SVeerasenareddy Burru #define CN93_R_OUT_CTL_ROR_D BIT_ULL(28) 167862cd659SVeerasenareddy Burru #define CN93_R_OUT_CTL_ES_P BIT_ULL(26) 168862cd659SVeerasenareddy Burru #define CN93_R_OUT_CTL_NSR_P BIT_ULL(25) 169862cd659SVeerasenareddy Burru #define CN93_R_OUT_CTL_ROR_P BIT_ULL(24) 170862cd659SVeerasenareddy Burru #define CN93_R_OUT_CTL_IMODE BIT_ULL(23) 171862cd659SVeerasenareddy Burru 172862cd659SVeerasenareddy Burru /* ############### Interrupt Moderation Registers ############### */ 173862cd659SVeerasenareddy Burru #define CN93_SDP_R_IN_INT_MDRT_CTL0_START 0x10280 174862cd659SVeerasenareddy Burru #define CN93_SDP_R_IN_INT_MDRT_CTL1_START 0x102A0 175862cd659SVeerasenareddy Burru #define CN93_SDP_R_IN_INT_MDRT_DBG_START 0x102C0 176862cd659SVeerasenareddy Burru 177862cd659SVeerasenareddy Burru #define CN93_SDP_R_OUT_INT_MDRT_CTL0_START 0x10380 178862cd659SVeerasenareddy Burru #define CN93_SDP_R_OUT_INT_MDRT_CTL1_START 0x103A0 179862cd659SVeerasenareddy Burru #define CN93_SDP_R_OUT_INT_MDRT_DBG_START 0x103C0 180862cd659SVeerasenareddy Burru 181862cd659SVeerasenareddy Burru #define CN93_SDP_R_IN_INT_MDRT_CTL0(ring) \ 182862cd659SVeerasenareddy Burru (CN93_SDP_R_IN_INT_MDRT_CTL0_START + ((ring) * CN93_RING_OFFSET)) 183862cd659SVeerasenareddy Burru 184862cd659SVeerasenareddy Burru #define CN93_SDP_R_IN_INT_MDRT_CTL1(ring) \ 185862cd659SVeerasenareddy Burru (CN93_SDP_R_IN_INT_MDRT_CTL1_START + ((ring) * CN93_RING_OFFSET)) 186862cd659SVeerasenareddy Burru 187862cd659SVeerasenareddy Burru #define CN93_SDP_R_IN_INT_MDRT_DBG(ring) \ 188862cd659SVeerasenareddy Burru (CN93_SDP_R_IN_INT_MDRT_DBG_START + ((ring) * CN93_RING_OFFSET)) 189862cd659SVeerasenareddy Burru 190862cd659SVeerasenareddy Burru #define CN93_SDP_R_OUT_INT_MDRT_CTL0(ring) \ 191862cd659SVeerasenareddy Burru (CN93_SDP_R_OUT_INT_MDRT_CTL0_START + ((ring) * CN93_RING_OFFSET)) 192862cd659SVeerasenareddy Burru 193862cd659SVeerasenareddy Burru #define CN93_SDP_R_OUT_INT_MDRT_CTL1(ring) \ 194862cd659SVeerasenareddy Burru (CN93_SDP_R_OUT_INT_MDRT_CTL1_START + ((ring) * CN93_RING_OFFSET)) 195862cd659SVeerasenareddy Burru 196862cd659SVeerasenareddy Burru #define CN93_SDP_R_OUT_INT_MDRT_DBG(ring) \ 197862cd659SVeerasenareddy Burru (CN93_SDP_R_OUT_INT_MDRT_DBG_START + ((ring) * CN93_RING_OFFSET)) 198862cd659SVeerasenareddy Burru 199862cd659SVeerasenareddy Burru /* ##################### Mail Box Registers ########################## */ 200862cd659SVeerasenareddy Burru /* INT register for VF. when a MBOX write from PF happed to a VF, 201862cd659SVeerasenareddy Burru * corresponding bit will be set in this register as well as in 202862cd659SVeerasenareddy Burru * PF_VF_INT register. 203862cd659SVeerasenareddy Burru * 204862cd659SVeerasenareddy Burru * This is a RO register, the int can be cleared by writing 1 to PF_VF_INT 205862cd659SVeerasenareddy Burru */ 206862cd659SVeerasenareddy Burru /* Basically first 3 are from PF to VF. The last one is data from VF to PF */ 207862cd659SVeerasenareddy Burru #define CN93_SDP_R_MBOX_PF_VF_DATA_START 0x10210 208862cd659SVeerasenareddy Burru #define CN93_SDP_R_MBOX_PF_VF_INT_START 0x10220 209862cd659SVeerasenareddy Burru #define CN93_SDP_R_MBOX_VF_PF_DATA_START 0x10230 210862cd659SVeerasenareddy Burru 211862cd659SVeerasenareddy Burru #define CN93_SDP_R_MBOX_PF_VF_DATA(ring) \ 212862cd659SVeerasenareddy Burru (CN93_SDP_R_MBOX_PF_VF_DATA_START + ((ring) * CN93_RING_OFFSET)) 213862cd659SVeerasenareddy Burru 214862cd659SVeerasenareddy Burru #define CN93_SDP_R_MBOX_PF_VF_INT(ring) \ 215862cd659SVeerasenareddy Burru (CN93_SDP_R_MBOX_PF_VF_INT_START + ((ring) * CN93_RING_OFFSET)) 216862cd659SVeerasenareddy Burru 217862cd659SVeerasenareddy Burru #define CN93_SDP_R_MBOX_VF_PF_DATA(ring) \ 218862cd659SVeerasenareddy Burru (CN93_SDP_R_MBOX_VF_PF_DATA_START + ((ring) * CN93_RING_OFFSET)) 219862cd659SVeerasenareddy Burru 220862cd659SVeerasenareddy Burru /* ##################### Interrupt Registers ########################## */ 221862cd659SVeerasenareddy Burru #define CN93_SDP_R_ERR_TYPE_START 0x10400 222862cd659SVeerasenareddy Burru 223862cd659SVeerasenareddy Burru #define CN93_SDP_R_ERR_TYPE(ring) \ 224862cd659SVeerasenareddy Burru (CN93_SDP_R_ERR_TYPE_START + ((ring) * CN93_RING_OFFSET)) 225862cd659SVeerasenareddy Burru 226862cd659SVeerasenareddy Burru #define CN93_SDP_R_MBOX_ISM_START 0x10500 227862cd659SVeerasenareddy Burru #define CN93_SDP_R_OUT_CNTS_ISM_START 0x10510 228862cd659SVeerasenareddy Burru #define CN93_SDP_R_IN_CNTS_ISM_START 0x10520 229862cd659SVeerasenareddy Burru 230862cd659SVeerasenareddy Burru #define CN93_SDP_R_MBOX_ISM(ring) \ 231862cd659SVeerasenareddy Burru (CN93_SDP_R_MBOX_ISM_START + ((ring) * CN93_RING_OFFSET)) 232862cd659SVeerasenareddy Burru 233862cd659SVeerasenareddy Burru #define CN93_SDP_R_OUT_CNTS_ISM(ring) \ 234862cd659SVeerasenareddy Burru (CN93_SDP_R_OUT_CNTS_ISM_START + ((ring) * CN93_RING_OFFSET)) 235862cd659SVeerasenareddy Burru 236862cd659SVeerasenareddy Burru #define CN93_SDP_R_IN_CNTS_ISM(ring) \ 237862cd659SVeerasenareddy Burru (CN93_SDP_R_IN_CNTS_ISM_START + ((ring) * CN93_RING_OFFSET)) 238862cd659SVeerasenareddy Burru 239862cd659SVeerasenareddy Burru #define CN93_SDP_EPF_MBOX_RINT_START 0x20100 240862cd659SVeerasenareddy Burru #define CN93_SDP_EPF_MBOX_RINT_W1S_START 0x20120 241862cd659SVeerasenareddy Burru #define CN93_SDP_EPF_MBOX_RINT_ENA_W1C_START 0x20140 242862cd659SVeerasenareddy Burru #define CN93_SDP_EPF_MBOX_RINT_ENA_W1S_START 0x20160 243862cd659SVeerasenareddy Burru 244862cd659SVeerasenareddy Burru #define CN93_SDP_EPF_VFIRE_RINT_START 0x20180 245862cd659SVeerasenareddy Burru #define CN93_SDP_EPF_VFIRE_RINT_W1S_START 0x201A0 246862cd659SVeerasenareddy Burru #define CN93_SDP_EPF_VFIRE_RINT_ENA_W1C_START 0x201C0 247862cd659SVeerasenareddy Burru #define CN93_SDP_EPF_VFIRE_RINT_ENA_W1S_START 0x201E0 248862cd659SVeerasenareddy Burru 249862cd659SVeerasenareddy Burru #define CN93_SDP_EPF_IRERR_RINT 0x20200 250862cd659SVeerasenareddy Burru #define CN93_SDP_EPF_IRERR_RINT_W1S 0x20210 251862cd659SVeerasenareddy Burru #define CN93_SDP_EPF_IRERR_RINT_ENA_W1C 0x20220 252862cd659SVeerasenareddy Burru #define CN93_SDP_EPF_IRERR_RINT_ENA_W1S 0x20230 253862cd659SVeerasenareddy Burru 254862cd659SVeerasenareddy Burru #define CN93_SDP_EPF_VFORE_RINT_START 0x20240 255862cd659SVeerasenareddy Burru #define CN93_SDP_EPF_VFORE_RINT_W1S_START 0x20260 256862cd659SVeerasenareddy Burru #define CN93_SDP_EPF_VFORE_RINT_ENA_W1C_START 0x20280 257862cd659SVeerasenareddy Burru #define CN93_SDP_EPF_VFORE_RINT_ENA_W1S_START 0x202A0 258862cd659SVeerasenareddy Burru 259862cd659SVeerasenareddy Burru #define CN93_SDP_EPF_ORERR_RINT 0x20320 260862cd659SVeerasenareddy Burru #define CN93_SDP_EPF_ORERR_RINT_W1S 0x20330 261862cd659SVeerasenareddy Burru #define CN93_SDP_EPF_ORERR_RINT_ENA_W1C 0x20340 262862cd659SVeerasenareddy Burru #define CN93_SDP_EPF_ORERR_RINT_ENA_W1S 0x20350 263862cd659SVeerasenareddy Burru 264862cd659SVeerasenareddy Burru #define CN93_SDP_EPF_OEI_RINT 0x20360 265862cd659SVeerasenareddy Burru #define CN93_SDP_EPF_OEI_RINT_W1S 0x20370 266862cd659SVeerasenareddy Burru #define CN93_SDP_EPF_OEI_RINT_ENA_W1C 0x20380 267862cd659SVeerasenareddy Burru #define CN93_SDP_EPF_OEI_RINT_ENA_W1S 0x20390 268862cd659SVeerasenareddy Burru 269862cd659SVeerasenareddy Burru #define CN93_SDP_EPF_DMA_RINT 0x20400 270862cd659SVeerasenareddy Burru #define CN93_SDP_EPF_DMA_RINT_W1S 0x20410 271862cd659SVeerasenareddy Burru #define CN93_SDP_EPF_DMA_RINT_ENA_W1C 0x20420 272862cd659SVeerasenareddy Burru #define CN93_SDP_EPF_DMA_RINT_ENA_W1S 0x20430 273862cd659SVeerasenareddy Burru 274862cd659SVeerasenareddy Burru #define CN93_SDP_EPF_DMA_INT_LEVEL_START 0x20440 275862cd659SVeerasenareddy Burru #define CN93_SDP_EPF_DMA_CNT_START 0x20460 276862cd659SVeerasenareddy Burru #define CN93_SDP_EPF_DMA_TIM_START 0x20480 277862cd659SVeerasenareddy Burru 278862cd659SVeerasenareddy Burru #define CN93_SDP_EPF_MISC_RINT 0x204A0 279862cd659SVeerasenareddy Burru #define CN93_SDP_EPF_MISC_RINT_W1S 0x204B0 280862cd659SVeerasenareddy Burru #define CN93_SDP_EPF_MISC_RINT_ENA_W1C 0x204C0 281862cd659SVeerasenareddy Burru #define CN93_SDP_EPF_MISC_RINT_ENA_W1S 0x204D0 282862cd659SVeerasenareddy Burru 283862cd659SVeerasenareddy Burru #define CN93_SDP_EPF_DMA_VF_RINT_START 0x204E0 284862cd659SVeerasenareddy Burru #define CN93_SDP_EPF_DMA_VF_RINT_W1S_START 0x20500 285862cd659SVeerasenareddy Burru #define CN93_SDP_EPF_DMA_VF_RINT_ENA_W1C_START 0x20520 286862cd659SVeerasenareddy Burru #define CN93_SDP_EPF_DMA_VF_RINT_ENA_W1S_START 0x20540 287862cd659SVeerasenareddy Burru 288862cd659SVeerasenareddy Burru #define CN93_SDP_EPF_PP_VF_RINT_START 0x20560 289862cd659SVeerasenareddy Burru #define CN93_SDP_EPF_PP_VF_RINT_W1S_START 0x20580 290862cd659SVeerasenareddy Burru #define CN93_SDP_EPF_PP_VF_RINT_ENA_W1C_START 0x205A0 291862cd659SVeerasenareddy Burru #define CN93_SDP_EPF_PP_VF_RINT_ENA_W1S_START 0x205C0 292862cd659SVeerasenareddy Burru 293862cd659SVeerasenareddy Burru #define CN93_SDP_EPF_MBOX_RINT(index) \ 294862cd659SVeerasenareddy Burru (CN93_SDP_EPF_MBOX_RINT_START + ((index) * CN93_BIT_ARRAY_OFFSET)) 295862cd659SVeerasenareddy Burru #define CN93_SDP_EPF_MBOX_RINT_W1S(index) \ 296862cd659SVeerasenareddy Burru (CN93_SDP_EPF_MBOX_RINT_W1S_START + ((index) * CN93_BIT_ARRAY_OFFSET)) 297862cd659SVeerasenareddy Burru #define CN93_SDP_EPF_MBOX_RINT_ENA_W1C(index) \ 298862cd659SVeerasenareddy Burru (CN93_SDP_EPF_MBOX_RINT_ENA_W1C_START + ((index) * CN93_BIT_ARRAY_OFFSET)) 299862cd659SVeerasenareddy Burru #define CN93_SDP_EPF_MBOX_RINT_ENA_W1S(index) \ 300862cd659SVeerasenareddy Burru (CN93_SDP_EPF_MBOX_RINT_ENA_W1S_START + ((index) * CN93_BIT_ARRAY_OFFSET)) 301862cd659SVeerasenareddy Burru 302862cd659SVeerasenareddy Burru #define CN93_SDP_EPF_VFIRE_RINT(index) \ 303862cd659SVeerasenareddy Burru (CN93_SDP_EPF_VFIRE_RINT_START + ((index) * CN93_BIT_ARRAY_OFFSET)) 304862cd659SVeerasenareddy Burru #define CN93_SDP_EPF_VFIRE_RINT_W1S(index) \ 305862cd659SVeerasenareddy Burru (CN93_SDP_EPF_VFIRE_RINT_W1S_START + ((index) * CN93_BIT_ARRAY_OFFSET)) 306862cd659SVeerasenareddy Burru #define CN93_SDP_EPF_VFIRE_RINT_ENA_W1C(index) \ 307862cd659SVeerasenareddy Burru (CN93_SDP_EPF_VFIRE_RINT_ENA_W1C_START + ((index) * CN93_BIT_ARRAY_OFFSET)) 308862cd659SVeerasenareddy Burru #define CN93_SDP_EPF_VFIRE_RINT_ENA_W1S(index) \ 309862cd659SVeerasenareddy Burru (CN93_SDP_EPF_VFIRE_RINT_ENA_W1S_START + ((index) * CN93_BIT_ARRAY_OFFSET)) 310862cd659SVeerasenareddy Burru 311862cd659SVeerasenareddy Burru #define CN93_SDP_EPF_VFORE_RINT(index) \ 312862cd659SVeerasenareddy Burru (CN93_SDP_EPF_VFORE_RINT_START + ((index) * CN93_BIT_ARRAY_OFFSET)) 313862cd659SVeerasenareddy Burru #define CN93_SDP_EPF_VFORE_RINT_W1S(index) \ 314862cd659SVeerasenareddy Burru (CN93_SDP_EPF_VFORE_RINT_W1S_START + ((index) * CN93_BIT_ARRAY_OFFSET)) 315862cd659SVeerasenareddy Burru #define CN93_SDP_EPF_VFORE_RINT_ENA_W1C(index) \ 316862cd659SVeerasenareddy Burru (CN93_SDP_EPF_VFORE_RINT_ENA_W1C_START + ((index) * CN93_BIT_ARRAY_OFFSET)) 317862cd659SVeerasenareddy Burru #define CN93_SDP_EPF_VFORE_RINT_ENA_W1S(index) \ 318862cd659SVeerasenareddy Burru (CN93_SDP_EPF_VFORE_RINT_ENA_W1S_START + ((index) * CN93_BIT_ARRAY_OFFSET)) 319862cd659SVeerasenareddy Burru 320862cd659SVeerasenareddy Burru #define CN93_SDP_EPF_DMA_VF_RINT(index) \ 321862cd659SVeerasenareddy Burru (CN93_SDP_EPF_DMA_VF_RINT_START + ((index) + CN93_BIT_ARRAY_OFFSET)) 322862cd659SVeerasenareddy Burru #define CN93_SDP_EPF_DMA_VF_RINT_W1S(index) \ 323862cd659SVeerasenareddy Burru (CN93_SDP_EPF_DMA_VF_RINT_W1S_START + ((index) + CN93_BIT_ARRAY_OFFSET)) 324862cd659SVeerasenareddy Burru #define CN93_SDP_EPF_DMA_VF_RINT_ENA_W1C(index) \ 325862cd659SVeerasenareddy Burru (CN93_SDP_EPF_DMA_VF_RINT_ENA_W1C_START + ((index) + CN93_BIT_ARRAY_OFFSET)) 326862cd659SVeerasenareddy Burru #define CN93_SDP_EPF_DMA_VF_RINT_ENA_W1S(index) \ 327862cd659SVeerasenareddy Burru (CN93_SDP_EPF_DMA_VF_RINT_ENA_W1S_START + ((index) + CN93_BIT_ARRAY_OFFSET)) 328862cd659SVeerasenareddy Burru 329862cd659SVeerasenareddy Burru #define CN93_SDP_EPF_PP_VF_RINT(index) \ 330862cd659SVeerasenareddy Burru (CN93_SDP_EPF_PP_VF_RINT_START + ((index) + CN93_BIT_ARRAY_OFFSET)) 331862cd659SVeerasenareddy Burru #define CN93_SDP_EPF_PP_VF_RINT_W1S(index) \ 332862cd659SVeerasenareddy Burru (CN93_SDP_EPF_PP_VF_RINT_W1S_START + ((index) + CN93_BIT_ARRAY_OFFSET)) 333862cd659SVeerasenareddy Burru #define CN93_SDP_EPF_PP_VF_RINT_ENA_W1C(index) \ 334862cd659SVeerasenareddy Burru (CN93_SDP_EPF_PP_VF_RINT_ENA_W1C_START + ((index) + CN93_BIT_ARRAY_OFFSET)) 335862cd659SVeerasenareddy Burru #define CN93_SDP_EPF_PP_VF_RINT_ENA_W1S(index) \ 336862cd659SVeerasenareddy Burru (CN93_SDP_EPF_PP_VF_RINT_ENA_W1S_START + ((index) + CN93_BIT_ARRAY_OFFSET)) 337862cd659SVeerasenareddy Burru 338862cd659SVeerasenareddy Burru /*------------------ Interrupt Masks ----------------*/ 339862cd659SVeerasenareddy Burru #define CN93_INTR_R_SEND_ISM BIT_ULL(63) 340862cd659SVeerasenareddy Burru #define CN93_INTR_R_OUT_INT BIT_ULL(62) 341862cd659SVeerasenareddy Burru #define CN93_INTR_R_IN_INT BIT_ULL(61) 342862cd659SVeerasenareddy Burru #define CN93_INTR_R_MBOX_INT BIT_ULL(60) 343862cd659SVeerasenareddy Burru #define CN93_INTR_R_RESEND BIT_ULL(59) 344862cd659SVeerasenareddy Burru #define CN93_INTR_R_CLR_TIM BIT_ULL(58) 345862cd659SVeerasenareddy Burru 346862cd659SVeerasenareddy Burru /* ####################### Ring Mapping Registers ################################## */ 347862cd659SVeerasenareddy Burru #define CN93_SDP_EPVF_RING_START 0x26000 348862cd659SVeerasenareddy Burru #define CN93_SDP_IN_RING_TB_MAP_START 0x28000 349862cd659SVeerasenareddy Burru #define CN93_SDP_IN_RATE_LIMIT_START 0x2A000 350862cd659SVeerasenareddy Burru #define CN93_SDP_MAC_PF_RING_CTL_START 0x2C000 351862cd659SVeerasenareddy Burru 352862cd659SVeerasenareddy Burru #define CN93_SDP_EPVF_RING(ring) \ 353862cd659SVeerasenareddy Burru (CN93_SDP_EPVF_RING_START + ((ring) * CN93_EPVF_RING_OFFSET)) 354862cd659SVeerasenareddy Burru #define CN93_SDP_IN_RING_TB_MAP(ring) \ 355862cd659SVeerasenareddy Burru (CN93_SDP_N_RING_TB_MAP_START + ((ring) * CN93_EPVF_RING_OFFSET)) 356862cd659SVeerasenareddy Burru #define CN93_SDP_IN_RATE_LIMIT(ring) \ 357862cd659SVeerasenareddy Burru (CN93_SDP_IN_RATE_LIMIT_START + ((ring) * CN93_EPVF_RING_OFFSET)) 358862cd659SVeerasenareddy Burru #define CN93_SDP_MAC_PF_RING_CTL(mac) \ 359862cd659SVeerasenareddy Burru (CN93_SDP_MAC_PF_RING_CTL_START + ((mac) * CN93_MAC_OFFSET)) 360862cd659SVeerasenareddy Burru 361862cd659SVeerasenareddy Burru #define CN93_SDP_MAC_PF_RING_CTL_NPFS(val) ((val) & 0xF) 362862cd659SVeerasenareddy Burru #define CN93_SDP_MAC_PF_RING_CTL_SRN(val) (((val) >> 8) & 0xFF) 363862cd659SVeerasenareddy Burru #define CN93_SDP_MAC_PF_RING_CTL_RPPF(val) (((val) >> 16) & 0x3F) 364862cd659SVeerasenareddy Burru 365862cd659SVeerasenareddy Burru /* Number of non-queue interrupts in CN93xx */ 366862cd659SVeerasenareddy Burru #define CN93_NUM_NON_IOQ_INTR 16 36724d43332SVeerasenareddy Burru 36824d43332SVeerasenareddy Burru /* bit 0 for control mbox interrupt */ 36924d43332SVeerasenareddy Burru #define CN93_SDP_EPF_OEI_RINT_DATA_BIT_MBOX BIT_ULL(0) 370*5cb96c29SVeerasenareddy Burru /* bit 1 for firmware heartbeat interrupt */ 371*5cb96c29SVeerasenareddy Burru #define CN93_SDP_EPF_OEI_RINT_DATA_BIT_HBEAT BIT_ULL(1) 37224d43332SVeerasenareddy Burru 373862cd659SVeerasenareddy Burru #endif /* _OCTEP_REGS_CN9K_PF_H_ */ 374