1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Marvell Octeon EP (EndPoint) Ethernet Driver 3 * 4 * Copyright (C) 2020 Marvell. 5 * 6 */ 7 8 #ifndef _OCTEP_MAIN_H_ 9 #define _OCTEP_MAIN_H_ 10 11 #include "octep_tx.h" 12 #include "octep_rx.h" 13 #include "octep_ctrl_mbox.h" 14 15 #define OCTEP_DRV_NAME "octeon_ep" 16 #define OCTEP_DRV_STRING "Marvell Octeon EndPoint NIC Driver" 17 18 #define OCTEP_PCIID_CN93_PF 0xB200177d 19 #define OCTEP_PCIID_CN93_VF 0xB203177d 20 21 #define OCTEP_PCI_DEVICE_ID_CN93_PF 0xB200 22 #define OCTEP_PCI_DEVICE_ID_CN93_VF 0xB203 23 24 #define OCTEP_PCI_DEVICE_ID_CNF95N_PF 0xB400 //95N PF 25 26 #define OCTEP_MAX_QUEUES 63 27 #define OCTEP_MAX_IQ OCTEP_MAX_QUEUES 28 #define OCTEP_MAX_OQ OCTEP_MAX_QUEUES 29 #define OCTEP_MAX_VF 64 30 31 #define OCTEP_MAX_MSIX_VECTORS OCTEP_MAX_OQ 32 33 /* Flags to disable and enable Interrupts */ 34 #define OCTEP_INPUT_INTR (1) 35 #define OCTEP_OUTPUT_INTR (2) 36 #define OCTEP_MBOX_INTR (4) 37 #define OCTEP_ALL_INTR 0xff 38 39 #define OCTEP_IQ_INTR_RESEND_BIT 59 40 #define OCTEP_OQ_INTR_RESEND_BIT 59 41 42 #define OCTEP_MMIO_REGIONS 3 43 /* PCI address space mapping information. 44 * Each of the 3 address spaces given by BAR0, BAR2 and BAR4 of 45 * Octeon gets mapped to different physical address spaces in 46 * the kernel. 47 */ 48 struct octep_mmio { 49 /* The physical address to which the PCI address space is mapped. */ 50 u8 __iomem *hw_addr; 51 52 /* Flag indicating the mapping was successful. */ 53 int mapped; 54 }; 55 56 struct octep_pci_win_regs { 57 u8 __iomem *pci_win_wr_addr; 58 u8 __iomem *pci_win_rd_addr; 59 u8 __iomem *pci_win_wr_data; 60 u8 __iomem *pci_win_rd_data; 61 }; 62 63 struct octep_hw_ops { 64 void (*setup_iq_regs)(struct octep_device *oct, int q); 65 void (*setup_oq_regs)(struct octep_device *oct, int q); 66 void (*setup_mbox_regs)(struct octep_device *oct, int mbox); 67 68 irqreturn_t (*non_ioq_intr_handler)(void *ioq_vector); 69 irqreturn_t (*ioq_intr_handler)(void *ioq_vector); 70 int (*soft_reset)(struct octep_device *oct); 71 void (*reinit_regs)(struct octep_device *oct); 72 u32 (*update_iq_read_idx)(struct octep_iq *iq); 73 74 void (*enable_interrupts)(struct octep_device *oct); 75 void (*disable_interrupts)(struct octep_device *oct); 76 77 void (*enable_io_queues)(struct octep_device *oct); 78 void (*disable_io_queues)(struct octep_device *oct); 79 void (*enable_iq)(struct octep_device *oct, int q); 80 void (*disable_iq)(struct octep_device *oct, int q); 81 void (*enable_oq)(struct octep_device *oct, int q); 82 void (*disable_oq)(struct octep_device *oct, int q); 83 void (*reset_io_queues)(struct octep_device *oct); 84 void (*dump_registers)(struct octep_device *oct); 85 }; 86 87 /* Octeon mailbox data */ 88 struct octep_mbox_data { 89 u32 cmd; 90 u32 total_len; 91 u32 recv_len; 92 u32 rsvd; 93 u64 *data; 94 }; 95 96 /* Octeon device mailbox */ 97 struct octep_mbox { 98 /* A spinlock to protect access to this q_mbox. */ 99 spinlock_t lock; 100 101 u32 q_no; 102 u32 state; 103 104 /* SLI_MAC_PF_MBOX_INT for PF, SLI_PKT_MBOX_INT for VF. */ 105 u8 __iomem *mbox_int_reg; 106 107 /* SLI_PKT_PF_VF_MBOX_SIG(0) for PF, 108 * SLI_PKT_PF_VF_MBOX_SIG(1) for VF. 109 */ 110 u8 __iomem *mbox_write_reg; 111 112 /* SLI_PKT_PF_VF_MBOX_SIG(1) for PF, 113 * SLI_PKT_PF_VF_MBOX_SIG(0) for VF. 114 */ 115 u8 __iomem *mbox_read_reg; 116 117 struct octep_mbox_data mbox_data; 118 }; 119 120 /* Tx/Rx queue vector per interrupt. */ 121 struct octep_ioq_vector { 122 char name[OCTEP_MSIX_NAME_SIZE]; 123 struct napi_struct napi; 124 struct octep_device *octep_dev; 125 struct octep_iq *iq; 126 struct octep_oq *oq; 127 cpumask_t affinity_mask; 128 }; 129 130 /* Octeon hardware/firmware offload capability flags. */ 131 #define OCTEP_CAP_TX_CHECKSUM BIT(0) 132 #define OCTEP_CAP_RX_CHECKSUM BIT(1) 133 #define OCTEP_CAP_TSO BIT(2) 134 135 /* Link modes */ 136 enum octep_link_mode_bit_indices { 137 OCTEP_LINK_MODE_10GBASE_T = 0, 138 OCTEP_LINK_MODE_10GBASE_R, 139 OCTEP_LINK_MODE_10GBASE_CR, 140 OCTEP_LINK_MODE_10GBASE_KR, 141 OCTEP_LINK_MODE_10GBASE_LR, 142 OCTEP_LINK_MODE_10GBASE_SR, 143 OCTEP_LINK_MODE_25GBASE_CR, 144 OCTEP_LINK_MODE_25GBASE_KR, 145 OCTEP_LINK_MODE_25GBASE_SR, 146 OCTEP_LINK_MODE_40GBASE_CR4, 147 OCTEP_LINK_MODE_40GBASE_KR4, 148 OCTEP_LINK_MODE_40GBASE_LR4, 149 OCTEP_LINK_MODE_40GBASE_SR4, 150 OCTEP_LINK_MODE_50GBASE_CR2, 151 OCTEP_LINK_MODE_50GBASE_KR2, 152 OCTEP_LINK_MODE_50GBASE_SR2, 153 OCTEP_LINK_MODE_50GBASE_CR, 154 OCTEP_LINK_MODE_50GBASE_KR, 155 OCTEP_LINK_MODE_50GBASE_LR, 156 OCTEP_LINK_MODE_50GBASE_SR, 157 OCTEP_LINK_MODE_100GBASE_CR4, 158 OCTEP_LINK_MODE_100GBASE_KR4, 159 OCTEP_LINK_MODE_100GBASE_LR4, 160 OCTEP_LINK_MODE_100GBASE_SR4, 161 OCTEP_LINK_MODE_NBITS 162 }; 163 164 /* Hardware interface link state information. */ 165 struct octep_iface_link_info { 166 /* Bitmap of Supported link speeds/modes. */ 167 u64 supported_modes; 168 169 /* Bitmap of Advertised link speeds/modes. */ 170 u64 advertised_modes; 171 172 /* Negotiated link speed in Mbps. */ 173 u32 speed; 174 175 /* MTU */ 176 u16 mtu; 177 178 /* Autonegotation state. */ 179 #define OCTEP_LINK_MODE_AUTONEG_SUPPORTED BIT(0) 180 #define OCTEP_LINK_MODE_AUTONEG_ADVERTISED BIT(1) 181 u8 autoneg; 182 183 /* Pause frames setting. */ 184 #define OCTEP_LINK_MODE_PAUSE_SUPPORTED BIT(0) 185 #define OCTEP_LINK_MODE_PAUSE_ADVERTISED BIT(1) 186 u8 pause; 187 188 /* Admin state of the link (ifconfig <iface> up/down */ 189 u8 admin_up; 190 191 /* Operational state of the link: physical link is up down */ 192 u8 oper_up; 193 }; 194 195 /* The Octeon device specific private data structure. 196 * Each Octeon device has this structure to represent all its components. 197 */ 198 struct octep_device { 199 struct octep_config *conf; 200 201 /* Octeon Chip type. */ 202 u16 chip_id; 203 u16 rev_id; 204 205 /* Device capabilities enabled */ 206 u64 caps_enabled; 207 /* Device capabilities supported */ 208 u64 caps_supported; 209 210 /* Pointer to basic Linux device */ 211 struct device *dev; 212 /* Linux PCI device pointer */ 213 struct pci_dev *pdev; 214 /* Netdev corresponding to the Octeon device */ 215 struct net_device *netdev; 216 217 /* memory mapped io range */ 218 struct octep_mmio mmio[OCTEP_MMIO_REGIONS]; 219 220 /* MAC address */ 221 u8 mac_addr[ETH_ALEN]; 222 223 /* Tx queues (IQ: Instruction Queue) */ 224 u16 num_iqs; 225 /* pkind value to be used in every Tx hardware descriptor */ 226 u8 pkind; 227 /* Pointers to Octeon Tx queues */ 228 struct octep_iq *iq[OCTEP_MAX_IQ]; 229 230 /* Rx queues (OQ: Output Queue) */ 231 u16 num_oqs; 232 /* Pointers to Octeon Rx queues */ 233 struct octep_oq *oq[OCTEP_MAX_OQ]; 234 235 /* Hardware port number of the PCIe interface */ 236 u16 pcie_port; 237 238 /* PCI Window registers to access some hardware CSRs */ 239 struct octep_pci_win_regs pci_win_regs; 240 /* Hardware operations */ 241 struct octep_hw_ops hw_ops; 242 243 /* IRQ info */ 244 u16 num_irqs; 245 u16 num_non_ioq_irqs; 246 char *non_ioq_irq_names; 247 struct msix_entry *msix_entries; 248 /* IOq information of it's corresponding MSI-X interrupt. */ 249 struct octep_ioq_vector *ioq_vector[OCTEP_MAX_QUEUES]; 250 251 /* Hardware Interface Tx statistics */ 252 struct octep_iface_tx_stats iface_tx_stats; 253 /* Hardware Interface Rx statistics */ 254 struct octep_iface_rx_stats iface_rx_stats; 255 256 /* Hardware Interface Link info like supported modes, aneg support */ 257 struct octep_iface_link_info link_info; 258 259 /* Mailbox to talk to VFs */ 260 struct octep_mbox *mbox[OCTEP_MAX_VF]; 261 262 /* Work entry to handle Tx timeout */ 263 struct work_struct tx_timeout_task; 264 265 /* control mbox over pf */ 266 struct octep_ctrl_mbox ctrl_mbox; 267 268 /* offset for iface stats */ 269 u32 ctrl_mbox_ifstats_offset; 270 271 /* Work entry to handle ctrl mbox interrupt */ 272 struct work_struct ctrl_mbox_task; 273 274 }; 275 276 static inline u16 OCTEP_MAJOR_REV(struct octep_device *oct) 277 { 278 u16 rev = (oct->rev_id & 0xC) >> 2; 279 280 return (rev == 0) ? 1 : rev; 281 } 282 283 static inline u16 OCTEP_MINOR_REV(struct octep_device *oct) 284 { 285 return (oct->rev_id & 0x3); 286 } 287 288 /* Octeon CSR read/write access APIs */ 289 #define octep_write_csr(octep_dev, reg_off, value) \ 290 writel(value, (octep_dev)->mmio[0].hw_addr + (reg_off)) 291 292 #define octep_write_csr64(octep_dev, reg_off, val64) \ 293 writeq(val64, (octep_dev)->mmio[0].hw_addr + (reg_off)) 294 295 #define octep_read_csr(octep_dev, reg_off) \ 296 readl((octep_dev)->mmio[0].hw_addr + (reg_off)) 297 298 #define octep_read_csr64(octep_dev, reg_off) \ 299 readq((octep_dev)->mmio[0].hw_addr + (reg_off)) 300 301 /* Read windowed register. 302 * @param oct - pointer to the Octeon device. 303 * @param addr - Address of the register to read. 304 * 305 * This routine is called to read from the indirectly accessed 306 * Octeon registers that are visible through a PCI BAR0 mapped window 307 * register. 308 * @return - 64 bit value read from the register. 309 */ 310 static inline u64 311 OCTEP_PCI_WIN_READ(struct octep_device *oct, u64 addr) 312 { 313 u64 val64; 314 315 addr |= 1ull << 53; /* read 8 bytes */ 316 writeq(addr, oct->pci_win_regs.pci_win_rd_addr); 317 val64 = readq(oct->pci_win_regs.pci_win_rd_data); 318 319 dev_dbg(&oct->pdev->dev, 320 "%s: reg: 0x%016llx val: 0x%016llx\n", __func__, addr, val64); 321 322 return val64; 323 } 324 325 /* Write windowed register. 326 * @param oct - pointer to the Octeon device. 327 * @param addr - Address of the register to write 328 * @param val - Value to write 329 * 330 * This routine is called to write to the indirectly accessed 331 * Octeon registers that are visible through a PCI BAR0 mapped window 332 * register. 333 * @return Nothing. 334 */ 335 static inline void 336 OCTEP_PCI_WIN_WRITE(struct octep_device *oct, u64 addr, u64 val) 337 { 338 writeq(addr, oct->pci_win_regs.pci_win_wr_addr); 339 writeq(val, oct->pci_win_regs.pci_win_wr_data); 340 341 dev_dbg(&oct->pdev->dev, 342 "%s: reg: 0x%016llx val: 0x%016llx\n", __func__, addr, val); 343 } 344 345 extern struct workqueue_struct *octep_wq; 346 347 int octep_device_setup(struct octep_device *oct); 348 int octep_setup_iqs(struct octep_device *oct); 349 void octep_free_iqs(struct octep_device *oct); 350 void octep_clean_iqs(struct octep_device *oct); 351 int octep_setup_oqs(struct octep_device *oct); 352 void octep_free_oqs(struct octep_device *oct); 353 void octep_oq_dbell_init(struct octep_device *oct); 354 void octep_device_setup_cn93_pf(struct octep_device *oct); 355 int octep_iq_process_completions(struct octep_iq *iq, u16 budget); 356 int octep_oq_process_rx(struct octep_oq *oq, int budget); 357 void octep_set_ethtool_ops(struct net_device *netdev); 358 359 #endif /* _OCTEP_MAIN_H_ */ 360