1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Marvell Octeon EP (EndPoint) Ethernet Driver
3  *
4  * Copyright (C) 2020 Marvell.
5  *
6  */
7  #ifndef __OCTEP_CTRL_MBOX_H__
8 #define __OCTEP_CTRL_MBOX_H__
9 
10 /*              barmem structure
11  * |===========================================|
12  * |Info (16 + 120 + 120 = 256 bytes)          |
13  * |-------------------------------------------|
14  * |magic number (8 bytes)                     |
15  * |bar memory size (4 bytes)                  |
16  * |reserved (4 bytes)                         |
17  * |-------------------------------------------|
18  * |host version (8 bytes)                     |
19  * |host status (8 bytes)                      |
20  * |host reserved (104 bytes)                  |
21  * |-------------------------------------------|
22  * |fw version (8 bytes)                       |
23  * |fw status (8 bytes)                        |
24  * |fw reserved (104 bytes)                    |
25  * |===========================================|
26  * |Host to Fw Queue info (16 bytes)           |
27  * |-------------------------------------------|
28  * |producer index (4 bytes)                   |
29  * |consumer index (4 bytes)                   |
30  * |max element size (4 bytes)                 |
31  * |reserved (4 bytes)                         |
32  * |===========================================|
33  * |Fw to Host Queue info (16 bytes)           |
34  * |-------------------------------------------|
35  * |producer index (4 bytes)                   |
36  * |consumer index (4 bytes)                   |
37  * |max element size (4 bytes)                 |
38  * |reserved (4 bytes)                         |
39  * |===========================================|
40  * |Host to Fw Queue ((total size-288/2) bytes)|
41  * |-------------------------------------------|
42  * |                                           |
43  * |===========================================|
44  * |===========================================|
45  * |Fw to Host Queue ((total size-288/2) bytes)|
46  * |-------------------------------------------|
47  * |                                           |
48  * |===========================================|
49  */
50 
51 #define OCTEP_CTRL_MBOX_MAGIC_NUMBER			0xdeaddeadbeefbeefull
52 
53 /* Valid request message */
54 #define OCTEP_CTRL_MBOX_MSG_HDR_FLAG_REQ		BIT(0)
55 /* Valid response message */
56 #define OCTEP_CTRL_MBOX_MSG_HDR_FLAG_RESP		BIT(1)
57 /* Valid notification, no response required */
58 #define OCTEP_CTRL_MBOX_MSG_HDR_FLAG_NOTIFY		BIT(2)
59 /* Valid custom message */
60 #define OCTEP_CTRL_MBOX_MSG_HDR_FLAG_CUSTOM		BIT(3)
61 
62 #define OCTEP_CTRL_MBOX_MSG_DESC_MAX			4
63 
64 enum octep_ctrl_mbox_status {
65 	OCTEP_CTRL_MBOX_STATUS_INVALID = 0,
66 	OCTEP_CTRL_MBOX_STATUS_INIT,
67 	OCTEP_CTRL_MBOX_STATUS_READY,
68 	OCTEP_CTRL_MBOX_STATUS_UNINIT
69 };
70 
71 /* mbox message */
72 union octep_ctrl_mbox_msg_hdr {
73 	u64 words[2];
74 	struct {
75 		/* must be 0 */
76 		u16 reserved1:15;
77 		/* vf_idx is valid if 1 */
78 		u16 is_vf:1;
79 		/* sender vf index 0-(n-1), 0 if (is_vf==0) */
80 		u16 vf_idx;
81 		/* total size of message excluding header */
82 		u32 sz;
83 		/* OCTEP_CTRL_MBOX_MSG_HDR_FLAG_* */
84 		u32 flags;
85 		/* identifier to match responses */
86 		u16 msg_id;
87 		u16 reserved2;
88 	} s;
89 };
90 
91 /* mbox message buffer */
92 struct octep_ctrl_mbox_msg_buf {
93 	u32 reserved1;
94 	u16 reserved2;
95 	/* size of buffer */
96 	u16 sz;
97 	/* pointer to message buffer */
98 	void *msg;
99 };
100 
101 /* mbox message */
102 struct octep_ctrl_mbox_msg {
103 	/* mbox transaction header */
104 	union octep_ctrl_mbox_msg_hdr hdr;
105 	/* number of sg buffer's */
106 	int sg_num;
107 	/* message buffer's */
108 	struct octep_ctrl_mbox_msg_buf sg_list[OCTEP_CTRL_MBOX_MSG_DESC_MAX];
109 };
110 
111 /* Mbox queue */
112 struct octep_ctrl_mbox_q {
113 	/* size of queue buffer */
114 	u32 sz;
115 	/* producer address in bar mem */
116 	u8 __iomem *hw_prod;
117 	/* consumer address in bar mem */
118 	u8 __iomem *hw_cons;
119 	/* q base address in bar mem */
120 	u8 __iomem *hw_q;
121 };
122 
123 struct octep_ctrl_mbox {
124 	/* size of bar memory */
125 	u32 barmem_sz;
126 	/* pointer to BAR memory */
127 	u8 __iomem *barmem;
128 	/* host-to-fw queue */
129 	struct octep_ctrl_mbox_q h2fq;
130 	/* fw-to-host queue */
131 	struct octep_ctrl_mbox_q f2hq;
132 	/* lock for h2fq */
133 	struct mutex h2fq_lock;
134 	/* lock for f2hq */
135 	struct mutex f2hq_lock;
136 };
137 
138 /* Initialize control mbox.
139  *
140  * @param mbox: non-null pointer to struct octep_ctrl_mbox.
141  *
142  * return value: 0 on success, -errno on failure.
143  */
144 int octep_ctrl_mbox_init(struct octep_ctrl_mbox *mbox);
145 
146 /* Send mbox message.
147  *
148  * @param mbox: non-null pointer to struct octep_ctrl_mbox.
149  * @param msg:  non-null pointer to struct octep_ctrl_mbox_msg.
150  *              Caller should fill msg.sz and msg.desc.sz for each message.
151  *
152  * return value: 0 on success, -errno on failure.
153  */
154 int octep_ctrl_mbox_send(struct octep_ctrl_mbox *mbox, struct octep_ctrl_mbox_msg *msg);
155 
156 /* Retrieve mbox message.
157  *
158  * @param mbox: non-null pointer to struct octep_ctrl_mbox.
159  * @param msg:  non-null pointer to struct octep_ctrl_mbox_msg.
160  *              Caller should fill msg.sz and msg.desc.sz for each message.
161  *
162  * return value: 0 on success, -errno on failure.
163  */
164 int octep_ctrl_mbox_recv(struct octep_ctrl_mbox *mbox, struct octep_ctrl_mbox_msg *msg);
165 
166 /* Uninitialize control mbox.
167  *
168  * @param mbox: non-null pointer to struct octep_ctrl_mbox.
169  *
170  * return value: 0 on success, -errno on failure.
171  */
172 int octep_ctrl_mbox_uninit(struct octep_ctrl_mbox *mbox);
173 
174 #endif /* __OCTEP_CTRL_MBOX_H__ */
175