1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Marvell Octeon EP (EndPoint) Ethernet Driver
3  *
4  * Copyright (C) 2020 Marvell.
5  *
6  */
7 
8 #ifndef _OCTEP_CONFIG_H_
9 #define _OCTEP_CONFIG_H_
10 
11 /* Tx instruction types by length */
12 #define OCTEP_32BYTE_INSTR  32
13 #define OCTEP_64BYTE_INSTR  64
14 
15 /* Tx Queue: maximum descriptors per ring */
16 #define OCTEP_IQ_MAX_DESCRIPTORS    1024
17 /* Minimum input (Tx) requests to be enqueued to ring doorbell */
18 #define OCTEP_DB_MIN                1
19 /* Packet threshold for Tx queue interrupt */
20 #define OCTEP_IQ_INTR_THRESHOLD     0x0
21 
22 /* Rx Queue: maximum descriptors per ring */
23 #define OCTEP_OQ_MAX_DESCRIPTORS   1024
24 
25 /* Rx buffer size: Use page size buffers.
26  * Build skb from allocated page buffer once the packet is received.
27  * When a gathered packet is received, make head page as skb head and
28  * page buffers in consecutive Rx descriptors as fragments.
29  */
30 #define OCTEP_OQ_BUF_SIZE          (SKB_WITH_OVERHEAD(PAGE_SIZE))
31 #define OCTEP_OQ_PKTS_PER_INTR     128
32 #define OCTEP_OQ_REFILL_THRESHOLD  (OCTEP_OQ_MAX_DESCRIPTORS / 4)
33 
34 #define OCTEP_OQ_INTR_PKT_THRESHOLD   1
35 #define OCTEP_OQ_INTR_TIME_THRESHOLD  10
36 
37 #define OCTEP_MSIX_NAME_SIZE      (IFNAMSIZ + 32)
38 
39 /* Tx Queue wake threshold
40  * wakeup a stopped Tx queue if minimum 2 descriptors are available.
41  * Even a skb with fragments consume only one Tx queue descriptor entry.
42  */
43 #define OCTEP_WAKE_QUEUE_THRESHOLD 2
44 
45 /* Minimum MTU supported by Octeon network interface */
46 #define OCTEP_MIN_MTU        ETH_MIN_MTU
47 /* Maximum MTU supported by Octeon interface*/
48 #define OCTEP_MAX_MTU        (10000 - (ETH_HLEN + ETH_FCS_LEN))
49 /* Default MTU */
50 #define OCTEP_DEFAULT_MTU    1500
51 
52 /* Macros to get octeon config params */
53 #define CFG_GET_IQ_CFG(cfg)             ((cfg)->iq)
54 #define CFG_GET_IQ_NUM_DESC(cfg)        ((cfg)->iq.num_descs)
55 #define CFG_GET_IQ_INSTR_TYPE(cfg)      ((cfg)->iq.instr_type)
56 #define CFG_GET_IQ_PKIND(cfg)           ((cfg)->iq.pkind)
57 #define CFG_GET_IQ_INSTR_SIZE(cfg)      (64)
58 #define CFG_GET_IQ_DB_MIN(cfg)          ((cfg)->iq.db_min)
59 #define CFG_GET_IQ_INTR_THRESHOLD(cfg)  ((cfg)->iq.intr_threshold)
60 
61 #define CFG_GET_OQ_NUM_DESC(cfg)          ((cfg)->oq.num_descs)
62 #define CFG_GET_OQ_BUF_SIZE(cfg)          ((cfg)->oq.buf_size)
63 #define CFG_GET_OQ_REFILL_THRESHOLD(cfg)  ((cfg)->oq.refill_threshold)
64 #define CFG_GET_OQ_INTR_PKT(cfg)          ((cfg)->oq.oq_intr_pkt)
65 #define CFG_GET_OQ_INTR_TIME(cfg)         ((cfg)->oq.oq_intr_time)
66 
67 #define CFG_GET_PORTS_MAX_IO_RINGS(cfg)    ((cfg)->pf_ring_cfg.max_io_rings)
68 #define CFG_GET_PORTS_ACTIVE_IO_RINGS(cfg) ((cfg)->pf_ring_cfg.active_io_rings)
69 #define CFG_GET_PORTS_PF_SRN(cfg)          ((cfg)->pf_ring_cfg.srn)
70 
71 #define CFG_GET_DPI_PKIND(cfg)            ((cfg)->core_cfg.dpi_pkind)
72 #define CFG_GET_CORE_TICS_PER_US(cfg)     ((cfg)->core_cfg.core_tics_per_us)
73 #define CFG_GET_COPROC_TICS_PER_US(cfg)   ((cfg)->core_cfg.coproc_tics_per_us)
74 
75 #define CFG_GET_MAX_VFS(cfg)        ((cfg)->sriov_cfg.max_vfs)
76 #define CFG_GET_ACTIVE_VFS(cfg)     ((cfg)->sriov_cfg.active_vfs)
77 #define CFG_GET_MAX_RPVF(cfg)       ((cfg)->sriov_cfg.max_rings_per_vf)
78 #define CFG_GET_ACTIVE_RPVF(cfg)    ((cfg)->sriov_cfg.active_rings_per_vf)
79 #define CFG_GET_VF_SRN(cfg)         ((cfg)->sriov_cfg.vf_srn)
80 
81 #define CFG_GET_IOQ_MSIX(cfg)            ((cfg)->msix_cfg.ioq_msix)
82 #define CFG_GET_NON_IOQ_MSIX(cfg)        ((cfg)->msix_cfg.non_ioq_msix)
83 #define CFG_GET_NON_IOQ_MSIX_NAMES(cfg)  ((cfg)->msix_cfg.non_ioq_msix_names)
84 
85 #define CFG_GET_CTRL_MBOX_MEM_ADDR(cfg)  ((cfg)->ctrl_mbox_cfg.barmem_addr)
86 
87 /* Hardware Tx Queue configuration. */
88 struct octep_iq_config {
89 	/* Size of the Input queue (number of commands) */
90 	u16 num_descs;
91 
92 	/* Command size - 32 or 64 bytes */
93 	u16 instr_type;
94 
95 	/* pkind for packets sent to Octeon */
96 	u16 pkind;
97 
98 	/* Minimum number of commands pending to be posted to Octeon before driver
99 	 * hits the Input queue doorbell.
100 	 */
101 	u16 db_min;
102 
103 	/* Trigger the IQ interrupt when processed cmd count reaches
104 	 * this level.
105 	 */
106 	u32 intr_threshold;
107 };
108 
109 /* Hardware Rx Queue configuration. */
110 struct octep_oq_config {
111 	/* Size of Output queue (number of descriptors) */
112 	u16 num_descs;
113 
114 	/* Size of buffer in this Output queue. */
115 	u16 buf_size;
116 
117 	/* The number of buffers that were consumed during packet processing
118 	 * by the driver on this Output queue before the driver attempts to
119 	 * replenish the descriptor ring with new buffers.
120 	 */
121 	u16 refill_threshold;
122 
123 	/* Interrupt Coalescing (Packet Count). Octeon will interrupt the host
124 	 * only if it sent as many packets as specified by this field.
125 	 * The driver usually does not use packet count interrupt coalescing.
126 	 */
127 	u32 oq_intr_pkt;
128 
129 	/* Interrupt Coalescing (Time Interval). Octeon will interrupt the host
130 	 * if at least one packet was sent in the time interval specified by
131 	 * this field. The driver uses time interval interrupt coalescing by
132 	 * default. The time is specified in microseconds.
133 	 */
134 	u32 oq_intr_time;
135 };
136 
137 /* Tx/Rx configuration */
138 struct octep_pf_ring_config {
139 	/* Max number of IOQs */
140 	u16 max_io_rings;
141 
142 	/* Number of active IOQs */
143 	u16 active_io_rings;
144 
145 	/* Starting IOQ number: this changes based on which PEM is used */
146 	u16 srn;
147 };
148 
149 /* Octeon Hardware SRIOV config */
150 struct octep_sriov_config {
151 	/* Max number of VF devices supported */
152 	u16 max_vfs;
153 
154 	/* Number of VF devices enabled   */
155 	u16 active_vfs;
156 
157 	/* Max number of rings assigned to VF  */
158 	u8 max_rings_per_vf;
159 
160 	/* Number of rings enabled per VF */
161 	u8 active_rings_per_vf;
162 
163 	/* starting ring number of VF's: ring-0 of VF-0 of the PF */
164 	u16 vf_srn;
165 };
166 
167 /* Octeon MSI-x config. */
168 struct octep_msix_config {
169 	/* Number of IOQ interrupts */
170 	u16 ioq_msix;
171 
172 	/* Number of Non IOQ interrupts */
173 	u16 non_ioq_msix;
174 
175 	/* Names of Non IOQ interrupts */
176 	char **non_ioq_msix_names;
177 };
178 
179 struct octep_ctrl_mbox_config {
180 	/* Barmem address for control mbox */
181 	void __iomem *barmem_addr;
182 };
183 
184 /* Data Structure to hold configuration limits and active config */
185 struct octep_config {
186 	/* Input Queue attributes. */
187 	struct octep_iq_config iq;
188 
189 	/* Output Queue attributes. */
190 	struct octep_oq_config oq;
191 
192 	/* NIC Port Configuration */
193 	struct octep_pf_ring_config pf_ring_cfg;
194 
195 	/* SRIOV configuration of the PF */
196 	struct octep_sriov_config sriov_cfg;
197 
198 	/* MSI-X interrupt config */
199 	struct octep_msix_config msix_cfg;
200 
201 	/* ctrl mbox config */
202 	struct octep_ctrl_mbox_config ctrl_mbox_cfg;
203 };
204 #endif /* _OCTEP_CONFIG_H_ */
205