1 /* 2 * Header Parser definitions for Marvell PPv2 Network Controller 3 * 4 * Copyright (C) 2014 Marvell 5 * 6 * Marcin Wojtas <mw@semihalf.com> 7 * 8 * This file is licensed under the terms of the GNU General Public 9 * License version 2. This program is licensed "as is" without any 10 * warranty of any kind, whether express or implied. 11 */ 12 #include <linux/kernel.h> 13 #include <linux/netdevice.h> 14 15 #include "mvpp2.h" 16 17 #ifndef _MVPP2_PRS_H_ 18 #define _MVPP2_PRS_H_ 19 20 /* Parser constants */ 21 #define MVPP2_PRS_TCAM_SRAM_SIZE 256 22 #define MVPP2_PRS_TCAM_WORDS 6 23 #define MVPP2_PRS_SRAM_WORDS 4 24 #define MVPP2_PRS_FLOW_ID_SIZE 64 25 #define MVPP2_PRS_FLOW_ID_MASK 0x3f 26 #define MVPP2_PRS_TCAM_ENTRY_INVALID 1 27 #define MVPP2_PRS_TCAM_DSA_TAGGED_BIT BIT(5) 28 #define MVPP2_PRS_IPV4_HEAD 0x40 29 #define MVPP2_PRS_IPV4_HEAD_MASK 0xf0 30 #define MVPP2_PRS_IPV4_MC 0xe0 31 #define MVPP2_PRS_IPV4_MC_MASK 0xf0 32 #define MVPP2_PRS_IPV4_BC_MASK 0xff 33 #define MVPP2_PRS_IPV4_IHL 0x5 34 #define MVPP2_PRS_IPV4_IHL_MASK 0xf 35 #define MVPP2_PRS_IPV6_MC 0xff 36 #define MVPP2_PRS_IPV6_MC_MASK 0xff 37 #define MVPP2_PRS_IPV6_HOP_MASK 0xff 38 #define MVPP2_PRS_TCAM_PROTO_MASK 0xff 39 #define MVPP2_PRS_TCAM_PROTO_MASK_L 0x3f 40 #define MVPP2_PRS_DBL_VLANS_MAX 100 41 #define MVPP2_PRS_CAST_MASK BIT(0) 42 #define MVPP2_PRS_MCAST_VAL BIT(0) 43 #define MVPP2_PRS_UCAST_VAL 0x0 44 45 /* Tcam structure: 46 * - lookup ID - 4 bits 47 * - port ID - 1 byte 48 * - additional information - 1 byte 49 * - header data - 8 bytes 50 * The fields are represented by MVPP2_PRS_TCAM_DATA_REG(5)->(0). 51 */ 52 #define MVPP2_PRS_AI_BITS 8 53 #define MVPP2_PRS_PORT_MASK 0xff 54 #define MVPP2_PRS_LU_MASK 0xf 55 #define MVPP2_PRS_TCAM_DATA_BYTE(offs) \ 56 (((offs) - ((offs) % 2)) * 2 + ((offs) % 2)) 57 #define MVPP2_PRS_TCAM_DATA_BYTE_EN(offs) \ 58 (((offs) * 2) - ((offs) % 2) + 2) 59 #define MVPP2_PRS_TCAM_AI_BYTE 16 60 #define MVPP2_PRS_TCAM_PORT_BYTE 17 61 #define MVPP2_PRS_TCAM_LU_BYTE 20 62 #define MVPP2_PRS_TCAM_EN_OFFS(offs) ((offs) + 2) 63 #define MVPP2_PRS_TCAM_INV_WORD 5 64 65 #define MVPP2_PRS_VID_TCAM_BYTE 2 66 67 /* TCAM range for unicast and multicast filtering. We have 25 entries per port, 68 * with 4 dedicated to UC filtering and the rest to multicast filtering. 69 * Additionnally we reserve one entry for the broadcast address, and one for 70 * each port's own address. 71 */ 72 #define MVPP2_PRS_MAC_UC_MC_FILT_MAX 25 73 #define MVPP2_PRS_MAC_RANGE_SIZE 80 74 75 /* Number of entries per port dedicated to UC and MC filtering */ 76 #define MVPP2_PRS_MAC_UC_FILT_MAX 4 77 #define MVPP2_PRS_MAC_MC_FILT_MAX (MVPP2_PRS_MAC_UC_MC_FILT_MAX - \ 78 MVPP2_PRS_MAC_UC_FILT_MAX) 79 80 /* There is a TCAM range reserved for VLAN filtering entries, range size is 33 81 * 10 VLAN ID filter entries per port 82 * 1 default VLAN filter entry per port 83 * It is assumed that there are 3 ports for filter, not including loopback port 84 */ 85 #define MVPP2_PRS_VLAN_FILT_MAX 11 86 #define MVPP2_PRS_VLAN_FILT_RANGE_SIZE 33 87 88 #define MVPP2_PRS_VLAN_FILT_MAX_ENTRY (MVPP2_PRS_VLAN_FILT_MAX - 2) 89 #define MVPP2_PRS_VLAN_FILT_DFLT_ENTRY (MVPP2_PRS_VLAN_FILT_MAX - 1) 90 91 /* Tcam entries ID */ 92 #define MVPP2_PE_DROP_ALL 0 93 #define MVPP2_PE_FIRST_FREE_TID 1 94 95 /* MAC filtering range */ 96 #define MVPP2_PE_MAC_RANGE_END (MVPP2_PE_VID_FILT_RANGE_START - 1) 97 #define MVPP2_PE_MAC_RANGE_START (MVPP2_PE_MAC_RANGE_END - \ 98 MVPP2_PRS_MAC_RANGE_SIZE + 1) 99 /* VLAN filtering range */ 100 #define MVPP2_PE_VID_FILT_RANGE_END (MVPP2_PRS_TCAM_SRAM_SIZE - 31) 101 #define MVPP2_PE_VID_FILT_RANGE_START (MVPP2_PE_VID_FILT_RANGE_END - \ 102 MVPP2_PRS_VLAN_FILT_RANGE_SIZE + 1) 103 #define MVPP2_PE_LAST_FREE_TID (MVPP2_PE_MAC_RANGE_START - 1) 104 #define MVPP2_PE_IP6_EXT_PROTO_UN (MVPP2_PRS_TCAM_SRAM_SIZE - 30) 105 #define MVPP2_PE_IP6_ADDR_UN (MVPP2_PRS_TCAM_SRAM_SIZE - 29) 106 #define MVPP2_PE_IP4_ADDR_UN (MVPP2_PRS_TCAM_SRAM_SIZE - 28) 107 #define MVPP2_PE_LAST_DEFAULT_FLOW (MVPP2_PRS_TCAM_SRAM_SIZE - 27) 108 #define MVPP2_PE_FIRST_DEFAULT_FLOW (MVPP2_PRS_TCAM_SRAM_SIZE - 22) 109 #define MVPP2_PE_EDSA_TAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 21) 110 #define MVPP2_PE_EDSA_UNTAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 20) 111 #define MVPP2_PE_DSA_TAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 19) 112 #define MVPP2_PE_DSA_UNTAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 18) 113 #define MVPP2_PE_ETYPE_EDSA_TAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 17) 114 #define MVPP2_PE_ETYPE_EDSA_UNTAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 16) 115 #define MVPP2_PE_ETYPE_DSA_TAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 15) 116 #define MVPP2_PE_ETYPE_DSA_UNTAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 14) 117 #define MVPP2_PE_MH_DEFAULT (MVPP2_PRS_TCAM_SRAM_SIZE - 13) 118 #define MVPP2_PE_DSA_DEFAULT (MVPP2_PRS_TCAM_SRAM_SIZE - 12) 119 #define MVPP2_PE_IP6_PROTO_UN (MVPP2_PRS_TCAM_SRAM_SIZE - 11) 120 #define MVPP2_PE_IP4_PROTO_UN (MVPP2_PRS_TCAM_SRAM_SIZE - 10) 121 #define MVPP2_PE_ETH_TYPE_UN (MVPP2_PRS_TCAM_SRAM_SIZE - 9) 122 #define MVPP2_PE_VID_FLTR_DEFAULT (MVPP2_PRS_TCAM_SRAM_SIZE - 8) 123 #define MVPP2_PE_VID_EDSA_FLTR_DEFAULT (MVPP2_PRS_TCAM_SRAM_SIZE - 7) 124 #define MVPP2_PE_VLAN_DBL (MVPP2_PRS_TCAM_SRAM_SIZE - 6) 125 #define MVPP2_PE_VLAN_NONE (MVPP2_PRS_TCAM_SRAM_SIZE - 5) 126 /* reserved */ 127 #define MVPP2_PE_MAC_MC_PROMISCUOUS (MVPP2_PRS_TCAM_SRAM_SIZE - 3) 128 #define MVPP2_PE_MAC_UC_PROMISCUOUS (MVPP2_PRS_TCAM_SRAM_SIZE - 2) 129 #define MVPP2_PE_MAC_NON_PROMISCUOUS (MVPP2_PRS_TCAM_SRAM_SIZE - 1) 130 131 #define MVPP2_PRS_VID_PORT_FIRST(port) (MVPP2_PE_VID_FILT_RANGE_START + \ 132 ((port) * MVPP2_PRS_VLAN_FILT_MAX)) 133 #define MVPP2_PRS_VID_PORT_LAST(port) (MVPP2_PRS_VID_PORT_FIRST(port) \ 134 + MVPP2_PRS_VLAN_FILT_MAX_ENTRY) 135 /* Index of default vid filter for given port */ 136 #define MVPP2_PRS_VID_PORT_DFLT(port) (MVPP2_PRS_VID_PORT_FIRST(port) \ 137 + MVPP2_PRS_VLAN_FILT_DFLT_ENTRY) 138 139 /* Sram structure 140 * The fields are represented by MVPP2_PRS_TCAM_DATA_REG(3)->(0). 141 */ 142 #define MVPP2_PRS_SRAM_RI_OFFS 0 143 #define MVPP2_PRS_SRAM_RI_WORD 0 144 #define MVPP2_PRS_SRAM_RI_CTRL_OFFS 32 145 #define MVPP2_PRS_SRAM_RI_CTRL_WORD 1 146 #define MVPP2_PRS_SRAM_RI_CTRL_BITS 32 147 #define MVPP2_PRS_SRAM_SHIFT_OFFS 64 148 #define MVPP2_PRS_SRAM_SHIFT_SIGN_BIT 72 149 #define MVPP2_PRS_SRAM_UDF_OFFS 73 150 #define MVPP2_PRS_SRAM_UDF_BITS 8 151 #define MVPP2_PRS_SRAM_UDF_MASK 0xff 152 #define MVPP2_PRS_SRAM_UDF_SIGN_BIT 81 153 #define MVPP2_PRS_SRAM_UDF_TYPE_OFFS 82 154 #define MVPP2_PRS_SRAM_UDF_TYPE_MASK 0x7 155 #define MVPP2_PRS_SRAM_UDF_TYPE_L3 1 156 #define MVPP2_PRS_SRAM_UDF_TYPE_L4 4 157 #define MVPP2_PRS_SRAM_OP_SEL_SHIFT_OFFS 85 158 #define MVPP2_PRS_SRAM_OP_SEL_SHIFT_MASK 0x3 159 #define MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD 1 160 #define MVPP2_PRS_SRAM_OP_SEL_SHIFT_IP4_ADD 2 161 #define MVPP2_PRS_SRAM_OP_SEL_SHIFT_IP6_ADD 3 162 #define MVPP2_PRS_SRAM_OP_SEL_UDF_OFFS 87 163 #define MVPP2_PRS_SRAM_OP_SEL_UDF_BITS 2 164 #define MVPP2_PRS_SRAM_OP_SEL_UDF_MASK 0x3 165 #define MVPP2_PRS_SRAM_OP_SEL_UDF_ADD 0 166 #define MVPP2_PRS_SRAM_OP_SEL_UDF_IP4_ADD 2 167 #define MVPP2_PRS_SRAM_OP_SEL_UDF_IP6_ADD 3 168 #define MVPP2_PRS_SRAM_OP_SEL_BASE_OFFS 89 169 #define MVPP2_PRS_SRAM_AI_OFFS 90 170 #define MVPP2_PRS_SRAM_AI_CTRL_OFFS 98 171 #define MVPP2_PRS_SRAM_AI_CTRL_BITS 8 172 #define MVPP2_PRS_SRAM_AI_MASK 0xff 173 #define MVPP2_PRS_SRAM_NEXT_LU_OFFS 106 174 #define MVPP2_PRS_SRAM_NEXT_LU_MASK 0xf 175 #define MVPP2_PRS_SRAM_LU_DONE_BIT 110 176 #define MVPP2_PRS_SRAM_LU_GEN_BIT 111 177 178 /* Sram result info bits assignment */ 179 #define MVPP2_PRS_RI_MAC_ME_MASK 0x1 180 #define MVPP2_PRS_RI_DSA_MASK 0x2 181 #define MVPP2_PRS_RI_VLAN_MASK (BIT(2) | BIT(3)) 182 #define MVPP2_PRS_RI_VLAN_NONE 0x0 183 #define MVPP2_PRS_RI_VLAN_SINGLE BIT(2) 184 #define MVPP2_PRS_RI_VLAN_DOUBLE BIT(3) 185 #define MVPP2_PRS_RI_VLAN_TRIPLE (BIT(2) | BIT(3)) 186 #define MVPP2_PRS_RI_CPU_CODE_MASK 0x70 187 #define MVPP2_PRS_RI_CPU_CODE_RX_SPEC BIT(4) 188 #define MVPP2_PRS_RI_L2_CAST_MASK (BIT(9) | BIT(10)) 189 #define MVPP2_PRS_RI_L2_UCAST 0x0 190 #define MVPP2_PRS_RI_L2_MCAST BIT(9) 191 #define MVPP2_PRS_RI_L2_BCAST BIT(10) 192 #define MVPP2_PRS_RI_PPPOE_MASK 0x800 193 #define MVPP2_PRS_RI_L3_PROTO_MASK (BIT(12) | BIT(13) | BIT(14)) 194 #define MVPP2_PRS_RI_L3_UN 0x0 195 #define MVPP2_PRS_RI_L3_IP4 BIT(12) 196 #define MVPP2_PRS_RI_L3_IP4_OPT BIT(13) 197 #define MVPP2_PRS_RI_L3_IP4_OTHER (BIT(12) | BIT(13)) 198 #define MVPP2_PRS_RI_L3_IP6 BIT(14) 199 #define MVPP2_PRS_RI_L3_IP6_EXT (BIT(12) | BIT(14)) 200 #define MVPP2_PRS_RI_L3_ARP (BIT(13) | BIT(14)) 201 #define MVPP2_PRS_RI_L3_ADDR_MASK (BIT(15) | BIT(16)) 202 #define MVPP2_PRS_RI_L3_UCAST 0x0 203 #define MVPP2_PRS_RI_L3_MCAST BIT(15) 204 #define MVPP2_PRS_RI_L3_BCAST (BIT(15) | BIT(16)) 205 #define MVPP2_PRS_RI_IP_FRAG_MASK 0x20000 206 #define MVPP2_PRS_RI_IP_FRAG_TRUE BIT(17) 207 #define MVPP2_PRS_RI_UDF3_MASK 0x300000 208 #define MVPP2_PRS_RI_UDF3_RX_SPECIAL BIT(21) 209 #define MVPP2_PRS_RI_L4_PROTO_MASK 0x1c00000 210 #define MVPP2_PRS_RI_L4_TCP BIT(22) 211 #define MVPP2_PRS_RI_L4_UDP BIT(23) 212 #define MVPP2_PRS_RI_L4_OTHER (BIT(22) | BIT(23)) 213 #define MVPP2_PRS_RI_UDF7_MASK 0x60000000 214 #define MVPP2_PRS_RI_UDF7_IP6_LITE BIT(29) 215 #define MVPP2_PRS_RI_DROP_MASK 0x80000000 216 217 /* Sram additional info bits assignment */ 218 #define MVPP2_PRS_IPV4_DIP_AI_BIT BIT(0) 219 #define MVPP2_PRS_IPV6_NO_EXT_AI_BIT BIT(0) 220 #define MVPP2_PRS_IPV6_EXT_AI_BIT BIT(1) 221 #define MVPP2_PRS_IPV6_EXT_AH_AI_BIT BIT(2) 222 #define MVPP2_PRS_IPV6_EXT_AH_LEN_AI_BIT BIT(3) 223 #define MVPP2_PRS_IPV6_EXT_AH_L4_AI_BIT BIT(4) 224 #define MVPP2_PRS_SINGLE_VLAN_AI 0 225 #define MVPP2_PRS_DBL_VLAN_AI_BIT BIT(7) 226 #define MVPP2_PRS_EDSA_VID_AI_BIT BIT(0) 227 228 /* DSA/EDSA type */ 229 #define MVPP2_PRS_TAGGED true 230 #define MVPP2_PRS_UNTAGGED false 231 #define MVPP2_PRS_EDSA true 232 #define MVPP2_PRS_DSA false 233 234 /* MAC entries, shadow udf */ 235 enum mvpp2_prs_udf { 236 MVPP2_PRS_UDF_MAC_DEF, 237 MVPP2_PRS_UDF_MAC_RANGE, 238 MVPP2_PRS_UDF_L2_DEF, 239 MVPP2_PRS_UDF_L2_DEF_COPY, 240 MVPP2_PRS_UDF_L2_USER, 241 }; 242 243 /* Lookup ID */ 244 enum mvpp2_prs_lookup { 245 MVPP2_PRS_LU_MH, 246 MVPP2_PRS_LU_MAC, 247 MVPP2_PRS_LU_DSA, 248 MVPP2_PRS_LU_VLAN, 249 MVPP2_PRS_LU_VID, 250 MVPP2_PRS_LU_L2, 251 MVPP2_PRS_LU_PPPOE, 252 MVPP2_PRS_LU_IP4, 253 MVPP2_PRS_LU_IP6, 254 MVPP2_PRS_LU_FLOWS, 255 MVPP2_PRS_LU_LAST, 256 }; 257 258 union mvpp2_prs_tcam_entry { 259 u32 word[MVPP2_PRS_TCAM_WORDS]; 260 u8 byte[MVPP2_PRS_TCAM_WORDS * 4]; 261 }; 262 263 union mvpp2_prs_sram_entry { 264 u32 word[MVPP2_PRS_SRAM_WORDS]; 265 u8 byte[MVPP2_PRS_SRAM_WORDS * 4]; 266 }; 267 268 struct mvpp2_prs_entry { 269 u32 index; 270 union mvpp2_prs_tcam_entry tcam; 271 union mvpp2_prs_sram_entry sram; 272 }; 273 274 struct mvpp2_prs_shadow { 275 bool valid; 276 bool finish; 277 278 /* Lookup ID */ 279 int lu; 280 281 /* User defined offset */ 282 int udf; 283 284 /* Result info */ 285 u32 ri; 286 u32 ri_mask; 287 }; 288 289 int mvpp2_prs_default_init(struct platform_device *pdev, struct mvpp2 *priv); 290 291 int mvpp2_prs_mac_da_accept(struct mvpp2_port *port, const u8 *da, bool add); 292 293 int mvpp2_prs_tag_mode_set(struct mvpp2 *priv, int port, int type); 294 295 int mvpp2_prs_def_flow(struct mvpp2_port *port); 296 297 void mvpp2_prs_vid_enable_filtering(struct mvpp2_port *port); 298 299 void mvpp2_prs_vid_disable_filtering(struct mvpp2_port *port); 300 301 int mvpp2_prs_vid_entry_add(struct mvpp2_port *port, u16 vid); 302 303 void mvpp2_prs_vid_entry_remove(struct mvpp2_port *port, u16 vid); 304 305 void mvpp2_prs_vid_remove_all(struct mvpp2_port *port); 306 307 void mvpp2_prs_mac_promisc_set(struct mvpp2 *priv, int port, 308 enum mvpp2_prs_l2_cast l2_cast, bool add); 309 310 void mvpp2_prs_mac_del_all(struct mvpp2_port *port); 311 312 int mvpp2_prs_update_mac_da(struct net_device *dev, const u8 *da); 313 314 #endif 315