1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Driver for Marvell PPv2 network controller for Armada 375 SoC. 4 * 5 * Copyright (C) 2014 Marvell 6 * 7 * Marcin Wojtas <mw@semihalf.com> 8 */ 9 10 #include <linux/acpi.h> 11 #include <linux/kernel.h> 12 #include <linux/netdevice.h> 13 #include <linux/etherdevice.h> 14 #include <linux/platform_device.h> 15 #include <linux/skbuff.h> 16 #include <linux/inetdevice.h> 17 #include <linux/mbus.h> 18 #include <linux/module.h> 19 #include <linux/mfd/syscon.h> 20 #include <linux/interrupt.h> 21 #include <linux/cpumask.h> 22 #include <linux/of.h> 23 #include <linux/of_irq.h> 24 #include <linux/of_mdio.h> 25 #include <linux/of_net.h> 26 #include <linux/of_address.h> 27 #include <linux/of_device.h> 28 #include <linux/phy.h> 29 #include <linux/phylink.h> 30 #include <linux/phy/phy.h> 31 #include <linux/clk.h> 32 #include <linux/hrtimer.h> 33 #include <linux/ktime.h> 34 #include <linux/regmap.h> 35 #include <uapi/linux/ppp_defs.h> 36 #include <net/ip.h> 37 #include <net/ipv6.h> 38 #include <net/tso.h> 39 40 #include "mvpp2.h" 41 #include "mvpp2_prs.h" 42 #include "mvpp2_cls.h" 43 44 enum mvpp2_bm_pool_log_num { 45 MVPP2_BM_SHORT, 46 MVPP2_BM_LONG, 47 MVPP2_BM_JUMBO, 48 MVPP2_BM_POOLS_NUM 49 }; 50 51 static struct { 52 int pkt_size; 53 int buf_num; 54 } mvpp2_pools[MVPP2_BM_POOLS_NUM]; 55 56 /* The prototype is added here to be used in start_dev when using ACPI. This 57 * will be removed once phylink is used for all modes (dt+ACPI). 58 */ 59 static void mvpp2_mac_config(struct net_device *dev, unsigned int mode, 60 const struct phylink_link_state *state); 61 static void mvpp2_mac_link_up(struct net_device *dev, unsigned int mode, 62 phy_interface_t interface, struct phy_device *phy); 63 64 /* Queue modes */ 65 #define MVPP2_QDIST_SINGLE_MODE 0 66 #define MVPP2_QDIST_MULTI_MODE 1 67 68 static int queue_mode = MVPP2_QDIST_MULTI_MODE; 69 70 module_param(queue_mode, int, 0444); 71 MODULE_PARM_DESC(queue_mode, "Set queue_mode (single=0, multi=1)"); 72 73 /* Utility/helper methods */ 74 75 void mvpp2_write(struct mvpp2 *priv, u32 offset, u32 data) 76 { 77 writel(data, priv->swth_base[0] + offset); 78 } 79 80 u32 mvpp2_read(struct mvpp2 *priv, u32 offset) 81 { 82 return readl(priv->swth_base[0] + offset); 83 } 84 85 static u32 mvpp2_read_relaxed(struct mvpp2 *priv, u32 offset) 86 { 87 return readl_relaxed(priv->swth_base[0] + offset); 88 } 89 90 static inline u32 mvpp2_cpu_to_thread(struct mvpp2 *priv, int cpu) 91 { 92 return cpu % priv->nthreads; 93 } 94 95 /* These accessors should be used to access: 96 * 97 * - per-thread registers, where each thread has its own copy of the 98 * register. 99 * 100 * MVPP2_BM_VIRT_ALLOC_REG 101 * MVPP2_BM_ADDR_HIGH_ALLOC 102 * MVPP22_BM_ADDR_HIGH_RLS_REG 103 * MVPP2_BM_VIRT_RLS_REG 104 * MVPP2_ISR_RX_TX_CAUSE_REG 105 * MVPP2_ISR_RX_TX_MASK_REG 106 * MVPP2_TXQ_NUM_REG 107 * MVPP2_AGGR_TXQ_UPDATE_REG 108 * MVPP2_TXQ_RSVD_REQ_REG 109 * MVPP2_TXQ_RSVD_RSLT_REG 110 * MVPP2_TXQ_SENT_REG 111 * MVPP2_RXQ_NUM_REG 112 * 113 * - global registers that must be accessed through a specific thread 114 * window, because they are related to an access to a per-thread 115 * register 116 * 117 * MVPP2_BM_PHY_ALLOC_REG (related to MVPP2_BM_VIRT_ALLOC_REG) 118 * MVPP2_BM_PHY_RLS_REG (related to MVPP2_BM_VIRT_RLS_REG) 119 * MVPP2_RXQ_THRESH_REG (related to MVPP2_RXQ_NUM_REG) 120 * MVPP2_RXQ_DESC_ADDR_REG (related to MVPP2_RXQ_NUM_REG) 121 * MVPP2_RXQ_DESC_SIZE_REG (related to MVPP2_RXQ_NUM_REG) 122 * MVPP2_RXQ_INDEX_REG (related to MVPP2_RXQ_NUM_REG) 123 * MVPP2_TXQ_PENDING_REG (related to MVPP2_TXQ_NUM_REG) 124 * MVPP2_TXQ_DESC_ADDR_REG (related to MVPP2_TXQ_NUM_REG) 125 * MVPP2_TXQ_DESC_SIZE_REG (related to MVPP2_TXQ_NUM_REG) 126 * MVPP2_TXQ_INDEX_REG (related to MVPP2_TXQ_NUM_REG) 127 * MVPP2_TXQ_PENDING_REG (related to MVPP2_TXQ_NUM_REG) 128 * MVPP2_TXQ_PREF_BUF_REG (related to MVPP2_TXQ_NUM_REG) 129 * MVPP2_TXQ_PREF_BUF_REG (related to MVPP2_TXQ_NUM_REG) 130 */ 131 static void mvpp2_thread_write(struct mvpp2 *priv, unsigned int thread, 132 u32 offset, u32 data) 133 { 134 writel(data, priv->swth_base[thread] + offset); 135 } 136 137 static u32 mvpp2_thread_read(struct mvpp2 *priv, unsigned int thread, 138 u32 offset) 139 { 140 return readl(priv->swth_base[thread] + offset); 141 } 142 143 static void mvpp2_thread_write_relaxed(struct mvpp2 *priv, unsigned int thread, 144 u32 offset, u32 data) 145 { 146 writel_relaxed(data, priv->swth_base[thread] + offset); 147 } 148 149 static u32 mvpp2_thread_read_relaxed(struct mvpp2 *priv, unsigned int thread, 150 u32 offset) 151 { 152 return readl_relaxed(priv->swth_base[thread] + offset); 153 } 154 155 static dma_addr_t mvpp2_txdesc_dma_addr_get(struct mvpp2_port *port, 156 struct mvpp2_tx_desc *tx_desc) 157 { 158 if (port->priv->hw_version == MVPP21) 159 return le32_to_cpu(tx_desc->pp21.buf_dma_addr); 160 else 161 return le64_to_cpu(tx_desc->pp22.buf_dma_addr_ptp) & 162 MVPP2_DESC_DMA_MASK; 163 } 164 165 static void mvpp2_txdesc_dma_addr_set(struct mvpp2_port *port, 166 struct mvpp2_tx_desc *tx_desc, 167 dma_addr_t dma_addr) 168 { 169 dma_addr_t addr, offset; 170 171 addr = dma_addr & ~MVPP2_TX_DESC_ALIGN; 172 offset = dma_addr & MVPP2_TX_DESC_ALIGN; 173 174 if (port->priv->hw_version == MVPP21) { 175 tx_desc->pp21.buf_dma_addr = cpu_to_le32(addr); 176 tx_desc->pp21.packet_offset = offset; 177 } else { 178 __le64 val = cpu_to_le64(addr); 179 180 tx_desc->pp22.buf_dma_addr_ptp &= ~cpu_to_le64(MVPP2_DESC_DMA_MASK); 181 tx_desc->pp22.buf_dma_addr_ptp |= val; 182 tx_desc->pp22.packet_offset = offset; 183 } 184 } 185 186 static size_t mvpp2_txdesc_size_get(struct mvpp2_port *port, 187 struct mvpp2_tx_desc *tx_desc) 188 { 189 if (port->priv->hw_version == MVPP21) 190 return le16_to_cpu(tx_desc->pp21.data_size); 191 else 192 return le16_to_cpu(tx_desc->pp22.data_size); 193 } 194 195 static void mvpp2_txdesc_size_set(struct mvpp2_port *port, 196 struct mvpp2_tx_desc *tx_desc, 197 size_t size) 198 { 199 if (port->priv->hw_version == MVPP21) 200 tx_desc->pp21.data_size = cpu_to_le16(size); 201 else 202 tx_desc->pp22.data_size = cpu_to_le16(size); 203 } 204 205 static void mvpp2_txdesc_txq_set(struct mvpp2_port *port, 206 struct mvpp2_tx_desc *tx_desc, 207 unsigned int txq) 208 { 209 if (port->priv->hw_version == MVPP21) 210 tx_desc->pp21.phys_txq = txq; 211 else 212 tx_desc->pp22.phys_txq = txq; 213 } 214 215 static void mvpp2_txdesc_cmd_set(struct mvpp2_port *port, 216 struct mvpp2_tx_desc *tx_desc, 217 unsigned int command) 218 { 219 if (port->priv->hw_version == MVPP21) 220 tx_desc->pp21.command = cpu_to_le32(command); 221 else 222 tx_desc->pp22.command = cpu_to_le32(command); 223 } 224 225 static unsigned int mvpp2_txdesc_offset_get(struct mvpp2_port *port, 226 struct mvpp2_tx_desc *tx_desc) 227 { 228 if (port->priv->hw_version == MVPP21) 229 return tx_desc->pp21.packet_offset; 230 else 231 return tx_desc->pp22.packet_offset; 232 } 233 234 static dma_addr_t mvpp2_rxdesc_dma_addr_get(struct mvpp2_port *port, 235 struct mvpp2_rx_desc *rx_desc) 236 { 237 if (port->priv->hw_version == MVPP21) 238 return le32_to_cpu(rx_desc->pp21.buf_dma_addr); 239 else 240 return le64_to_cpu(rx_desc->pp22.buf_dma_addr_key_hash) & 241 MVPP2_DESC_DMA_MASK; 242 } 243 244 static unsigned long mvpp2_rxdesc_cookie_get(struct mvpp2_port *port, 245 struct mvpp2_rx_desc *rx_desc) 246 { 247 if (port->priv->hw_version == MVPP21) 248 return le32_to_cpu(rx_desc->pp21.buf_cookie); 249 else 250 return le64_to_cpu(rx_desc->pp22.buf_cookie_misc) & 251 MVPP2_DESC_DMA_MASK; 252 } 253 254 static size_t mvpp2_rxdesc_size_get(struct mvpp2_port *port, 255 struct mvpp2_rx_desc *rx_desc) 256 { 257 if (port->priv->hw_version == MVPP21) 258 return le16_to_cpu(rx_desc->pp21.data_size); 259 else 260 return le16_to_cpu(rx_desc->pp22.data_size); 261 } 262 263 static u32 mvpp2_rxdesc_status_get(struct mvpp2_port *port, 264 struct mvpp2_rx_desc *rx_desc) 265 { 266 if (port->priv->hw_version == MVPP21) 267 return le32_to_cpu(rx_desc->pp21.status); 268 else 269 return le32_to_cpu(rx_desc->pp22.status); 270 } 271 272 static void mvpp2_txq_inc_get(struct mvpp2_txq_pcpu *txq_pcpu) 273 { 274 txq_pcpu->txq_get_index++; 275 if (txq_pcpu->txq_get_index == txq_pcpu->size) 276 txq_pcpu->txq_get_index = 0; 277 } 278 279 static void mvpp2_txq_inc_put(struct mvpp2_port *port, 280 struct mvpp2_txq_pcpu *txq_pcpu, 281 struct sk_buff *skb, 282 struct mvpp2_tx_desc *tx_desc) 283 { 284 struct mvpp2_txq_pcpu_buf *tx_buf = 285 txq_pcpu->buffs + txq_pcpu->txq_put_index; 286 tx_buf->skb = skb; 287 tx_buf->size = mvpp2_txdesc_size_get(port, tx_desc); 288 tx_buf->dma = mvpp2_txdesc_dma_addr_get(port, tx_desc) + 289 mvpp2_txdesc_offset_get(port, tx_desc); 290 txq_pcpu->txq_put_index++; 291 if (txq_pcpu->txq_put_index == txq_pcpu->size) 292 txq_pcpu->txq_put_index = 0; 293 } 294 295 /* Get number of physical egress port */ 296 static inline int mvpp2_egress_port(struct mvpp2_port *port) 297 { 298 return MVPP2_MAX_TCONT + port->id; 299 } 300 301 /* Get number of physical TXQ */ 302 static inline int mvpp2_txq_phys(int port, int txq) 303 { 304 return (MVPP2_MAX_TCONT + port) * MVPP2_MAX_TXQ + txq; 305 } 306 307 static void *mvpp2_frag_alloc(const struct mvpp2_bm_pool *pool) 308 { 309 if (likely(pool->frag_size <= PAGE_SIZE)) 310 return netdev_alloc_frag(pool->frag_size); 311 else 312 return kmalloc(pool->frag_size, GFP_ATOMIC); 313 } 314 315 static void mvpp2_frag_free(const struct mvpp2_bm_pool *pool, void *data) 316 { 317 if (likely(pool->frag_size <= PAGE_SIZE)) 318 skb_free_frag(data); 319 else 320 kfree(data); 321 } 322 323 /* Buffer Manager configuration routines */ 324 325 /* Create pool */ 326 static int mvpp2_bm_pool_create(struct platform_device *pdev, 327 struct mvpp2 *priv, 328 struct mvpp2_bm_pool *bm_pool, int size) 329 { 330 u32 val; 331 332 /* Number of buffer pointers must be a multiple of 16, as per 333 * hardware constraints 334 */ 335 if (!IS_ALIGNED(size, 16)) 336 return -EINVAL; 337 338 /* PPv2.1 needs 8 bytes per buffer pointer, PPv2.2 needs 16 339 * bytes per buffer pointer 340 */ 341 if (priv->hw_version == MVPP21) 342 bm_pool->size_bytes = 2 * sizeof(u32) * size; 343 else 344 bm_pool->size_bytes = 2 * sizeof(u64) * size; 345 346 bm_pool->virt_addr = dma_alloc_coherent(&pdev->dev, bm_pool->size_bytes, 347 &bm_pool->dma_addr, 348 GFP_KERNEL); 349 if (!bm_pool->virt_addr) 350 return -ENOMEM; 351 352 if (!IS_ALIGNED((unsigned long)bm_pool->virt_addr, 353 MVPP2_BM_POOL_PTR_ALIGN)) { 354 dma_free_coherent(&pdev->dev, bm_pool->size_bytes, 355 bm_pool->virt_addr, bm_pool->dma_addr); 356 dev_err(&pdev->dev, "BM pool %d is not %d bytes aligned\n", 357 bm_pool->id, MVPP2_BM_POOL_PTR_ALIGN); 358 return -ENOMEM; 359 } 360 361 mvpp2_write(priv, MVPP2_BM_POOL_BASE_REG(bm_pool->id), 362 lower_32_bits(bm_pool->dma_addr)); 363 mvpp2_write(priv, MVPP2_BM_POOL_SIZE_REG(bm_pool->id), size); 364 365 val = mvpp2_read(priv, MVPP2_BM_POOL_CTRL_REG(bm_pool->id)); 366 val |= MVPP2_BM_START_MASK; 367 mvpp2_write(priv, MVPP2_BM_POOL_CTRL_REG(bm_pool->id), val); 368 369 bm_pool->size = size; 370 bm_pool->pkt_size = 0; 371 bm_pool->buf_num = 0; 372 373 return 0; 374 } 375 376 /* Set pool buffer size */ 377 static void mvpp2_bm_pool_bufsize_set(struct mvpp2 *priv, 378 struct mvpp2_bm_pool *bm_pool, 379 int buf_size) 380 { 381 u32 val; 382 383 bm_pool->buf_size = buf_size; 384 385 val = ALIGN(buf_size, 1 << MVPP2_POOL_BUF_SIZE_OFFSET); 386 mvpp2_write(priv, MVPP2_POOL_BUF_SIZE_REG(bm_pool->id), val); 387 } 388 389 static void mvpp2_bm_bufs_get_addrs(struct device *dev, struct mvpp2 *priv, 390 struct mvpp2_bm_pool *bm_pool, 391 dma_addr_t *dma_addr, 392 phys_addr_t *phys_addr) 393 { 394 unsigned int thread = mvpp2_cpu_to_thread(priv, get_cpu()); 395 396 *dma_addr = mvpp2_thread_read(priv, thread, 397 MVPP2_BM_PHY_ALLOC_REG(bm_pool->id)); 398 *phys_addr = mvpp2_thread_read(priv, thread, MVPP2_BM_VIRT_ALLOC_REG); 399 400 if (priv->hw_version == MVPP22) { 401 u32 val; 402 u32 dma_addr_highbits, phys_addr_highbits; 403 404 val = mvpp2_thread_read(priv, thread, MVPP22_BM_ADDR_HIGH_ALLOC); 405 dma_addr_highbits = (val & MVPP22_BM_ADDR_HIGH_PHYS_MASK); 406 phys_addr_highbits = (val & MVPP22_BM_ADDR_HIGH_VIRT_MASK) >> 407 MVPP22_BM_ADDR_HIGH_VIRT_SHIFT; 408 409 if (sizeof(dma_addr_t) == 8) 410 *dma_addr |= (u64)dma_addr_highbits << 32; 411 412 if (sizeof(phys_addr_t) == 8) 413 *phys_addr |= (u64)phys_addr_highbits << 32; 414 } 415 416 put_cpu(); 417 } 418 419 /* Free all buffers from the pool */ 420 static void mvpp2_bm_bufs_free(struct device *dev, struct mvpp2 *priv, 421 struct mvpp2_bm_pool *bm_pool, int buf_num) 422 { 423 int i; 424 425 if (buf_num > bm_pool->buf_num) { 426 WARN(1, "Pool does not have so many bufs pool(%d) bufs(%d)\n", 427 bm_pool->id, buf_num); 428 buf_num = bm_pool->buf_num; 429 } 430 431 for (i = 0; i < buf_num; i++) { 432 dma_addr_t buf_dma_addr; 433 phys_addr_t buf_phys_addr; 434 void *data; 435 436 mvpp2_bm_bufs_get_addrs(dev, priv, bm_pool, 437 &buf_dma_addr, &buf_phys_addr); 438 439 dma_unmap_single(dev, buf_dma_addr, 440 bm_pool->buf_size, DMA_FROM_DEVICE); 441 442 data = (void *)phys_to_virt(buf_phys_addr); 443 if (!data) 444 break; 445 446 mvpp2_frag_free(bm_pool, data); 447 } 448 449 /* Update BM driver with number of buffers removed from pool */ 450 bm_pool->buf_num -= i; 451 } 452 453 /* Check number of buffers in BM pool */ 454 static int mvpp2_check_hw_buf_num(struct mvpp2 *priv, struct mvpp2_bm_pool *bm_pool) 455 { 456 int buf_num = 0; 457 458 buf_num += mvpp2_read(priv, MVPP2_BM_POOL_PTRS_NUM_REG(bm_pool->id)) & 459 MVPP22_BM_POOL_PTRS_NUM_MASK; 460 buf_num += mvpp2_read(priv, MVPP2_BM_BPPI_PTRS_NUM_REG(bm_pool->id)) & 461 MVPP2_BM_BPPI_PTR_NUM_MASK; 462 463 /* HW has one buffer ready which is not reflected in the counters */ 464 if (buf_num) 465 buf_num += 1; 466 467 return buf_num; 468 } 469 470 /* Cleanup pool */ 471 static int mvpp2_bm_pool_destroy(struct platform_device *pdev, 472 struct mvpp2 *priv, 473 struct mvpp2_bm_pool *bm_pool) 474 { 475 int buf_num; 476 u32 val; 477 478 buf_num = mvpp2_check_hw_buf_num(priv, bm_pool); 479 mvpp2_bm_bufs_free(&pdev->dev, priv, bm_pool, buf_num); 480 481 /* Check buffer counters after free */ 482 buf_num = mvpp2_check_hw_buf_num(priv, bm_pool); 483 if (buf_num) { 484 WARN(1, "cannot free all buffers in pool %d, buf_num left %d\n", 485 bm_pool->id, bm_pool->buf_num); 486 return 0; 487 } 488 489 val = mvpp2_read(priv, MVPP2_BM_POOL_CTRL_REG(bm_pool->id)); 490 val |= MVPP2_BM_STOP_MASK; 491 mvpp2_write(priv, MVPP2_BM_POOL_CTRL_REG(bm_pool->id), val); 492 493 dma_free_coherent(&pdev->dev, bm_pool->size_bytes, 494 bm_pool->virt_addr, 495 bm_pool->dma_addr); 496 return 0; 497 } 498 499 static int mvpp2_bm_pools_init(struct platform_device *pdev, 500 struct mvpp2 *priv) 501 { 502 int i, err, size; 503 struct mvpp2_bm_pool *bm_pool; 504 505 /* Create all pools with maximum size */ 506 size = MVPP2_BM_POOL_SIZE_MAX; 507 for (i = 0; i < MVPP2_BM_POOLS_NUM; i++) { 508 bm_pool = &priv->bm_pools[i]; 509 bm_pool->id = i; 510 err = mvpp2_bm_pool_create(pdev, priv, bm_pool, size); 511 if (err) 512 goto err_unroll_pools; 513 mvpp2_bm_pool_bufsize_set(priv, bm_pool, 0); 514 } 515 return 0; 516 517 err_unroll_pools: 518 dev_err(&pdev->dev, "failed to create BM pool %d, size %d\n", i, size); 519 for (i = i - 1; i >= 0; i--) 520 mvpp2_bm_pool_destroy(pdev, priv, &priv->bm_pools[i]); 521 return err; 522 } 523 524 static int mvpp2_bm_init(struct platform_device *pdev, struct mvpp2 *priv) 525 { 526 int i, err; 527 528 for (i = 0; i < MVPP2_BM_POOLS_NUM; i++) { 529 /* Mask BM all interrupts */ 530 mvpp2_write(priv, MVPP2_BM_INTR_MASK_REG(i), 0); 531 /* Clear BM cause register */ 532 mvpp2_write(priv, MVPP2_BM_INTR_CAUSE_REG(i), 0); 533 } 534 535 /* Allocate and initialize BM pools */ 536 priv->bm_pools = devm_kcalloc(&pdev->dev, MVPP2_BM_POOLS_NUM, 537 sizeof(*priv->bm_pools), GFP_KERNEL); 538 if (!priv->bm_pools) 539 return -ENOMEM; 540 541 err = mvpp2_bm_pools_init(pdev, priv); 542 if (err < 0) 543 return err; 544 return 0; 545 } 546 547 static void mvpp2_setup_bm_pool(void) 548 { 549 /* Short pool */ 550 mvpp2_pools[MVPP2_BM_SHORT].buf_num = MVPP2_BM_SHORT_BUF_NUM; 551 mvpp2_pools[MVPP2_BM_SHORT].pkt_size = MVPP2_BM_SHORT_PKT_SIZE; 552 553 /* Long pool */ 554 mvpp2_pools[MVPP2_BM_LONG].buf_num = MVPP2_BM_LONG_BUF_NUM; 555 mvpp2_pools[MVPP2_BM_LONG].pkt_size = MVPP2_BM_LONG_PKT_SIZE; 556 557 /* Jumbo pool */ 558 mvpp2_pools[MVPP2_BM_JUMBO].buf_num = MVPP2_BM_JUMBO_BUF_NUM; 559 mvpp2_pools[MVPP2_BM_JUMBO].pkt_size = MVPP2_BM_JUMBO_PKT_SIZE; 560 } 561 562 /* Attach long pool to rxq */ 563 static void mvpp2_rxq_long_pool_set(struct mvpp2_port *port, 564 int lrxq, int long_pool) 565 { 566 u32 val, mask; 567 int prxq; 568 569 /* Get queue physical ID */ 570 prxq = port->rxqs[lrxq]->id; 571 572 if (port->priv->hw_version == MVPP21) 573 mask = MVPP21_RXQ_POOL_LONG_MASK; 574 else 575 mask = MVPP22_RXQ_POOL_LONG_MASK; 576 577 val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(prxq)); 578 val &= ~mask; 579 val |= (long_pool << MVPP2_RXQ_POOL_LONG_OFFS) & mask; 580 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(prxq), val); 581 } 582 583 /* Attach short pool to rxq */ 584 static void mvpp2_rxq_short_pool_set(struct mvpp2_port *port, 585 int lrxq, int short_pool) 586 { 587 u32 val, mask; 588 int prxq; 589 590 /* Get queue physical ID */ 591 prxq = port->rxqs[lrxq]->id; 592 593 if (port->priv->hw_version == MVPP21) 594 mask = MVPP21_RXQ_POOL_SHORT_MASK; 595 else 596 mask = MVPP22_RXQ_POOL_SHORT_MASK; 597 598 val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(prxq)); 599 val &= ~mask; 600 val |= (short_pool << MVPP2_RXQ_POOL_SHORT_OFFS) & mask; 601 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(prxq), val); 602 } 603 604 static void *mvpp2_buf_alloc(struct mvpp2_port *port, 605 struct mvpp2_bm_pool *bm_pool, 606 dma_addr_t *buf_dma_addr, 607 phys_addr_t *buf_phys_addr, 608 gfp_t gfp_mask) 609 { 610 dma_addr_t dma_addr; 611 void *data; 612 613 data = mvpp2_frag_alloc(bm_pool); 614 if (!data) 615 return NULL; 616 617 dma_addr = dma_map_single(port->dev->dev.parent, data, 618 MVPP2_RX_BUF_SIZE(bm_pool->pkt_size), 619 DMA_FROM_DEVICE); 620 if (unlikely(dma_mapping_error(port->dev->dev.parent, dma_addr))) { 621 mvpp2_frag_free(bm_pool, data); 622 return NULL; 623 } 624 *buf_dma_addr = dma_addr; 625 *buf_phys_addr = virt_to_phys(data); 626 627 return data; 628 } 629 630 /* Release buffer to BM */ 631 static inline void mvpp2_bm_pool_put(struct mvpp2_port *port, int pool, 632 dma_addr_t buf_dma_addr, 633 phys_addr_t buf_phys_addr) 634 { 635 unsigned int thread = mvpp2_cpu_to_thread(port->priv, get_cpu()); 636 unsigned long flags = 0; 637 638 if (test_bit(thread, &port->priv->lock_map)) 639 spin_lock_irqsave(&port->bm_lock[thread], flags); 640 641 if (port->priv->hw_version == MVPP22) { 642 u32 val = 0; 643 644 if (sizeof(dma_addr_t) == 8) 645 val |= upper_32_bits(buf_dma_addr) & 646 MVPP22_BM_ADDR_HIGH_PHYS_RLS_MASK; 647 648 if (sizeof(phys_addr_t) == 8) 649 val |= (upper_32_bits(buf_phys_addr) 650 << MVPP22_BM_ADDR_HIGH_VIRT_RLS_SHIFT) & 651 MVPP22_BM_ADDR_HIGH_VIRT_RLS_MASK; 652 653 mvpp2_thread_write_relaxed(port->priv, thread, 654 MVPP22_BM_ADDR_HIGH_RLS_REG, val); 655 } 656 657 /* MVPP2_BM_VIRT_RLS_REG is not interpreted by HW, and simply 658 * returned in the "cookie" field of the RX 659 * descriptor. Instead of storing the virtual address, we 660 * store the physical address 661 */ 662 mvpp2_thread_write_relaxed(port->priv, thread, 663 MVPP2_BM_VIRT_RLS_REG, buf_phys_addr); 664 mvpp2_thread_write_relaxed(port->priv, thread, 665 MVPP2_BM_PHY_RLS_REG(pool), buf_dma_addr); 666 667 if (test_bit(thread, &port->priv->lock_map)) 668 spin_unlock_irqrestore(&port->bm_lock[thread], flags); 669 670 put_cpu(); 671 } 672 673 /* Allocate buffers for the pool */ 674 static int mvpp2_bm_bufs_add(struct mvpp2_port *port, 675 struct mvpp2_bm_pool *bm_pool, int buf_num) 676 { 677 int i, buf_size, total_size; 678 dma_addr_t dma_addr; 679 phys_addr_t phys_addr; 680 void *buf; 681 682 buf_size = MVPP2_RX_BUF_SIZE(bm_pool->pkt_size); 683 total_size = MVPP2_RX_TOTAL_SIZE(buf_size); 684 685 if (buf_num < 0 || 686 (buf_num + bm_pool->buf_num > bm_pool->size)) { 687 netdev_err(port->dev, 688 "cannot allocate %d buffers for pool %d\n", 689 buf_num, bm_pool->id); 690 return 0; 691 } 692 693 for (i = 0; i < buf_num; i++) { 694 buf = mvpp2_buf_alloc(port, bm_pool, &dma_addr, 695 &phys_addr, GFP_KERNEL); 696 if (!buf) 697 break; 698 699 mvpp2_bm_pool_put(port, bm_pool->id, dma_addr, 700 phys_addr); 701 } 702 703 /* Update BM driver with number of buffers added to pool */ 704 bm_pool->buf_num += i; 705 706 netdev_dbg(port->dev, 707 "pool %d: pkt_size=%4d, buf_size=%4d, total_size=%4d\n", 708 bm_pool->id, bm_pool->pkt_size, buf_size, total_size); 709 710 netdev_dbg(port->dev, 711 "pool %d: %d of %d buffers added\n", 712 bm_pool->id, i, buf_num); 713 return i; 714 } 715 716 /* Notify the driver that BM pool is being used as specific type and return the 717 * pool pointer on success 718 */ 719 static struct mvpp2_bm_pool * 720 mvpp2_bm_pool_use(struct mvpp2_port *port, unsigned pool, int pkt_size) 721 { 722 struct mvpp2_bm_pool *new_pool = &port->priv->bm_pools[pool]; 723 int num; 724 725 if (pool >= MVPP2_BM_POOLS_NUM) { 726 netdev_err(port->dev, "Invalid pool %d\n", pool); 727 return NULL; 728 } 729 730 /* Allocate buffers in case BM pool is used as long pool, but packet 731 * size doesn't match MTU or BM pool hasn't being used yet 732 */ 733 if (new_pool->pkt_size == 0) { 734 int pkts_num; 735 736 /* Set default buffer number or free all the buffers in case 737 * the pool is not empty 738 */ 739 pkts_num = new_pool->buf_num; 740 if (pkts_num == 0) 741 pkts_num = mvpp2_pools[pool].buf_num; 742 else 743 mvpp2_bm_bufs_free(port->dev->dev.parent, 744 port->priv, new_pool, pkts_num); 745 746 new_pool->pkt_size = pkt_size; 747 new_pool->frag_size = 748 SKB_DATA_ALIGN(MVPP2_RX_BUF_SIZE(pkt_size)) + 749 MVPP2_SKB_SHINFO_SIZE; 750 751 /* Allocate buffers for this pool */ 752 num = mvpp2_bm_bufs_add(port, new_pool, pkts_num); 753 if (num != pkts_num) { 754 WARN(1, "pool %d: %d of %d allocated\n", 755 new_pool->id, num, pkts_num); 756 return NULL; 757 } 758 } 759 760 mvpp2_bm_pool_bufsize_set(port->priv, new_pool, 761 MVPP2_RX_BUF_SIZE(new_pool->pkt_size)); 762 763 return new_pool; 764 } 765 766 /* Initialize pools for swf */ 767 static int mvpp2_swf_bm_pool_init(struct mvpp2_port *port) 768 { 769 int rxq; 770 enum mvpp2_bm_pool_log_num long_log_pool, short_log_pool; 771 772 /* If port pkt_size is higher than 1518B: 773 * HW Long pool - SW Jumbo pool, HW Short pool - SW Long pool 774 * else: HW Long pool - SW Long pool, HW Short pool - SW Short pool 775 */ 776 if (port->pkt_size > MVPP2_BM_LONG_PKT_SIZE) { 777 long_log_pool = MVPP2_BM_JUMBO; 778 short_log_pool = MVPP2_BM_LONG; 779 } else { 780 long_log_pool = MVPP2_BM_LONG; 781 short_log_pool = MVPP2_BM_SHORT; 782 } 783 784 if (!port->pool_long) { 785 port->pool_long = 786 mvpp2_bm_pool_use(port, long_log_pool, 787 mvpp2_pools[long_log_pool].pkt_size); 788 if (!port->pool_long) 789 return -ENOMEM; 790 791 port->pool_long->port_map |= BIT(port->id); 792 793 for (rxq = 0; rxq < port->nrxqs; rxq++) 794 mvpp2_rxq_long_pool_set(port, rxq, port->pool_long->id); 795 } 796 797 if (!port->pool_short) { 798 port->pool_short = 799 mvpp2_bm_pool_use(port, short_log_pool, 800 mvpp2_pools[short_log_pool].pkt_size); 801 if (!port->pool_short) 802 return -ENOMEM; 803 804 port->pool_short->port_map |= BIT(port->id); 805 806 for (rxq = 0; rxq < port->nrxqs; rxq++) 807 mvpp2_rxq_short_pool_set(port, rxq, 808 port->pool_short->id); 809 } 810 811 return 0; 812 } 813 814 static int mvpp2_bm_update_mtu(struct net_device *dev, int mtu) 815 { 816 struct mvpp2_port *port = netdev_priv(dev); 817 enum mvpp2_bm_pool_log_num new_long_pool; 818 int pkt_size = MVPP2_RX_PKT_SIZE(mtu); 819 820 /* If port MTU is higher than 1518B: 821 * HW Long pool - SW Jumbo pool, HW Short pool - SW Long pool 822 * else: HW Long pool - SW Long pool, HW Short pool - SW Short pool 823 */ 824 if (pkt_size > MVPP2_BM_LONG_PKT_SIZE) 825 new_long_pool = MVPP2_BM_JUMBO; 826 else 827 new_long_pool = MVPP2_BM_LONG; 828 829 if (new_long_pool != port->pool_long->id) { 830 /* Remove port from old short & long pool */ 831 port->pool_long = mvpp2_bm_pool_use(port, port->pool_long->id, 832 port->pool_long->pkt_size); 833 port->pool_long->port_map &= ~BIT(port->id); 834 port->pool_long = NULL; 835 836 port->pool_short = mvpp2_bm_pool_use(port, port->pool_short->id, 837 port->pool_short->pkt_size); 838 port->pool_short->port_map &= ~BIT(port->id); 839 port->pool_short = NULL; 840 841 port->pkt_size = pkt_size; 842 843 /* Add port to new short & long pool */ 844 mvpp2_swf_bm_pool_init(port); 845 846 /* Update L4 checksum when jumbo enable/disable on port */ 847 if (new_long_pool == MVPP2_BM_JUMBO && port->id != 0) { 848 dev->features &= ~(NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM); 849 dev->hw_features &= ~(NETIF_F_IP_CSUM | 850 NETIF_F_IPV6_CSUM); 851 } else { 852 dev->features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM; 853 dev->hw_features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM; 854 } 855 } 856 857 dev->mtu = mtu; 858 dev->wanted_features = dev->features; 859 860 netdev_update_features(dev); 861 return 0; 862 } 863 864 static inline void mvpp2_interrupts_enable(struct mvpp2_port *port) 865 { 866 int i, sw_thread_mask = 0; 867 868 for (i = 0; i < port->nqvecs; i++) 869 sw_thread_mask |= port->qvecs[i].sw_thread_mask; 870 871 mvpp2_write(port->priv, MVPP2_ISR_ENABLE_REG(port->id), 872 MVPP2_ISR_ENABLE_INTERRUPT(sw_thread_mask)); 873 } 874 875 static inline void mvpp2_interrupts_disable(struct mvpp2_port *port) 876 { 877 int i, sw_thread_mask = 0; 878 879 for (i = 0; i < port->nqvecs; i++) 880 sw_thread_mask |= port->qvecs[i].sw_thread_mask; 881 882 mvpp2_write(port->priv, MVPP2_ISR_ENABLE_REG(port->id), 883 MVPP2_ISR_DISABLE_INTERRUPT(sw_thread_mask)); 884 } 885 886 static inline void mvpp2_qvec_interrupt_enable(struct mvpp2_queue_vector *qvec) 887 { 888 struct mvpp2_port *port = qvec->port; 889 890 mvpp2_write(port->priv, MVPP2_ISR_ENABLE_REG(port->id), 891 MVPP2_ISR_ENABLE_INTERRUPT(qvec->sw_thread_mask)); 892 } 893 894 static inline void mvpp2_qvec_interrupt_disable(struct mvpp2_queue_vector *qvec) 895 { 896 struct mvpp2_port *port = qvec->port; 897 898 mvpp2_write(port->priv, MVPP2_ISR_ENABLE_REG(port->id), 899 MVPP2_ISR_DISABLE_INTERRUPT(qvec->sw_thread_mask)); 900 } 901 902 /* Mask the current thread's Rx/Tx interrupts 903 * Called by on_each_cpu(), guaranteed to run with migration disabled, 904 * using smp_processor_id() is OK. 905 */ 906 static void mvpp2_interrupts_mask(void *arg) 907 { 908 struct mvpp2_port *port = arg; 909 910 /* If the thread isn't used, don't do anything */ 911 if (smp_processor_id() > port->priv->nthreads) 912 return; 913 914 mvpp2_thread_write(port->priv, 915 mvpp2_cpu_to_thread(port->priv, smp_processor_id()), 916 MVPP2_ISR_RX_TX_MASK_REG(port->id), 0); 917 } 918 919 /* Unmask the current thread's Rx/Tx interrupts. 920 * Called by on_each_cpu(), guaranteed to run with migration disabled, 921 * using smp_processor_id() is OK. 922 */ 923 static void mvpp2_interrupts_unmask(void *arg) 924 { 925 struct mvpp2_port *port = arg; 926 u32 val; 927 928 /* If the thread isn't used, don't do anything */ 929 if (smp_processor_id() > port->priv->nthreads) 930 return; 931 932 val = MVPP2_CAUSE_MISC_SUM_MASK | 933 MVPP2_CAUSE_RXQ_OCCUP_DESC_ALL_MASK(port->priv->hw_version); 934 if (port->has_tx_irqs) 935 val |= MVPP2_CAUSE_TXQ_OCCUP_DESC_ALL_MASK; 936 937 mvpp2_thread_write(port->priv, 938 mvpp2_cpu_to_thread(port->priv, smp_processor_id()), 939 MVPP2_ISR_RX_TX_MASK_REG(port->id), val); 940 } 941 942 static void 943 mvpp2_shared_interrupt_mask_unmask(struct mvpp2_port *port, bool mask) 944 { 945 u32 val; 946 int i; 947 948 if (port->priv->hw_version != MVPP22) 949 return; 950 951 if (mask) 952 val = 0; 953 else 954 val = MVPP2_CAUSE_RXQ_OCCUP_DESC_ALL_MASK(MVPP22); 955 956 for (i = 0; i < port->nqvecs; i++) { 957 struct mvpp2_queue_vector *v = port->qvecs + i; 958 959 if (v->type != MVPP2_QUEUE_VECTOR_SHARED) 960 continue; 961 962 mvpp2_thread_write(port->priv, v->sw_thread_id, 963 MVPP2_ISR_RX_TX_MASK_REG(port->id), val); 964 } 965 } 966 967 /* Port configuration routines */ 968 969 static void mvpp22_gop_init_rgmii(struct mvpp2_port *port) 970 { 971 struct mvpp2 *priv = port->priv; 972 u32 val; 973 974 regmap_read(priv->sysctrl_base, GENCONF_PORT_CTRL0, &val); 975 val |= GENCONF_PORT_CTRL0_BUS_WIDTH_SELECT; 976 regmap_write(priv->sysctrl_base, GENCONF_PORT_CTRL0, val); 977 978 regmap_read(priv->sysctrl_base, GENCONF_CTRL0, &val); 979 if (port->gop_id == 2) 980 val |= GENCONF_CTRL0_PORT0_RGMII | GENCONF_CTRL0_PORT1_RGMII; 981 else if (port->gop_id == 3) 982 val |= GENCONF_CTRL0_PORT1_RGMII_MII; 983 regmap_write(priv->sysctrl_base, GENCONF_CTRL0, val); 984 } 985 986 static void mvpp22_gop_init_sgmii(struct mvpp2_port *port) 987 { 988 struct mvpp2 *priv = port->priv; 989 u32 val; 990 991 regmap_read(priv->sysctrl_base, GENCONF_PORT_CTRL0, &val); 992 val |= GENCONF_PORT_CTRL0_BUS_WIDTH_SELECT | 993 GENCONF_PORT_CTRL0_RX_DATA_SAMPLE; 994 regmap_write(priv->sysctrl_base, GENCONF_PORT_CTRL0, val); 995 996 if (port->gop_id > 1) { 997 regmap_read(priv->sysctrl_base, GENCONF_CTRL0, &val); 998 if (port->gop_id == 2) 999 val &= ~GENCONF_CTRL0_PORT0_RGMII; 1000 else if (port->gop_id == 3) 1001 val &= ~GENCONF_CTRL0_PORT1_RGMII_MII; 1002 regmap_write(priv->sysctrl_base, GENCONF_CTRL0, val); 1003 } 1004 } 1005 1006 static void mvpp22_gop_init_10gkr(struct mvpp2_port *port) 1007 { 1008 struct mvpp2 *priv = port->priv; 1009 void __iomem *mpcs = priv->iface_base + MVPP22_MPCS_BASE(port->gop_id); 1010 void __iomem *xpcs = priv->iface_base + MVPP22_XPCS_BASE(port->gop_id); 1011 u32 val; 1012 1013 /* XPCS */ 1014 val = readl(xpcs + MVPP22_XPCS_CFG0); 1015 val &= ~(MVPP22_XPCS_CFG0_PCS_MODE(0x3) | 1016 MVPP22_XPCS_CFG0_ACTIVE_LANE(0x3)); 1017 val |= MVPP22_XPCS_CFG0_ACTIVE_LANE(2); 1018 writel(val, xpcs + MVPP22_XPCS_CFG0); 1019 1020 /* MPCS */ 1021 val = readl(mpcs + MVPP22_MPCS_CTRL); 1022 val &= ~MVPP22_MPCS_CTRL_FWD_ERR_CONN; 1023 writel(val, mpcs + MVPP22_MPCS_CTRL); 1024 1025 val = readl(mpcs + MVPP22_MPCS_CLK_RESET); 1026 val &= ~(MVPP22_MPCS_CLK_RESET_DIV_RATIO(0x7) | MAC_CLK_RESET_MAC | 1027 MAC_CLK_RESET_SD_RX | MAC_CLK_RESET_SD_TX); 1028 val |= MVPP22_MPCS_CLK_RESET_DIV_RATIO(1); 1029 writel(val, mpcs + MVPP22_MPCS_CLK_RESET); 1030 1031 val &= ~MVPP22_MPCS_CLK_RESET_DIV_SET; 1032 val |= MAC_CLK_RESET_MAC | MAC_CLK_RESET_SD_RX | MAC_CLK_RESET_SD_TX; 1033 writel(val, mpcs + MVPP22_MPCS_CLK_RESET); 1034 } 1035 1036 static int mvpp22_gop_init(struct mvpp2_port *port) 1037 { 1038 struct mvpp2 *priv = port->priv; 1039 u32 val; 1040 1041 if (!priv->sysctrl_base) 1042 return 0; 1043 1044 switch (port->phy_interface) { 1045 case PHY_INTERFACE_MODE_RGMII: 1046 case PHY_INTERFACE_MODE_RGMII_ID: 1047 case PHY_INTERFACE_MODE_RGMII_RXID: 1048 case PHY_INTERFACE_MODE_RGMII_TXID: 1049 if (port->gop_id == 0) 1050 goto invalid_conf; 1051 mvpp22_gop_init_rgmii(port); 1052 break; 1053 case PHY_INTERFACE_MODE_SGMII: 1054 case PHY_INTERFACE_MODE_1000BASEX: 1055 case PHY_INTERFACE_MODE_2500BASEX: 1056 mvpp22_gop_init_sgmii(port); 1057 break; 1058 case PHY_INTERFACE_MODE_10GKR: 1059 if (port->gop_id != 0) 1060 goto invalid_conf; 1061 mvpp22_gop_init_10gkr(port); 1062 break; 1063 default: 1064 goto unsupported_conf; 1065 } 1066 1067 regmap_read(priv->sysctrl_base, GENCONF_PORT_CTRL1, &val); 1068 val |= GENCONF_PORT_CTRL1_RESET(port->gop_id) | 1069 GENCONF_PORT_CTRL1_EN(port->gop_id); 1070 regmap_write(priv->sysctrl_base, GENCONF_PORT_CTRL1, val); 1071 1072 regmap_read(priv->sysctrl_base, GENCONF_PORT_CTRL0, &val); 1073 val |= GENCONF_PORT_CTRL0_CLK_DIV_PHASE_CLR; 1074 regmap_write(priv->sysctrl_base, GENCONF_PORT_CTRL0, val); 1075 1076 regmap_read(priv->sysctrl_base, GENCONF_SOFT_RESET1, &val); 1077 val |= GENCONF_SOFT_RESET1_GOP; 1078 regmap_write(priv->sysctrl_base, GENCONF_SOFT_RESET1, val); 1079 1080 unsupported_conf: 1081 return 0; 1082 1083 invalid_conf: 1084 netdev_err(port->dev, "Invalid port configuration\n"); 1085 return -EINVAL; 1086 } 1087 1088 static void mvpp22_gop_unmask_irq(struct mvpp2_port *port) 1089 { 1090 u32 val; 1091 1092 if (phy_interface_mode_is_rgmii(port->phy_interface) || 1093 port->phy_interface == PHY_INTERFACE_MODE_SGMII || 1094 port->phy_interface == PHY_INTERFACE_MODE_1000BASEX || 1095 port->phy_interface == PHY_INTERFACE_MODE_2500BASEX) { 1096 /* Enable the GMAC link status irq for this port */ 1097 val = readl(port->base + MVPP22_GMAC_INT_SUM_MASK); 1098 val |= MVPP22_GMAC_INT_SUM_MASK_LINK_STAT; 1099 writel(val, port->base + MVPP22_GMAC_INT_SUM_MASK); 1100 } 1101 1102 if (port->gop_id == 0) { 1103 /* Enable the XLG/GIG irqs for this port */ 1104 val = readl(port->base + MVPP22_XLG_EXT_INT_MASK); 1105 if (port->phy_interface == PHY_INTERFACE_MODE_10GKR) 1106 val |= MVPP22_XLG_EXT_INT_MASK_XLG; 1107 else 1108 val |= MVPP22_XLG_EXT_INT_MASK_GIG; 1109 writel(val, port->base + MVPP22_XLG_EXT_INT_MASK); 1110 } 1111 } 1112 1113 static void mvpp22_gop_mask_irq(struct mvpp2_port *port) 1114 { 1115 u32 val; 1116 1117 if (port->gop_id == 0) { 1118 val = readl(port->base + MVPP22_XLG_EXT_INT_MASK); 1119 val &= ~(MVPP22_XLG_EXT_INT_MASK_XLG | 1120 MVPP22_XLG_EXT_INT_MASK_GIG); 1121 writel(val, port->base + MVPP22_XLG_EXT_INT_MASK); 1122 } 1123 1124 if (phy_interface_mode_is_rgmii(port->phy_interface) || 1125 port->phy_interface == PHY_INTERFACE_MODE_SGMII || 1126 port->phy_interface == PHY_INTERFACE_MODE_1000BASEX || 1127 port->phy_interface == PHY_INTERFACE_MODE_2500BASEX) { 1128 val = readl(port->base + MVPP22_GMAC_INT_SUM_MASK); 1129 val &= ~MVPP22_GMAC_INT_SUM_MASK_LINK_STAT; 1130 writel(val, port->base + MVPP22_GMAC_INT_SUM_MASK); 1131 } 1132 } 1133 1134 static void mvpp22_gop_setup_irq(struct mvpp2_port *port) 1135 { 1136 u32 val; 1137 1138 if (phy_interface_mode_is_rgmii(port->phy_interface) || 1139 port->phy_interface == PHY_INTERFACE_MODE_SGMII || 1140 port->phy_interface == PHY_INTERFACE_MODE_1000BASEX || 1141 port->phy_interface == PHY_INTERFACE_MODE_2500BASEX) { 1142 val = readl(port->base + MVPP22_GMAC_INT_MASK); 1143 val |= MVPP22_GMAC_INT_MASK_LINK_STAT; 1144 writel(val, port->base + MVPP22_GMAC_INT_MASK); 1145 } 1146 1147 if (port->gop_id == 0) { 1148 val = readl(port->base + MVPP22_XLG_INT_MASK); 1149 val |= MVPP22_XLG_INT_MASK_LINK; 1150 writel(val, port->base + MVPP22_XLG_INT_MASK); 1151 } 1152 1153 mvpp22_gop_unmask_irq(port); 1154 } 1155 1156 /* Sets the PHY mode of the COMPHY (which configures the serdes lanes). 1157 * 1158 * The PHY mode used by the PPv2 driver comes from the network subsystem, while 1159 * the one given to the COMPHY comes from the generic PHY subsystem. Hence they 1160 * differ. 1161 * 1162 * The COMPHY configures the serdes lanes regardless of the actual use of the 1163 * lanes by the physical layer. This is why configurations like 1164 * "PPv2 (2500BaseX) - COMPHY (2500SGMII)" are valid. 1165 */ 1166 static int mvpp22_comphy_init(struct mvpp2_port *port) 1167 { 1168 enum phy_mode mode; 1169 int ret; 1170 1171 if (!port->comphy) 1172 return 0; 1173 1174 switch (port->phy_interface) { 1175 case PHY_INTERFACE_MODE_SGMII: 1176 case PHY_INTERFACE_MODE_1000BASEX: 1177 mode = PHY_MODE_SGMII; 1178 break; 1179 case PHY_INTERFACE_MODE_2500BASEX: 1180 mode = PHY_MODE_2500SGMII; 1181 break; 1182 case PHY_INTERFACE_MODE_10GKR: 1183 mode = PHY_MODE_10GKR; 1184 break; 1185 default: 1186 return -EINVAL; 1187 } 1188 1189 ret = phy_set_mode(port->comphy, mode); 1190 if (ret) 1191 return ret; 1192 1193 return phy_power_on(port->comphy); 1194 } 1195 1196 static void mvpp2_port_enable(struct mvpp2_port *port) 1197 { 1198 u32 val; 1199 1200 /* Only GOP port 0 has an XLG MAC */ 1201 if (port->gop_id == 0 && 1202 (port->phy_interface == PHY_INTERFACE_MODE_XAUI || 1203 port->phy_interface == PHY_INTERFACE_MODE_10GKR)) { 1204 val = readl(port->base + MVPP22_XLG_CTRL0_REG); 1205 val |= MVPP22_XLG_CTRL0_PORT_EN | 1206 MVPP22_XLG_CTRL0_MAC_RESET_DIS; 1207 val &= ~MVPP22_XLG_CTRL0_MIB_CNT_DIS; 1208 writel(val, port->base + MVPP22_XLG_CTRL0_REG); 1209 } else { 1210 val = readl(port->base + MVPP2_GMAC_CTRL_0_REG); 1211 val |= MVPP2_GMAC_PORT_EN_MASK; 1212 val |= MVPP2_GMAC_MIB_CNTR_EN_MASK; 1213 writel(val, port->base + MVPP2_GMAC_CTRL_0_REG); 1214 } 1215 } 1216 1217 static void mvpp2_port_disable(struct mvpp2_port *port) 1218 { 1219 u32 val; 1220 1221 /* Only GOP port 0 has an XLG MAC */ 1222 if (port->gop_id == 0 && 1223 (port->phy_interface == PHY_INTERFACE_MODE_XAUI || 1224 port->phy_interface == PHY_INTERFACE_MODE_10GKR)) { 1225 val = readl(port->base + MVPP22_XLG_CTRL0_REG); 1226 val &= ~MVPP22_XLG_CTRL0_PORT_EN; 1227 writel(val, port->base + MVPP22_XLG_CTRL0_REG); 1228 1229 /* Disable & reset should be done separately */ 1230 val &= ~MVPP22_XLG_CTRL0_MAC_RESET_DIS; 1231 writel(val, port->base + MVPP22_XLG_CTRL0_REG); 1232 } else { 1233 val = readl(port->base + MVPP2_GMAC_CTRL_0_REG); 1234 val &= ~(MVPP2_GMAC_PORT_EN_MASK); 1235 writel(val, port->base + MVPP2_GMAC_CTRL_0_REG); 1236 } 1237 } 1238 1239 /* Set IEEE 802.3x Flow Control Xon Packet Transmission Mode */ 1240 static void mvpp2_port_periodic_xon_disable(struct mvpp2_port *port) 1241 { 1242 u32 val; 1243 1244 val = readl(port->base + MVPP2_GMAC_CTRL_1_REG) & 1245 ~MVPP2_GMAC_PERIODIC_XON_EN_MASK; 1246 writel(val, port->base + MVPP2_GMAC_CTRL_1_REG); 1247 } 1248 1249 /* Configure loopback port */ 1250 static void mvpp2_port_loopback_set(struct mvpp2_port *port, 1251 const struct phylink_link_state *state) 1252 { 1253 u32 val; 1254 1255 val = readl(port->base + MVPP2_GMAC_CTRL_1_REG); 1256 1257 if (state->speed == 1000) 1258 val |= MVPP2_GMAC_GMII_LB_EN_MASK; 1259 else 1260 val &= ~MVPP2_GMAC_GMII_LB_EN_MASK; 1261 1262 if (port->phy_interface == PHY_INTERFACE_MODE_SGMII || 1263 port->phy_interface == PHY_INTERFACE_MODE_1000BASEX || 1264 port->phy_interface == PHY_INTERFACE_MODE_2500BASEX) 1265 val |= MVPP2_GMAC_PCS_LB_EN_MASK; 1266 else 1267 val &= ~MVPP2_GMAC_PCS_LB_EN_MASK; 1268 1269 writel(val, port->base + MVPP2_GMAC_CTRL_1_REG); 1270 } 1271 1272 struct mvpp2_ethtool_counter { 1273 unsigned int offset; 1274 const char string[ETH_GSTRING_LEN]; 1275 bool reg_is_64b; 1276 }; 1277 1278 static u64 mvpp2_read_count(struct mvpp2_port *port, 1279 const struct mvpp2_ethtool_counter *counter) 1280 { 1281 u64 val; 1282 1283 val = readl(port->stats_base + counter->offset); 1284 if (counter->reg_is_64b) 1285 val += (u64)readl(port->stats_base + counter->offset + 4) << 32; 1286 1287 return val; 1288 } 1289 1290 /* Due to the fact that software statistics and hardware statistics are, by 1291 * design, incremented at different moments in the chain of packet processing, 1292 * it is very likely that incoming packets could have been dropped after being 1293 * counted by hardware but before reaching software statistics (most probably 1294 * multicast packets), and in the oppposite way, during transmission, FCS bytes 1295 * are added in between as well as TSO skb will be split and header bytes added. 1296 * Hence, statistics gathered from userspace with ifconfig (software) and 1297 * ethtool (hardware) cannot be compared. 1298 */ 1299 static const struct mvpp2_ethtool_counter mvpp2_ethtool_regs[] = { 1300 { MVPP2_MIB_GOOD_OCTETS_RCVD, "good_octets_received", true }, 1301 { MVPP2_MIB_BAD_OCTETS_RCVD, "bad_octets_received" }, 1302 { MVPP2_MIB_CRC_ERRORS_SENT, "crc_errors_sent" }, 1303 { MVPP2_MIB_UNICAST_FRAMES_RCVD, "unicast_frames_received" }, 1304 { MVPP2_MIB_BROADCAST_FRAMES_RCVD, "broadcast_frames_received" }, 1305 { MVPP2_MIB_MULTICAST_FRAMES_RCVD, "multicast_frames_received" }, 1306 { MVPP2_MIB_FRAMES_64_OCTETS, "frames_64_octets" }, 1307 { MVPP2_MIB_FRAMES_65_TO_127_OCTETS, "frames_65_to_127_octet" }, 1308 { MVPP2_MIB_FRAMES_128_TO_255_OCTETS, "frames_128_to_255_octet" }, 1309 { MVPP2_MIB_FRAMES_256_TO_511_OCTETS, "frames_256_to_511_octet" }, 1310 { MVPP2_MIB_FRAMES_512_TO_1023_OCTETS, "frames_512_to_1023_octet" }, 1311 { MVPP2_MIB_FRAMES_1024_TO_MAX_OCTETS, "frames_1024_to_max_octet" }, 1312 { MVPP2_MIB_GOOD_OCTETS_SENT, "good_octets_sent", true }, 1313 { MVPP2_MIB_UNICAST_FRAMES_SENT, "unicast_frames_sent" }, 1314 { MVPP2_MIB_MULTICAST_FRAMES_SENT, "multicast_frames_sent" }, 1315 { MVPP2_MIB_BROADCAST_FRAMES_SENT, "broadcast_frames_sent" }, 1316 { MVPP2_MIB_FC_SENT, "fc_sent" }, 1317 { MVPP2_MIB_FC_RCVD, "fc_received" }, 1318 { MVPP2_MIB_RX_FIFO_OVERRUN, "rx_fifo_overrun" }, 1319 { MVPP2_MIB_UNDERSIZE_RCVD, "undersize_received" }, 1320 { MVPP2_MIB_FRAGMENTS_RCVD, "fragments_received" }, 1321 { MVPP2_MIB_OVERSIZE_RCVD, "oversize_received" }, 1322 { MVPP2_MIB_JABBER_RCVD, "jabber_received" }, 1323 { MVPP2_MIB_MAC_RCV_ERROR, "mac_receive_error" }, 1324 { MVPP2_MIB_BAD_CRC_EVENT, "bad_crc_event" }, 1325 { MVPP2_MIB_COLLISION, "collision" }, 1326 { MVPP2_MIB_LATE_COLLISION, "late_collision" }, 1327 }; 1328 1329 static void mvpp2_ethtool_get_strings(struct net_device *netdev, u32 sset, 1330 u8 *data) 1331 { 1332 if (sset == ETH_SS_STATS) { 1333 int i; 1334 1335 for (i = 0; i < ARRAY_SIZE(mvpp2_ethtool_regs); i++) 1336 memcpy(data + i * ETH_GSTRING_LEN, 1337 &mvpp2_ethtool_regs[i].string, ETH_GSTRING_LEN); 1338 } 1339 } 1340 1341 static void mvpp2_gather_hw_statistics(struct work_struct *work) 1342 { 1343 struct delayed_work *del_work = to_delayed_work(work); 1344 struct mvpp2_port *port = container_of(del_work, struct mvpp2_port, 1345 stats_work); 1346 u64 *pstats; 1347 int i; 1348 1349 mutex_lock(&port->gather_stats_lock); 1350 1351 pstats = port->ethtool_stats; 1352 for (i = 0; i < ARRAY_SIZE(mvpp2_ethtool_regs); i++) 1353 *pstats++ += mvpp2_read_count(port, &mvpp2_ethtool_regs[i]); 1354 1355 /* No need to read again the counters right after this function if it 1356 * was called asynchronously by the user (ie. use of ethtool). 1357 */ 1358 cancel_delayed_work(&port->stats_work); 1359 queue_delayed_work(port->priv->stats_queue, &port->stats_work, 1360 MVPP2_MIB_COUNTERS_STATS_DELAY); 1361 1362 mutex_unlock(&port->gather_stats_lock); 1363 } 1364 1365 static void mvpp2_ethtool_get_stats(struct net_device *dev, 1366 struct ethtool_stats *stats, u64 *data) 1367 { 1368 struct mvpp2_port *port = netdev_priv(dev); 1369 1370 /* Update statistics for the given port, then take the lock to avoid 1371 * concurrent accesses on the ethtool_stats structure during its copy. 1372 */ 1373 mvpp2_gather_hw_statistics(&port->stats_work.work); 1374 1375 mutex_lock(&port->gather_stats_lock); 1376 memcpy(data, port->ethtool_stats, 1377 sizeof(u64) * ARRAY_SIZE(mvpp2_ethtool_regs)); 1378 mutex_unlock(&port->gather_stats_lock); 1379 } 1380 1381 static int mvpp2_ethtool_get_sset_count(struct net_device *dev, int sset) 1382 { 1383 if (sset == ETH_SS_STATS) 1384 return ARRAY_SIZE(mvpp2_ethtool_regs); 1385 1386 return -EOPNOTSUPP; 1387 } 1388 1389 static void mvpp2_port_reset(struct mvpp2_port *port) 1390 { 1391 u32 val; 1392 unsigned int i; 1393 1394 /* Read the GOP statistics to reset the hardware counters */ 1395 for (i = 0; i < ARRAY_SIZE(mvpp2_ethtool_regs); i++) 1396 mvpp2_read_count(port, &mvpp2_ethtool_regs[i]); 1397 1398 val = readl(port->base + MVPP2_GMAC_CTRL_2_REG) & 1399 ~MVPP2_GMAC_PORT_RESET_MASK; 1400 writel(val, port->base + MVPP2_GMAC_CTRL_2_REG); 1401 1402 while (readl(port->base + MVPP2_GMAC_CTRL_2_REG) & 1403 MVPP2_GMAC_PORT_RESET_MASK) 1404 continue; 1405 } 1406 1407 /* Change maximum receive size of the port */ 1408 static inline void mvpp2_gmac_max_rx_size_set(struct mvpp2_port *port) 1409 { 1410 u32 val; 1411 1412 val = readl(port->base + MVPP2_GMAC_CTRL_0_REG); 1413 val &= ~MVPP2_GMAC_MAX_RX_SIZE_MASK; 1414 val |= (((port->pkt_size - MVPP2_MH_SIZE) / 2) << 1415 MVPP2_GMAC_MAX_RX_SIZE_OFFS); 1416 writel(val, port->base + MVPP2_GMAC_CTRL_0_REG); 1417 } 1418 1419 /* Change maximum receive size of the port */ 1420 static inline void mvpp2_xlg_max_rx_size_set(struct mvpp2_port *port) 1421 { 1422 u32 val; 1423 1424 val = readl(port->base + MVPP22_XLG_CTRL1_REG); 1425 val &= ~MVPP22_XLG_CTRL1_FRAMESIZELIMIT_MASK; 1426 val |= ((port->pkt_size - MVPP2_MH_SIZE) / 2) << 1427 MVPP22_XLG_CTRL1_FRAMESIZELIMIT_OFFS; 1428 writel(val, port->base + MVPP22_XLG_CTRL1_REG); 1429 } 1430 1431 /* Set defaults to the MVPP2 port */ 1432 static void mvpp2_defaults_set(struct mvpp2_port *port) 1433 { 1434 int tx_port_num, val, queue, ptxq, lrxq; 1435 1436 if (port->priv->hw_version == MVPP21) { 1437 /* Update TX FIFO MIN Threshold */ 1438 val = readl(port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG); 1439 val &= ~MVPP2_GMAC_TX_FIFO_MIN_TH_ALL_MASK; 1440 /* Min. TX threshold must be less than minimal packet length */ 1441 val |= MVPP2_GMAC_TX_FIFO_MIN_TH_MASK(64 - 4 - 2); 1442 writel(val, port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG); 1443 } 1444 1445 /* Disable Legacy WRR, Disable EJP, Release from reset */ 1446 tx_port_num = mvpp2_egress_port(port); 1447 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, 1448 tx_port_num); 1449 mvpp2_write(port->priv, MVPP2_TXP_SCHED_CMD_1_REG, 0); 1450 1451 /* Set TXQ scheduling to Round-Robin */ 1452 mvpp2_write(port->priv, MVPP2_TXP_SCHED_FIXED_PRIO_REG, 0); 1453 1454 /* Close bandwidth for all queues */ 1455 for (queue = 0; queue < MVPP2_MAX_TXQ; queue++) { 1456 ptxq = mvpp2_txq_phys(port->id, queue); 1457 mvpp2_write(port->priv, 1458 MVPP2_TXQ_SCHED_TOKEN_CNTR_REG(ptxq), 0); 1459 } 1460 1461 /* Set refill period to 1 usec, refill tokens 1462 * and bucket size to maximum 1463 */ 1464 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PERIOD_REG, 1465 port->priv->tclk / USEC_PER_SEC); 1466 val = mvpp2_read(port->priv, MVPP2_TXP_SCHED_REFILL_REG); 1467 val &= ~MVPP2_TXP_REFILL_PERIOD_ALL_MASK; 1468 val |= MVPP2_TXP_REFILL_PERIOD_MASK(1); 1469 val |= MVPP2_TXP_REFILL_TOKENS_ALL_MASK; 1470 mvpp2_write(port->priv, MVPP2_TXP_SCHED_REFILL_REG, val); 1471 val = MVPP2_TXP_TOKEN_SIZE_MAX; 1472 mvpp2_write(port->priv, MVPP2_TXP_SCHED_TOKEN_SIZE_REG, val); 1473 1474 /* Set MaximumLowLatencyPacketSize value to 256 */ 1475 mvpp2_write(port->priv, MVPP2_RX_CTRL_REG(port->id), 1476 MVPP2_RX_USE_PSEUDO_FOR_CSUM_MASK | 1477 MVPP2_RX_LOW_LATENCY_PKT_SIZE(256)); 1478 1479 /* Enable Rx cache snoop */ 1480 for (lrxq = 0; lrxq < port->nrxqs; lrxq++) { 1481 queue = port->rxqs[lrxq]->id; 1482 val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(queue)); 1483 val |= MVPP2_SNOOP_PKT_SIZE_MASK | 1484 MVPP2_SNOOP_BUF_HDR_MASK; 1485 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(queue), val); 1486 } 1487 1488 /* At default, mask all interrupts to all present cpus */ 1489 mvpp2_interrupts_disable(port); 1490 } 1491 1492 /* Enable/disable receiving packets */ 1493 static void mvpp2_ingress_enable(struct mvpp2_port *port) 1494 { 1495 u32 val; 1496 int lrxq, queue; 1497 1498 for (lrxq = 0; lrxq < port->nrxqs; lrxq++) { 1499 queue = port->rxqs[lrxq]->id; 1500 val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(queue)); 1501 val &= ~MVPP2_RXQ_DISABLE_MASK; 1502 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(queue), val); 1503 } 1504 } 1505 1506 static void mvpp2_ingress_disable(struct mvpp2_port *port) 1507 { 1508 u32 val; 1509 int lrxq, queue; 1510 1511 for (lrxq = 0; lrxq < port->nrxqs; lrxq++) { 1512 queue = port->rxqs[lrxq]->id; 1513 val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(queue)); 1514 val |= MVPP2_RXQ_DISABLE_MASK; 1515 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(queue), val); 1516 } 1517 } 1518 1519 /* Enable transmit via physical egress queue 1520 * - HW starts take descriptors from DRAM 1521 */ 1522 static void mvpp2_egress_enable(struct mvpp2_port *port) 1523 { 1524 u32 qmap; 1525 int queue; 1526 int tx_port_num = mvpp2_egress_port(port); 1527 1528 /* Enable all initialized TXs. */ 1529 qmap = 0; 1530 for (queue = 0; queue < port->ntxqs; queue++) { 1531 struct mvpp2_tx_queue *txq = port->txqs[queue]; 1532 1533 if (txq->descs) 1534 qmap |= (1 << queue); 1535 } 1536 1537 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num); 1538 mvpp2_write(port->priv, MVPP2_TXP_SCHED_Q_CMD_REG, qmap); 1539 } 1540 1541 /* Disable transmit via physical egress queue 1542 * - HW doesn't take descriptors from DRAM 1543 */ 1544 static void mvpp2_egress_disable(struct mvpp2_port *port) 1545 { 1546 u32 reg_data; 1547 int delay; 1548 int tx_port_num = mvpp2_egress_port(port); 1549 1550 /* Issue stop command for active channels only */ 1551 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num); 1552 reg_data = (mvpp2_read(port->priv, MVPP2_TXP_SCHED_Q_CMD_REG)) & 1553 MVPP2_TXP_SCHED_ENQ_MASK; 1554 if (reg_data != 0) 1555 mvpp2_write(port->priv, MVPP2_TXP_SCHED_Q_CMD_REG, 1556 (reg_data << MVPP2_TXP_SCHED_DISQ_OFFSET)); 1557 1558 /* Wait for all Tx activity to terminate. */ 1559 delay = 0; 1560 do { 1561 if (delay >= MVPP2_TX_DISABLE_TIMEOUT_MSEC) { 1562 netdev_warn(port->dev, 1563 "Tx stop timed out, status=0x%08x\n", 1564 reg_data); 1565 break; 1566 } 1567 mdelay(1); 1568 delay++; 1569 1570 /* Check port TX Command register that all 1571 * Tx queues are stopped 1572 */ 1573 reg_data = mvpp2_read(port->priv, MVPP2_TXP_SCHED_Q_CMD_REG); 1574 } while (reg_data & MVPP2_TXP_SCHED_ENQ_MASK); 1575 } 1576 1577 /* Rx descriptors helper methods */ 1578 1579 /* Get number of Rx descriptors occupied by received packets */ 1580 static inline int 1581 mvpp2_rxq_received(struct mvpp2_port *port, int rxq_id) 1582 { 1583 u32 val = mvpp2_read(port->priv, MVPP2_RXQ_STATUS_REG(rxq_id)); 1584 1585 return val & MVPP2_RXQ_OCCUPIED_MASK; 1586 } 1587 1588 /* Update Rx queue status with the number of occupied and available 1589 * Rx descriptor slots. 1590 */ 1591 static inline void 1592 mvpp2_rxq_status_update(struct mvpp2_port *port, int rxq_id, 1593 int used_count, int free_count) 1594 { 1595 /* Decrement the number of used descriptors and increment count 1596 * increment the number of free descriptors. 1597 */ 1598 u32 val = used_count | (free_count << MVPP2_RXQ_NUM_NEW_OFFSET); 1599 1600 mvpp2_write(port->priv, MVPP2_RXQ_STATUS_UPDATE_REG(rxq_id), val); 1601 } 1602 1603 /* Get pointer to next RX descriptor to be processed by SW */ 1604 static inline struct mvpp2_rx_desc * 1605 mvpp2_rxq_next_desc_get(struct mvpp2_rx_queue *rxq) 1606 { 1607 int rx_desc = rxq->next_desc_to_proc; 1608 1609 rxq->next_desc_to_proc = MVPP2_QUEUE_NEXT_DESC(rxq, rx_desc); 1610 prefetch(rxq->descs + rxq->next_desc_to_proc); 1611 return rxq->descs + rx_desc; 1612 } 1613 1614 /* Set rx queue offset */ 1615 static void mvpp2_rxq_offset_set(struct mvpp2_port *port, 1616 int prxq, int offset) 1617 { 1618 u32 val; 1619 1620 /* Convert offset from bytes to units of 32 bytes */ 1621 offset = offset >> 5; 1622 1623 val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(prxq)); 1624 val &= ~MVPP2_RXQ_PACKET_OFFSET_MASK; 1625 1626 /* Offset is in */ 1627 val |= ((offset << MVPP2_RXQ_PACKET_OFFSET_OFFS) & 1628 MVPP2_RXQ_PACKET_OFFSET_MASK); 1629 1630 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(prxq), val); 1631 } 1632 1633 /* Tx descriptors helper methods */ 1634 1635 /* Get pointer to next Tx descriptor to be processed (send) by HW */ 1636 static struct mvpp2_tx_desc * 1637 mvpp2_txq_next_desc_get(struct mvpp2_tx_queue *txq) 1638 { 1639 int tx_desc = txq->next_desc_to_proc; 1640 1641 txq->next_desc_to_proc = MVPP2_QUEUE_NEXT_DESC(txq, tx_desc); 1642 return txq->descs + tx_desc; 1643 } 1644 1645 /* Update HW with number of aggregated Tx descriptors to be sent 1646 * 1647 * Called only from mvpp2_tx(), so migration is disabled, using 1648 * smp_processor_id() is OK. 1649 */ 1650 static void mvpp2_aggr_txq_pend_desc_add(struct mvpp2_port *port, int pending) 1651 { 1652 /* aggregated access - relevant TXQ number is written in TX desc */ 1653 mvpp2_thread_write(port->priv, 1654 mvpp2_cpu_to_thread(port->priv, smp_processor_id()), 1655 MVPP2_AGGR_TXQ_UPDATE_REG, pending); 1656 } 1657 1658 /* Check if there are enough free descriptors in aggregated txq. 1659 * If not, update the number of occupied descriptors and repeat the check. 1660 * 1661 * Called only from mvpp2_tx(), so migration is disabled, using 1662 * smp_processor_id() is OK. 1663 */ 1664 static int mvpp2_aggr_desc_num_check(struct mvpp2_port *port, 1665 struct mvpp2_tx_queue *aggr_txq, int num) 1666 { 1667 if ((aggr_txq->count + num) > MVPP2_AGGR_TXQ_SIZE) { 1668 /* Update number of occupied aggregated Tx descriptors */ 1669 unsigned int thread = 1670 mvpp2_cpu_to_thread(port->priv, smp_processor_id()); 1671 u32 val = mvpp2_read_relaxed(port->priv, 1672 MVPP2_AGGR_TXQ_STATUS_REG(thread)); 1673 1674 aggr_txq->count = val & MVPP2_AGGR_TXQ_PENDING_MASK; 1675 1676 if ((aggr_txq->count + num) > MVPP2_AGGR_TXQ_SIZE) 1677 return -ENOMEM; 1678 } 1679 return 0; 1680 } 1681 1682 /* Reserved Tx descriptors allocation request 1683 * 1684 * Called only from mvpp2_txq_reserved_desc_num_proc(), itself called 1685 * only by mvpp2_tx(), so migration is disabled, using 1686 * smp_processor_id() is OK. 1687 */ 1688 static int mvpp2_txq_alloc_reserved_desc(struct mvpp2_port *port, 1689 struct mvpp2_tx_queue *txq, int num) 1690 { 1691 unsigned int thread = mvpp2_cpu_to_thread(port->priv, smp_processor_id()); 1692 struct mvpp2 *priv = port->priv; 1693 u32 val; 1694 1695 val = (txq->id << MVPP2_TXQ_RSVD_REQ_Q_OFFSET) | num; 1696 mvpp2_thread_write_relaxed(priv, thread, MVPP2_TXQ_RSVD_REQ_REG, val); 1697 1698 val = mvpp2_thread_read_relaxed(priv, thread, MVPP2_TXQ_RSVD_RSLT_REG); 1699 1700 return val & MVPP2_TXQ_RSVD_RSLT_MASK; 1701 } 1702 1703 /* Check if there are enough reserved descriptors for transmission. 1704 * If not, request chunk of reserved descriptors and check again. 1705 */ 1706 static int mvpp2_txq_reserved_desc_num_proc(struct mvpp2_port *port, 1707 struct mvpp2_tx_queue *txq, 1708 struct mvpp2_txq_pcpu *txq_pcpu, 1709 int num) 1710 { 1711 int req, desc_count; 1712 unsigned int thread; 1713 1714 if (txq_pcpu->reserved_num >= num) 1715 return 0; 1716 1717 /* Not enough descriptors reserved! Update the reserved descriptor 1718 * count and check again. 1719 */ 1720 1721 desc_count = 0; 1722 /* Compute total of used descriptors */ 1723 for (thread = 0; thread < port->priv->nthreads; thread++) { 1724 struct mvpp2_txq_pcpu *txq_pcpu_aux; 1725 1726 txq_pcpu_aux = per_cpu_ptr(txq->pcpu, thread); 1727 desc_count += txq_pcpu_aux->count; 1728 desc_count += txq_pcpu_aux->reserved_num; 1729 } 1730 1731 req = max(MVPP2_CPU_DESC_CHUNK, num - txq_pcpu->reserved_num); 1732 desc_count += req; 1733 1734 if (desc_count > 1735 (txq->size - (MVPP2_MAX_THREADS * MVPP2_CPU_DESC_CHUNK))) 1736 return -ENOMEM; 1737 1738 txq_pcpu->reserved_num += mvpp2_txq_alloc_reserved_desc(port, txq, req); 1739 1740 /* OK, the descriptor could have been updated: check again. */ 1741 if (txq_pcpu->reserved_num < num) 1742 return -ENOMEM; 1743 return 0; 1744 } 1745 1746 /* Release the last allocated Tx descriptor. Useful to handle DMA 1747 * mapping failures in the Tx path. 1748 */ 1749 static void mvpp2_txq_desc_put(struct mvpp2_tx_queue *txq) 1750 { 1751 if (txq->next_desc_to_proc == 0) 1752 txq->next_desc_to_proc = txq->last_desc - 1; 1753 else 1754 txq->next_desc_to_proc--; 1755 } 1756 1757 /* Set Tx descriptors fields relevant for CSUM calculation */ 1758 static u32 mvpp2_txq_desc_csum(int l3_offs, __be16 l3_proto, 1759 int ip_hdr_len, int l4_proto) 1760 { 1761 u32 command; 1762 1763 /* fields: L3_offset, IP_hdrlen, L3_type, G_IPv4_chk, 1764 * G_L4_chk, L4_type required only for checksum calculation 1765 */ 1766 command = (l3_offs << MVPP2_TXD_L3_OFF_SHIFT); 1767 command |= (ip_hdr_len << MVPP2_TXD_IP_HLEN_SHIFT); 1768 command |= MVPP2_TXD_IP_CSUM_DISABLE; 1769 1770 if (l3_proto == htons(ETH_P_IP)) { 1771 command &= ~MVPP2_TXD_IP_CSUM_DISABLE; /* enable IPv4 csum */ 1772 command &= ~MVPP2_TXD_L3_IP6; /* enable IPv4 */ 1773 } else { 1774 command |= MVPP2_TXD_L3_IP6; /* enable IPv6 */ 1775 } 1776 1777 if (l4_proto == IPPROTO_TCP) { 1778 command &= ~MVPP2_TXD_L4_UDP; /* enable TCP */ 1779 command &= ~MVPP2_TXD_L4_CSUM_FRAG; /* generate L4 csum */ 1780 } else if (l4_proto == IPPROTO_UDP) { 1781 command |= MVPP2_TXD_L4_UDP; /* enable UDP */ 1782 command &= ~MVPP2_TXD_L4_CSUM_FRAG; /* generate L4 csum */ 1783 } else { 1784 command |= MVPP2_TXD_L4_CSUM_NOT; 1785 } 1786 1787 return command; 1788 } 1789 1790 /* Get number of sent descriptors and decrement counter. 1791 * The number of sent descriptors is returned. 1792 * Per-thread access 1793 * 1794 * Called only from mvpp2_txq_done(), called from mvpp2_tx() 1795 * (migration disabled) and from the TX completion tasklet (migration 1796 * disabled) so using smp_processor_id() is OK. 1797 */ 1798 static inline int mvpp2_txq_sent_desc_proc(struct mvpp2_port *port, 1799 struct mvpp2_tx_queue *txq) 1800 { 1801 u32 val; 1802 1803 /* Reading status reg resets transmitted descriptor counter */ 1804 val = mvpp2_thread_read_relaxed(port->priv, 1805 mvpp2_cpu_to_thread(port->priv, smp_processor_id()), 1806 MVPP2_TXQ_SENT_REG(txq->id)); 1807 1808 return (val & MVPP2_TRANSMITTED_COUNT_MASK) >> 1809 MVPP2_TRANSMITTED_COUNT_OFFSET; 1810 } 1811 1812 /* Called through on_each_cpu(), so runs on all CPUs, with migration 1813 * disabled, therefore using smp_processor_id() is OK. 1814 */ 1815 static void mvpp2_txq_sent_counter_clear(void *arg) 1816 { 1817 struct mvpp2_port *port = arg; 1818 int queue; 1819 1820 /* If the thread isn't used, don't do anything */ 1821 if (smp_processor_id() > port->priv->nthreads) 1822 return; 1823 1824 for (queue = 0; queue < port->ntxqs; queue++) { 1825 int id = port->txqs[queue]->id; 1826 1827 mvpp2_thread_read(port->priv, 1828 mvpp2_cpu_to_thread(port->priv, smp_processor_id()), 1829 MVPP2_TXQ_SENT_REG(id)); 1830 } 1831 } 1832 1833 /* Set max sizes for Tx queues */ 1834 static void mvpp2_txp_max_tx_size_set(struct mvpp2_port *port) 1835 { 1836 u32 val, size, mtu; 1837 int txq, tx_port_num; 1838 1839 mtu = port->pkt_size * 8; 1840 if (mtu > MVPP2_TXP_MTU_MAX) 1841 mtu = MVPP2_TXP_MTU_MAX; 1842 1843 /* WA for wrong Token bucket update: Set MTU value = 3*real MTU value */ 1844 mtu = 3 * mtu; 1845 1846 /* Indirect access to registers */ 1847 tx_port_num = mvpp2_egress_port(port); 1848 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num); 1849 1850 /* Set MTU */ 1851 val = mvpp2_read(port->priv, MVPP2_TXP_SCHED_MTU_REG); 1852 val &= ~MVPP2_TXP_MTU_MAX; 1853 val |= mtu; 1854 mvpp2_write(port->priv, MVPP2_TXP_SCHED_MTU_REG, val); 1855 1856 /* TXP token size and all TXQs token size must be larger that MTU */ 1857 val = mvpp2_read(port->priv, MVPP2_TXP_SCHED_TOKEN_SIZE_REG); 1858 size = val & MVPP2_TXP_TOKEN_SIZE_MAX; 1859 if (size < mtu) { 1860 size = mtu; 1861 val &= ~MVPP2_TXP_TOKEN_SIZE_MAX; 1862 val |= size; 1863 mvpp2_write(port->priv, MVPP2_TXP_SCHED_TOKEN_SIZE_REG, val); 1864 } 1865 1866 for (txq = 0; txq < port->ntxqs; txq++) { 1867 val = mvpp2_read(port->priv, 1868 MVPP2_TXQ_SCHED_TOKEN_SIZE_REG(txq)); 1869 size = val & MVPP2_TXQ_TOKEN_SIZE_MAX; 1870 1871 if (size < mtu) { 1872 size = mtu; 1873 val &= ~MVPP2_TXQ_TOKEN_SIZE_MAX; 1874 val |= size; 1875 mvpp2_write(port->priv, 1876 MVPP2_TXQ_SCHED_TOKEN_SIZE_REG(txq), 1877 val); 1878 } 1879 } 1880 } 1881 1882 /* Set the number of packets that will be received before Rx interrupt 1883 * will be generated by HW. 1884 */ 1885 static void mvpp2_rx_pkts_coal_set(struct mvpp2_port *port, 1886 struct mvpp2_rx_queue *rxq) 1887 { 1888 unsigned int thread = mvpp2_cpu_to_thread(port->priv, get_cpu()); 1889 1890 if (rxq->pkts_coal > MVPP2_OCCUPIED_THRESH_MASK) 1891 rxq->pkts_coal = MVPP2_OCCUPIED_THRESH_MASK; 1892 1893 mvpp2_thread_write(port->priv, thread, MVPP2_RXQ_NUM_REG, rxq->id); 1894 mvpp2_thread_write(port->priv, thread, MVPP2_RXQ_THRESH_REG, 1895 rxq->pkts_coal); 1896 1897 put_cpu(); 1898 } 1899 1900 /* For some reason in the LSP this is done on each CPU. Why ? */ 1901 static void mvpp2_tx_pkts_coal_set(struct mvpp2_port *port, 1902 struct mvpp2_tx_queue *txq) 1903 { 1904 unsigned int thread = mvpp2_cpu_to_thread(port->priv, get_cpu()); 1905 u32 val; 1906 1907 if (txq->done_pkts_coal > MVPP2_TXQ_THRESH_MASK) 1908 txq->done_pkts_coal = MVPP2_TXQ_THRESH_MASK; 1909 1910 val = (txq->done_pkts_coal << MVPP2_TXQ_THRESH_OFFSET); 1911 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_NUM_REG, txq->id); 1912 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_THRESH_REG, val); 1913 1914 put_cpu(); 1915 } 1916 1917 static u32 mvpp2_usec_to_cycles(u32 usec, unsigned long clk_hz) 1918 { 1919 u64 tmp = (u64)clk_hz * usec; 1920 1921 do_div(tmp, USEC_PER_SEC); 1922 1923 return tmp > U32_MAX ? U32_MAX : tmp; 1924 } 1925 1926 static u32 mvpp2_cycles_to_usec(u32 cycles, unsigned long clk_hz) 1927 { 1928 u64 tmp = (u64)cycles * USEC_PER_SEC; 1929 1930 do_div(tmp, clk_hz); 1931 1932 return tmp > U32_MAX ? U32_MAX : tmp; 1933 } 1934 1935 /* Set the time delay in usec before Rx interrupt */ 1936 static void mvpp2_rx_time_coal_set(struct mvpp2_port *port, 1937 struct mvpp2_rx_queue *rxq) 1938 { 1939 unsigned long freq = port->priv->tclk; 1940 u32 val = mvpp2_usec_to_cycles(rxq->time_coal, freq); 1941 1942 if (val > MVPP2_MAX_ISR_RX_THRESHOLD) { 1943 rxq->time_coal = 1944 mvpp2_cycles_to_usec(MVPP2_MAX_ISR_RX_THRESHOLD, freq); 1945 1946 /* re-evaluate to get actual register value */ 1947 val = mvpp2_usec_to_cycles(rxq->time_coal, freq); 1948 } 1949 1950 mvpp2_write(port->priv, MVPP2_ISR_RX_THRESHOLD_REG(rxq->id), val); 1951 } 1952 1953 static void mvpp2_tx_time_coal_set(struct mvpp2_port *port) 1954 { 1955 unsigned long freq = port->priv->tclk; 1956 u32 val = mvpp2_usec_to_cycles(port->tx_time_coal, freq); 1957 1958 if (val > MVPP2_MAX_ISR_TX_THRESHOLD) { 1959 port->tx_time_coal = 1960 mvpp2_cycles_to_usec(MVPP2_MAX_ISR_TX_THRESHOLD, freq); 1961 1962 /* re-evaluate to get actual register value */ 1963 val = mvpp2_usec_to_cycles(port->tx_time_coal, freq); 1964 } 1965 1966 mvpp2_write(port->priv, MVPP2_ISR_TX_THRESHOLD_REG(port->id), val); 1967 } 1968 1969 /* Free Tx queue skbuffs */ 1970 static void mvpp2_txq_bufs_free(struct mvpp2_port *port, 1971 struct mvpp2_tx_queue *txq, 1972 struct mvpp2_txq_pcpu *txq_pcpu, int num) 1973 { 1974 int i; 1975 1976 for (i = 0; i < num; i++) { 1977 struct mvpp2_txq_pcpu_buf *tx_buf = 1978 txq_pcpu->buffs + txq_pcpu->txq_get_index; 1979 1980 if (!IS_TSO_HEADER(txq_pcpu, tx_buf->dma)) 1981 dma_unmap_single(port->dev->dev.parent, tx_buf->dma, 1982 tx_buf->size, DMA_TO_DEVICE); 1983 if (tx_buf->skb) 1984 dev_kfree_skb_any(tx_buf->skb); 1985 1986 mvpp2_txq_inc_get(txq_pcpu); 1987 } 1988 } 1989 1990 static inline struct mvpp2_rx_queue *mvpp2_get_rx_queue(struct mvpp2_port *port, 1991 u32 cause) 1992 { 1993 int queue = fls(cause) - 1; 1994 1995 return port->rxqs[queue]; 1996 } 1997 1998 static inline struct mvpp2_tx_queue *mvpp2_get_tx_queue(struct mvpp2_port *port, 1999 u32 cause) 2000 { 2001 int queue = fls(cause) - 1; 2002 2003 return port->txqs[queue]; 2004 } 2005 2006 /* Handle end of transmission */ 2007 static void mvpp2_txq_done(struct mvpp2_port *port, struct mvpp2_tx_queue *txq, 2008 struct mvpp2_txq_pcpu *txq_pcpu) 2009 { 2010 struct netdev_queue *nq = netdev_get_tx_queue(port->dev, txq->log_id); 2011 int tx_done; 2012 2013 if (txq_pcpu->thread != mvpp2_cpu_to_thread(port->priv, smp_processor_id())) 2014 netdev_err(port->dev, "wrong cpu on the end of Tx processing\n"); 2015 2016 tx_done = mvpp2_txq_sent_desc_proc(port, txq); 2017 if (!tx_done) 2018 return; 2019 mvpp2_txq_bufs_free(port, txq, txq_pcpu, tx_done); 2020 2021 txq_pcpu->count -= tx_done; 2022 2023 if (netif_tx_queue_stopped(nq)) 2024 if (txq_pcpu->count <= txq_pcpu->wake_threshold) 2025 netif_tx_wake_queue(nq); 2026 } 2027 2028 static unsigned int mvpp2_tx_done(struct mvpp2_port *port, u32 cause, 2029 unsigned int thread) 2030 { 2031 struct mvpp2_tx_queue *txq; 2032 struct mvpp2_txq_pcpu *txq_pcpu; 2033 unsigned int tx_todo = 0; 2034 2035 while (cause) { 2036 txq = mvpp2_get_tx_queue(port, cause); 2037 if (!txq) 2038 break; 2039 2040 txq_pcpu = per_cpu_ptr(txq->pcpu, thread); 2041 2042 if (txq_pcpu->count) { 2043 mvpp2_txq_done(port, txq, txq_pcpu); 2044 tx_todo += txq_pcpu->count; 2045 } 2046 2047 cause &= ~(1 << txq->log_id); 2048 } 2049 return tx_todo; 2050 } 2051 2052 /* Rx/Tx queue initialization/cleanup methods */ 2053 2054 /* Allocate and initialize descriptors for aggr TXQ */ 2055 static int mvpp2_aggr_txq_init(struct platform_device *pdev, 2056 struct mvpp2_tx_queue *aggr_txq, 2057 unsigned int thread, struct mvpp2 *priv) 2058 { 2059 u32 txq_dma; 2060 2061 /* Allocate memory for TX descriptors */ 2062 aggr_txq->descs = dma_zalloc_coherent(&pdev->dev, 2063 MVPP2_AGGR_TXQ_SIZE * MVPP2_DESC_ALIGNED_SIZE, 2064 &aggr_txq->descs_dma, GFP_KERNEL); 2065 if (!aggr_txq->descs) 2066 return -ENOMEM; 2067 2068 aggr_txq->last_desc = MVPP2_AGGR_TXQ_SIZE - 1; 2069 2070 /* Aggr TXQ no reset WA */ 2071 aggr_txq->next_desc_to_proc = mvpp2_read(priv, 2072 MVPP2_AGGR_TXQ_INDEX_REG(thread)); 2073 2074 /* Set Tx descriptors queue starting address indirect 2075 * access 2076 */ 2077 if (priv->hw_version == MVPP21) 2078 txq_dma = aggr_txq->descs_dma; 2079 else 2080 txq_dma = aggr_txq->descs_dma >> 2081 MVPP22_AGGR_TXQ_DESC_ADDR_OFFS; 2082 2083 mvpp2_write(priv, MVPP2_AGGR_TXQ_DESC_ADDR_REG(thread), txq_dma); 2084 mvpp2_write(priv, MVPP2_AGGR_TXQ_DESC_SIZE_REG(thread), 2085 MVPP2_AGGR_TXQ_SIZE); 2086 2087 return 0; 2088 } 2089 2090 /* Create a specified Rx queue */ 2091 static int mvpp2_rxq_init(struct mvpp2_port *port, 2092 struct mvpp2_rx_queue *rxq) 2093 2094 { 2095 unsigned int thread; 2096 u32 rxq_dma; 2097 2098 rxq->size = port->rx_ring_size; 2099 2100 /* Allocate memory for RX descriptors */ 2101 rxq->descs = dma_alloc_coherent(port->dev->dev.parent, 2102 rxq->size * MVPP2_DESC_ALIGNED_SIZE, 2103 &rxq->descs_dma, GFP_KERNEL); 2104 if (!rxq->descs) 2105 return -ENOMEM; 2106 2107 rxq->last_desc = rxq->size - 1; 2108 2109 /* Zero occupied and non-occupied counters - direct access */ 2110 mvpp2_write(port->priv, MVPP2_RXQ_STATUS_REG(rxq->id), 0); 2111 2112 /* Set Rx descriptors queue starting address - indirect access */ 2113 thread = mvpp2_cpu_to_thread(port->priv, get_cpu()); 2114 mvpp2_thread_write(port->priv, thread, MVPP2_RXQ_NUM_REG, rxq->id); 2115 if (port->priv->hw_version == MVPP21) 2116 rxq_dma = rxq->descs_dma; 2117 else 2118 rxq_dma = rxq->descs_dma >> MVPP22_DESC_ADDR_OFFS; 2119 mvpp2_thread_write(port->priv, thread, MVPP2_RXQ_DESC_ADDR_REG, rxq_dma); 2120 mvpp2_thread_write(port->priv, thread, MVPP2_RXQ_DESC_SIZE_REG, rxq->size); 2121 mvpp2_thread_write(port->priv, thread, MVPP2_RXQ_INDEX_REG, 0); 2122 put_cpu(); 2123 2124 /* Set Offset */ 2125 mvpp2_rxq_offset_set(port, rxq->id, NET_SKB_PAD); 2126 2127 /* Set coalescing pkts and time */ 2128 mvpp2_rx_pkts_coal_set(port, rxq); 2129 mvpp2_rx_time_coal_set(port, rxq); 2130 2131 /* Add number of descriptors ready for receiving packets */ 2132 mvpp2_rxq_status_update(port, rxq->id, 0, rxq->size); 2133 2134 return 0; 2135 } 2136 2137 /* Push packets received by the RXQ to BM pool */ 2138 static void mvpp2_rxq_drop_pkts(struct mvpp2_port *port, 2139 struct mvpp2_rx_queue *rxq) 2140 { 2141 int rx_received, i; 2142 2143 rx_received = mvpp2_rxq_received(port, rxq->id); 2144 if (!rx_received) 2145 return; 2146 2147 for (i = 0; i < rx_received; i++) { 2148 struct mvpp2_rx_desc *rx_desc = mvpp2_rxq_next_desc_get(rxq); 2149 u32 status = mvpp2_rxdesc_status_get(port, rx_desc); 2150 int pool; 2151 2152 pool = (status & MVPP2_RXD_BM_POOL_ID_MASK) >> 2153 MVPP2_RXD_BM_POOL_ID_OFFS; 2154 2155 mvpp2_bm_pool_put(port, pool, 2156 mvpp2_rxdesc_dma_addr_get(port, rx_desc), 2157 mvpp2_rxdesc_cookie_get(port, rx_desc)); 2158 } 2159 mvpp2_rxq_status_update(port, rxq->id, rx_received, rx_received); 2160 } 2161 2162 /* Cleanup Rx queue */ 2163 static void mvpp2_rxq_deinit(struct mvpp2_port *port, 2164 struct mvpp2_rx_queue *rxq) 2165 { 2166 unsigned int thread; 2167 2168 mvpp2_rxq_drop_pkts(port, rxq); 2169 2170 if (rxq->descs) 2171 dma_free_coherent(port->dev->dev.parent, 2172 rxq->size * MVPP2_DESC_ALIGNED_SIZE, 2173 rxq->descs, 2174 rxq->descs_dma); 2175 2176 rxq->descs = NULL; 2177 rxq->last_desc = 0; 2178 rxq->next_desc_to_proc = 0; 2179 rxq->descs_dma = 0; 2180 2181 /* Clear Rx descriptors queue starting address and size; 2182 * free descriptor number 2183 */ 2184 mvpp2_write(port->priv, MVPP2_RXQ_STATUS_REG(rxq->id), 0); 2185 thread = mvpp2_cpu_to_thread(port->priv, get_cpu()); 2186 mvpp2_thread_write(port->priv, thread, MVPP2_RXQ_NUM_REG, rxq->id); 2187 mvpp2_thread_write(port->priv, thread, MVPP2_RXQ_DESC_ADDR_REG, 0); 2188 mvpp2_thread_write(port->priv, thread, MVPP2_RXQ_DESC_SIZE_REG, 0); 2189 put_cpu(); 2190 } 2191 2192 /* Create and initialize a Tx queue */ 2193 static int mvpp2_txq_init(struct mvpp2_port *port, 2194 struct mvpp2_tx_queue *txq) 2195 { 2196 u32 val; 2197 unsigned int thread; 2198 int desc, desc_per_txq, tx_port_num; 2199 struct mvpp2_txq_pcpu *txq_pcpu; 2200 2201 txq->size = port->tx_ring_size; 2202 2203 /* Allocate memory for Tx descriptors */ 2204 txq->descs = dma_alloc_coherent(port->dev->dev.parent, 2205 txq->size * MVPP2_DESC_ALIGNED_SIZE, 2206 &txq->descs_dma, GFP_KERNEL); 2207 if (!txq->descs) 2208 return -ENOMEM; 2209 2210 txq->last_desc = txq->size - 1; 2211 2212 /* Set Tx descriptors queue starting address - indirect access */ 2213 thread = mvpp2_cpu_to_thread(port->priv, get_cpu()); 2214 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_NUM_REG, txq->id); 2215 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_DESC_ADDR_REG, 2216 txq->descs_dma); 2217 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_DESC_SIZE_REG, 2218 txq->size & MVPP2_TXQ_DESC_SIZE_MASK); 2219 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_INDEX_REG, 0); 2220 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_RSVD_CLR_REG, 2221 txq->id << MVPP2_TXQ_RSVD_CLR_OFFSET); 2222 val = mvpp2_thread_read(port->priv, thread, MVPP2_TXQ_PENDING_REG); 2223 val &= ~MVPP2_TXQ_PENDING_MASK; 2224 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_PENDING_REG, val); 2225 2226 /* Calculate base address in prefetch buffer. We reserve 16 descriptors 2227 * for each existing TXQ. 2228 * TCONTS for PON port must be continuous from 0 to MVPP2_MAX_TCONT 2229 * GBE ports assumed to be continuous from 0 to MVPP2_MAX_PORTS 2230 */ 2231 desc_per_txq = 16; 2232 desc = (port->id * MVPP2_MAX_TXQ * desc_per_txq) + 2233 (txq->log_id * desc_per_txq); 2234 2235 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_PREF_BUF_REG, 2236 MVPP2_PREF_BUF_PTR(desc) | MVPP2_PREF_BUF_SIZE_16 | 2237 MVPP2_PREF_BUF_THRESH(desc_per_txq / 2)); 2238 put_cpu(); 2239 2240 /* WRR / EJP configuration - indirect access */ 2241 tx_port_num = mvpp2_egress_port(port); 2242 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num); 2243 2244 val = mvpp2_read(port->priv, MVPP2_TXQ_SCHED_REFILL_REG(txq->log_id)); 2245 val &= ~MVPP2_TXQ_REFILL_PERIOD_ALL_MASK; 2246 val |= MVPP2_TXQ_REFILL_PERIOD_MASK(1); 2247 val |= MVPP2_TXQ_REFILL_TOKENS_ALL_MASK; 2248 mvpp2_write(port->priv, MVPP2_TXQ_SCHED_REFILL_REG(txq->log_id), val); 2249 2250 val = MVPP2_TXQ_TOKEN_SIZE_MAX; 2251 mvpp2_write(port->priv, MVPP2_TXQ_SCHED_TOKEN_SIZE_REG(txq->log_id), 2252 val); 2253 2254 for (thread = 0; thread < port->priv->nthreads; thread++) { 2255 txq_pcpu = per_cpu_ptr(txq->pcpu, thread); 2256 txq_pcpu->size = txq->size; 2257 txq_pcpu->buffs = kmalloc_array(txq_pcpu->size, 2258 sizeof(*txq_pcpu->buffs), 2259 GFP_KERNEL); 2260 if (!txq_pcpu->buffs) 2261 return -ENOMEM; 2262 2263 txq_pcpu->count = 0; 2264 txq_pcpu->reserved_num = 0; 2265 txq_pcpu->txq_put_index = 0; 2266 txq_pcpu->txq_get_index = 0; 2267 txq_pcpu->tso_headers = NULL; 2268 2269 txq_pcpu->stop_threshold = txq->size - MVPP2_MAX_SKB_DESCS; 2270 txq_pcpu->wake_threshold = txq_pcpu->stop_threshold / 2; 2271 2272 txq_pcpu->tso_headers = 2273 dma_alloc_coherent(port->dev->dev.parent, 2274 txq_pcpu->size * TSO_HEADER_SIZE, 2275 &txq_pcpu->tso_headers_dma, 2276 GFP_KERNEL); 2277 if (!txq_pcpu->tso_headers) 2278 return -ENOMEM; 2279 } 2280 2281 return 0; 2282 } 2283 2284 /* Free allocated TXQ resources */ 2285 static void mvpp2_txq_deinit(struct mvpp2_port *port, 2286 struct mvpp2_tx_queue *txq) 2287 { 2288 struct mvpp2_txq_pcpu *txq_pcpu; 2289 unsigned int thread; 2290 2291 for (thread = 0; thread < port->priv->nthreads; thread++) { 2292 txq_pcpu = per_cpu_ptr(txq->pcpu, thread); 2293 kfree(txq_pcpu->buffs); 2294 2295 if (txq_pcpu->tso_headers) 2296 dma_free_coherent(port->dev->dev.parent, 2297 txq_pcpu->size * TSO_HEADER_SIZE, 2298 txq_pcpu->tso_headers, 2299 txq_pcpu->tso_headers_dma); 2300 2301 txq_pcpu->tso_headers = NULL; 2302 } 2303 2304 if (txq->descs) 2305 dma_free_coherent(port->dev->dev.parent, 2306 txq->size * MVPP2_DESC_ALIGNED_SIZE, 2307 txq->descs, txq->descs_dma); 2308 2309 txq->descs = NULL; 2310 txq->last_desc = 0; 2311 txq->next_desc_to_proc = 0; 2312 txq->descs_dma = 0; 2313 2314 /* Set minimum bandwidth for disabled TXQs */ 2315 mvpp2_write(port->priv, MVPP2_TXQ_SCHED_TOKEN_CNTR_REG(txq->id), 0); 2316 2317 /* Set Tx descriptors queue starting address and size */ 2318 thread = mvpp2_cpu_to_thread(port->priv, get_cpu()); 2319 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_NUM_REG, txq->id); 2320 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_DESC_ADDR_REG, 0); 2321 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_DESC_SIZE_REG, 0); 2322 put_cpu(); 2323 } 2324 2325 /* Cleanup Tx ports */ 2326 static void mvpp2_txq_clean(struct mvpp2_port *port, struct mvpp2_tx_queue *txq) 2327 { 2328 struct mvpp2_txq_pcpu *txq_pcpu; 2329 int delay, pending; 2330 unsigned int thread = mvpp2_cpu_to_thread(port->priv, get_cpu()); 2331 u32 val; 2332 2333 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_NUM_REG, txq->id); 2334 val = mvpp2_thread_read(port->priv, thread, MVPP2_TXQ_PREF_BUF_REG); 2335 val |= MVPP2_TXQ_DRAIN_EN_MASK; 2336 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_PREF_BUF_REG, val); 2337 2338 /* The napi queue has been stopped so wait for all packets 2339 * to be transmitted. 2340 */ 2341 delay = 0; 2342 do { 2343 if (delay >= MVPP2_TX_PENDING_TIMEOUT_MSEC) { 2344 netdev_warn(port->dev, 2345 "port %d: cleaning queue %d timed out\n", 2346 port->id, txq->log_id); 2347 break; 2348 } 2349 mdelay(1); 2350 delay++; 2351 2352 pending = mvpp2_thread_read(port->priv, thread, 2353 MVPP2_TXQ_PENDING_REG); 2354 pending &= MVPP2_TXQ_PENDING_MASK; 2355 } while (pending); 2356 2357 val &= ~MVPP2_TXQ_DRAIN_EN_MASK; 2358 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_PREF_BUF_REG, val); 2359 put_cpu(); 2360 2361 for (thread = 0; thread < port->priv->nthreads; thread++) { 2362 txq_pcpu = per_cpu_ptr(txq->pcpu, thread); 2363 2364 /* Release all packets */ 2365 mvpp2_txq_bufs_free(port, txq, txq_pcpu, txq_pcpu->count); 2366 2367 /* Reset queue */ 2368 txq_pcpu->count = 0; 2369 txq_pcpu->txq_put_index = 0; 2370 txq_pcpu->txq_get_index = 0; 2371 } 2372 } 2373 2374 /* Cleanup all Tx queues */ 2375 static void mvpp2_cleanup_txqs(struct mvpp2_port *port) 2376 { 2377 struct mvpp2_tx_queue *txq; 2378 int queue; 2379 u32 val; 2380 2381 val = mvpp2_read(port->priv, MVPP2_TX_PORT_FLUSH_REG); 2382 2383 /* Reset Tx ports and delete Tx queues */ 2384 val |= MVPP2_TX_PORT_FLUSH_MASK(port->id); 2385 mvpp2_write(port->priv, MVPP2_TX_PORT_FLUSH_REG, val); 2386 2387 for (queue = 0; queue < port->ntxqs; queue++) { 2388 txq = port->txqs[queue]; 2389 mvpp2_txq_clean(port, txq); 2390 mvpp2_txq_deinit(port, txq); 2391 } 2392 2393 on_each_cpu(mvpp2_txq_sent_counter_clear, port, 1); 2394 2395 val &= ~MVPP2_TX_PORT_FLUSH_MASK(port->id); 2396 mvpp2_write(port->priv, MVPP2_TX_PORT_FLUSH_REG, val); 2397 } 2398 2399 /* Cleanup all Rx queues */ 2400 static void mvpp2_cleanup_rxqs(struct mvpp2_port *port) 2401 { 2402 int queue; 2403 2404 for (queue = 0; queue < port->nrxqs; queue++) 2405 mvpp2_rxq_deinit(port, port->rxqs[queue]); 2406 } 2407 2408 /* Init all Rx queues for port */ 2409 static int mvpp2_setup_rxqs(struct mvpp2_port *port) 2410 { 2411 int queue, err; 2412 2413 for (queue = 0; queue < port->nrxqs; queue++) { 2414 err = mvpp2_rxq_init(port, port->rxqs[queue]); 2415 if (err) 2416 goto err_cleanup; 2417 } 2418 return 0; 2419 2420 err_cleanup: 2421 mvpp2_cleanup_rxqs(port); 2422 return err; 2423 } 2424 2425 /* Init all tx queues for port */ 2426 static int mvpp2_setup_txqs(struct mvpp2_port *port) 2427 { 2428 struct mvpp2_tx_queue *txq; 2429 int queue, err, cpu; 2430 2431 for (queue = 0; queue < port->ntxqs; queue++) { 2432 txq = port->txqs[queue]; 2433 err = mvpp2_txq_init(port, txq); 2434 if (err) 2435 goto err_cleanup; 2436 2437 /* Assign this queue to a CPU */ 2438 cpu = queue % num_present_cpus(); 2439 netif_set_xps_queue(port->dev, cpumask_of(cpu), queue); 2440 } 2441 2442 if (port->has_tx_irqs) { 2443 mvpp2_tx_time_coal_set(port); 2444 for (queue = 0; queue < port->ntxqs; queue++) { 2445 txq = port->txqs[queue]; 2446 mvpp2_tx_pkts_coal_set(port, txq); 2447 } 2448 } 2449 2450 on_each_cpu(mvpp2_txq_sent_counter_clear, port, 1); 2451 return 0; 2452 2453 err_cleanup: 2454 mvpp2_cleanup_txqs(port); 2455 return err; 2456 } 2457 2458 /* The callback for per-port interrupt */ 2459 static irqreturn_t mvpp2_isr(int irq, void *dev_id) 2460 { 2461 struct mvpp2_queue_vector *qv = dev_id; 2462 2463 mvpp2_qvec_interrupt_disable(qv); 2464 2465 napi_schedule(&qv->napi); 2466 2467 return IRQ_HANDLED; 2468 } 2469 2470 /* Per-port interrupt for link status changes */ 2471 static irqreturn_t mvpp2_link_status_isr(int irq, void *dev_id) 2472 { 2473 struct mvpp2_port *port = (struct mvpp2_port *)dev_id; 2474 struct net_device *dev = port->dev; 2475 bool event = false, link = false; 2476 u32 val; 2477 2478 mvpp22_gop_mask_irq(port); 2479 2480 if (port->gop_id == 0 && 2481 port->phy_interface == PHY_INTERFACE_MODE_10GKR) { 2482 val = readl(port->base + MVPP22_XLG_INT_STAT); 2483 if (val & MVPP22_XLG_INT_STAT_LINK) { 2484 event = true; 2485 val = readl(port->base + MVPP22_XLG_STATUS); 2486 if (val & MVPP22_XLG_STATUS_LINK_UP) 2487 link = true; 2488 } 2489 } else if (phy_interface_mode_is_rgmii(port->phy_interface) || 2490 port->phy_interface == PHY_INTERFACE_MODE_SGMII || 2491 port->phy_interface == PHY_INTERFACE_MODE_1000BASEX || 2492 port->phy_interface == PHY_INTERFACE_MODE_2500BASEX) { 2493 val = readl(port->base + MVPP22_GMAC_INT_STAT); 2494 if (val & MVPP22_GMAC_INT_STAT_LINK) { 2495 event = true; 2496 val = readl(port->base + MVPP2_GMAC_STATUS0); 2497 if (val & MVPP2_GMAC_STATUS0_LINK_UP) 2498 link = true; 2499 } 2500 } 2501 2502 if (port->phylink) { 2503 phylink_mac_change(port->phylink, link); 2504 goto handled; 2505 } 2506 2507 if (!netif_running(dev) || !event) 2508 goto handled; 2509 2510 if (link) { 2511 mvpp2_interrupts_enable(port); 2512 2513 mvpp2_egress_enable(port); 2514 mvpp2_ingress_enable(port); 2515 netif_carrier_on(dev); 2516 netif_tx_wake_all_queues(dev); 2517 } else { 2518 netif_tx_stop_all_queues(dev); 2519 netif_carrier_off(dev); 2520 mvpp2_ingress_disable(port); 2521 mvpp2_egress_disable(port); 2522 2523 mvpp2_interrupts_disable(port); 2524 } 2525 2526 handled: 2527 mvpp22_gop_unmask_irq(port); 2528 return IRQ_HANDLED; 2529 } 2530 2531 static void mvpp2_timer_set(struct mvpp2_port_pcpu *port_pcpu) 2532 { 2533 ktime_t interval; 2534 2535 if (!port_pcpu->timer_scheduled) { 2536 port_pcpu->timer_scheduled = true; 2537 interval = MVPP2_TXDONE_HRTIMER_PERIOD_NS; 2538 hrtimer_start(&port_pcpu->tx_done_timer, interval, 2539 HRTIMER_MODE_REL_PINNED); 2540 } 2541 } 2542 2543 static void mvpp2_tx_proc_cb(unsigned long data) 2544 { 2545 struct net_device *dev = (struct net_device *)data; 2546 struct mvpp2_port *port = netdev_priv(dev); 2547 struct mvpp2_port_pcpu *port_pcpu; 2548 unsigned int tx_todo, cause; 2549 2550 port_pcpu = per_cpu_ptr(port->pcpu, 2551 mvpp2_cpu_to_thread(port->priv, smp_processor_id())); 2552 2553 if (!netif_running(dev)) 2554 return; 2555 port_pcpu->timer_scheduled = false; 2556 2557 /* Process all the Tx queues */ 2558 cause = (1 << port->ntxqs) - 1; 2559 tx_todo = mvpp2_tx_done(port, cause, 2560 mvpp2_cpu_to_thread(port->priv, smp_processor_id())); 2561 2562 /* Set the timer in case not all the packets were processed */ 2563 if (tx_todo) 2564 mvpp2_timer_set(port_pcpu); 2565 } 2566 2567 static enum hrtimer_restart mvpp2_hr_timer_cb(struct hrtimer *timer) 2568 { 2569 struct mvpp2_port_pcpu *port_pcpu = container_of(timer, 2570 struct mvpp2_port_pcpu, 2571 tx_done_timer); 2572 2573 tasklet_schedule(&port_pcpu->tx_done_tasklet); 2574 2575 return HRTIMER_NORESTART; 2576 } 2577 2578 /* Main RX/TX processing routines */ 2579 2580 /* Display more error info */ 2581 static void mvpp2_rx_error(struct mvpp2_port *port, 2582 struct mvpp2_rx_desc *rx_desc) 2583 { 2584 u32 status = mvpp2_rxdesc_status_get(port, rx_desc); 2585 size_t sz = mvpp2_rxdesc_size_get(port, rx_desc); 2586 char *err_str = NULL; 2587 2588 switch (status & MVPP2_RXD_ERR_CODE_MASK) { 2589 case MVPP2_RXD_ERR_CRC: 2590 err_str = "crc"; 2591 break; 2592 case MVPP2_RXD_ERR_OVERRUN: 2593 err_str = "overrun"; 2594 break; 2595 case MVPP2_RXD_ERR_RESOURCE: 2596 err_str = "resource"; 2597 break; 2598 } 2599 if (err_str && net_ratelimit()) 2600 netdev_err(port->dev, 2601 "bad rx status %08x (%s error), size=%zu\n", 2602 status, err_str, sz); 2603 } 2604 2605 /* Handle RX checksum offload */ 2606 static void mvpp2_rx_csum(struct mvpp2_port *port, u32 status, 2607 struct sk_buff *skb) 2608 { 2609 if (((status & MVPP2_RXD_L3_IP4) && 2610 !(status & MVPP2_RXD_IP4_HEADER_ERR)) || 2611 (status & MVPP2_RXD_L3_IP6)) 2612 if (((status & MVPP2_RXD_L4_UDP) || 2613 (status & MVPP2_RXD_L4_TCP)) && 2614 (status & MVPP2_RXD_L4_CSUM_OK)) { 2615 skb->csum = 0; 2616 skb->ip_summed = CHECKSUM_UNNECESSARY; 2617 return; 2618 } 2619 2620 skb->ip_summed = CHECKSUM_NONE; 2621 } 2622 2623 /* Reuse skb if possible, or allocate a new skb and add it to BM pool */ 2624 static int mvpp2_rx_refill(struct mvpp2_port *port, 2625 struct mvpp2_bm_pool *bm_pool, int pool) 2626 { 2627 dma_addr_t dma_addr; 2628 phys_addr_t phys_addr; 2629 void *buf; 2630 2631 /* No recycle or too many buffers are in use, so allocate a new skb */ 2632 buf = mvpp2_buf_alloc(port, bm_pool, &dma_addr, &phys_addr, 2633 GFP_ATOMIC); 2634 if (!buf) 2635 return -ENOMEM; 2636 2637 mvpp2_bm_pool_put(port, pool, dma_addr, phys_addr); 2638 2639 return 0; 2640 } 2641 2642 /* Handle tx checksum */ 2643 static u32 mvpp2_skb_tx_csum(struct mvpp2_port *port, struct sk_buff *skb) 2644 { 2645 if (skb->ip_summed == CHECKSUM_PARTIAL) { 2646 int ip_hdr_len = 0; 2647 u8 l4_proto; 2648 __be16 l3_proto = vlan_get_protocol(skb); 2649 2650 if (l3_proto == htons(ETH_P_IP)) { 2651 struct iphdr *ip4h = ip_hdr(skb); 2652 2653 /* Calculate IPv4 checksum and L4 checksum */ 2654 ip_hdr_len = ip4h->ihl; 2655 l4_proto = ip4h->protocol; 2656 } else if (l3_proto == htons(ETH_P_IPV6)) { 2657 struct ipv6hdr *ip6h = ipv6_hdr(skb); 2658 2659 /* Read l4_protocol from one of IPv6 extra headers */ 2660 if (skb_network_header_len(skb) > 0) 2661 ip_hdr_len = (skb_network_header_len(skb) >> 2); 2662 l4_proto = ip6h->nexthdr; 2663 } else { 2664 return MVPP2_TXD_L4_CSUM_NOT; 2665 } 2666 2667 return mvpp2_txq_desc_csum(skb_network_offset(skb), 2668 l3_proto, ip_hdr_len, l4_proto); 2669 } 2670 2671 return MVPP2_TXD_L4_CSUM_NOT | MVPP2_TXD_IP_CSUM_DISABLE; 2672 } 2673 2674 /* Main rx processing */ 2675 static int mvpp2_rx(struct mvpp2_port *port, struct napi_struct *napi, 2676 int rx_todo, struct mvpp2_rx_queue *rxq) 2677 { 2678 struct net_device *dev = port->dev; 2679 int rx_received; 2680 int rx_done = 0; 2681 u32 rcvd_pkts = 0; 2682 u32 rcvd_bytes = 0; 2683 2684 /* Get number of received packets and clamp the to-do */ 2685 rx_received = mvpp2_rxq_received(port, rxq->id); 2686 if (rx_todo > rx_received) 2687 rx_todo = rx_received; 2688 2689 while (rx_done < rx_todo) { 2690 struct mvpp2_rx_desc *rx_desc = mvpp2_rxq_next_desc_get(rxq); 2691 struct mvpp2_bm_pool *bm_pool; 2692 struct sk_buff *skb; 2693 unsigned int frag_size; 2694 dma_addr_t dma_addr; 2695 phys_addr_t phys_addr; 2696 u32 rx_status; 2697 int pool, rx_bytes, err; 2698 void *data; 2699 2700 rx_done++; 2701 rx_status = mvpp2_rxdesc_status_get(port, rx_desc); 2702 rx_bytes = mvpp2_rxdesc_size_get(port, rx_desc); 2703 rx_bytes -= MVPP2_MH_SIZE; 2704 dma_addr = mvpp2_rxdesc_dma_addr_get(port, rx_desc); 2705 phys_addr = mvpp2_rxdesc_cookie_get(port, rx_desc); 2706 data = (void *)phys_to_virt(phys_addr); 2707 2708 pool = (rx_status & MVPP2_RXD_BM_POOL_ID_MASK) >> 2709 MVPP2_RXD_BM_POOL_ID_OFFS; 2710 bm_pool = &port->priv->bm_pools[pool]; 2711 2712 /* In case of an error, release the requested buffer pointer 2713 * to the Buffer Manager. This request process is controlled 2714 * by the hardware, and the information about the buffer is 2715 * comprised by the RX descriptor. 2716 */ 2717 if (rx_status & MVPP2_RXD_ERR_SUMMARY) { 2718 err_drop_frame: 2719 dev->stats.rx_errors++; 2720 mvpp2_rx_error(port, rx_desc); 2721 /* Return the buffer to the pool */ 2722 mvpp2_bm_pool_put(port, pool, dma_addr, phys_addr); 2723 continue; 2724 } 2725 2726 if (bm_pool->frag_size > PAGE_SIZE) 2727 frag_size = 0; 2728 else 2729 frag_size = bm_pool->frag_size; 2730 2731 skb = build_skb(data, frag_size); 2732 if (!skb) { 2733 netdev_warn(port->dev, "skb build failed\n"); 2734 goto err_drop_frame; 2735 } 2736 2737 err = mvpp2_rx_refill(port, bm_pool, pool); 2738 if (err) { 2739 netdev_err(port->dev, "failed to refill BM pools\n"); 2740 goto err_drop_frame; 2741 } 2742 2743 dma_unmap_single(dev->dev.parent, dma_addr, 2744 bm_pool->buf_size, DMA_FROM_DEVICE); 2745 2746 rcvd_pkts++; 2747 rcvd_bytes += rx_bytes; 2748 2749 skb_reserve(skb, MVPP2_MH_SIZE + NET_SKB_PAD); 2750 skb_put(skb, rx_bytes); 2751 skb->protocol = eth_type_trans(skb, dev); 2752 mvpp2_rx_csum(port, rx_status, skb); 2753 2754 napi_gro_receive(napi, skb); 2755 } 2756 2757 if (rcvd_pkts) { 2758 struct mvpp2_pcpu_stats *stats = this_cpu_ptr(port->stats); 2759 2760 u64_stats_update_begin(&stats->syncp); 2761 stats->rx_packets += rcvd_pkts; 2762 stats->rx_bytes += rcvd_bytes; 2763 u64_stats_update_end(&stats->syncp); 2764 } 2765 2766 /* Update Rx queue management counters */ 2767 wmb(); 2768 mvpp2_rxq_status_update(port, rxq->id, rx_done, rx_done); 2769 2770 return rx_todo; 2771 } 2772 2773 static inline void 2774 tx_desc_unmap_put(struct mvpp2_port *port, struct mvpp2_tx_queue *txq, 2775 struct mvpp2_tx_desc *desc) 2776 { 2777 unsigned int thread = mvpp2_cpu_to_thread(port->priv, smp_processor_id()); 2778 struct mvpp2_txq_pcpu *txq_pcpu = per_cpu_ptr(txq->pcpu, thread); 2779 2780 dma_addr_t buf_dma_addr = 2781 mvpp2_txdesc_dma_addr_get(port, desc); 2782 size_t buf_sz = 2783 mvpp2_txdesc_size_get(port, desc); 2784 if (!IS_TSO_HEADER(txq_pcpu, buf_dma_addr)) 2785 dma_unmap_single(port->dev->dev.parent, buf_dma_addr, 2786 buf_sz, DMA_TO_DEVICE); 2787 mvpp2_txq_desc_put(txq); 2788 } 2789 2790 /* Handle tx fragmentation processing */ 2791 static int mvpp2_tx_frag_process(struct mvpp2_port *port, struct sk_buff *skb, 2792 struct mvpp2_tx_queue *aggr_txq, 2793 struct mvpp2_tx_queue *txq) 2794 { 2795 unsigned int thread = mvpp2_cpu_to_thread(port->priv, smp_processor_id()); 2796 struct mvpp2_txq_pcpu *txq_pcpu = per_cpu_ptr(txq->pcpu, thread); 2797 struct mvpp2_tx_desc *tx_desc; 2798 int i; 2799 dma_addr_t buf_dma_addr; 2800 2801 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { 2802 skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 2803 void *addr = page_address(frag->page.p) + frag->page_offset; 2804 2805 tx_desc = mvpp2_txq_next_desc_get(aggr_txq); 2806 mvpp2_txdesc_txq_set(port, tx_desc, txq->id); 2807 mvpp2_txdesc_size_set(port, tx_desc, frag->size); 2808 2809 buf_dma_addr = dma_map_single(port->dev->dev.parent, addr, 2810 frag->size, DMA_TO_DEVICE); 2811 if (dma_mapping_error(port->dev->dev.parent, buf_dma_addr)) { 2812 mvpp2_txq_desc_put(txq); 2813 goto cleanup; 2814 } 2815 2816 mvpp2_txdesc_dma_addr_set(port, tx_desc, buf_dma_addr); 2817 2818 if (i == (skb_shinfo(skb)->nr_frags - 1)) { 2819 /* Last descriptor */ 2820 mvpp2_txdesc_cmd_set(port, tx_desc, 2821 MVPP2_TXD_L_DESC); 2822 mvpp2_txq_inc_put(port, txq_pcpu, skb, tx_desc); 2823 } else { 2824 /* Descriptor in the middle: Not First, Not Last */ 2825 mvpp2_txdesc_cmd_set(port, tx_desc, 0); 2826 mvpp2_txq_inc_put(port, txq_pcpu, NULL, tx_desc); 2827 } 2828 } 2829 2830 return 0; 2831 cleanup: 2832 /* Release all descriptors that were used to map fragments of 2833 * this packet, as well as the corresponding DMA mappings 2834 */ 2835 for (i = i - 1; i >= 0; i--) { 2836 tx_desc = txq->descs + i; 2837 tx_desc_unmap_put(port, txq, tx_desc); 2838 } 2839 2840 return -ENOMEM; 2841 } 2842 2843 static inline void mvpp2_tso_put_hdr(struct sk_buff *skb, 2844 struct net_device *dev, 2845 struct mvpp2_tx_queue *txq, 2846 struct mvpp2_tx_queue *aggr_txq, 2847 struct mvpp2_txq_pcpu *txq_pcpu, 2848 int hdr_sz) 2849 { 2850 struct mvpp2_port *port = netdev_priv(dev); 2851 struct mvpp2_tx_desc *tx_desc = mvpp2_txq_next_desc_get(aggr_txq); 2852 dma_addr_t addr; 2853 2854 mvpp2_txdesc_txq_set(port, tx_desc, txq->id); 2855 mvpp2_txdesc_size_set(port, tx_desc, hdr_sz); 2856 2857 addr = txq_pcpu->tso_headers_dma + 2858 txq_pcpu->txq_put_index * TSO_HEADER_SIZE; 2859 mvpp2_txdesc_dma_addr_set(port, tx_desc, addr); 2860 2861 mvpp2_txdesc_cmd_set(port, tx_desc, mvpp2_skb_tx_csum(port, skb) | 2862 MVPP2_TXD_F_DESC | 2863 MVPP2_TXD_PADDING_DISABLE); 2864 mvpp2_txq_inc_put(port, txq_pcpu, NULL, tx_desc); 2865 } 2866 2867 static inline int mvpp2_tso_put_data(struct sk_buff *skb, 2868 struct net_device *dev, struct tso_t *tso, 2869 struct mvpp2_tx_queue *txq, 2870 struct mvpp2_tx_queue *aggr_txq, 2871 struct mvpp2_txq_pcpu *txq_pcpu, 2872 int sz, bool left, bool last) 2873 { 2874 struct mvpp2_port *port = netdev_priv(dev); 2875 struct mvpp2_tx_desc *tx_desc = mvpp2_txq_next_desc_get(aggr_txq); 2876 dma_addr_t buf_dma_addr; 2877 2878 mvpp2_txdesc_txq_set(port, tx_desc, txq->id); 2879 mvpp2_txdesc_size_set(port, tx_desc, sz); 2880 2881 buf_dma_addr = dma_map_single(dev->dev.parent, tso->data, sz, 2882 DMA_TO_DEVICE); 2883 if (unlikely(dma_mapping_error(dev->dev.parent, buf_dma_addr))) { 2884 mvpp2_txq_desc_put(txq); 2885 return -ENOMEM; 2886 } 2887 2888 mvpp2_txdesc_dma_addr_set(port, tx_desc, buf_dma_addr); 2889 2890 if (!left) { 2891 mvpp2_txdesc_cmd_set(port, tx_desc, MVPP2_TXD_L_DESC); 2892 if (last) { 2893 mvpp2_txq_inc_put(port, txq_pcpu, skb, tx_desc); 2894 return 0; 2895 } 2896 } else { 2897 mvpp2_txdesc_cmd_set(port, tx_desc, 0); 2898 } 2899 2900 mvpp2_txq_inc_put(port, txq_pcpu, NULL, tx_desc); 2901 return 0; 2902 } 2903 2904 static int mvpp2_tx_tso(struct sk_buff *skb, struct net_device *dev, 2905 struct mvpp2_tx_queue *txq, 2906 struct mvpp2_tx_queue *aggr_txq, 2907 struct mvpp2_txq_pcpu *txq_pcpu) 2908 { 2909 struct mvpp2_port *port = netdev_priv(dev); 2910 struct tso_t tso; 2911 int hdr_sz = skb_transport_offset(skb) + tcp_hdrlen(skb); 2912 int i, len, descs = 0; 2913 2914 /* Check number of available descriptors */ 2915 if (mvpp2_aggr_desc_num_check(port, aggr_txq, tso_count_descs(skb)) || 2916 mvpp2_txq_reserved_desc_num_proc(port, txq, txq_pcpu, 2917 tso_count_descs(skb))) 2918 return 0; 2919 2920 tso_start(skb, &tso); 2921 len = skb->len - hdr_sz; 2922 while (len > 0) { 2923 int left = min_t(int, skb_shinfo(skb)->gso_size, len); 2924 char *hdr = txq_pcpu->tso_headers + 2925 txq_pcpu->txq_put_index * TSO_HEADER_SIZE; 2926 2927 len -= left; 2928 descs++; 2929 2930 tso_build_hdr(skb, hdr, &tso, left, len == 0); 2931 mvpp2_tso_put_hdr(skb, dev, txq, aggr_txq, txq_pcpu, hdr_sz); 2932 2933 while (left > 0) { 2934 int sz = min_t(int, tso.size, left); 2935 left -= sz; 2936 descs++; 2937 2938 if (mvpp2_tso_put_data(skb, dev, &tso, txq, aggr_txq, 2939 txq_pcpu, sz, left, len == 0)) 2940 goto release; 2941 tso_build_data(skb, &tso, sz); 2942 } 2943 } 2944 2945 return descs; 2946 2947 release: 2948 for (i = descs - 1; i >= 0; i--) { 2949 struct mvpp2_tx_desc *tx_desc = txq->descs + i; 2950 tx_desc_unmap_put(port, txq, tx_desc); 2951 } 2952 return 0; 2953 } 2954 2955 /* Main tx processing */ 2956 static netdev_tx_t mvpp2_tx(struct sk_buff *skb, struct net_device *dev) 2957 { 2958 struct mvpp2_port *port = netdev_priv(dev); 2959 struct mvpp2_tx_queue *txq, *aggr_txq; 2960 struct mvpp2_txq_pcpu *txq_pcpu; 2961 struct mvpp2_tx_desc *tx_desc; 2962 dma_addr_t buf_dma_addr; 2963 unsigned long flags = 0; 2964 unsigned int thread; 2965 int frags = 0; 2966 u16 txq_id; 2967 u32 tx_cmd; 2968 2969 thread = mvpp2_cpu_to_thread(port->priv, smp_processor_id()); 2970 2971 txq_id = skb_get_queue_mapping(skb); 2972 txq = port->txqs[txq_id]; 2973 txq_pcpu = per_cpu_ptr(txq->pcpu, thread); 2974 aggr_txq = &port->priv->aggr_txqs[thread]; 2975 2976 if (test_bit(thread, &port->priv->lock_map)) 2977 spin_lock_irqsave(&port->tx_lock[thread], flags); 2978 2979 if (skb_is_gso(skb)) { 2980 frags = mvpp2_tx_tso(skb, dev, txq, aggr_txq, txq_pcpu); 2981 goto out; 2982 } 2983 frags = skb_shinfo(skb)->nr_frags + 1; 2984 2985 /* Check number of available descriptors */ 2986 if (mvpp2_aggr_desc_num_check(port, aggr_txq, frags) || 2987 mvpp2_txq_reserved_desc_num_proc(port, txq, txq_pcpu, frags)) { 2988 frags = 0; 2989 goto out; 2990 } 2991 2992 /* Get a descriptor for the first part of the packet */ 2993 tx_desc = mvpp2_txq_next_desc_get(aggr_txq); 2994 mvpp2_txdesc_txq_set(port, tx_desc, txq->id); 2995 mvpp2_txdesc_size_set(port, tx_desc, skb_headlen(skb)); 2996 2997 buf_dma_addr = dma_map_single(dev->dev.parent, skb->data, 2998 skb_headlen(skb), DMA_TO_DEVICE); 2999 if (unlikely(dma_mapping_error(dev->dev.parent, buf_dma_addr))) { 3000 mvpp2_txq_desc_put(txq); 3001 frags = 0; 3002 goto out; 3003 } 3004 3005 mvpp2_txdesc_dma_addr_set(port, tx_desc, buf_dma_addr); 3006 3007 tx_cmd = mvpp2_skb_tx_csum(port, skb); 3008 3009 if (frags == 1) { 3010 /* First and Last descriptor */ 3011 tx_cmd |= MVPP2_TXD_F_DESC | MVPP2_TXD_L_DESC; 3012 mvpp2_txdesc_cmd_set(port, tx_desc, tx_cmd); 3013 mvpp2_txq_inc_put(port, txq_pcpu, skb, tx_desc); 3014 } else { 3015 /* First but not Last */ 3016 tx_cmd |= MVPP2_TXD_F_DESC | MVPP2_TXD_PADDING_DISABLE; 3017 mvpp2_txdesc_cmd_set(port, tx_desc, tx_cmd); 3018 mvpp2_txq_inc_put(port, txq_pcpu, NULL, tx_desc); 3019 3020 /* Continue with other skb fragments */ 3021 if (mvpp2_tx_frag_process(port, skb, aggr_txq, txq)) { 3022 tx_desc_unmap_put(port, txq, tx_desc); 3023 frags = 0; 3024 } 3025 } 3026 3027 out: 3028 if (frags > 0) { 3029 struct mvpp2_pcpu_stats *stats = per_cpu_ptr(port->stats, thread); 3030 struct netdev_queue *nq = netdev_get_tx_queue(dev, txq_id); 3031 3032 txq_pcpu->reserved_num -= frags; 3033 txq_pcpu->count += frags; 3034 aggr_txq->count += frags; 3035 3036 /* Enable transmit */ 3037 wmb(); 3038 mvpp2_aggr_txq_pend_desc_add(port, frags); 3039 3040 if (txq_pcpu->count >= txq_pcpu->stop_threshold) 3041 netif_tx_stop_queue(nq); 3042 3043 u64_stats_update_begin(&stats->syncp); 3044 stats->tx_packets++; 3045 stats->tx_bytes += skb->len; 3046 u64_stats_update_end(&stats->syncp); 3047 } else { 3048 dev->stats.tx_dropped++; 3049 dev_kfree_skb_any(skb); 3050 } 3051 3052 /* Finalize TX processing */ 3053 if (!port->has_tx_irqs && txq_pcpu->count >= txq->done_pkts_coal) 3054 mvpp2_txq_done(port, txq, txq_pcpu); 3055 3056 /* Set the timer in case not all frags were processed */ 3057 if (!port->has_tx_irqs && txq_pcpu->count <= frags && 3058 txq_pcpu->count > 0) { 3059 struct mvpp2_port_pcpu *port_pcpu = per_cpu_ptr(port->pcpu, thread); 3060 3061 mvpp2_timer_set(port_pcpu); 3062 } 3063 3064 if (test_bit(thread, &port->priv->lock_map)) 3065 spin_unlock_irqrestore(&port->tx_lock[thread], flags); 3066 3067 return NETDEV_TX_OK; 3068 } 3069 3070 static inline void mvpp2_cause_error(struct net_device *dev, int cause) 3071 { 3072 if (cause & MVPP2_CAUSE_FCS_ERR_MASK) 3073 netdev_err(dev, "FCS error\n"); 3074 if (cause & MVPP2_CAUSE_RX_FIFO_OVERRUN_MASK) 3075 netdev_err(dev, "rx fifo overrun error\n"); 3076 if (cause & MVPP2_CAUSE_TX_FIFO_UNDERRUN_MASK) 3077 netdev_err(dev, "tx fifo underrun error\n"); 3078 } 3079 3080 static int mvpp2_poll(struct napi_struct *napi, int budget) 3081 { 3082 u32 cause_rx_tx, cause_rx, cause_tx, cause_misc; 3083 int rx_done = 0; 3084 struct mvpp2_port *port = netdev_priv(napi->dev); 3085 struct mvpp2_queue_vector *qv; 3086 unsigned int thread = mvpp2_cpu_to_thread(port->priv, smp_processor_id()); 3087 3088 qv = container_of(napi, struct mvpp2_queue_vector, napi); 3089 3090 /* Rx/Tx cause register 3091 * 3092 * Bits 0-15: each bit indicates received packets on the Rx queue 3093 * (bit 0 is for Rx queue 0). 3094 * 3095 * Bits 16-23: each bit indicates transmitted packets on the Tx queue 3096 * (bit 16 is for Tx queue 0). 3097 * 3098 * Each CPU has its own Rx/Tx cause register 3099 */ 3100 cause_rx_tx = mvpp2_thread_read_relaxed(port->priv, qv->sw_thread_id, 3101 MVPP2_ISR_RX_TX_CAUSE_REG(port->id)); 3102 3103 cause_misc = cause_rx_tx & MVPP2_CAUSE_MISC_SUM_MASK; 3104 if (cause_misc) { 3105 mvpp2_cause_error(port->dev, cause_misc); 3106 3107 /* Clear the cause register */ 3108 mvpp2_write(port->priv, MVPP2_ISR_MISC_CAUSE_REG, 0); 3109 mvpp2_thread_write(port->priv, thread, 3110 MVPP2_ISR_RX_TX_CAUSE_REG(port->id), 3111 cause_rx_tx & ~MVPP2_CAUSE_MISC_SUM_MASK); 3112 } 3113 3114 if (port->has_tx_irqs) { 3115 cause_tx = cause_rx_tx & MVPP2_CAUSE_TXQ_OCCUP_DESC_ALL_MASK; 3116 if (cause_tx) { 3117 cause_tx >>= MVPP2_CAUSE_TXQ_OCCUP_DESC_ALL_OFFSET; 3118 mvpp2_tx_done(port, cause_tx, qv->sw_thread_id); 3119 } 3120 } 3121 3122 /* Process RX packets */ 3123 cause_rx = cause_rx_tx & 3124 MVPP2_CAUSE_RXQ_OCCUP_DESC_ALL_MASK(port->priv->hw_version); 3125 cause_rx <<= qv->first_rxq; 3126 cause_rx |= qv->pending_cause_rx; 3127 while (cause_rx && budget > 0) { 3128 int count; 3129 struct mvpp2_rx_queue *rxq; 3130 3131 rxq = mvpp2_get_rx_queue(port, cause_rx); 3132 if (!rxq) 3133 break; 3134 3135 count = mvpp2_rx(port, napi, budget, rxq); 3136 rx_done += count; 3137 budget -= count; 3138 if (budget > 0) { 3139 /* Clear the bit associated to this Rx queue 3140 * so that next iteration will continue from 3141 * the next Rx queue. 3142 */ 3143 cause_rx &= ~(1 << rxq->logic_rxq); 3144 } 3145 } 3146 3147 if (budget > 0) { 3148 cause_rx = 0; 3149 napi_complete_done(napi, rx_done); 3150 3151 mvpp2_qvec_interrupt_enable(qv); 3152 } 3153 qv->pending_cause_rx = cause_rx; 3154 return rx_done; 3155 } 3156 3157 static void mvpp22_mode_reconfigure(struct mvpp2_port *port) 3158 { 3159 u32 ctrl3; 3160 3161 /* comphy reconfiguration */ 3162 mvpp22_comphy_init(port); 3163 3164 /* gop reconfiguration */ 3165 mvpp22_gop_init(port); 3166 3167 /* Only GOP port 0 has an XLG MAC */ 3168 if (port->gop_id == 0) { 3169 ctrl3 = readl(port->base + MVPP22_XLG_CTRL3_REG); 3170 ctrl3 &= ~MVPP22_XLG_CTRL3_MACMODESELECT_MASK; 3171 3172 if (port->phy_interface == PHY_INTERFACE_MODE_XAUI || 3173 port->phy_interface == PHY_INTERFACE_MODE_10GKR) 3174 ctrl3 |= MVPP22_XLG_CTRL3_MACMODESELECT_10G; 3175 else 3176 ctrl3 |= MVPP22_XLG_CTRL3_MACMODESELECT_GMAC; 3177 3178 writel(ctrl3, port->base + MVPP22_XLG_CTRL3_REG); 3179 } 3180 3181 if (port->gop_id == 0 && 3182 (port->phy_interface == PHY_INTERFACE_MODE_XAUI || 3183 port->phy_interface == PHY_INTERFACE_MODE_10GKR)) 3184 mvpp2_xlg_max_rx_size_set(port); 3185 else 3186 mvpp2_gmac_max_rx_size_set(port); 3187 } 3188 3189 /* Set hw internals when starting port */ 3190 static void mvpp2_start_dev(struct mvpp2_port *port) 3191 { 3192 int i; 3193 3194 mvpp2_txp_max_tx_size_set(port); 3195 3196 for (i = 0; i < port->nqvecs; i++) 3197 napi_enable(&port->qvecs[i].napi); 3198 3199 /* Enable interrupts on all threads */ 3200 mvpp2_interrupts_enable(port); 3201 3202 if (port->priv->hw_version == MVPP22) 3203 mvpp22_mode_reconfigure(port); 3204 3205 if (port->phylink) { 3206 phylink_start(port->phylink); 3207 } else { 3208 /* Phylink isn't used as of now for ACPI, so the MAC has to be 3209 * configured manually when the interface is started. This will 3210 * be removed as soon as the phylink ACPI support lands in. 3211 */ 3212 struct phylink_link_state state = { 3213 .interface = port->phy_interface, 3214 }; 3215 mvpp2_mac_config(port->dev, MLO_AN_INBAND, &state); 3216 mvpp2_mac_link_up(port->dev, MLO_AN_INBAND, port->phy_interface, 3217 NULL); 3218 } 3219 3220 netif_tx_start_all_queues(port->dev); 3221 } 3222 3223 /* Set hw internals when stopping port */ 3224 static void mvpp2_stop_dev(struct mvpp2_port *port) 3225 { 3226 int i; 3227 3228 /* Disable interrupts on all threads */ 3229 mvpp2_interrupts_disable(port); 3230 3231 for (i = 0; i < port->nqvecs; i++) 3232 napi_disable(&port->qvecs[i].napi); 3233 3234 if (port->phylink) 3235 phylink_stop(port->phylink); 3236 phy_power_off(port->comphy); 3237 } 3238 3239 static int mvpp2_check_ringparam_valid(struct net_device *dev, 3240 struct ethtool_ringparam *ring) 3241 { 3242 u16 new_rx_pending = ring->rx_pending; 3243 u16 new_tx_pending = ring->tx_pending; 3244 3245 if (ring->rx_pending == 0 || ring->tx_pending == 0) 3246 return -EINVAL; 3247 3248 if (ring->rx_pending > MVPP2_MAX_RXD_MAX) 3249 new_rx_pending = MVPP2_MAX_RXD_MAX; 3250 else if (!IS_ALIGNED(ring->rx_pending, 16)) 3251 new_rx_pending = ALIGN(ring->rx_pending, 16); 3252 3253 if (ring->tx_pending > MVPP2_MAX_TXD_MAX) 3254 new_tx_pending = MVPP2_MAX_TXD_MAX; 3255 else if (!IS_ALIGNED(ring->tx_pending, 32)) 3256 new_tx_pending = ALIGN(ring->tx_pending, 32); 3257 3258 /* The Tx ring size cannot be smaller than the minimum number of 3259 * descriptors needed for TSO. 3260 */ 3261 if (new_tx_pending < MVPP2_MAX_SKB_DESCS) 3262 new_tx_pending = ALIGN(MVPP2_MAX_SKB_DESCS, 32); 3263 3264 if (ring->rx_pending != new_rx_pending) { 3265 netdev_info(dev, "illegal Rx ring size value %d, round to %d\n", 3266 ring->rx_pending, new_rx_pending); 3267 ring->rx_pending = new_rx_pending; 3268 } 3269 3270 if (ring->tx_pending != new_tx_pending) { 3271 netdev_info(dev, "illegal Tx ring size value %d, round to %d\n", 3272 ring->tx_pending, new_tx_pending); 3273 ring->tx_pending = new_tx_pending; 3274 } 3275 3276 return 0; 3277 } 3278 3279 static void mvpp21_get_mac_address(struct mvpp2_port *port, unsigned char *addr) 3280 { 3281 u32 mac_addr_l, mac_addr_m, mac_addr_h; 3282 3283 mac_addr_l = readl(port->base + MVPP2_GMAC_CTRL_1_REG); 3284 mac_addr_m = readl(port->priv->lms_base + MVPP2_SRC_ADDR_MIDDLE); 3285 mac_addr_h = readl(port->priv->lms_base + MVPP2_SRC_ADDR_HIGH); 3286 addr[0] = (mac_addr_h >> 24) & 0xFF; 3287 addr[1] = (mac_addr_h >> 16) & 0xFF; 3288 addr[2] = (mac_addr_h >> 8) & 0xFF; 3289 addr[3] = mac_addr_h & 0xFF; 3290 addr[4] = mac_addr_m & 0xFF; 3291 addr[5] = (mac_addr_l >> MVPP2_GMAC_SA_LOW_OFFS) & 0xFF; 3292 } 3293 3294 static int mvpp2_irqs_init(struct mvpp2_port *port) 3295 { 3296 int err, i; 3297 3298 for (i = 0; i < port->nqvecs; i++) { 3299 struct mvpp2_queue_vector *qv = port->qvecs + i; 3300 3301 if (qv->type == MVPP2_QUEUE_VECTOR_PRIVATE) { 3302 qv->mask = kzalloc(cpumask_size(), GFP_KERNEL); 3303 if (!qv->mask) { 3304 err = -ENOMEM; 3305 goto err; 3306 } 3307 3308 irq_set_status_flags(qv->irq, IRQ_NO_BALANCING); 3309 } 3310 3311 err = request_irq(qv->irq, mvpp2_isr, 0, port->dev->name, qv); 3312 if (err) 3313 goto err; 3314 3315 if (qv->type == MVPP2_QUEUE_VECTOR_PRIVATE) { 3316 unsigned int cpu; 3317 3318 for_each_present_cpu(cpu) { 3319 if (mvpp2_cpu_to_thread(port->priv, cpu) == 3320 qv->sw_thread_id) 3321 cpumask_set_cpu(cpu, qv->mask); 3322 } 3323 3324 irq_set_affinity_hint(qv->irq, qv->mask); 3325 } 3326 } 3327 3328 return 0; 3329 err: 3330 for (i = 0; i < port->nqvecs; i++) { 3331 struct mvpp2_queue_vector *qv = port->qvecs + i; 3332 3333 irq_set_affinity_hint(qv->irq, NULL); 3334 kfree(qv->mask); 3335 qv->mask = NULL; 3336 free_irq(qv->irq, qv); 3337 } 3338 3339 return err; 3340 } 3341 3342 static void mvpp2_irqs_deinit(struct mvpp2_port *port) 3343 { 3344 int i; 3345 3346 for (i = 0; i < port->nqvecs; i++) { 3347 struct mvpp2_queue_vector *qv = port->qvecs + i; 3348 3349 irq_set_affinity_hint(qv->irq, NULL); 3350 kfree(qv->mask); 3351 qv->mask = NULL; 3352 irq_clear_status_flags(qv->irq, IRQ_NO_BALANCING); 3353 free_irq(qv->irq, qv); 3354 } 3355 } 3356 3357 static bool mvpp22_rss_is_supported(void) 3358 { 3359 return queue_mode == MVPP2_QDIST_MULTI_MODE; 3360 } 3361 3362 static int mvpp2_open(struct net_device *dev) 3363 { 3364 struct mvpp2_port *port = netdev_priv(dev); 3365 struct mvpp2 *priv = port->priv; 3366 unsigned char mac_bcast[ETH_ALEN] = { 3367 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }; 3368 bool valid = false; 3369 int err; 3370 3371 err = mvpp2_prs_mac_da_accept(port, mac_bcast, true); 3372 if (err) { 3373 netdev_err(dev, "mvpp2_prs_mac_da_accept BC failed\n"); 3374 return err; 3375 } 3376 err = mvpp2_prs_mac_da_accept(port, dev->dev_addr, true); 3377 if (err) { 3378 netdev_err(dev, "mvpp2_prs_mac_da_accept own addr failed\n"); 3379 return err; 3380 } 3381 err = mvpp2_prs_tag_mode_set(port->priv, port->id, MVPP2_TAG_TYPE_MH); 3382 if (err) { 3383 netdev_err(dev, "mvpp2_prs_tag_mode_set failed\n"); 3384 return err; 3385 } 3386 err = mvpp2_prs_def_flow(port); 3387 if (err) { 3388 netdev_err(dev, "mvpp2_prs_def_flow failed\n"); 3389 return err; 3390 } 3391 3392 /* Allocate the Rx/Tx queues */ 3393 err = mvpp2_setup_rxqs(port); 3394 if (err) { 3395 netdev_err(port->dev, "cannot allocate Rx queues\n"); 3396 return err; 3397 } 3398 3399 err = mvpp2_setup_txqs(port); 3400 if (err) { 3401 netdev_err(port->dev, "cannot allocate Tx queues\n"); 3402 goto err_cleanup_rxqs; 3403 } 3404 3405 err = mvpp2_irqs_init(port); 3406 if (err) { 3407 netdev_err(port->dev, "cannot init IRQs\n"); 3408 goto err_cleanup_txqs; 3409 } 3410 3411 /* Phylink isn't supported yet in ACPI mode */ 3412 if (port->of_node) { 3413 err = phylink_of_phy_connect(port->phylink, port->of_node, 0); 3414 if (err) { 3415 netdev_err(port->dev, "could not attach PHY (%d)\n", 3416 err); 3417 goto err_free_irq; 3418 } 3419 3420 valid = true; 3421 } 3422 3423 if (priv->hw_version == MVPP22 && port->link_irq && !port->phylink) { 3424 err = request_irq(port->link_irq, mvpp2_link_status_isr, 0, 3425 dev->name, port); 3426 if (err) { 3427 netdev_err(port->dev, "cannot request link IRQ %d\n", 3428 port->link_irq); 3429 goto err_free_irq; 3430 } 3431 3432 mvpp22_gop_setup_irq(port); 3433 3434 /* In default link is down */ 3435 netif_carrier_off(port->dev); 3436 3437 valid = true; 3438 } else { 3439 port->link_irq = 0; 3440 } 3441 3442 if (!valid) { 3443 netdev_err(port->dev, 3444 "invalid configuration: no dt or link IRQ"); 3445 goto err_free_irq; 3446 } 3447 3448 /* Unmask interrupts on all CPUs */ 3449 on_each_cpu(mvpp2_interrupts_unmask, port, 1); 3450 mvpp2_shared_interrupt_mask_unmask(port, false); 3451 3452 mvpp2_start_dev(port); 3453 3454 /* Start hardware statistics gathering */ 3455 queue_delayed_work(priv->stats_queue, &port->stats_work, 3456 MVPP2_MIB_COUNTERS_STATS_DELAY); 3457 3458 return 0; 3459 3460 err_free_irq: 3461 mvpp2_irqs_deinit(port); 3462 err_cleanup_txqs: 3463 mvpp2_cleanup_txqs(port); 3464 err_cleanup_rxqs: 3465 mvpp2_cleanup_rxqs(port); 3466 return err; 3467 } 3468 3469 static int mvpp2_stop(struct net_device *dev) 3470 { 3471 struct mvpp2_port *port = netdev_priv(dev); 3472 struct mvpp2_port_pcpu *port_pcpu; 3473 unsigned int thread; 3474 3475 mvpp2_stop_dev(port); 3476 3477 /* Mask interrupts on all threads */ 3478 on_each_cpu(mvpp2_interrupts_mask, port, 1); 3479 mvpp2_shared_interrupt_mask_unmask(port, true); 3480 3481 if (port->phylink) 3482 phylink_disconnect_phy(port->phylink); 3483 if (port->link_irq) 3484 free_irq(port->link_irq, port); 3485 3486 mvpp2_irqs_deinit(port); 3487 if (!port->has_tx_irqs) { 3488 for (thread = 0; thread < port->priv->nthreads; thread++) { 3489 port_pcpu = per_cpu_ptr(port->pcpu, thread); 3490 3491 hrtimer_cancel(&port_pcpu->tx_done_timer); 3492 port_pcpu->timer_scheduled = false; 3493 tasklet_kill(&port_pcpu->tx_done_tasklet); 3494 } 3495 } 3496 mvpp2_cleanup_rxqs(port); 3497 mvpp2_cleanup_txqs(port); 3498 3499 cancel_delayed_work_sync(&port->stats_work); 3500 3501 return 0; 3502 } 3503 3504 static int mvpp2_prs_mac_da_accept_list(struct mvpp2_port *port, 3505 struct netdev_hw_addr_list *list) 3506 { 3507 struct netdev_hw_addr *ha; 3508 int ret; 3509 3510 netdev_hw_addr_list_for_each(ha, list) { 3511 ret = mvpp2_prs_mac_da_accept(port, ha->addr, true); 3512 if (ret) 3513 return ret; 3514 } 3515 3516 return 0; 3517 } 3518 3519 static void mvpp2_set_rx_promisc(struct mvpp2_port *port, bool enable) 3520 { 3521 if (!enable && (port->dev->features & NETIF_F_HW_VLAN_CTAG_FILTER)) 3522 mvpp2_prs_vid_enable_filtering(port); 3523 else 3524 mvpp2_prs_vid_disable_filtering(port); 3525 3526 mvpp2_prs_mac_promisc_set(port->priv, port->id, 3527 MVPP2_PRS_L2_UNI_CAST, enable); 3528 3529 mvpp2_prs_mac_promisc_set(port->priv, port->id, 3530 MVPP2_PRS_L2_MULTI_CAST, enable); 3531 } 3532 3533 static void mvpp2_set_rx_mode(struct net_device *dev) 3534 { 3535 struct mvpp2_port *port = netdev_priv(dev); 3536 3537 /* Clear the whole UC and MC list */ 3538 mvpp2_prs_mac_del_all(port); 3539 3540 if (dev->flags & IFF_PROMISC) { 3541 mvpp2_set_rx_promisc(port, true); 3542 return; 3543 } 3544 3545 mvpp2_set_rx_promisc(port, false); 3546 3547 if (netdev_uc_count(dev) > MVPP2_PRS_MAC_UC_FILT_MAX || 3548 mvpp2_prs_mac_da_accept_list(port, &dev->uc)) 3549 mvpp2_prs_mac_promisc_set(port->priv, port->id, 3550 MVPP2_PRS_L2_UNI_CAST, true); 3551 3552 if (dev->flags & IFF_ALLMULTI) { 3553 mvpp2_prs_mac_promisc_set(port->priv, port->id, 3554 MVPP2_PRS_L2_MULTI_CAST, true); 3555 return; 3556 } 3557 3558 if (netdev_mc_count(dev) > MVPP2_PRS_MAC_MC_FILT_MAX || 3559 mvpp2_prs_mac_da_accept_list(port, &dev->mc)) 3560 mvpp2_prs_mac_promisc_set(port->priv, port->id, 3561 MVPP2_PRS_L2_MULTI_CAST, true); 3562 } 3563 3564 static int mvpp2_set_mac_address(struct net_device *dev, void *p) 3565 { 3566 const struct sockaddr *addr = p; 3567 int err; 3568 3569 if (!is_valid_ether_addr(addr->sa_data)) 3570 return -EADDRNOTAVAIL; 3571 3572 err = mvpp2_prs_update_mac_da(dev, addr->sa_data); 3573 if (err) { 3574 /* Reconfigure parser accept the original MAC address */ 3575 mvpp2_prs_update_mac_da(dev, dev->dev_addr); 3576 netdev_err(dev, "failed to change MAC address\n"); 3577 } 3578 return err; 3579 } 3580 3581 static int mvpp2_change_mtu(struct net_device *dev, int mtu) 3582 { 3583 struct mvpp2_port *port = netdev_priv(dev); 3584 int err; 3585 3586 if (!IS_ALIGNED(MVPP2_RX_PKT_SIZE(mtu), 8)) { 3587 netdev_info(dev, "illegal MTU value %d, round to %d\n", mtu, 3588 ALIGN(MVPP2_RX_PKT_SIZE(mtu), 8)); 3589 mtu = ALIGN(MVPP2_RX_PKT_SIZE(mtu), 8); 3590 } 3591 3592 if (!netif_running(dev)) { 3593 err = mvpp2_bm_update_mtu(dev, mtu); 3594 if (!err) { 3595 port->pkt_size = MVPP2_RX_PKT_SIZE(mtu); 3596 return 0; 3597 } 3598 3599 /* Reconfigure BM to the original MTU */ 3600 err = mvpp2_bm_update_mtu(dev, dev->mtu); 3601 if (err) 3602 goto log_error; 3603 } 3604 3605 mvpp2_stop_dev(port); 3606 3607 err = mvpp2_bm_update_mtu(dev, mtu); 3608 if (!err) { 3609 port->pkt_size = MVPP2_RX_PKT_SIZE(mtu); 3610 goto out_start; 3611 } 3612 3613 /* Reconfigure BM to the original MTU */ 3614 err = mvpp2_bm_update_mtu(dev, dev->mtu); 3615 if (err) 3616 goto log_error; 3617 3618 out_start: 3619 mvpp2_start_dev(port); 3620 mvpp2_egress_enable(port); 3621 mvpp2_ingress_enable(port); 3622 3623 return 0; 3624 log_error: 3625 netdev_err(dev, "failed to change MTU\n"); 3626 return err; 3627 } 3628 3629 static void 3630 mvpp2_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats) 3631 { 3632 struct mvpp2_port *port = netdev_priv(dev); 3633 unsigned int start; 3634 unsigned int cpu; 3635 3636 for_each_possible_cpu(cpu) { 3637 struct mvpp2_pcpu_stats *cpu_stats; 3638 u64 rx_packets; 3639 u64 rx_bytes; 3640 u64 tx_packets; 3641 u64 tx_bytes; 3642 3643 cpu_stats = per_cpu_ptr(port->stats, cpu); 3644 do { 3645 start = u64_stats_fetch_begin_irq(&cpu_stats->syncp); 3646 rx_packets = cpu_stats->rx_packets; 3647 rx_bytes = cpu_stats->rx_bytes; 3648 tx_packets = cpu_stats->tx_packets; 3649 tx_bytes = cpu_stats->tx_bytes; 3650 } while (u64_stats_fetch_retry_irq(&cpu_stats->syncp, start)); 3651 3652 stats->rx_packets += rx_packets; 3653 stats->rx_bytes += rx_bytes; 3654 stats->tx_packets += tx_packets; 3655 stats->tx_bytes += tx_bytes; 3656 } 3657 3658 stats->rx_errors = dev->stats.rx_errors; 3659 stats->rx_dropped = dev->stats.rx_dropped; 3660 stats->tx_dropped = dev->stats.tx_dropped; 3661 } 3662 3663 static int mvpp2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) 3664 { 3665 struct mvpp2_port *port = netdev_priv(dev); 3666 3667 if (!port->phylink) 3668 return -ENOTSUPP; 3669 3670 return phylink_mii_ioctl(port->phylink, ifr, cmd); 3671 } 3672 3673 static int mvpp2_vlan_rx_add_vid(struct net_device *dev, __be16 proto, u16 vid) 3674 { 3675 struct mvpp2_port *port = netdev_priv(dev); 3676 int ret; 3677 3678 ret = mvpp2_prs_vid_entry_add(port, vid); 3679 if (ret) 3680 netdev_err(dev, "rx-vlan-filter offloading cannot accept more than %d VIDs per port\n", 3681 MVPP2_PRS_VLAN_FILT_MAX - 1); 3682 return ret; 3683 } 3684 3685 static int mvpp2_vlan_rx_kill_vid(struct net_device *dev, __be16 proto, u16 vid) 3686 { 3687 struct mvpp2_port *port = netdev_priv(dev); 3688 3689 mvpp2_prs_vid_entry_remove(port, vid); 3690 return 0; 3691 } 3692 3693 static int mvpp2_set_features(struct net_device *dev, 3694 netdev_features_t features) 3695 { 3696 netdev_features_t changed = dev->features ^ features; 3697 struct mvpp2_port *port = netdev_priv(dev); 3698 3699 if (changed & NETIF_F_HW_VLAN_CTAG_FILTER) { 3700 if (features & NETIF_F_HW_VLAN_CTAG_FILTER) { 3701 mvpp2_prs_vid_enable_filtering(port); 3702 } else { 3703 /* Invalidate all registered VID filters for this 3704 * port 3705 */ 3706 mvpp2_prs_vid_remove_all(port); 3707 3708 mvpp2_prs_vid_disable_filtering(port); 3709 } 3710 } 3711 3712 if (changed & NETIF_F_RXHASH) { 3713 if (features & NETIF_F_RXHASH) 3714 mvpp22_rss_enable(port); 3715 else 3716 mvpp22_rss_disable(port); 3717 } 3718 3719 return 0; 3720 } 3721 3722 /* Ethtool methods */ 3723 3724 static int mvpp2_ethtool_nway_reset(struct net_device *dev) 3725 { 3726 struct mvpp2_port *port = netdev_priv(dev); 3727 3728 if (!port->phylink) 3729 return -ENOTSUPP; 3730 3731 return phylink_ethtool_nway_reset(port->phylink); 3732 } 3733 3734 /* Set interrupt coalescing for ethtools */ 3735 static int mvpp2_ethtool_set_coalesce(struct net_device *dev, 3736 struct ethtool_coalesce *c) 3737 { 3738 struct mvpp2_port *port = netdev_priv(dev); 3739 int queue; 3740 3741 for (queue = 0; queue < port->nrxqs; queue++) { 3742 struct mvpp2_rx_queue *rxq = port->rxqs[queue]; 3743 3744 rxq->time_coal = c->rx_coalesce_usecs; 3745 rxq->pkts_coal = c->rx_max_coalesced_frames; 3746 mvpp2_rx_pkts_coal_set(port, rxq); 3747 mvpp2_rx_time_coal_set(port, rxq); 3748 } 3749 3750 if (port->has_tx_irqs) { 3751 port->tx_time_coal = c->tx_coalesce_usecs; 3752 mvpp2_tx_time_coal_set(port); 3753 } 3754 3755 for (queue = 0; queue < port->ntxqs; queue++) { 3756 struct mvpp2_tx_queue *txq = port->txqs[queue]; 3757 3758 txq->done_pkts_coal = c->tx_max_coalesced_frames; 3759 3760 if (port->has_tx_irqs) 3761 mvpp2_tx_pkts_coal_set(port, txq); 3762 } 3763 3764 return 0; 3765 } 3766 3767 /* get coalescing for ethtools */ 3768 static int mvpp2_ethtool_get_coalesce(struct net_device *dev, 3769 struct ethtool_coalesce *c) 3770 { 3771 struct mvpp2_port *port = netdev_priv(dev); 3772 3773 c->rx_coalesce_usecs = port->rxqs[0]->time_coal; 3774 c->rx_max_coalesced_frames = port->rxqs[0]->pkts_coal; 3775 c->tx_max_coalesced_frames = port->txqs[0]->done_pkts_coal; 3776 c->tx_coalesce_usecs = port->tx_time_coal; 3777 return 0; 3778 } 3779 3780 static void mvpp2_ethtool_get_drvinfo(struct net_device *dev, 3781 struct ethtool_drvinfo *drvinfo) 3782 { 3783 strlcpy(drvinfo->driver, MVPP2_DRIVER_NAME, 3784 sizeof(drvinfo->driver)); 3785 strlcpy(drvinfo->version, MVPP2_DRIVER_VERSION, 3786 sizeof(drvinfo->version)); 3787 strlcpy(drvinfo->bus_info, dev_name(&dev->dev), 3788 sizeof(drvinfo->bus_info)); 3789 } 3790 3791 static void mvpp2_ethtool_get_ringparam(struct net_device *dev, 3792 struct ethtool_ringparam *ring) 3793 { 3794 struct mvpp2_port *port = netdev_priv(dev); 3795 3796 ring->rx_max_pending = MVPP2_MAX_RXD_MAX; 3797 ring->tx_max_pending = MVPP2_MAX_TXD_MAX; 3798 ring->rx_pending = port->rx_ring_size; 3799 ring->tx_pending = port->tx_ring_size; 3800 } 3801 3802 static int mvpp2_ethtool_set_ringparam(struct net_device *dev, 3803 struct ethtool_ringparam *ring) 3804 { 3805 struct mvpp2_port *port = netdev_priv(dev); 3806 u16 prev_rx_ring_size = port->rx_ring_size; 3807 u16 prev_tx_ring_size = port->tx_ring_size; 3808 int err; 3809 3810 err = mvpp2_check_ringparam_valid(dev, ring); 3811 if (err) 3812 return err; 3813 3814 if (!netif_running(dev)) { 3815 port->rx_ring_size = ring->rx_pending; 3816 port->tx_ring_size = ring->tx_pending; 3817 return 0; 3818 } 3819 3820 /* The interface is running, so we have to force a 3821 * reallocation of the queues 3822 */ 3823 mvpp2_stop_dev(port); 3824 mvpp2_cleanup_rxqs(port); 3825 mvpp2_cleanup_txqs(port); 3826 3827 port->rx_ring_size = ring->rx_pending; 3828 port->tx_ring_size = ring->tx_pending; 3829 3830 err = mvpp2_setup_rxqs(port); 3831 if (err) { 3832 /* Reallocate Rx queues with the original ring size */ 3833 port->rx_ring_size = prev_rx_ring_size; 3834 ring->rx_pending = prev_rx_ring_size; 3835 err = mvpp2_setup_rxqs(port); 3836 if (err) 3837 goto err_out; 3838 } 3839 err = mvpp2_setup_txqs(port); 3840 if (err) { 3841 /* Reallocate Tx queues with the original ring size */ 3842 port->tx_ring_size = prev_tx_ring_size; 3843 ring->tx_pending = prev_tx_ring_size; 3844 err = mvpp2_setup_txqs(port); 3845 if (err) 3846 goto err_clean_rxqs; 3847 } 3848 3849 mvpp2_start_dev(port); 3850 mvpp2_egress_enable(port); 3851 mvpp2_ingress_enable(port); 3852 3853 return 0; 3854 3855 err_clean_rxqs: 3856 mvpp2_cleanup_rxqs(port); 3857 err_out: 3858 netdev_err(dev, "failed to change ring parameters"); 3859 return err; 3860 } 3861 3862 static void mvpp2_ethtool_get_pause_param(struct net_device *dev, 3863 struct ethtool_pauseparam *pause) 3864 { 3865 struct mvpp2_port *port = netdev_priv(dev); 3866 3867 if (!port->phylink) 3868 return; 3869 3870 phylink_ethtool_get_pauseparam(port->phylink, pause); 3871 } 3872 3873 static int mvpp2_ethtool_set_pause_param(struct net_device *dev, 3874 struct ethtool_pauseparam *pause) 3875 { 3876 struct mvpp2_port *port = netdev_priv(dev); 3877 3878 if (!port->phylink) 3879 return -ENOTSUPP; 3880 3881 return phylink_ethtool_set_pauseparam(port->phylink, pause); 3882 } 3883 3884 static int mvpp2_ethtool_get_link_ksettings(struct net_device *dev, 3885 struct ethtool_link_ksettings *cmd) 3886 { 3887 struct mvpp2_port *port = netdev_priv(dev); 3888 3889 if (!port->phylink) 3890 return -ENOTSUPP; 3891 3892 return phylink_ethtool_ksettings_get(port->phylink, cmd); 3893 } 3894 3895 static int mvpp2_ethtool_set_link_ksettings(struct net_device *dev, 3896 const struct ethtool_link_ksettings *cmd) 3897 { 3898 struct mvpp2_port *port = netdev_priv(dev); 3899 3900 if (!port->phylink) 3901 return -ENOTSUPP; 3902 3903 return phylink_ethtool_ksettings_set(port->phylink, cmd); 3904 } 3905 3906 static int mvpp2_ethtool_get_rxnfc(struct net_device *dev, 3907 struct ethtool_rxnfc *info, u32 *rules) 3908 { 3909 struct mvpp2_port *port = netdev_priv(dev); 3910 int ret = 0; 3911 3912 if (!mvpp22_rss_is_supported()) 3913 return -EOPNOTSUPP; 3914 3915 switch (info->cmd) { 3916 case ETHTOOL_GRXFH: 3917 ret = mvpp2_ethtool_rxfh_get(port, info); 3918 break; 3919 case ETHTOOL_GRXRINGS: 3920 info->data = port->nrxqs; 3921 break; 3922 default: 3923 return -ENOTSUPP; 3924 } 3925 3926 return ret; 3927 } 3928 3929 static int mvpp2_ethtool_set_rxnfc(struct net_device *dev, 3930 struct ethtool_rxnfc *info) 3931 { 3932 struct mvpp2_port *port = netdev_priv(dev); 3933 int ret = 0; 3934 3935 if (!mvpp22_rss_is_supported()) 3936 return -EOPNOTSUPP; 3937 3938 switch (info->cmd) { 3939 case ETHTOOL_SRXFH: 3940 ret = mvpp2_ethtool_rxfh_set(port, info); 3941 break; 3942 default: 3943 return -EOPNOTSUPP; 3944 } 3945 return ret; 3946 } 3947 3948 static u32 mvpp2_ethtool_get_rxfh_indir_size(struct net_device *dev) 3949 { 3950 return mvpp22_rss_is_supported() ? MVPP22_RSS_TABLE_ENTRIES : 0; 3951 } 3952 3953 static int mvpp2_ethtool_get_rxfh(struct net_device *dev, u32 *indir, u8 *key, 3954 u8 *hfunc) 3955 { 3956 struct mvpp2_port *port = netdev_priv(dev); 3957 3958 if (!mvpp22_rss_is_supported()) 3959 return -EOPNOTSUPP; 3960 3961 if (indir) 3962 memcpy(indir, port->indir, 3963 ARRAY_SIZE(port->indir) * sizeof(port->indir[0])); 3964 3965 if (hfunc) 3966 *hfunc = ETH_RSS_HASH_CRC32; 3967 3968 return 0; 3969 } 3970 3971 static int mvpp2_ethtool_set_rxfh(struct net_device *dev, const u32 *indir, 3972 const u8 *key, const u8 hfunc) 3973 { 3974 struct mvpp2_port *port = netdev_priv(dev); 3975 3976 if (!mvpp22_rss_is_supported()) 3977 return -EOPNOTSUPP; 3978 3979 if (hfunc != ETH_RSS_HASH_NO_CHANGE && hfunc != ETH_RSS_HASH_CRC32) 3980 return -EOPNOTSUPP; 3981 3982 if (key) 3983 return -EOPNOTSUPP; 3984 3985 if (indir) { 3986 memcpy(port->indir, indir, 3987 ARRAY_SIZE(port->indir) * sizeof(port->indir[0])); 3988 mvpp22_rss_fill_table(port, port->id); 3989 } 3990 3991 return 0; 3992 } 3993 3994 /* Device ops */ 3995 3996 static const struct net_device_ops mvpp2_netdev_ops = { 3997 .ndo_open = mvpp2_open, 3998 .ndo_stop = mvpp2_stop, 3999 .ndo_start_xmit = mvpp2_tx, 4000 .ndo_set_rx_mode = mvpp2_set_rx_mode, 4001 .ndo_set_mac_address = mvpp2_set_mac_address, 4002 .ndo_change_mtu = mvpp2_change_mtu, 4003 .ndo_get_stats64 = mvpp2_get_stats64, 4004 .ndo_do_ioctl = mvpp2_ioctl, 4005 .ndo_vlan_rx_add_vid = mvpp2_vlan_rx_add_vid, 4006 .ndo_vlan_rx_kill_vid = mvpp2_vlan_rx_kill_vid, 4007 .ndo_set_features = mvpp2_set_features, 4008 }; 4009 4010 static const struct ethtool_ops mvpp2_eth_tool_ops = { 4011 .nway_reset = mvpp2_ethtool_nway_reset, 4012 .get_link = ethtool_op_get_link, 4013 .set_coalesce = mvpp2_ethtool_set_coalesce, 4014 .get_coalesce = mvpp2_ethtool_get_coalesce, 4015 .get_drvinfo = mvpp2_ethtool_get_drvinfo, 4016 .get_ringparam = mvpp2_ethtool_get_ringparam, 4017 .set_ringparam = mvpp2_ethtool_set_ringparam, 4018 .get_strings = mvpp2_ethtool_get_strings, 4019 .get_ethtool_stats = mvpp2_ethtool_get_stats, 4020 .get_sset_count = mvpp2_ethtool_get_sset_count, 4021 .get_pauseparam = mvpp2_ethtool_get_pause_param, 4022 .set_pauseparam = mvpp2_ethtool_set_pause_param, 4023 .get_link_ksettings = mvpp2_ethtool_get_link_ksettings, 4024 .set_link_ksettings = mvpp2_ethtool_set_link_ksettings, 4025 .get_rxnfc = mvpp2_ethtool_get_rxnfc, 4026 .set_rxnfc = mvpp2_ethtool_set_rxnfc, 4027 .get_rxfh_indir_size = mvpp2_ethtool_get_rxfh_indir_size, 4028 .get_rxfh = mvpp2_ethtool_get_rxfh, 4029 .set_rxfh = mvpp2_ethtool_set_rxfh, 4030 4031 }; 4032 4033 /* Used for PPv2.1, or PPv2.2 with the old Device Tree binding that 4034 * had a single IRQ defined per-port. 4035 */ 4036 static int mvpp2_simple_queue_vectors_init(struct mvpp2_port *port, 4037 struct device_node *port_node) 4038 { 4039 struct mvpp2_queue_vector *v = &port->qvecs[0]; 4040 4041 v->first_rxq = 0; 4042 v->nrxqs = port->nrxqs; 4043 v->type = MVPP2_QUEUE_VECTOR_SHARED; 4044 v->sw_thread_id = 0; 4045 v->sw_thread_mask = *cpumask_bits(cpu_online_mask); 4046 v->port = port; 4047 v->irq = irq_of_parse_and_map(port_node, 0); 4048 if (v->irq <= 0) 4049 return -EINVAL; 4050 netif_napi_add(port->dev, &v->napi, mvpp2_poll, 4051 NAPI_POLL_WEIGHT); 4052 4053 port->nqvecs = 1; 4054 4055 return 0; 4056 } 4057 4058 static int mvpp2_multi_queue_vectors_init(struct mvpp2_port *port, 4059 struct device_node *port_node) 4060 { 4061 struct mvpp2 *priv = port->priv; 4062 struct mvpp2_queue_vector *v; 4063 int i, ret; 4064 4065 switch (queue_mode) { 4066 case MVPP2_QDIST_SINGLE_MODE: 4067 port->nqvecs = priv->nthreads + 1; 4068 break; 4069 case MVPP2_QDIST_MULTI_MODE: 4070 port->nqvecs = priv->nthreads; 4071 break; 4072 } 4073 4074 for (i = 0; i < port->nqvecs; i++) { 4075 char irqname[16]; 4076 4077 v = port->qvecs + i; 4078 4079 v->port = port; 4080 v->type = MVPP2_QUEUE_VECTOR_PRIVATE; 4081 v->sw_thread_id = i; 4082 v->sw_thread_mask = BIT(i); 4083 4084 if (port->flags & MVPP2_F_DT_COMPAT) 4085 snprintf(irqname, sizeof(irqname), "tx-cpu%d", i); 4086 else 4087 snprintf(irqname, sizeof(irqname), "hif%d", i); 4088 4089 if (queue_mode == MVPP2_QDIST_MULTI_MODE) { 4090 v->first_rxq = i * MVPP2_DEFAULT_RXQ; 4091 v->nrxqs = MVPP2_DEFAULT_RXQ; 4092 } else if (queue_mode == MVPP2_QDIST_SINGLE_MODE && 4093 i == (port->nqvecs - 1)) { 4094 v->first_rxq = 0; 4095 v->nrxqs = port->nrxqs; 4096 v->type = MVPP2_QUEUE_VECTOR_SHARED; 4097 4098 if (port->flags & MVPP2_F_DT_COMPAT) 4099 strncpy(irqname, "rx-shared", sizeof(irqname)); 4100 } 4101 4102 if (port_node) 4103 v->irq = of_irq_get_byname(port_node, irqname); 4104 else 4105 v->irq = fwnode_irq_get(port->fwnode, i); 4106 if (v->irq <= 0) { 4107 ret = -EINVAL; 4108 goto err; 4109 } 4110 4111 netif_napi_add(port->dev, &v->napi, mvpp2_poll, 4112 NAPI_POLL_WEIGHT); 4113 } 4114 4115 return 0; 4116 4117 err: 4118 for (i = 0; i < port->nqvecs; i++) 4119 irq_dispose_mapping(port->qvecs[i].irq); 4120 return ret; 4121 } 4122 4123 static int mvpp2_queue_vectors_init(struct mvpp2_port *port, 4124 struct device_node *port_node) 4125 { 4126 if (port->has_tx_irqs) 4127 return mvpp2_multi_queue_vectors_init(port, port_node); 4128 else 4129 return mvpp2_simple_queue_vectors_init(port, port_node); 4130 } 4131 4132 static void mvpp2_queue_vectors_deinit(struct mvpp2_port *port) 4133 { 4134 int i; 4135 4136 for (i = 0; i < port->nqvecs; i++) 4137 irq_dispose_mapping(port->qvecs[i].irq); 4138 } 4139 4140 /* Configure Rx queue group interrupt for this port */ 4141 static void mvpp2_rx_irqs_setup(struct mvpp2_port *port) 4142 { 4143 struct mvpp2 *priv = port->priv; 4144 u32 val; 4145 int i; 4146 4147 if (priv->hw_version == MVPP21) { 4148 mvpp2_write(priv, MVPP21_ISR_RXQ_GROUP_REG(port->id), 4149 port->nrxqs); 4150 return; 4151 } 4152 4153 /* Handle the more complicated PPv2.2 case */ 4154 for (i = 0; i < port->nqvecs; i++) { 4155 struct mvpp2_queue_vector *qv = port->qvecs + i; 4156 4157 if (!qv->nrxqs) 4158 continue; 4159 4160 val = qv->sw_thread_id; 4161 val |= port->id << MVPP22_ISR_RXQ_GROUP_INDEX_GROUP_OFFSET; 4162 mvpp2_write(priv, MVPP22_ISR_RXQ_GROUP_INDEX_REG, val); 4163 4164 val = qv->first_rxq; 4165 val |= qv->nrxqs << MVPP22_ISR_RXQ_SUB_GROUP_SIZE_OFFSET; 4166 mvpp2_write(priv, MVPP22_ISR_RXQ_SUB_GROUP_CONFIG_REG, val); 4167 } 4168 } 4169 4170 /* Initialize port HW */ 4171 static int mvpp2_port_init(struct mvpp2_port *port) 4172 { 4173 struct device *dev = port->dev->dev.parent; 4174 struct mvpp2 *priv = port->priv; 4175 struct mvpp2_txq_pcpu *txq_pcpu; 4176 unsigned int thread; 4177 int queue, err; 4178 4179 /* Checks for hardware constraints */ 4180 if (port->first_rxq + port->nrxqs > 4181 MVPP2_MAX_PORTS * priv->max_port_rxqs) 4182 return -EINVAL; 4183 4184 if (port->nrxqs % MVPP2_DEFAULT_RXQ || 4185 port->nrxqs > priv->max_port_rxqs || port->ntxqs > MVPP2_MAX_TXQ) 4186 return -EINVAL; 4187 4188 /* Disable port */ 4189 mvpp2_egress_disable(port); 4190 mvpp2_port_disable(port); 4191 4192 port->tx_time_coal = MVPP2_TXDONE_COAL_USEC; 4193 4194 port->txqs = devm_kcalloc(dev, port->ntxqs, sizeof(*port->txqs), 4195 GFP_KERNEL); 4196 if (!port->txqs) 4197 return -ENOMEM; 4198 4199 /* Associate physical Tx queues to this port and initialize. 4200 * The mapping is predefined. 4201 */ 4202 for (queue = 0; queue < port->ntxqs; queue++) { 4203 int queue_phy_id = mvpp2_txq_phys(port->id, queue); 4204 struct mvpp2_tx_queue *txq; 4205 4206 txq = devm_kzalloc(dev, sizeof(*txq), GFP_KERNEL); 4207 if (!txq) { 4208 err = -ENOMEM; 4209 goto err_free_percpu; 4210 } 4211 4212 txq->pcpu = alloc_percpu(struct mvpp2_txq_pcpu); 4213 if (!txq->pcpu) { 4214 err = -ENOMEM; 4215 goto err_free_percpu; 4216 } 4217 4218 txq->id = queue_phy_id; 4219 txq->log_id = queue; 4220 txq->done_pkts_coal = MVPP2_TXDONE_COAL_PKTS_THRESH; 4221 for (thread = 0; thread < priv->nthreads; thread++) { 4222 txq_pcpu = per_cpu_ptr(txq->pcpu, thread); 4223 txq_pcpu->thread = thread; 4224 } 4225 4226 port->txqs[queue] = txq; 4227 } 4228 4229 port->rxqs = devm_kcalloc(dev, port->nrxqs, sizeof(*port->rxqs), 4230 GFP_KERNEL); 4231 if (!port->rxqs) { 4232 err = -ENOMEM; 4233 goto err_free_percpu; 4234 } 4235 4236 /* Allocate and initialize Rx queue for this port */ 4237 for (queue = 0; queue < port->nrxqs; queue++) { 4238 struct mvpp2_rx_queue *rxq; 4239 4240 /* Map physical Rx queue to port's logical Rx queue */ 4241 rxq = devm_kzalloc(dev, sizeof(*rxq), GFP_KERNEL); 4242 if (!rxq) { 4243 err = -ENOMEM; 4244 goto err_free_percpu; 4245 } 4246 /* Map this Rx queue to a physical queue */ 4247 rxq->id = port->first_rxq + queue; 4248 rxq->port = port->id; 4249 rxq->logic_rxq = queue; 4250 4251 port->rxqs[queue] = rxq; 4252 } 4253 4254 mvpp2_rx_irqs_setup(port); 4255 4256 /* Create Rx descriptor rings */ 4257 for (queue = 0; queue < port->nrxqs; queue++) { 4258 struct mvpp2_rx_queue *rxq = port->rxqs[queue]; 4259 4260 rxq->size = port->rx_ring_size; 4261 rxq->pkts_coal = MVPP2_RX_COAL_PKTS; 4262 rxq->time_coal = MVPP2_RX_COAL_USEC; 4263 } 4264 4265 mvpp2_ingress_disable(port); 4266 4267 /* Port default configuration */ 4268 mvpp2_defaults_set(port); 4269 4270 /* Port's classifier configuration */ 4271 mvpp2_cls_oversize_rxq_set(port); 4272 mvpp2_cls_port_config(port); 4273 4274 if (mvpp22_rss_is_supported()) 4275 mvpp22_rss_port_init(port); 4276 4277 /* Provide an initial Rx packet size */ 4278 port->pkt_size = MVPP2_RX_PKT_SIZE(port->dev->mtu); 4279 4280 /* Initialize pools for swf */ 4281 err = mvpp2_swf_bm_pool_init(port); 4282 if (err) 4283 goto err_free_percpu; 4284 4285 return 0; 4286 4287 err_free_percpu: 4288 for (queue = 0; queue < port->ntxqs; queue++) { 4289 if (!port->txqs[queue]) 4290 continue; 4291 free_percpu(port->txqs[queue]->pcpu); 4292 } 4293 return err; 4294 } 4295 4296 static bool mvpp22_port_has_legacy_tx_irqs(struct device_node *port_node, 4297 unsigned long *flags) 4298 { 4299 char *irqs[5] = { "rx-shared", "tx-cpu0", "tx-cpu1", "tx-cpu2", 4300 "tx-cpu3" }; 4301 int i; 4302 4303 for (i = 0; i < 5; i++) 4304 if (of_property_match_string(port_node, "interrupt-names", 4305 irqs[i]) < 0) 4306 return false; 4307 4308 *flags |= MVPP2_F_DT_COMPAT; 4309 return true; 4310 } 4311 4312 /* Checks if the port dt description has the required Tx interrupts: 4313 * - PPv2.1: there are no such interrupts. 4314 * - PPv2.2: 4315 * - The old DTs have: "rx-shared", "tx-cpuX" with X in [0...3] 4316 * - The new ones have: "hifX" with X in [0..8] 4317 * 4318 * All those variants are supported to keep the backward compatibility. 4319 */ 4320 static bool mvpp2_port_has_irqs(struct mvpp2 *priv, 4321 struct device_node *port_node, 4322 unsigned long *flags) 4323 { 4324 char name[5]; 4325 int i; 4326 4327 /* ACPI */ 4328 if (!port_node) 4329 return true; 4330 4331 if (priv->hw_version == MVPP21) 4332 return false; 4333 4334 if (mvpp22_port_has_legacy_tx_irqs(port_node, flags)) 4335 return true; 4336 4337 for (i = 0; i < MVPP2_MAX_THREADS; i++) { 4338 snprintf(name, 5, "hif%d", i); 4339 if (of_property_match_string(port_node, "interrupt-names", 4340 name) < 0) 4341 return false; 4342 } 4343 4344 return true; 4345 } 4346 4347 static void mvpp2_port_copy_mac_addr(struct net_device *dev, struct mvpp2 *priv, 4348 struct fwnode_handle *fwnode, 4349 char **mac_from) 4350 { 4351 struct mvpp2_port *port = netdev_priv(dev); 4352 char hw_mac_addr[ETH_ALEN] = {0}; 4353 char fw_mac_addr[ETH_ALEN]; 4354 4355 if (fwnode_get_mac_address(fwnode, fw_mac_addr, ETH_ALEN)) { 4356 *mac_from = "firmware node"; 4357 ether_addr_copy(dev->dev_addr, fw_mac_addr); 4358 return; 4359 } 4360 4361 if (priv->hw_version == MVPP21) { 4362 mvpp21_get_mac_address(port, hw_mac_addr); 4363 if (is_valid_ether_addr(hw_mac_addr)) { 4364 *mac_from = "hardware"; 4365 ether_addr_copy(dev->dev_addr, hw_mac_addr); 4366 return; 4367 } 4368 } 4369 4370 *mac_from = "random"; 4371 eth_hw_addr_random(dev); 4372 } 4373 4374 static void mvpp2_phylink_validate(struct net_device *dev, 4375 unsigned long *supported, 4376 struct phylink_link_state *state) 4377 { 4378 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, }; 4379 4380 phylink_set(mask, Autoneg); 4381 phylink_set_port_modes(mask); 4382 phylink_set(mask, Pause); 4383 phylink_set(mask, Asym_Pause); 4384 4385 switch (state->interface) { 4386 case PHY_INTERFACE_MODE_10GKR: 4387 phylink_set(mask, 10000baseCR_Full); 4388 phylink_set(mask, 10000baseSR_Full); 4389 phylink_set(mask, 10000baseLR_Full); 4390 phylink_set(mask, 10000baseLRM_Full); 4391 phylink_set(mask, 10000baseER_Full); 4392 phylink_set(mask, 10000baseKR_Full); 4393 /* Fall-through */ 4394 default: 4395 phylink_set(mask, 10baseT_Half); 4396 phylink_set(mask, 10baseT_Full); 4397 phylink_set(mask, 100baseT_Half); 4398 phylink_set(mask, 100baseT_Full); 4399 phylink_set(mask, 10000baseT_Full); 4400 /* Fall-through */ 4401 case PHY_INTERFACE_MODE_1000BASEX: 4402 case PHY_INTERFACE_MODE_2500BASEX: 4403 phylink_set(mask, 1000baseT_Full); 4404 phylink_set(mask, 1000baseX_Full); 4405 phylink_set(mask, 2500baseX_Full); 4406 } 4407 4408 bitmap_and(supported, supported, mask, __ETHTOOL_LINK_MODE_MASK_NBITS); 4409 bitmap_and(state->advertising, state->advertising, mask, 4410 __ETHTOOL_LINK_MODE_MASK_NBITS); 4411 } 4412 4413 static void mvpp22_xlg_link_state(struct mvpp2_port *port, 4414 struct phylink_link_state *state) 4415 { 4416 u32 val; 4417 4418 state->speed = SPEED_10000; 4419 state->duplex = 1; 4420 state->an_complete = 1; 4421 4422 val = readl(port->base + MVPP22_XLG_STATUS); 4423 state->link = !!(val & MVPP22_XLG_STATUS_LINK_UP); 4424 4425 state->pause = 0; 4426 val = readl(port->base + MVPP22_XLG_CTRL0_REG); 4427 if (val & MVPP22_XLG_CTRL0_TX_FLOW_CTRL_EN) 4428 state->pause |= MLO_PAUSE_TX; 4429 if (val & MVPP22_XLG_CTRL0_RX_FLOW_CTRL_EN) 4430 state->pause |= MLO_PAUSE_RX; 4431 } 4432 4433 static void mvpp2_gmac_link_state(struct mvpp2_port *port, 4434 struct phylink_link_state *state) 4435 { 4436 u32 val; 4437 4438 val = readl(port->base + MVPP2_GMAC_STATUS0); 4439 4440 state->an_complete = !!(val & MVPP2_GMAC_STATUS0_AN_COMPLETE); 4441 state->link = !!(val & MVPP2_GMAC_STATUS0_LINK_UP); 4442 state->duplex = !!(val & MVPP2_GMAC_STATUS0_FULL_DUPLEX); 4443 4444 switch (port->phy_interface) { 4445 case PHY_INTERFACE_MODE_1000BASEX: 4446 state->speed = SPEED_1000; 4447 break; 4448 case PHY_INTERFACE_MODE_2500BASEX: 4449 state->speed = SPEED_2500; 4450 break; 4451 default: 4452 if (val & MVPP2_GMAC_STATUS0_GMII_SPEED) 4453 state->speed = SPEED_1000; 4454 else if (val & MVPP2_GMAC_STATUS0_MII_SPEED) 4455 state->speed = SPEED_100; 4456 else 4457 state->speed = SPEED_10; 4458 } 4459 4460 state->pause = 0; 4461 if (val & MVPP2_GMAC_STATUS0_RX_PAUSE) 4462 state->pause |= MLO_PAUSE_RX; 4463 if (val & MVPP2_GMAC_STATUS0_TX_PAUSE) 4464 state->pause |= MLO_PAUSE_TX; 4465 } 4466 4467 static int mvpp2_phylink_mac_link_state(struct net_device *dev, 4468 struct phylink_link_state *state) 4469 { 4470 struct mvpp2_port *port = netdev_priv(dev); 4471 4472 if (port->priv->hw_version == MVPP22 && port->gop_id == 0) { 4473 u32 mode = readl(port->base + MVPP22_XLG_CTRL3_REG); 4474 mode &= MVPP22_XLG_CTRL3_MACMODESELECT_MASK; 4475 4476 if (mode == MVPP22_XLG_CTRL3_MACMODESELECT_10G) { 4477 mvpp22_xlg_link_state(port, state); 4478 return 1; 4479 } 4480 } 4481 4482 mvpp2_gmac_link_state(port, state); 4483 return 1; 4484 } 4485 4486 static void mvpp2_mac_an_restart(struct net_device *dev) 4487 { 4488 struct mvpp2_port *port = netdev_priv(dev); 4489 u32 val; 4490 4491 if (port->phy_interface != PHY_INTERFACE_MODE_SGMII) 4492 return; 4493 4494 val = readl(port->base + MVPP2_GMAC_AUTONEG_CONFIG); 4495 /* The RESTART_AN bit is cleared by the h/w after restarting the AN 4496 * process. 4497 */ 4498 val |= MVPP2_GMAC_IN_BAND_RESTART_AN | MVPP2_GMAC_IN_BAND_AUTONEG; 4499 writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG); 4500 } 4501 4502 static void mvpp2_xlg_config(struct mvpp2_port *port, unsigned int mode, 4503 const struct phylink_link_state *state) 4504 { 4505 u32 ctrl0, ctrl4; 4506 4507 ctrl0 = readl(port->base + MVPP22_XLG_CTRL0_REG); 4508 ctrl4 = readl(port->base + MVPP22_XLG_CTRL4_REG); 4509 4510 if (state->pause & MLO_PAUSE_TX) 4511 ctrl0 |= MVPP22_XLG_CTRL0_TX_FLOW_CTRL_EN; 4512 if (state->pause & MLO_PAUSE_RX) 4513 ctrl0 |= MVPP22_XLG_CTRL0_RX_FLOW_CTRL_EN; 4514 4515 ctrl4 &= ~MVPP22_XLG_CTRL4_MACMODSELECT_GMAC; 4516 ctrl4 |= MVPP22_XLG_CTRL4_FWD_FC | MVPP22_XLG_CTRL4_FWD_PFC | 4517 MVPP22_XLG_CTRL4_EN_IDLE_CHECK; 4518 4519 writel(ctrl0, port->base + MVPP22_XLG_CTRL0_REG); 4520 writel(ctrl4, port->base + MVPP22_XLG_CTRL4_REG); 4521 } 4522 4523 static void mvpp2_gmac_config(struct mvpp2_port *port, unsigned int mode, 4524 const struct phylink_link_state *state) 4525 { 4526 u32 an, ctrl0, ctrl2, ctrl4; 4527 4528 an = readl(port->base + MVPP2_GMAC_AUTONEG_CONFIG); 4529 ctrl0 = readl(port->base + MVPP2_GMAC_CTRL_0_REG); 4530 ctrl2 = readl(port->base + MVPP2_GMAC_CTRL_2_REG); 4531 ctrl4 = readl(port->base + MVPP22_GMAC_CTRL_4_REG); 4532 4533 /* Force link down */ 4534 an &= ~MVPP2_GMAC_FORCE_LINK_PASS; 4535 an |= MVPP2_GMAC_FORCE_LINK_DOWN; 4536 writel(an, port->base + MVPP2_GMAC_AUTONEG_CONFIG); 4537 4538 /* Set the GMAC in a reset state */ 4539 ctrl2 |= MVPP2_GMAC_PORT_RESET_MASK; 4540 writel(ctrl2, port->base + MVPP2_GMAC_CTRL_2_REG); 4541 4542 an &= ~(MVPP2_GMAC_CONFIG_MII_SPEED | MVPP2_GMAC_CONFIG_GMII_SPEED | 4543 MVPP2_GMAC_AN_SPEED_EN | MVPP2_GMAC_FC_ADV_EN | 4544 MVPP2_GMAC_FC_ADV_ASM_EN | MVPP2_GMAC_FLOW_CTRL_AUTONEG | 4545 MVPP2_GMAC_CONFIG_FULL_DUPLEX | MVPP2_GMAC_AN_DUPLEX_EN | 4546 MVPP2_GMAC_FORCE_LINK_DOWN); 4547 ctrl0 &= ~MVPP2_GMAC_PORT_TYPE_MASK; 4548 ctrl2 &= ~(MVPP2_GMAC_PORT_RESET_MASK | MVPP2_GMAC_PCS_ENABLE_MASK); 4549 4550 if (state->interface == PHY_INTERFACE_MODE_1000BASEX || 4551 state->interface == PHY_INTERFACE_MODE_2500BASEX) { 4552 /* 1000BaseX and 2500BaseX ports cannot negotiate speed nor can 4553 * they negotiate duplex: they are always operating with a fixed 4554 * speed of 1000/2500Mbps in full duplex, so force 1000/2500 4555 * speed and full duplex here. 4556 */ 4557 ctrl0 |= MVPP2_GMAC_PORT_TYPE_MASK; 4558 an |= MVPP2_GMAC_CONFIG_GMII_SPEED | 4559 MVPP2_GMAC_CONFIG_FULL_DUPLEX; 4560 } else if (!phy_interface_mode_is_rgmii(state->interface)) { 4561 an |= MVPP2_GMAC_AN_SPEED_EN | MVPP2_GMAC_FLOW_CTRL_AUTONEG; 4562 } 4563 4564 if (state->duplex) 4565 an |= MVPP2_GMAC_CONFIG_FULL_DUPLEX; 4566 if (phylink_test(state->advertising, Pause)) 4567 an |= MVPP2_GMAC_FC_ADV_EN; 4568 if (phylink_test(state->advertising, Asym_Pause)) 4569 an |= MVPP2_GMAC_FC_ADV_ASM_EN; 4570 4571 if (state->interface == PHY_INTERFACE_MODE_SGMII || 4572 state->interface == PHY_INTERFACE_MODE_1000BASEX || 4573 state->interface == PHY_INTERFACE_MODE_2500BASEX) { 4574 an |= MVPP2_GMAC_IN_BAND_AUTONEG; 4575 ctrl2 |= MVPP2_GMAC_INBAND_AN_MASK | MVPP2_GMAC_PCS_ENABLE_MASK; 4576 4577 ctrl4 &= ~(MVPP22_CTRL4_EXT_PIN_GMII_SEL | 4578 MVPP22_CTRL4_RX_FC_EN | MVPP22_CTRL4_TX_FC_EN); 4579 ctrl4 |= MVPP22_CTRL4_SYNC_BYPASS_DIS | 4580 MVPP22_CTRL4_DP_CLK_SEL | 4581 MVPP22_CTRL4_QSGMII_BYPASS_ACTIVE; 4582 4583 if (state->pause & MLO_PAUSE_TX) 4584 ctrl4 |= MVPP22_CTRL4_TX_FC_EN; 4585 if (state->pause & MLO_PAUSE_RX) 4586 ctrl4 |= MVPP22_CTRL4_RX_FC_EN; 4587 } else if (phy_interface_mode_is_rgmii(state->interface)) { 4588 an |= MVPP2_GMAC_IN_BAND_AUTONEG_BYPASS; 4589 4590 if (state->speed == SPEED_1000) 4591 an |= MVPP2_GMAC_CONFIG_GMII_SPEED; 4592 else if (state->speed == SPEED_100) 4593 an |= MVPP2_GMAC_CONFIG_MII_SPEED; 4594 4595 ctrl4 &= ~MVPP22_CTRL4_DP_CLK_SEL; 4596 ctrl4 |= MVPP22_CTRL4_EXT_PIN_GMII_SEL | 4597 MVPP22_CTRL4_SYNC_BYPASS_DIS | 4598 MVPP22_CTRL4_QSGMII_BYPASS_ACTIVE; 4599 } 4600 4601 writel(ctrl0, port->base + MVPP2_GMAC_CTRL_0_REG); 4602 writel(ctrl2, port->base + MVPP2_GMAC_CTRL_2_REG); 4603 writel(ctrl4, port->base + MVPP22_GMAC_CTRL_4_REG); 4604 writel(an, port->base + MVPP2_GMAC_AUTONEG_CONFIG); 4605 } 4606 4607 static void mvpp2_mac_config(struct net_device *dev, unsigned int mode, 4608 const struct phylink_link_state *state) 4609 { 4610 struct mvpp2_port *port = netdev_priv(dev); 4611 4612 /* Check for invalid configuration */ 4613 if (state->interface == PHY_INTERFACE_MODE_10GKR && port->gop_id != 0) { 4614 netdev_err(dev, "Invalid mode on %s\n", dev->name); 4615 return; 4616 } 4617 4618 /* Make sure the port is disabled when reconfiguring the mode */ 4619 mvpp2_port_disable(port); 4620 4621 if (port->priv->hw_version == MVPP22 && 4622 port->phy_interface != state->interface) { 4623 port->phy_interface = state->interface; 4624 4625 /* Reconfigure the serdes lanes */ 4626 phy_power_off(port->comphy); 4627 mvpp22_mode_reconfigure(port); 4628 } 4629 4630 /* mac (re)configuration */ 4631 if (state->interface == PHY_INTERFACE_MODE_10GKR) 4632 mvpp2_xlg_config(port, mode, state); 4633 else if (phy_interface_mode_is_rgmii(state->interface) || 4634 state->interface == PHY_INTERFACE_MODE_SGMII || 4635 state->interface == PHY_INTERFACE_MODE_1000BASEX || 4636 state->interface == PHY_INTERFACE_MODE_2500BASEX) 4637 mvpp2_gmac_config(port, mode, state); 4638 4639 if (port->priv->hw_version == MVPP21 && port->flags & MVPP2_F_LOOPBACK) 4640 mvpp2_port_loopback_set(port, state); 4641 4642 mvpp2_port_enable(port); 4643 } 4644 4645 static void mvpp2_mac_link_up(struct net_device *dev, unsigned int mode, 4646 phy_interface_t interface, struct phy_device *phy) 4647 { 4648 struct mvpp2_port *port = netdev_priv(dev); 4649 u32 val; 4650 4651 if (!phylink_autoneg_inband(mode) && 4652 interface != PHY_INTERFACE_MODE_10GKR) { 4653 val = readl(port->base + MVPP2_GMAC_AUTONEG_CONFIG); 4654 val &= ~MVPP2_GMAC_FORCE_LINK_DOWN; 4655 if (phy_interface_mode_is_rgmii(interface)) 4656 val |= MVPP2_GMAC_FORCE_LINK_PASS; 4657 writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG); 4658 } 4659 4660 mvpp2_port_enable(port); 4661 4662 mvpp2_egress_enable(port); 4663 mvpp2_ingress_enable(port); 4664 netif_tx_wake_all_queues(dev); 4665 } 4666 4667 static void mvpp2_mac_link_down(struct net_device *dev, unsigned int mode, 4668 phy_interface_t interface) 4669 { 4670 struct mvpp2_port *port = netdev_priv(dev); 4671 u32 val; 4672 4673 if (!phylink_autoneg_inband(mode) && 4674 interface != PHY_INTERFACE_MODE_10GKR) { 4675 val = readl(port->base + MVPP2_GMAC_AUTONEG_CONFIG); 4676 val &= ~MVPP2_GMAC_FORCE_LINK_PASS; 4677 val |= MVPP2_GMAC_FORCE_LINK_DOWN; 4678 writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG); 4679 } 4680 4681 netif_tx_stop_all_queues(dev); 4682 mvpp2_egress_disable(port); 4683 mvpp2_ingress_disable(port); 4684 4685 /* When using link interrupts to notify phylink of a MAC state change, 4686 * we do not want the port to be disabled (we want to receive further 4687 * interrupts, to be notified when the port will have a link later). 4688 */ 4689 if (!port->has_phy) 4690 return; 4691 4692 mvpp2_port_disable(port); 4693 } 4694 4695 static const struct phylink_mac_ops mvpp2_phylink_ops = { 4696 .validate = mvpp2_phylink_validate, 4697 .mac_link_state = mvpp2_phylink_mac_link_state, 4698 .mac_an_restart = mvpp2_mac_an_restart, 4699 .mac_config = mvpp2_mac_config, 4700 .mac_link_up = mvpp2_mac_link_up, 4701 .mac_link_down = mvpp2_mac_link_down, 4702 }; 4703 4704 /* Ports initialization */ 4705 static int mvpp2_port_probe(struct platform_device *pdev, 4706 struct fwnode_handle *port_fwnode, 4707 struct mvpp2 *priv) 4708 { 4709 struct phy *comphy = NULL; 4710 struct mvpp2_port *port; 4711 struct mvpp2_port_pcpu *port_pcpu; 4712 struct device_node *port_node = to_of_node(port_fwnode); 4713 struct net_device *dev; 4714 struct resource *res; 4715 struct phylink *phylink; 4716 char *mac_from = ""; 4717 unsigned int ntxqs, nrxqs, thread; 4718 unsigned long flags = 0; 4719 bool has_tx_irqs; 4720 u32 id; 4721 int features; 4722 int phy_mode; 4723 int err, i; 4724 4725 has_tx_irqs = mvpp2_port_has_irqs(priv, port_node, &flags); 4726 if (!has_tx_irqs && queue_mode == MVPP2_QDIST_MULTI_MODE) { 4727 dev_err(&pdev->dev, 4728 "not enough IRQs to support multi queue mode\n"); 4729 return -EINVAL; 4730 } 4731 4732 ntxqs = MVPP2_MAX_TXQ; 4733 if (priv->hw_version == MVPP22 && queue_mode == MVPP2_QDIST_MULTI_MODE) 4734 nrxqs = MVPP2_DEFAULT_RXQ * num_possible_cpus(); 4735 else 4736 nrxqs = MVPP2_DEFAULT_RXQ; 4737 4738 dev = alloc_etherdev_mqs(sizeof(*port), ntxqs, nrxqs); 4739 if (!dev) 4740 return -ENOMEM; 4741 4742 phy_mode = fwnode_get_phy_mode(port_fwnode); 4743 if (phy_mode < 0) { 4744 dev_err(&pdev->dev, "incorrect phy mode\n"); 4745 err = phy_mode; 4746 goto err_free_netdev; 4747 } 4748 4749 if (port_node) { 4750 comphy = devm_of_phy_get(&pdev->dev, port_node, NULL); 4751 if (IS_ERR(comphy)) { 4752 if (PTR_ERR(comphy) == -EPROBE_DEFER) { 4753 err = -EPROBE_DEFER; 4754 goto err_free_netdev; 4755 } 4756 comphy = NULL; 4757 } 4758 } 4759 4760 if (fwnode_property_read_u32(port_fwnode, "port-id", &id)) { 4761 err = -EINVAL; 4762 dev_err(&pdev->dev, "missing port-id value\n"); 4763 goto err_free_netdev; 4764 } 4765 4766 dev->tx_queue_len = MVPP2_MAX_TXD_MAX; 4767 dev->watchdog_timeo = 5 * HZ; 4768 dev->netdev_ops = &mvpp2_netdev_ops; 4769 dev->ethtool_ops = &mvpp2_eth_tool_ops; 4770 4771 port = netdev_priv(dev); 4772 port->dev = dev; 4773 port->fwnode = port_fwnode; 4774 port->has_phy = !!of_find_property(port_node, "phy", NULL); 4775 port->ntxqs = ntxqs; 4776 port->nrxqs = nrxqs; 4777 port->priv = priv; 4778 port->has_tx_irqs = has_tx_irqs; 4779 port->flags = flags; 4780 4781 err = mvpp2_queue_vectors_init(port, port_node); 4782 if (err) 4783 goto err_free_netdev; 4784 4785 if (port_node) 4786 port->link_irq = of_irq_get_byname(port_node, "link"); 4787 else 4788 port->link_irq = fwnode_irq_get(port_fwnode, port->nqvecs + 1); 4789 if (port->link_irq == -EPROBE_DEFER) { 4790 err = -EPROBE_DEFER; 4791 goto err_deinit_qvecs; 4792 } 4793 if (port->link_irq <= 0) 4794 /* the link irq is optional */ 4795 port->link_irq = 0; 4796 4797 if (fwnode_property_read_bool(port_fwnode, "marvell,loopback")) 4798 port->flags |= MVPP2_F_LOOPBACK; 4799 4800 port->id = id; 4801 if (priv->hw_version == MVPP21) 4802 port->first_rxq = port->id * port->nrxqs; 4803 else 4804 port->first_rxq = port->id * priv->max_port_rxqs; 4805 4806 port->of_node = port_node; 4807 port->phy_interface = phy_mode; 4808 port->comphy = comphy; 4809 4810 if (priv->hw_version == MVPP21) { 4811 res = platform_get_resource(pdev, IORESOURCE_MEM, 2 + id); 4812 port->base = devm_ioremap_resource(&pdev->dev, res); 4813 if (IS_ERR(port->base)) { 4814 err = PTR_ERR(port->base); 4815 goto err_free_irq; 4816 } 4817 4818 port->stats_base = port->priv->lms_base + 4819 MVPP21_MIB_COUNTERS_OFFSET + 4820 port->gop_id * MVPP21_MIB_COUNTERS_PORT_SZ; 4821 } else { 4822 if (fwnode_property_read_u32(port_fwnode, "gop-port-id", 4823 &port->gop_id)) { 4824 err = -EINVAL; 4825 dev_err(&pdev->dev, "missing gop-port-id value\n"); 4826 goto err_deinit_qvecs; 4827 } 4828 4829 port->base = priv->iface_base + MVPP22_GMAC_BASE(port->gop_id); 4830 port->stats_base = port->priv->iface_base + 4831 MVPP22_MIB_COUNTERS_OFFSET + 4832 port->gop_id * MVPP22_MIB_COUNTERS_PORT_SZ; 4833 } 4834 4835 /* Alloc per-cpu and ethtool stats */ 4836 port->stats = netdev_alloc_pcpu_stats(struct mvpp2_pcpu_stats); 4837 if (!port->stats) { 4838 err = -ENOMEM; 4839 goto err_free_irq; 4840 } 4841 4842 port->ethtool_stats = devm_kcalloc(&pdev->dev, 4843 ARRAY_SIZE(mvpp2_ethtool_regs), 4844 sizeof(u64), GFP_KERNEL); 4845 if (!port->ethtool_stats) { 4846 err = -ENOMEM; 4847 goto err_free_stats; 4848 } 4849 4850 mutex_init(&port->gather_stats_lock); 4851 INIT_DELAYED_WORK(&port->stats_work, mvpp2_gather_hw_statistics); 4852 4853 mvpp2_port_copy_mac_addr(dev, priv, port_fwnode, &mac_from); 4854 4855 port->tx_ring_size = MVPP2_MAX_TXD_DFLT; 4856 port->rx_ring_size = MVPP2_MAX_RXD_DFLT; 4857 SET_NETDEV_DEV(dev, &pdev->dev); 4858 4859 err = mvpp2_port_init(port); 4860 if (err < 0) { 4861 dev_err(&pdev->dev, "failed to init port %d\n", id); 4862 goto err_free_stats; 4863 } 4864 4865 mvpp2_port_periodic_xon_disable(port); 4866 4867 mvpp2_port_reset(port); 4868 4869 port->pcpu = alloc_percpu(struct mvpp2_port_pcpu); 4870 if (!port->pcpu) { 4871 err = -ENOMEM; 4872 goto err_free_txq_pcpu; 4873 } 4874 4875 if (!port->has_tx_irqs) { 4876 for (thread = 0; thread < priv->nthreads; thread++) { 4877 port_pcpu = per_cpu_ptr(port->pcpu, thread); 4878 4879 hrtimer_init(&port_pcpu->tx_done_timer, CLOCK_MONOTONIC, 4880 HRTIMER_MODE_REL_PINNED); 4881 port_pcpu->tx_done_timer.function = mvpp2_hr_timer_cb; 4882 port_pcpu->timer_scheduled = false; 4883 4884 tasklet_init(&port_pcpu->tx_done_tasklet, 4885 mvpp2_tx_proc_cb, 4886 (unsigned long)dev); 4887 } 4888 } 4889 4890 features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | 4891 NETIF_F_TSO; 4892 dev->features = features | NETIF_F_RXCSUM; 4893 dev->hw_features |= features | NETIF_F_RXCSUM | NETIF_F_GRO | 4894 NETIF_F_HW_VLAN_CTAG_FILTER; 4895 4896 if (mvpp22_rss_is_supported()) 4897 dev->hw_features |= NETIF_F_RXHASH; 4898 4899 if (port->pool_long->id == MVPP2_BM_JUMBO && port->id != 0) { 4900 dev->features &= ~(NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM); 4901 dev->hw_features &= ~(NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM); 4902 } 4903 4904 dev->vlan_features |= features; 4905 dev->gso_max_segs = MVPP2_MAX_TSO_SEGS; 4906 dev->priv_flags |= IFF_UNICAST_FLT; 4907 4908 /* MTU range: 68 - 9704 */ 4909 dev->min_mtu = ETH_MIN_MTU; 4910 /* 9704 == 9728 - 20 and rounding to 8 */ 4911 dev->max_mtu = MVPP2_BM_JUMBO_PKT_SIZE; 4912 dev->dev.of_node = port_node; 4913 4914 /* Phylink isn't used w/ ACPI as of now */ 4915 if (port_node) { 4916 phylink = phylink_create(dev, port_fwnode, phy_mode, 4917 &mvpp2_phylink_ops); 4918 if (IS_ERR(phylink)) { 4919 err = PTR_ERR(phylink); 4920 goto err_free_port_pcpu; 4921 } 4922 port->phylink = phylink; 4923 } else { 4924 port->phylink = NULL; 4925 } 4926 4927 err = register_netdev(dev); 4928 if (err < 0) { 4929 dev_err(&pdev->dev, "failed to register netdev\n"); 4930 goto err_phylink; 4931 } 4932 netdev_info(dev, "Using %s mac address %pM\n", mac_from, dev->dev_addr); 4933 4934 priv->port_list[priv->port_count++] = port; 4935 4936 return 0; 4937 4938 err_phylink: 4939 if (port->phylink) 4940 phylink_destroy(port->phylink); 4941 err_free_port_pcpu: 4942 free_percpu(port->pcpu); 4943 err_free_txq_pcpu: 4944 for (i = 0; i < port->ntxqs; i++) 4945 free_percpu(port->txqs[i]->pcpu); 4946 err_free_stats: 4947 free_percpu(port->stats); 4948 err_free_irq: 4949 if (port->link_irq) 4950 irq_dispose_mapping(port->link_irq); 4951 err_deinit_qvecs: 4952 mvpp2_queue_vectors_deinit(port); 4953 err_free_netdev: 4954 free_netdev(dev); 4955 return err; 4956 } 4957 4958 /* Ports removal routine */ 4959 static void mvpp2_port_remove(struct mvpp2_port *port) 4960 { 4961 int i; 4962 4963 unregister_netdev(port->dev); 4964 if (port->phylink) 4965 phylink_destroy(port->phylink); 4966 free_percpu(port->pcpu); 4967 free_percpu(port->stats); 4968 for (i = 0; i < port->ntxqs; i++) 4969 free_percpu(port->txqs[i]->pcpu); 4970 mvpp2_queue_vectors_deinit(port); 4971 if (port->link_irq) 4972 irq_dispose_mapping(port->link_irq); 4973 free_netdev(port->dev); 4974 } 4975 4976 /* Initialize decoding windows */ 4977 static void mvpp2_conf_mbus_windows(const struct mbus_dram_target_info *dram, 4978 struct mvpp2 *priv) 4979 { 4980 u32 win_enable; 4981 int i; 4982 4983 for (i = 0; i < 6; i++) { 4984 mvpp2_write(priv, MVPP2_WIN_BASE(i), 0); 4985 mvpp2_write(priv, MVPP2_WIN_SIZE(i), 0); 4986 4987 if (i < 4) 4988 mvpp2_write(priv, MVPP2_WIN_REMAP(i), 0); 4989 } 4990 4991 win_enable = 0; 4992 4993 for (i = 0; i < dram->num_cs; i++) { 4994 const struct mbus_dram_window *cs = dram->cs + i; 4995 4996 mvpp2_write(priv, MVPP2_WIN_BASE(i), 4997 (cs->base & 0xffff0000) | (cs->mbus_attr << 8) | 4998 dram->mbus_dram_target_id); 4999 5000 mvpp2_write(priv, MVPP2_WIN_SIZE(i), 5001 (cs->size - 1) & 0xffff0000); 5002 5003 win_enable |= (1 << i); 5004 } 5005 5006 mvpp2_write(priv, MVPP2_BASE_ADDR_ENABLE, win_enable); 5007 } 5008 5009 /* Initialize Rx FIFO's */ 5010 static void mvpp2_rx_fifo_init(struct mvpp2 *priv) 5011 { 5012 int port; 5013 5014 for (port = 0; port < MVPP2_MAX_PORTS; port++) { 5015 mvpp2_write(priv, MVPP2_RX_DATA_FIFO_SIZE_REG(port), 5016 MVPP2_RX_FIFO_PORT_DATA_SIZE_4KB); 5017 mvpp2_write(priv, MVPP2_RX_ATTR_FIFO_SIZE_REG(port), 5018 MVPP2_RX_FIFO_PORT_ATTR_SIZE_4KB); 5019 } 5020 5021 mvpp2_write(priv, MVPP2_RX_MIN_PKT_SIZE_REG, 5022 MVPP2_RX_FIFO_PORT_MIN_PKT); 5023 mvpp2_write(priv, MVPP2_RX_FIFO_INIT_REG, 0x1); 5024 } 5025 5026 static void mvpp22_rx_fifo_init(struct mvpp2 *priv) 5027 { 5028 int port; 5029 5030 /* The FIFO size parameters are set depending on the maximum speed a 5031 * given port can handle: 5032 * - Port 0: 10Gbps 5033 * - Port 1: 2.5Gbps 5034 * - Ports 2 and 3: 1Gbps 5035 */ 5036 5037 mvpp2_write(priv, MVPP2_RX_DATA_FIFO_SIZE_REG(0), 5038 MVPP2_RX_FIFO_PORT_DATA_SIZE_32KB); 5039 mvpp2_write(priv, MVPP2_RX_ATTR_FIFO_SIZE_REG(0), 5040 MVPP2_RX_FIFO_PORT_ATTR_SIZE_32KB); 5041 5042 mvpp2_write(priv, MVPP2_RX_DATA_FIFO_SIZE_REG(1), 5043 MVPP2_RX_FIFO_PORT_DATA_SIZE_8KB); 5044 mvpp2_write(priv, MVPP2_RX_ATTR_FIFO_SIZE_REG(1), 5045 MVPP2_RX_FIFO_PORT_ATTR_SIZE_8KB); 5046 5047 for (port = 2; port < MVPP2_MAX_PORTS; port++) { 5048 mvpp2_write(priv, MVPP2_RX_DATA_FIFO_SIZE_REG(port), 5049 MVPP2_RX_FIFO_PORT_DATA_SIZE_4KB); 5050 mvpp2_write(priv, MVPP2_RX_ATTR_FIFO_SIZE_REG(port), 5051 MVPP2_RX_FIFO_PORT_ATTR_SIZE_4KB); 5052 } 5053 5054 mvpp2_write(priv, MVPP2_RX_MIN_PKT_SIZE_REG, 5055 MVPP2_RX_FIFO_PORT_MIN_PKT); 5056 mvpp2_write(priv, MVPP2_RX_FIFO_INIT_REG, 0x1); 5057 } 5058 5059 /* Initialize Tx FIFO's: the total FIFO size is 19kB on PPv2.2 and 10G 5060 * interfaces must have a Tx FIFO size of 10kB. As only port 0 can do 10G, 5061 * configure its Tx FIFO size to 10kB and the others ports Tx FIFO size to 3kB. 5062 */ 5063 static void mvpp22_tx_fifo_init(struct mvpp2 *priv) 5064 { 5065 int port, size, thrs; 5066 5067 for (port = 0; port < MVPP2_MAX_PORTS; port++) { 5068 if (port == 0) { 5069 size = MVPP22_TX_FIFO_DATA_SIZE_10KB; 5070 thrs = MVPP2_TX_FIFO_THRESHOLD_10KB; 5071 } else { 5072 size = MVPP22_TX_FIFO_DATA_SIZE_3KB; 5073 thrs = MVPP2_TX_FIFO_THRESHOLD_3KB; 5074 } 5075 mvpp2_write(priv, MVPP22_TX_FIFO_SIZE_REG(port), size); 5076 mvpp2_write(priv, MVPP22_TX_FIFO_THRESH_REG(port), thrs); 5077 } 5078 } 5079 5080 static void mvpp2_axi_init(struct mvpp2 *priv) 5081 { 5082 u32 val, rdval, wrval; 5083 5084 mvpp2_write(priv, MVPP22_BM_ADDR_HIGH_RLS_REG, 0x0); 5085 5086 /* AXI Bridge Configuration */ 5087 5088 rdval = MVPP22_AXI_CODE_CACHE_RD_CACHE 5089 << MVPP22_AXI_ATTR_CACHE_OFFS; 5090 rdval |= MVPP22_AXI_CODE_DOMAIN_OUTER_DOM 5091 << MVPP22_AXI_ATTR_DOMAIN_OFFS; 5092 5093 wrval = MVPP22_AXI_CODE_CACHE_WR_CACHE 5094 << MVPP22_AXI_ATTR_CACHE_OFFS; 5095 wrval |= MVPP22_AXI_CODE_DOMAIN_OUTER_DOM 5096 << MVPP22_AXI_ATTR_DOMAIN_OFFS; 5097 5098 /* BM */ 5099 mvpp2_write(priv, MVPP22_AXI_BM_WR_ATTR_REG, wrval); 5100 mvpp2_write(priv, MVPP22_AXI_BM_RD_ATTR_REG, rdval); 5101 5102 /* Descriptors */ 5103 mvpp2_write(priv, MVPP22_AXI_AGGRQ_DESCR_RD_ATTR_REG, rdval); 5104 mvpp2_write(priv, MVPP22_AXI_TXQ_DESCR_WR_ATTR_REG, wrval); 5105 mvpp2_write(priv, MVPP22_AXI_TXQ_DESCR_RD_ATTR_REG, rdval); 5106 mvpp2_write(priv, MVPP22_AXI_RXQ_DESCR_WR_ATTR_REG, wrval); 5107 5108 /* Buffer Data */ 5109 mvpp2_write(priv, MVPP22_AXI_TX_DATA_RD_ATTR_REG, rdval); 5110 mvpp2_write(priv, MVPP22_AXI_RX_DATA_WR_ATTR_REG, wrval); 5111 5112 val = MVPP22_AXI_CODE_CACHE_NON_CACHE 5113 << MVPP22_AXI_CODE_CACHE_OFFS; 5114 val |= MVPP22_AXI_CODE_DOMAIN_SYSTEM 5115 << MVPP22_AXI_CODE_DOMAIN_OFFS; 5116 mvpp2_write(priv, MVPP22_AXI_RD_NORMAL_CODE_REG, val); 5117 mvpp2_write(priv, MVPP22_AXI_WR_NORMAL_CODE_REG, val); 5118 5119 val = MVPP22_AXI_CODE_CACHE_RD_CACHE 5120 << MVPP22_AXI_CODE_CACHE_OFFS; 5121 val |= MVPP22_AXI_CODE_DOMAIN_OUTER_DOM 5122 << MVPP22_AXI_CODE_DOMAIN_OFFS; 5123 5124 mvpp2_write(priv, MVPP22_AXI_RD_SNOOP_CODE_REG, val); 5125 5126 val = MVPP22_AXI_CODE_CACHE_WR_CACHE 5127 << MVPP22_AXI_CODE_CACHE_OFFS; 5128 val |= MVPP22_AXI_CODE_DOMAIN_OUTER_DOM 5129 << MVPP22_AXI_CODE_DOMAIN_OFFS; 5130 5131 mvpp2_write(priv, MVPP22_AXI_WR_SNOOP_CODE_REG, val); 5132 } 5133 5134 /* Initialize network controller common part HW */ 5135 static int mvpp2_init(struct platform_device *pdev, struct mvpp2 *priv) 5136 { 5137 const struct mbus_dram_target_info *dram_target_info; 5138 int err, i; 5139 u32 val; 5140 5141 /* MBUS windows configuration */ 5142 dram_target_info = mv_mbus_dram_info(); 5143 if (dram_target_info) 5144 mvpp2_conf_mbus_windows(dram_target_info, priv); 5145 5146 if (priv->hw_version == MVPP22) 5147 mvpp2_axi_init(priv); 5148 5149 /* Disable HW PHY polling */ 5150 if (priv->hw_version == MVPP21) { 5151 val = readl(priv->lms_base + MVPP2_PHY_AN_CFG0_REG); 5152 val |= MVPP2_PHY_AN_STOP_SMI0_MASK; 5153 writel(val, priv->lms_base + MVPP2_PHY_AN_CFG0_REG); 5154 } else { 5155 val = readl(priv->iface_base + MVPP22_SMI_MISC_CFG_REG); 5156 val &= ~MVPP22_SMI_POLLING_EN; 5157 writel(val, priv->iface_base + MVPP22_SMI_MISC_CFG_REG); 5158 } 5159 5160 /* Allocate and initialize aggregated TXQs */ 5161 priv->aggr_txqs = devm_kcalloc(&pdev->dev, MVPP2_MAX_THREADS, 5162 sizeof(*priv->aggr_txqs), 5163 GFP_KERNEL); 5164 if (!priv->aggr_txqs) 5165 return -ENOMEM; 5166 5167 for (i = 0; i < MVPP2_MAX_THREADS; i++) { 5168 priv->aggr_txqs[i].id = i; 5169 priv->aggr_txqs[i].size = MVPP2_AGGR_TXQ_SIZE; 5170 err = mvpp2_aggr_txq_init(pdev, &priv->aggr_txqs[i], i, priv); 5171 if (err < 0) 5172 return err; 5173 } 5174 5175 /* Fifo Init */ 5176 if (priv->hw_version == MVPP21) { 5177 mvpp2_rx_fifo_init(priv); 5178 } else { 5179 mvpp22_rx_fifo_init(priv); 5180 mvpp22_tx_fifo_init(priv); 5181 } 5182 5183 if (priv->hw_version == MVPP21) 5184 writel(MVPP2_EXT_GLOBAL_CTRL_DEFAULT, 5185 priv->lms_base + MVPP2_MNG_EXTENDED_GLOBAL_CTRL_REG); 5186 5187 /* Allow cache snoop when transmiting packets */ 5188 mvpp2_write(priv, MVPP2_TX_SNOOP_REG, 0x1); 5189 5190 /* Buffer Manager initialization */ 5191 err = mvpp2_bm_init(pdev, priv); 5192 if (err < 0) 5193 return err; 5194 5195 /* Parser default initialization */ 5196 err = mvpp2_prs_default_init(pdev, priv); 5197 if (err < 0) 5198 return err; 5199 5200 /* Classifier default initialization */ 5201 mvpp2_cls_init(priv); 5202 5203 return 0; 5204 } 5205 5206 static int mvpp2_probe(struct platform_device *pdev) 5207 { 5208 const struct acpi_device_id *acpi_id; 5209 struct fwnode_handle *fwnode = pdev->dev.fwnode; 5210 struct fwnode_handle *port_fwnode; 5211 struct mvpp2 *priv; 5212 struct resource *res; 5213 void __iomem *base; 5214 int i, shared; 5215 int err; 5216 5217 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); 5218 if (!priv) 5219 return -ENOMEM; 5220 5221 if (has_acpi_companion(&pdev->dev)) { 5222 acpi_id = acpi_match_device(pdev->dev.driver->acpi_match_table, 5223 &pdev->dev); 5224 priv->hw_version = (unsigned long)acpi_id->driver_data; 5225 } else { 5226 priv->hw_version = 5227 (unsigned long)of_device_get_match_data(&pdev->dev); 5228 } 5229 5230 /* multi queue mode isn't supported on PPV2.1, fallback to single 5231 * mode 5232 */ 5233 if (priv->hw_version == MVPP21) 5234 queue_mode = MVPP2_QDIST_SINGLE_MODE; 5235 5236 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 5237 base = devm_ioremap_resource(&pdev->dev, res); 5238 if (IS_ERR(base)) 5239 return PTR_ERR(base); 5240 5241 if (priv->hw_version == MVPP21) { 5242 res = platform_get_resource(pdev, IORESOURCE_MEM, 1); 5243 priv->lms_base = devm_ioremap_resource(&pdev->dev, res); 5244 if (IS_ERR(priv->lms_base)) 5245 return PTR_ERR(priv->lms_base); 5246 } else { 5247 res = platform_get_resource(pdev, IORESOURCE_MEM, 1); 5248 if (has_acpi_companion(&pdev->dev)) { 5249 /* In case the MDIO memory region is declared in 5250 * the ACPI, it can already appear as 'in-use' 5251 * in the OS. Because it is overlapped by second 5252 * region of the network controller, make 5253 * sure it is released, before requesting it again. 5254 * The care is taken by mvpp2 driver to avoid 5255 * concurrent access to this memory region. 5256 */ 5257 release_resource(res); 5258 } 5259 priv->iface_base = devm_ioremap_resource(&pdev->dev, res); 5260 if (IS_ERR(priv->iface_base)) 5261 return PTR_ERR(priv->iface_base); 5262 } 5263 5264 if (priv->hw_version == MVPP22 && dev_of_node(&pdev->dev)) { 5265 priv->sysctrl_base = 5266 syscon_regmap_lookup_by_phandle(pdev->dev.of_node, 5267 "marvell,system-controller"); 5268 if (IS_ERR(priv->sysctrl_base)) 5269 /* The system controller regmap is optional for dt 5270 * compatibility reasons. When not provided, the 5271 * configuration of the GoP relies on the 5272 * firmware/bootloader. 5273 */ 5274 priv->sysctrl_base = NULL; 5275 } 5276 5277 mvpp2_setup_bm_pool(); 5278 5279 5280 priv->nthreads = min_t(unsigned int, num_present_cpus(), 5281 MVPP2_MAX_THREADS); 5282 5283 shared = num_present_cpus() - priv->nthreads; 5284 if (shared > 0) 5285 bitmap_fill(&priv->lock_map, 5286 min_t(int, shared, MVPP2_MAX_THREADS)); 5287 5288 for (i = 0; i < MVPP2_MAX_THREADS; i++) { 5289 u32 addr_space_sz; 5290 5291 addr_space_sz = (priv->hw_version == MVPP21 ? 5292 MVPP21_ADDR_SPACE_SZ : MVPP22_ADDR_SPACE_SZ); 5293 priv->swth_base[i] = base + i * addr_space_sz; 5294 } 5295 5296 if (priv->hw_version == MVPP21) 5297 priv->max_port_rxqs = 8; 5298 else 5299 priv->max_port_rxqs = 32; 5300 5301 if (dev_of_node(&pdev->dev)) { 5302 priv->pp_clk = devm_clk_get(&pdev->dev, "pp_clk"); 5303 if (IS_ERR(priv->pp_clk)) 5304 return PTR_ERR(priv->pp_clk); 5305 err = clk_prepare_enable(priv->pp_clk); 5306 if (err < 0) 5307 return err; 5308 5309 priv->gop_clk = devm_clk_get(&pdev->dev, "gop_clk"); 5310 if (IS_ERR(priv->gop_clk)) { 5311 err = PTR_ERR(priv->gop_clk); 5312 goto err_pp_clk; 5313 } 5314 err = clk_prepare_enable(priv->gop_clk); 5315 if (err < 0) 5316 goto err_pp_clk; 5317 5318 if (priv->hw_version == MVPP22) { 5319 priv->mg_clk = devm_clk_get(&pdev->dev, "mg_clk"); 5320 if (IS_ERR(priv->mg_clk)) { 5321 err = PTR_ERR(priv->mg_clk); 5322 goto err_gop_clk; 5323 } 5324 5325 err = clk_prepare_enable(priv->mg_clk); 5326 if (err < 0) 5327 goto err_gop_clk; 5328 5329 priv->mg_core_clk = devm_clk_get(&pdev->dev, "mg_core_clk"); 5330 if (IS_ERR(priv->mg_core_clk)) { 5331 priv->mg_core_clk = NULL; 5332 } else { 5333 err = clk_prepare_enable(priv->mg_core_clk); 5334 if (err < 0) 5335 goto err_mg_clk; 5336 } 5337 } 5338 5339 priv->axi_clk = devm_clk_get(&pdev->dev, "axi_clk"); 5340 if (IS_ERR(priv->axi_clk)) { 5341 err = PTR_ERR(priv->axi_clk); 5342 if (err == -EPROBE_DEFER) 5343 goto err_mg_core_clk; 5344 priv->axi_clk = NULL; 5345 } else { 5346 err = clk_prepare_enable(priv->axi_clk); 5347 if (err < 0) 5348 goto err_mg_core_clk; 5349 } 5350 5351 /* Get system's tclk rate */ 5352 priv->tclk = clk_get_rate(priv->pp_clk); 5353 } else if (device_property_read_u32(&pdev->dev, "clock-frequency", 5354 &priv->tclk)) { 5355 dev_err(&pdev->dev, "missing clock-frequency value\n"); 5356 return -EINVAL; 5357 } 5358 5359 if (priv->hw_version == MVPP22) { 5360 err = dma_set_mask(&pdev->dev, MVPP2_DESC_DMA_MASK); 5361 if (err) 5362 goto err_axi_clk; 5363 /* Sadly, the BM pools all share the same register to 5364 * store the high 32 bits of their address. So they 5365 * must all have the same high 32 bits, which forces 5366 * us to restrict coherent memory to DMA_BIT_MASK(32). 5367 */ 5368 err = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32)); 5369 if (err) 5370 goto err_axi_clk; 5371 } 5372 5373 /* Initialize network controller */ 5374 err = mvpp2_init(pdev, priv); 5375 if (err < 0) { 5376 dev_err(&pdev->dev, "failed to initialize controller\n"); 5377 goto err_axi_clk; 5378 } 5379 5380 /* Initialize ports */ 5381 fwnode_for_each_available_child_node(fwnode, port_fwnode) { 5382 err = mvpp2_port_probe(pdev, port_fwnode, priv); 5383 if (err < 0) 5384 goto err_port_probe; 5385 } 5386 5387 if (priv->port_count == 0) { 5388 dev_err(&pdev->dev, "no ports enabled\n"); 5389 err = -ENODEV; 5390 goto err_axi_clk; 5391 } 5392 5393 /* Statistics must be gathered regularly because some of them (like 5394 * packets counters) are 32-bit registers and could overflow quite 5395 * quickly. For instance, a 10Gb link used at full bandwidth with the 5396 * smallest packets (64B) will overflow a 32-bit counter in less than 5397 * 30 seconds. Then, use a workqueue to fill 64-bit counters. 5398 */ 5399 snprintf(priv->queue_name, sizeof(priv->queue_name), 5400 "stats-wq-%s%s", netdev_name(priv->port_list[0]->dev), 5401 priv->port_count > 1 ? "+" : ""); 5402 priv->stats_queue = create_singlethread_workqueue(priv->queue_name); 5403 if (!priv->stats_queue) { 5404 err = -ENOMEM; 5405 goto err_port_probe; 5406 } 5407 5408 mvpp2_dbgfs_init(priv, pdev->name); 5409 5410 platform_set_drvdata(pdev, priv); 5411 return 0; 5412 5413 err_port_probe: 5414 i = 0; 5415 fwnode_for_each_available_child_node(fwnode, port_fwnode) { 5416 if (priv->port_list[i]) 5417 mvpp2_port_remove(priv->port_list[i]); 5418 i++; 5419 } 5420 err_axi_clk: 5421 clk_disable_unprepare(priv->axi_clk); 5422 5423 err_mg_core_clk: 5424 if (priv->hw_version == MVPP22) 5425 clk_disable_unprepare(priv->mg_core_clk); 5426 err_mg_clk: 5427 if (priv->hw_version == MVPP22) 5428 clk_disable_unprepare(priv->mg_clk); 5429 err_gop_clk: 5430 clk_disable_unprepare(priv->gop_clk); 5431 err_pp_clk: 5432 clk_disable_unprepare(priv->pp_clk); 5433 return err; 5434 } 5435 5436 static int mvpp2_remove(struct platform_device *pdev) 5437 { 5438 struct mvpp2 *priv = platform_get_drvdata(pdev); 5439 struct fwnode_handle *fwnode = pdev->dev.fwnode; 5440 struct fwnode_handle *port_fwnode; 5441 int i = 0; 5442 5443 mvpp2_dbgfs_cleanup(priv); 5444 5445 flush_workqueue(priv->stats_queue); 5446 destroy_workqueue(priv->stats_queue); 5447 5448 fwnode_for_each_available_child_node(fwnode, port_fwnode) { 5449 if (priv->port_list[i]) { 5450 mutex_destroy(&priv->port_list[i]->gather_stats_lock); 5451 mvpp2_port_remove(priv->port_list[i]); 5452 } 5453 i++; 5454 } 5455 5456 for (i = 0; i < MVPP2_BM_POOLS_NUM; i++) { 5457 struct mvpp2_bm_pool *bm_pool = &priv->bm_pools[i]; 5458 5459 mvpp2_bm_pool_destroy(pdev, priv, bm_pool); 5460 } 5461 5462 for (i = 0; i < MVPP2_MAX_THREADS; i++) { 5463 struct mvpp2_tx_queue *aggr_txq = &priv->aggr_txqs[i]; 5464 5465 dma_free_coherent(&pdev->dev, 5466 MVPP2_AGGR_TXQ_SIZE * MVPP2_DESC_ALIGNED_SIZE, 5467 aggr_txq->descs, 5468 aggr_txq->descs_dma); 5469 } 5470 5471 if (is_acpi_node(port_fwnode)) 5472 return 0; 5473 5474 clk_disable_unprepare(priv->axi_clk); 5475 clk_disable_unprepare(priv->mg_core_clk); 5476 clk_disable_unprepare(priv->mg_clk); 5477 clk_disable_unprepare(priv->pp_clk); 5478 clk_disable_unprepare(priv->gop_clk); 5479 5480 return 0; 5481 } 5482 5483 static const struct of_device_id mvpp2_match[] = { 5484 { 5485 .compatible = "marvell,armada-375-pp2", 5486 .data = (void *)MVPP21, 5487 }, 5488 { 5489 .compatible = "marvell,armada-7k-pp22", 5490 .data = (void *)MVPP22, 5491 }, 5492 { } 5493 }; 5494 MODULE_DEVICE_TABLE(of, mvpp2_match); 5495 5496 static const struct acpi_device_id mvpp2_acpi_match[] = { 5497 { "MRVL0110", MVPP22 }, 5498 { }, 5499 }; 5500 MODULE_DEVICE_TABLE(acpi, mvpp2_acpi_match); 5501 5502 static struct platform_driver mvpp2_driver = { 5503 .probe = mvpp2_probe, 5504 .remove = mvpp2_remove, 5505 .driver = { 5506 .name = MVPP2_DRIVER_NAME, 5507 .of_match_table = mvpp2_match, 5508 .acpi_match_table = ACPI_PTR(mvpp2_acpi_match), 5509 }, 5510 }; 5511 5512 module_platform_driver(mvpp2_driver); 5513 5514 MODULE_DESCRIPTION("Marvell PPv2 Ethernet Driver - www.marvell.com"); 5515 MODULE_AUTHOR("Marcin Wojtas <mw@semihalf.com>"); 5516 MODULE_LICENSE("GPL v2"); 5517