1 /* 2 * Driver for Marvell PPv2 network controller for Armada 375 SoC. 3 * 4 * Copyright (C) 2014 Marvell 5 * 6 * Marcin Wojtas <mw@semihalf.com> 7 * 8 * This file is licensed under the terms of the GNU General Public 9 * License version 2. This program is licensed "as is" without any 10 * warranty of any kind, whether express or implied. 11 */ 12 13 #include <linux/acpi.h> 14 #include <linux/kernel.h> 15 #include <linux/netdevice.h> 16 #include <linux/etherdevice.h> 17 #include <linux/platform_device.h> 18 #include <linux/skbuff.h> 19 #include <linux/inetdevice.h> 20 #include <linux/mbus.h> 21 #include <linux/module.h> 22 #include <linux/mfd/syscon.h> 23 #include <linux/interrupt.h> 24 #include <linux/cpumask.h> 25 #include <linux/of.h> 26 #include <linux/of_irq.h> 27 #include <linux/of_mdio.h> 28 #include <linux/of_net.h> 29 #include <linux/of_address.h> 30 #include <linux/of_device.h> 31 #include <linux/phy.h> 32 #include <linux/phylink.h> 33 #include <linux/phy/phy.h> 34 #include <linux/clk.h> 35 #include <linux/hrtimer.h> 36 #include <linux/ktime.h> 37 #include <linux/regmap.h> 38 #include <uapi/linux/ppp_defs.h> 39 #include <net/ip.h> 40 #include <net/ipv6.h> 41 #include <net/tso.h> 42 43 #include "mvpp2.h" 44 #include "mvpp2_prs.h" 45 #include "mvpp2_cls.h" 46 47 enum mvpp2_bm_pool_log_num { 48 MVPP2_BM_SHORT, 49 MVPP2_BM_LONG, 50 MVPP2_BM_JUMBO, 51 MVPP2_BM_POOLS_NUM 52 }; 53 54 static struct { 55 int pkt_size; 56 int buf_num; 57 } mvpp2_pools[MVPP2_BM_POOLS_NUM]; 58 59 /* The prototype is added here to be used in start_dev when using ACPI. This 60 * will be removed once phylink is used for all modes (dt+ACPI). 61 */ 62 static void mvpp2_mac_config(struct net_device *dev, unsigned int mode, 63 const struct phylink_link_state *state); 64 65 /* Queue modes */ 66 #define MVPP2_QDIST_SINGLE_MODE 0 67 #define MVPP2_QDIST_MULTI_MODE 1 68 69 static int queue_mode = MVPP2_QDIST_SINGLE_MODE; 70 71 module_param(queue_mode, int, 0444); 72 MODULE_PARM_DESC(queue_mode, "Set queue_mode (single=0, multi=1)"); 73 74 /* Utility/helper methods */ 75 76 void mvpp2_write(struct mvpp2 *priv, u32 offset, u32 data) 77 { 78 writel(data, priv->swth_base[0] + offset); 79 } 80 81 u32 mvpp2_read(struct mvpp2 *priv, u32 offset) 82 { 83 return readl(priv->swth_base[0] + offset); 84 } 85 86 u32 mvpp2_read_relaxed(struct mvpp2 *priv, u32 offset) 87 { 88 return readl_relaxed(priv->swth_base[0] + offset); 89 } 90 /* These accessors should be used to access: 91 * 92 * - per-CPU registers, where each CPU has its own copy of the 93 * register. 94 * 95 * MVPP2_BM_VIRT_ALLOC_REG 96 * MVPP2_BM_ADDR_HIGH_ALLOC 97 * MVPP22_BM_ADDR_HIGH_RLS_REG 98 * MVPP2_BM_VIRT_RLS_REG 99 * MVPP2_ISR_RX_TX_CAUSE_REG 100 * MVPP2_ISR_RX_TX_MASK_REG 101 * MVPP2_TXQ_NUM_REG 102 * MVPP2_AGGR_TXQ_UPDATE_REG 103 * MVPP2_TXQ_RSVD_REQ_REG 104 * MVPP2_TXQ_RSVD_RSLT_REG 105 * MVPP2_TXQ_SENT_REG 106 * MVPP2_RXQ_NUM_REG 107 * 108 * - global registers that must be accessed through a specific CPU 109 * window, because they are related to an access to a per-CPU 110 * register 111 * 112 * MVPP2_BM_PHY_ALLOC_REG (related to MVPP2_BM_VIRT_ALLOC_REG) 113 * MVPP2_BM_PHY_RLS_REG (related to MVPP2_BM_VIRT_RLS_REG) 114 * MVPP2_RXQ_THRESH_REG (related to MVPP2_RXQ_NUM_REG) 115 * MVPP2_RXQ_DESC_ADDR_REG (related to MVPP2_RXQ_NUM_REG) 116 * MVPP2_RXQ_DESC_SIZE_REG (related to MVPP2_RXQ_NUM_REG) 117 * MVPP2_RXQ_INDEX_REG (related to MVPP2_RXQ_NUM_REG) 118 * MVPP2_TXQ_PENDING_REG (related to MVPP2_TXQ_NUM_REG) 119 * MVPP2_TXQ_DESC_ADDR_REG (related to MVPP2_TXQ_NUM_REG) 120 * MVPP2_TXQ_DESC_SIZE_REG (related to MVPP2_TXQ_NUM_REG) 121 * MVPP2_TXQ_INDEX_REG (related to MVPP2_TXQ_NUM_REG) 122 * MVPP2_TXQ_PENDING_REG (related to MVPP2_TXQ_NUM_REG) 123 * MVPP2_TXQ_PREF_BUF_REG (related to MVPP2_TXQ_NUM_REG) 124 * MVPP2_TXQ_PREF_BUF_REG (related to MVPP2_TXQ_NUM_REG) 125 */ 126 void mvpp2_percpu_write(struct mvpp2 *priv, int cpu, 127 u32 offset, u32 data) 128 { 129 writel(data, priv->swth_base[cpu] + offset); 130 } 131 132 u32 mvpp2_percpu_read(struct mvpp2 *priv, int cpu, 133 u32 offset) 134 { 135 return readl(priv->swth_base[cpu] + offset); 136 } 137 138 void mvpp2_percpu_write_relaxed(struct mvpp2 *priv, int cpu, 139 u32 offset, u32 data) 140 { 141 writel_relaxed(data, priv->swth_base[cpu] + offset); 142 } 143 144 static u32 mvpp2_percpu_read_relaxed(struct mvpp2 *priv, int cpu, 145 u32 offset) 146 { 147 return readl_relaxed(priv->swth_base[cpu] + offset); 148 } 149 150 static dma_addr_t mvpp2_txdesc_dma_addr_get(struct mvpp2_port *port, 151 struct mvpp2_tx_desc *tx_desc) 152 { 153 if (port->priv->hw_version == MVPP21) 154 return tx_desc->pp21.buf_dma_addr; 155 else 156 return tx_desc->pp22.buf_dma_addr_ptp & MVPP2_DESC_DMA_MASK; 157 } 158 159 static void mvpp2_txdesc_dma_addr_set(struct mvpp2_port *port, 160 struct mvpp2_tx_desc *tx_desc, 161 dma_addr_t dma_addr) 162 { 163 dma_addr_t addr, offset; 164 165 addr = dma_addr & ~MVPP2_TX_DESC_ALIGN; 166 offset = dma_addr & MVPP2_TX_DESC_ALIGN; 167 168 if (port->priv->hw_version == MVPP21) { 169 tx_desc->pp21.buf_dma_addr = addr; 170 tx_desc->pp21.packet_offset = offset; 171 } else { 172 u64 val = (u64)addr; 173 174 tx_desc->pp22.buf_dma_addr_ptp &= ~MVPP2_DESC_DMA_MASK; 175 tx_desc->pp22.buf_dma_addr_ptp |= val; 176 tx_desc->pp22.packet_offset = offset; 177 } 178 } 179 180 static size_t mvpp2_txdesc_size_get(struct mvpp2_port *port, 181 struct mvpp2_tx_desc *tx_desc) 182 { 183 if (port->priv->hw_version == MVPP21) 184 return tx_desc->pp21.data_size; 185 else 186 return tx_desc->pp22.data_size; 187 } 188 189 static void mvpp2_txdesc_size_set(struct mvpp2_port *port, 190 struct mvpp2_tx_desc *tx_desc, 191 size_t size) 192 { 193 if (port->priv->hw_version == MVPP21) 194 tx_desc->pp21.data_size = size; 195 else 196 tx_desc->pp22.data_size = size; 197 } 198 199 static void mvpp2_txdesc_txq_set(struct mvpp2_port *port, 200 struct mvpp2_tx_desc *tx_desc, 201 unsigned int txq) 202 { 203 if (port->priv->hw_version == MVPP21) 204 tx_desc->pp21.phys_txq = txq; 205 else 206 tx_desc->pp22.phys_txq = txq; 207 } 208 209 static void mvpp2_txdesc_cmd_set(struct mvpp2_port *port, 210 struct mvpp2_tx_desc *tx_desc, 211 unsigned int command) 212 { 213 if (port->priv->hw_version == MVPP21) 214 tx_desc->pp21.command = command; 215 else 216 tx_desc->pp22.command = command; 217 } 218 219 static unsigned int mvpp2_txdesc_offset_get(struct mvpp2_port *port, 220 struct mvpp2_tx_desc *tx_desc) 221 { 222 if (port->priv->hw_version == MVPP21) 223 return tx_desc->pp21.packet_offset; 224 else 225 return tx_desc->pp22.packet_offset; 226 } 227 228 static dma_addr_t mvpp2_rxdesc_dma_addr_get(struct mvpp2_port *port, 229 struct mvpp2_rx_desc *rx_desc) 230 { 231 if (port->priv->hw_version == MVPP21) 232 return rx_desc->pp21.buf_dma_addr; 233 else 234 return rx_desc->pp22.buf_dma_addr_key_hash & MVPP2_DESC_DMA_MASK; 235 } 236 237 static unsigned long mvpp2_rxdesc_cookie_get(struct mvpp2_port *port, 238 struct mvpp2_rx_desc *rx_desc) 239 { 240 if (port->priv->hw_version == MVPP21) 241 return rx_desc->pp21.buf_cookie; 242 else 243 return rx_desc->pp22.buf_cookie_misc & MVPP2_DESC_DMA_MASK; 244 } 245 246 static size_t mvpp2_rxdesc_size_get(struct mvpp2_port *port, 247 struct mvpp2_rx_desc *rx_desc) 248 { 249 if (port->priv->hw_version == MVPP21) 250 return rx_desc->pp21.data_size; 251 else 252 return rx_desc->pp22.data_size; 253 } 254 255 static u32 mvpp2_rxdesc_status_get(struct mvpp2_port *port, 256 struct mvpp2_rx_desc *rx_desc) 257 { 258 if (port->priv->hw_version == MVPP21) 259 return rx_desc->pp21.status; 260 else 261 return rx_desc->pp22.status; 262 } 263 264 static void mvpp2_txq_inc_get(struct mvpp2_txq_pcpu *txq_pcpu) 265 { 266 txq_pcpu->txq_get_index++; 267 if (txq_pcpu->txq_get_index == txq_pcpu->size) 268 txq_pcpu->txq_get_index = 0; 269 } 270 271 static void mvpp2_txq_inc_put(struct mvpp2_port *port, 272 struct mvpp2_txq_pcpu *txq_pcpu, 273 struct sk_buff *skb, 274 struct mvpp2_tx_desc *tx_desc) 275 { 276 struct mvpp2_txq_pcpu_buf *tx_buf = 277 txq_pcpu->buffs + txq_pcpu->txq_put_index; 278 tx_buf->skb = skb; 279 tx_buf->size = mvpp2_txdesc_size_get(port, tx_desc); 280 tx_buf->dma = mvpp2_txdesc_dma_addr_get(port, tx_desc) + 281 mvpp2_txdesc_offset_get(port, tx_desc); 282 txq_pcpu->txq_put_index++; 283 if (txq_pcpu->txq_put_index == txq_pcpu->size) 284 txq_pcpu->txq_put_index = 0; 285 } 286 287 /* Get number of physical egress port */ 288 static inline int mvpp2_egress_port(struct mvpp2_port *port) 289 { 290 return MVPP2_MAX_TCONT + port->id; 291 } 292 293 /* Get number of physical TXQ */ 294 static inline int mvpp2_txq_phys(int port, int txq) 295 { 296 return (MVPP2_MAX_TCONT + port) * MVPP2_MAX_TXQ + txq; 297 } 298 299 static void *mvpp2_frag_alloc(const struct mvpp2_bm_pool *pool) 300 { 301 if (likely(pool->frag_size <= PAGE_SIZE)) 302 return netdev_alloc_frag(pool->frag_size); 303 else 304 return kmalloc(pool->frag_size, GFP_ATOMIC); 305 } 306 307 static void mvpp2_frag_free(const struct mvpp2_bm_pool *pool, void *data) 308 { 309 if (likely(pool->frag_size <= PAGE_SIZE)) 310 skb_free_frag(data); 311 else 312 kfree(data); 313 } 314 315 /* Buffer Manager configuration routines */ 316 317 /* Create pool */ 318 static int mvpp2_bm_pool_create(struct platform_device *pdev, 319 struct mvpp2 *priv, 320 struct mvpp2_bm_pool *bm_pool, int size) 321 { 322 u32 val; 323 324 /* Number of buffer pointers must be a multiple of 16, as per 325 * hardware constraints 326 */ 327 if (!IS_ALIGNED(size, 16)) 328 return -EINVAL; 329 330 /* PPv2.1 needs 8 bytes per buffer pointer, PPv2.2 needs 16 331 * bytes per buffer pointer 332 */ 333 if (priv->hw_version == MVPP21) 334 bm_pool->size_bytes = 2 * sizeof(u32) * size; 335 else 336 bm_pool->size_bytes = 2 * sizeof(u64) * size; 337 338 bm_pool->virt_addr = dma_alloc_coherent(&pdev->dev, bm_pool->size_bytes, 339 &bm_pool->dma_addr, 340 GFP_KERNEL); 341 if (!bm_pool->virt_addr) 342 return -ENOMEM; 343 344 if (!IS_ALIGNED((unsigned long)bm_pool->virt_addr, 345 MVPP2_BM_POOL_PTR_ALIGN)) { 346 dma_free_coherent(&pdev->dev, bm_pool->size_bytes, 347 bm_pool->virt_addr, bm_pool->dma_addr); 348 dev_err(&pdev->dev, "BM pool %d is not %d bytes aligned\n", 349 bm_pool->id, MVPP2_BM_POOL_PTR_ALIGN); 350 return -ENOMEM; 351 } 352 353 mvpp2_write(priv, MVPP2_BM_POOL_BASE_REG(bm_pool->id), 354 lower_32_bits(bm_pool->dma_addr)); 355 mvpp2_write(priv, MVPP2_BM_POOL_SIZE_REG(bm_pool->id), size); 356 357 val = mvpp2_read(priv, MVPP2_BM_POOL_CTRL_REG(bm_pool->id)); 358 val |= MVPP2_BM_START_MASK; 359 mvpp2_write(priv, MVPP2_BM_POOL_CTRL_REG(bm_pool->id), val); 360 361 bm_pool->size = size; 362 bm_pool->pkt_size = 0; 363 bm_pool->buf_num = 0; 364 365 return 0; 366 } 367 368 /* Set pool buffer size */ 369 static void mvpp2_bm_pool_bufsize_set(struct mvpp2 *priv, 370 struct mvpp2_bm_pool *bm_pool, 371 int buf_size) 372 { 373 u32 val; 374 375 bm_pool->buf_size = buf_size; 376 377 val = ALIGN(buf_size, 1 << MVPP2_POOL_BUF_SIZE_OFFSET); 378 mvpp2_write(priv, MVPP2_POOL_BUF_SIZE_REG(bm_pool->id), val); 379 } 380 381 static void mvpp2_bm_bufs_get_addrs(struct device *dev, struct mvpp2 *priv, 382 struct mvpp2_bm_pool *bm_pool, 383 dma_addr_t *dma_addr, 384 phys_addr_t *phys_addr) 385 { 386 int cpu = get_cpu(); 387 388 *dma_addr = mvpp2_percpu_read(priv, cpu, 389 MVPP2_BM_PHY_ALLOC_REG(bm_pool->id)); 390 *phys_addr = mvpp2_percpu_read(priv, cpu, MVPP2_BM_VIRT_ALLOC_REG); 391 392 if (priv->hw_version == MVPP22) { 393 u32 val; 394 u32 dma_addr_highbits, phys_addr_highbits; 395 396 val = mvpp2_percpu_read(priv, cpu, MVPP22_BM_ADDR_HIGH_ALLOC); 397 dma_addr_highbits = (val & MVPP22_BM_ADDR_HIGH_PHYS_MASK); 398 phys_addr_highbits = (val & MVPP22_BM_ADDR_HIGH_VIRT_MASK) >> 399 MVPP22_BM_ADDR_HIGH_VIRT_SHIFT; 400 401 if (sizeof(dma_addr_t) == 8) 402 *dma_addr |= (u64)dma_addr_highbits << 32; 403 404 if (sizeof(phys_addr_t) == 8) 405 *phys_addr |= (u64)phys_addr_highbits << 32; 406 } 407 408 put_cpu(); 409 } 410 411 /* Free all buffers from the pool */ 412 static void mvpp2_bm_bufs_free(struct device *dev, struct mvpp2 *priv, 413 struct mvpp2_bm_pool *bm_pool, int buf_num) 414 { 415 int i; 416 417 if (buf_num > bm_pool->buf_num) { 418 WARN(1, "Pool does not have so many bufs pool(%d) bufs(%d)\n", 419 bm_pool->id, buf_num); 420 buf_num = bm_pool->buf_num; 421 } 422 423 for (i = 0; i < buf_num; i++) { 424 dma_addr_t buf_dma_addr; 425 phys_addr_t buf_phys_addr; 426 void *data; 427 428 mvpp2_bm_bufs_get_addrs(dev, priv, bm_pool, 429 &buf_dma_addr, &buf_phys_addr); 430 431 dma_unmap_single(dev, buf_dma_addr, 432 bm_pool->buf_size, DMA_FROM_DEVICE); 433 434 data = (void *)phys_to_virt(buf_phys_addr); 435 if (!data) 436 break; 437 438 mvpp2_frag_free(bm_pool, data); 439 } 440 441 /* Update BM driver with number of buffers removed from pool */ 442 bm_pool->buf_num -= i; 443 } 444 445 /* Check number of buffers in BM pool */ 446 static int mvpp2_check_hw_buf_num(struct mvpp2 *priv, struct mvpp2_bm_pool *bm_pool) 447 { 448 int buf_num = 0; 449 450 buf_num += mvpp2_read(priv, MVPP2_BM_POOL_PTRS_NUM_REG(bm_pool->id)) & 451 MVPP22_BM_POOL_PTRS_NUM_MASK; 452 buf_num += mvpp2_read(priv, MVPP2_BM_BPPI_PTRS_NUM_REG(bm_pool->id)) & 453 MVPP2_BM_BPPI_PTR_NUM_MASK; 454 455 /* HW has one buffer ready which is not reflected in the counters */ 456 if (buf_num) 457 buf_num += 1; 458 459 return buf_num; 460 } 461 462 /* Cleanup pool */ 463 static int mvpp2_bm_pool_destroy(struct platform_device *pdev, 464 struct mvpp2 *priv, 465 struct mvpp2_bm_pool *bm_pool) 466 { 467 int buf_num; 468 u32 val; 469 470 buf_num = mvpp2_check_hw_buf_num(priv, bm_pool); 471 mvpp2_bm_bufs_free(&pdev->dev, priv, bm_pool, buf_num); 472 473 /* Check buffer counters after free */ 474 buf_num = mvpp2_check_hw_buf_num(priv, bm_pool); 475 if (buf_num) { 476 WARN(1, "cannot free all buffers in pool %d, buf_num left %d\n", 477 bm_pool->id, bm_pool->buf_num); 478 return 0; 479 } 480 481 val = mvpp2_read(priv, MVPP2_BM_POOL_CTRL_REG(bm_pool->id)); 482 val |= MVPP2_BM_STOP_MASK; 483 mvpp2_write(priv, MVPP2_BM_POOL_CTRL_REG(bm_pool->id), val); 484 485 dma_free_coherent(&pdev->dev, bm_pool->size_bytes, 486 bm_pool->virt_addr, 487 bm_pool->dma_addr); 488 return 0; 489 } 490 491 static int mvpp2_bm_pools_init(struct platform_device *pdev, 492 struct mvpp2 *priv) 493 { 494 int i, err, size; 495 struct mvpp2_bm_pool *bm_pool; 496 497 /* Create all pools with maximum size */ 498 size = MVPP2_BM_POOL_SIZE_MAX; 499 for (i = 0; i < MVPP2_BM_POOLS_NUM; i++) { 500 bm_pool = &priv->bm_pools[i]; 501 bm_pool->id = i; 502 err = mvpp2_bm_pool_create(pdev, priv, bm_pool, size); 503 if (err) 504 goto err_unroll_pools; 505 mvpp2_bm_pool_bufsize_set(priv, bm_pool, 0); 506 } 507 return 0; 508 509 err_unroll_pools: 510 dev_err(&pdev->dev, "failed to create BM pool %d, size %d\n", i, size); 511 for (i = i - 1; i >= 0; i--) 512 mvpp2_bm_pool_destroy(pdev, priv, &priv->bm_pools[i]); 513 return err; 514 } 515 516 static int mvpp2_bm_init(struct platform_device *pdev, struct mvpp2 *priv) 517 { 518 int i, err; 519 520 for (i = 0; i < MVPP2_BM_POOLS_NUM; i++) { 521 /* Mask BM all interrupts */ 522 mvpp2_write(priv, MVPP2_BM_INTR_MASK_REG(i), 0); 523 /* Clear BM cause register */ 524 mvpp2_write(priv, MVPP2_BM_INTR_CAUSE_REG(i), 0); 525 } 526 527 /* Allocate and initialize BM pools */ 528 priv->bm_pools = devm_kcalloc(&pdev->dev, MVPP2_BM_POOLS_NUM, 529 sizeof(*priv->bm_pools), GFP_KERNEL); 530 if (!priv->bm_pools) 531 return -ENOMEM; 532 533 err = mvpp2_bm_pools_init(pdev, priv); 534 if (err < 0) 535 return err; 536 return 0; 537 } 538 539 static void mvpp2_setup_bm_pool(void) 540 { 541 /* Short pool */ 542 mvpp2_pools[MVPP2_BM_SHORT].buf_num = MVPP2_BM_SHORT_BUF_NUM; 543 mvpp2_pools[MVPP2_BM_SHORT].pkt_size = MVPP2_BM_SHORT_PKT_SIZE; 544 545 /* Long pool */ 546 mvpp2_pools[MVPP2_BM_LONG].buf_num = MVPP2_BM_LONG_BUF_NUM; 547 mvpp2_pools[MVPP2_BM_LONG].pkt_size = MVPP2_BM_LONG_PKT_SIZE; 548 549 /* Jumbo pool */ 550 mvpp2_pools[MVPP2_BM_JUMBO].buf_num = MVPP2_BM_JUMBO_BUF_NUM; 551 mvpp2_pools[MVPP2_BM_JUMBO].pkt_size = MVPP2_BM_JUMBO_PKT_SIZE; 552 } 553 554 /* Attach long pool to rxq */ 555 static void mvpp2_rxq_long_pool_set(struct mvpp2_port *port, 556 int lrxq, int long_pool) 557 { 558 u32 val, mask; 559 int prxq; 560 561 /* Get queue physical ID */ 562 prxq = port->rxqs[lrxq]->id; 563 564 if (port->priv->hw_version == MVPP21) 565 mask = MVPP21_RXQ_POOL_LONG_MASK; 566 else 567 mask = MVPP22_RXQ_POOL_LONG_MASK; 568 569 val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(prxq)); 570 val &= ~mask; 571 val |= (long_pool << MVPP2_RXQ_POOL_LONG_OFFS) & mask; 572 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(prxq), val); 573 } 574 575 /* Attach short pool to rxq */ 576 static void mvpp2_rxq_short_pool_set(struct mvpp2_port *port, 577 int lrxq, int short_pool) 578 { 579 u32 val, mask; 580 int prxq; 581 582 /* Get queue physical ID */ 583 prxq = port->rxqs[lrxq]->id; 584 585 if (port->priv->hw_version == MVPP21) 586 mask = MVPP21_RXQ_POOL_SHORT_MASK; 587 else 588 mask = MVPP22_RXQ_POOL_SHORT_MASK; 589 590 val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(prxq)); 591 val &= ~mask; 592 val |= (short_pool << MVPP2_RXQ_POOL_SHORT_OFFS) & mask; 593 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(prxq), val); 594 } 595 596 static void *mvpp2_buf_alloc(struct mvpp2_port *port, 597 struct mvpp2_bm_pool *bm_pool, 598 dma_addr_t *buf_dma_addr, 599 phys_addr_t *buf_phys_addr, 600 gfp_t gfp_mask) 601 { 602 dma_addr_t dma_addr; 603 void *data; 604 605 data = mvpp2_frag_alloc(bm_pool); 606 if (!data) 607 return NULL; 608 609 dma_addr = dma_map_single(port->dev->dev.parent, data, 610 MVPP2_RX_BUF_SIZE(bm_pool->pkt_size), 611 DMA_FROM_DEVICE); 612 if (unlikely(dma_mapping_error(port->dev->dev.parent, dma_addr))) { 613 mvpp2_frag_free(bm_pool, data); 614 return NULL; 615 } 616 *buf_dma_addr = dma_addr; 617 *buf_phys_addr = virt_to_phys(data); 618 619 return data; 620 } 621 622 /* Release buffer to BM */ 623 static inline void mvpp2_bm_pool_put(struct mvpp2_port *port, int pool, 624 dma_addr_t buf_dma_addr, 625 phys_addr_t buf_phys_addr) 626 { 627 int cpu = get_cpu(); 628 629 if (port->priv->hw_version == MVPP22) { 630 u32 val = 0; 631 632 if (sizeof(dma_addr_t) == 8) 633 val |= upper_32_bits(buf_dma_addr) & 634 MVPP22_BM_ADDR_HIGH_PHYS_RLS_MASK; 635 636 if (sizeof(phys_addr_t) == 8) 637 val |= (upper_32_bits(buf_phys_addr) 638 << MVPP22_BM_ADDR_HIGH_VIRT_RLS_SHIFT) & 639 MVPP22_BM_ADDR_HIGH_VIRT_RLS_MASK; 640 641 mvpp2_percpu_write_relaxed(port->priv, cpu, 642 MVPP22_BM_ADDR_HIGH_RLS_REG, val); 643 } 644 645 /* MVPP2_BM_VIRT_RLS_REG is not interpreted by HW, and simply 646 * returned in the "cookie" field of the RX 647 * descriptor. Instead of storing the virtual address, we 648 * store the physical address 649 */ 650 mvpp2_percpu_write_relaxed(port->priv, cpu, 651 MVPP2_BM_VIRT_RLS_REG, buf_phys_addr); 652 mvpp2_percpu_write_relaxed(port->priv, cpu, 653 MVPP2_BM_PHY_RLS_REG(pool), buf_dma_addr); 654 655 put_cpu(); 656 } 657 658 /* Allocate buffers for the pool */ 659 static int mvpp2_bm_bufs_add(struct mvpp2_port *port, 660 struct mvpp2_bm_pool *bm_pool, int buf_num) 661 { 662 int i, buf_size, total_size; 663 dma_addr_t dma_addr; 664 phys_addr_t phys_addr; 665 void *buf; 666 667 buf_size = MVPP2_RX_BUF_SIZE(bm_pool->pkt_size); 668 total_size = MVPP2_RX_TOTAL_SIZE(buf_size); 669 670 if (buf_num < 0 || 671 (buf_num + bm_pool->buf_num > bm_pool->size)) { 672 netdev_err(port->dev, 673 "cannot allocate %d buffers for pool %d\n", 674 buf_num, bm_pool->id); 675 return 0; 676 } 677 678 for (i = 0; i < buf_num; i++) { 679 buf = mvpp2_buf_alloc(port, bm_pool, &dma_addr, 680 &phys_addr, GFP_KERNEL); 681 if (!buf) 682 break; 683 684 mvpp2_bm_pool_put(port, bm_pool->id, dma_addr, 685 phys_addr); 686 } 687 688 /* Update BM driver with number of buffers added to pool */ 689 bm_pool->buf_num += i; 690 691 netdev_dbg(port->dev, 692 "pool %d: pkt_size=%4d, buf_size=%4d, total_size=%4d\n", 693 bm_pool->id, bm_pool->pkt_size, buf_size, total_size); 694 695 netdev_dbg(port->dev, 696 "pool %d: %d of %d buffers added\n", 697 bm_pool->id, i, buf_num); 698 return i; 699 } 700 701 /* Notify the driver that BM pool is being used as specific type and return the 702 * pool pointer on success 703 */ 704 static struct mvpp2_bm_pool * 705 mvpp2_bm_pool_use(struct mvpp2_port *port, unsigned pool, int pkt_size) 706 { 707 struct mvpp2_bm_pool *new_pool = &port->priv->bm_pools[pool]; 708 int num; 709 710 if (pool >= MVPP2_BM_POOLS_NUM) { 711 netdev_err(port->dev, "Invalid pool %d\n", pool); 712 return NULL; 713 } 714 715 /* Allocate buffers in case BM pool is used as long pool, but packet 716 * size doesn't match MTU or BM pool hasn't being used yet 717 */ 718 if (new_pool->pkt_size == 0) { 719 int pkts_num; 720 721 /* Set default buffer number or free all the buffers in case 722 * the pool is not empty 723 */ 724 pkts_num = new_pool->buf_num; 725 if (pkts_num == 0) 726 pkts_num = mvpp2_pools[pool].buf_num; 727 else 728 mvpp2_bm_bufs_free(port->dev->dev.parent, 729 port->priv, new_pool, pkts_num); 730 731 new_pool->pkt_size = pkt_size; 732 new_pool->frag_size = 733 SKB_DATA_ALIGN(MVPP2_RX_BUF_SIZE(pkt_size)) + 734 MVPP2_SKB_SHINFO_SIZE; 735 736 /* Allocate buffers for this pool */ 737 num = mvpp2_bm_bufs_add(port, new_pool, pkts_num); 738 if (num != pkts_num) { 739 WARN(1, "pool %d: %d of %d allocated\n", 740 new_pool->id, num, pkts_num); 741 return NULL; 742 } 743 } 744 745 mvpp2_bm_pool_bufsize_set(port->priv, new_pool, 746 MVPP2_RX_BUF_SIZE(new_pool->pkt_size)); 747 748 return new_pool; 749 } 750 751 /* Initialize pools for swf */ 752 static int mvpp2_swf_bm_pool_init(struct mvpp2_port *port) 753 { 754 int rxq; 755 enum mvpp2_bm_pool_log_num long_log_pool, short_log_pool; 756 757 /* If port pkt_size is higher than 1518B: 758 * HW Long pool - SW Jumbo pool, HW Short pool - SW Long pool 759 * else: HW Long pool - SW Long pool, HW Short pool - SW Short pool 760 */ 761 if (port->pkt_size > MVPP2_BM_LONG_PKT_SIZE) { 762 long_log_pool = MVPP2_BM_JUMBO; 763 short_log_pool = MVPP2_BM_LONG; 764 } else { 765 long_log_pool = MVPP2_BM_LONG; 766 short_log_pool = MVPP2_BM_SHORT; 767 } 768 769 if (!port->pool_long) { 770 port->pool_long = 771 mvpp2_bm_pool_use(port, long_log_pool, 772 mvpp2_pools[long_log_pool].pkt_size); 773 if (!port->pool_long) 774 return -ENOMEM; 775 776 port->pool_long->port_map |= BIT(port->id); 777 778 for (rxq = 0; rxq < port->nrxqs; rxq++) 779 mvpp2_rxq_long_pool_set(port, rxq, port->pool_long->id); 780 } 781 782 if (!port->pool_short) { 783 port->pool_short = 784 mvpp2_bm_pool_use(port, short_log_pool, 785 mvpp2_pools[short_log_pool].pkt_size); 786 if (!port->pool_short) 787 return -ENOMEM; 788 789 port->pool_short->port_map |= BIT(port->id); 790 791 for (rxq = 0; rxq < port->nrxqs; rxq++) 792 mvpp2_rxq_short_pool_set(port, rxq, 793 port->pool_short->id); 794 } 795 796 return 0; 797 } 798 799 static int mvpp2_bm_update_mtu(struct net_device *dev, int mtu) 800 { 801 struct mvpp2_port *port = netdev_priv(dev); 802 enum mvpp2_bm_pool_log_num new_long_pool; 803 int pkt_size = MVPP2_RX_PKT_SIZE(mtu); 804 805 /* If port MTU is higher than 1518B: 806 * HW Long pool - SW Jumbo pool, HW Short pool - SW Long pool 807 * else: HW Long pool - SW Long pool, HW Short pool - SW Short pool 808 */ 809 if (pkt_size > MVPP2_BM_LONG_PKT_SIZE) 810 new_long_pool = MVPP2_BM_JUMBO; 811 else 812 new_long_pool = MVPP2_BM_LONG; 813 814 if (new_long_pool != port->pool_long->id) { 815 /* Remove port from old short & long pool */ 816 port->pool_long = mvpp2_bm_pool_use(port, port->pool_long->id, 817 port->pool_long->pkt_size); 818 port->pool_long->port_map &= ~BIT(port->id); 819 port->pool_long = NULL; 820 821 port->pool_short = mvpp2_bm_pool_use(port, port->pool_short->id, 822 port->pool_short->pkt_size); 823 port->pool_short->port_map &= ~BIT(port->id); 824 port->pool_short = NULL; 825 826 port->pkt_size = pkt_size; 827 828 /* Add port to new short & long pool */ 829 mvpp2_swf_bm_pool_init(port); 830 831 /* Update L4 checksum when jumbo enable/disable on port */ 832 if (new_long_pool == MVPP2_BM_JUMBO && port->id != 0) { 833 dev->features &= ~(NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM); 834 dev->hw_features &= ~(NETIF_F_IP_CSUM | 835 NETIF_F_IPV6_CSUM); 836 } else { 837 dev->features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM; 838 dev->hw_features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM; 839 } 840 } 841 842 dev->mtu = mtu; 843 dev->wanted_features = dev->features; 844 845 netdev_update_features(dev); 846 return 0; 847 } 848 849 static inline void mvpp2_interrupts_enable(struct mvpp2_port *port) 850 { 851 int i, sw_thread_mask = 0; 852 853 for (i = 0; i < port->nqvecs; i++) 854 sw_thread_mask |= port->qvecs[i].sw_thread_mask; 855 856 mvpp2_write(port->priv, MVPP2_ISR_ENABLE_REG(port->id), 857 MVPP2_ISR_ENABLE_INTERRUPT(sw_thread_mask)); 858 } 859 860 static inline void mvpp2_interrupts_disable(struct mvpp2_port *port) 861 { 862 int i, sw_thread_mask = 0; 863 864 for (i = 0; i < port->nqvecs; i++) 865 sw_thread_mask |= port->qvecs[i].sw_thread_mask; 866 867 mvpp2_write(port->priv, MVPP2_ISR_ENABLE_REG(port->id), 868 MVPP2_ISR_DISABLE_INTERRUPT(sw_thread_mask)); 869 } 870 871 static inline void mvpp2_qvec_interrupt_enable(struct mvpp2_queue_vector *qvec) 872 { 873 struct mvpp2_port *port = qvec->port; 874 875 mvpp2_write(port->priv, MVPP2_ISR_ENABLE_REG(port->id), 876 MVPP2_ISR_ENABLE_INTERRUPT(qvec->sw_thread_mask)); 877 } 878 879 static inline void mvpp2_qvec_interrupt_disable(struct mvpp2_queue_vector *qvec) 880 { 881 struct mvpp2_port *port = qvec->port; 882 883 mvpp2_write(port->priv, MVPP2_ISR_ENABLE_REG(port->id), 884 MVPP2_ISR_DISABLE_INTERRUPT(qvec->sw_thread_mask)); 885 } 886 887 /* Mask the current CPU's Rx/Tx interrupts 888 * Called by on_each_cpu(), guaranteed to run with migration disabled, 889 * using smp_processor_id() is OK. 890 */ 891 static void mvpp2_interrupts_mask(void *arg) 892 { 893 struct mvpp2_port *port = arg; 894 895 mvpp2_percpu_write(port->priv, smp_processor_id(), 896 MVPP2_ISR_RX_TX_MASK_REG(port->id), 0); 897 } 898 899 /* Unmask the current CPU's Rx/Tx interrupts. 900 * Called by on_each_cpu(), guaranteed to run with migration disabled, 901 * using smp_processor_id() is OK. 902 */ 903 static void mvpp2_interrupts_unmask(void *arg) 904 { 905 struct mvpp2_port *port = arg; 906 u32 val; 907 908 val = MVPP2_CAUSE_MISC_SUM_MASK | 909 MVPP2_CAUSE_RXQ_OCCUP_DESC_ALL_MASK; 910 if (port->has_tx_irqs) 911 val |= MVPP2_CAUSE_TXQ_OCCUP_DESC_ALL_MASK; 912 913 mvpp2_percpu_write(port->priv, smp_processor_id(), 914 MVPP2_ISR_RX_TX_MASK_REG(port->id), val); 915 } 916 917 static void 918 mvpp2_shared_interrupt_mask_unmask(struct mvpp2_port *port, bool mask) 919 { 920 u32 val; 921 int i; 922 923 if (port->priv->hw_version != MVPP22) 924 return; 925 926 if (mask) 927 val = 0; 928 else 929 val = MVPP2_CAUSE_RXQ_OCCUP_DESC_ALL_MASK; 930 931 for (i = 0; i < port->nqvecs; i++) { 932 struct mvpp2_queue_vector *v = port->qvecs + i; 933 934 if (v->type != MVPP2_QUEUE_VECTOR_SHARED) 935 continue; 936 937 mvpp2_percpu_write(port->priv, v->sw_thread_id, 938 MVPP2_ISR_RX_TX_MASK_REG(port->id), val); 939 } 940 } 941 942 /* Port configuration routines */ 943 944 static void mvpp22_gop_init_rgmii(struct mvpp2_port *port) 945 { 946 struct mvpp2 *priv = port->priv; 947 u32 val; 948 949 regmap_read(priv->sysctrl_base, GENCONF_PORT_CTRL0, &val); 950 val |= GENCONF_PORT_CTRL0_BUS_WIDTH_SELECT; 951 regmap_write(priv->sysctrl_base, GENCONF_PORT_CTRL0, val); 952 953 regmap_read(priv->sysctrl_base, GENCONF_CTRL0, &val); 954 if (port->gop_id == 2) 955 val |= GENCONF_CTRL0_PORT0_RGMII | GENCONF_CTRL0_PORT1_RGMII; 956 else if (port->gop_id == 3) 957 val |= GENCONF_CTRL0_PORT1_RGMII_MII; 958 regmap_write(priv->sysctrl_base, GENCONF_CTRL0, val); 959 } 960 961 static void mvpp22_gop_init_sgmii(struct mvpp2_port *port) 962 { 963 struct mvpp2 *priv = port->priv; 964 u32 val; 965 966 regmap_read(priv->sysctrl_base, GENCONF_PORT_CTRL0, &val); 967 val |= GENCONF_PORT_CTRL0_BUS_WIDTH_SELECT | 968 GENCONF_PORT_CTRL0_RX_DATA_SAMPLE; 969 regmap_write(priv->sysctrl_base, GENCONF_PORT_CTRL0, val); 970 971 if (port->gop_id > 1) { 972 regmap_read(priv->sysctrl_base, GENCONF_CTRL0, &val); 973 if (port->gop_id == 2) 974 val &= ~GENCONF_CTRL0_PORT0_RGMII; 975 else if (port->gop_id == 3) 976 val &= ~GENCONF_CTRL0_PORT1_RGMII_MII; 977 regmap_write(priv->sysctrl_base, GENCONF_CTRL0, val); 978 } 979 } 980 981 static void mvpp22_gop_init_10gkr(struct mvpp2_port *port) 982 { 983 struct mvpp2 *priv = port->priv; 984 void __iomem *mpcs = priv->iface_base + MVPP22_MPCS_BASE(port->gop_id); 985 void __iomem *xpcs = priv->iface_base + MVPP22_XPCS_BASE(port->gop_id); 986 u32 val; 987 988 /* XPCS */ 989 val = readl(xpcs + MVPP22_XPCS_CFG0); 990 val &= ~(MVPP22_XPCS_CFG0_PCS_MODE(0x3) | 991 MVPP22_XPCS_CFG0_ACTIVE_LANE(0x3)); 992 val |= MVPP22_XPCS_CFG0_ACTIVE_LANE(2); 993 writel(val, xpcs + MVPP22_XPCS_CFG0); 994 995 /* MPCS */ 996 val = readl(mpcs + MVPP22_MPCS_CTRL); 997 val &= ~MVPP22_MPCS_CTRL_FWD_ERR_CONN; 998 writel(val, mpcs + MVPP22_MPCS_CTRL); 999 1000 val = readl(mpcs + MVPP22_MPCS_CLK_RESET); 1001 val &= ~(MVPP22_MPCS_CLK_RESET_DIV_RATIO(0x7) | MAC_CLK_RESET_MAC | 1002 MAC_CLK_RESET_SD_RX | MAC_CLK_RESET_SD_TX); 1003 val |= MVPP22_MPCS_CLK_RESET_DIV_RATIO(1); 1004 writel(val, mpcs + MVPP22_MPCS_CLK_RESET); 1005 1006 val &= ~MVPP22_MPCS_CLK_RESET_DIV_SET; 1007 val |= MAC_CLK_RESET_MAC | MAC_CLK_RESET_SD_RX | MAC_CLK_RESET_SD_TX; 1008 writel(val, mpcs + MVPP22_MPCS_CLK_RESET); 1009 } 1010 1011 static int mvpp22_gop_init(struct mvpp2_port *port) 1012 { 1013 struct mvpp2 *priv = port->priv; 1014 u32 val; 1015 1016 if (!priv->sysctrl_base) 1017 return 0; 1018 1019 switch (port->phy_interface) { 1020 case PHY_INTERFACE_MODE_RGMII: 1021 case PHY_INTERFACE_MODE_RGMII_ID: 1022 case PHY_INTERFACE_MODE_RGMII_RXID: 1023 case PHY_INTERFACE_MODE_RGMII_TXID: 1024 if (port->gop_id == 0) 1025 goto invalid_conf; 1026 mvpp22_gop_init_rgmii(port); 1027 break; 1028 case PHY_INTERFACE_MODE_SGMII: 1029 case PHY_INTERFACE_MODE_1000BASEX: 1030 case PHY_INTERFACE_MODE_2500BASEX: 1031 mvpp22_gop_init_sgmii(port); 1032 break; 1033 case PHY_INTERFACE_MODE_10GKR: 1034 if (port->gop_id != 0) 1035 goto invalid_conf; 1036 mvpp22_gop_init_10gkr(port); 1037 break; 1038 default: 1039 goto unsupported_conf; 1040 } 1041 1042 regmap_read(priv->sysctrl_base, GENCONF_PORT_CTRL1, &val); 1043 val |= GENCONF_PORT_CTRL1_RESET(port->gop_id) | 1044 GENCONF_PORT_CTRL1_EN(port->gop_id); 1045 regmap_write(priv->sysctrl_base, GENCONF_PORT_CTRL1, val); 1046 1047 regmap_read(priv->sysctrl_base, GENCONF_PORT_CTRL0, &val); 1048 val |= GENCONF_PORT_CTRL0_CLK_DIV_PHASE_CLR; 1049 regmap_write(priv->sysctrl_base, GENCONF_PORT_CTRL0, val); 1050 1051 regmap_read(priv->sysctrl_base, GENCONF_SOFT_RESET1, &val); 1052 val |= GENCONF_SOFT_RESET1_GOP; 1053 regmap_write(priv->sysctrl_base, GENCONF_SOFT_RESET1, val); 1054 1055 unsupported_conf: 1056 return 0; 1057 1058 invalid_conf: 1059 netdev_err(port->dev, "Invalid port configuration\n"); 1060 return -EINVAL; 1061 } 1062 1063 static void mvpp22_gop_unmask_irq(struct mvpp2_port *port) 1064 { 1065 u32 val; 1066 1067 if (phy_interface_mode_is_rgmii(port->phy_interface) || 1068 port->phy_interface == PHY_INTERFACE_MODE_SGMII || 1069 port->phy_interface == PHY_INTERFACE_MODE_1000BASEX || 1070 port->phy_interface == PHY_INTERFACE_MODE_2500BASEX) { 1071 /* Enable the GMAC link status irq for this port */ 1072 val = readl(port->base + MVPP22_GMAC_INT_SUM_MASK); 1073 val |= MVPP22_GMAC_INT_SUM_MASK_LINK_STAT; 1074 writel(val, port->base + MVPP22_GMAC_INT_SUM_MASK); 1075 } 1076 1077 if (port->gop_id == 0) { 1078 /* Enable the XLG/GIG irqs for this port */ 1079 val = readl(port->base + MVPP22_XLG_EXT_INT_MASK); 1080 if (port->phy_interface == PHY_INTERFACE_MODE_10GKR) 1081 val |= MVPP22_XLG_EXT_INT_MASK_XLG; 1082 else 1083 val |= MVPP22_XLG_EXT_INT_MASK_GIG; 1084 writel(val, port->base + MVPP22_XLG_EXT_INT_MASK); 1085 } 1086 } 1087 1088 static void mvpp22_gop_mask_irq(struct mvpp2_port *port) 1089 { 1090 u32 val; 1091 1092 if (port->gop_id == 0) { 1093 val = readl(port->base + MVPP22_XLG_EXT_INT_MASK); 1094 val &= ~(MVPP22_XLG_EXT_INT_MASK_XLG | 1095 MVPP22_XLG_EXT_INT_MASK_GIG); 1096 writel(val, port->base + MVPP22_XLG_EXT_INT_MASK); 1097 } 1098 1099 if (phy_interface_mode_is_rgmii(port->phy_interface) || 1100 port->phy_interface == PHY_INTERFACE_MODE_SGMII || 1101 port->phy_interface == PHY_INTERFACE_MODE_1000BASEX || 1102 port->phy_interface == PHY_INTERFACE_MODE_2500BASEX) { 1103 val = readl(port->base + MVPP22_GMAC_INT_SUM_MASK); 1104 val &= ~MVPP22_GMAC_INT_SUM_MASK_LINK_STAT; 1105 writel(val, port->base + MVPP22_GMAC_INT_SUM_MASK); 1106 } 1107 } 1108 1109 static void mvpp22_gop_setup_irq(struct mvpp2_port *port) 1110 { 1111 u32 val; 1112 1113 if (phy_interface_mode_is_rgmii(port->phy_interface) || 1114 port->phy_interface == PHY_INTERFACE_MODE_SGMII || 1115 port->phy_interface == PHY_INTERFACE_MODE_1000BASEX || 1116 port->phy_interface == PHY_INTERFACE_MODE_2500BASEX) { 1117 val = readl(port->base + MVPP22_GMAC_INT_MASK); 1118 val |= MVPP22_GMAC_INT_MASK_LINK_STAT; 1119 writel(val, port->base + MVPP22_GMAC_INT_MASK); 1120 } 1121 1122 if (port->gop_id == 0) { 1123 val = readl(port->base + MVPP22_XLG_INT_MASK); 1124 val |= MVPP22_XLG_INT_MASK_LINK; 1125 writel(val, port->base + MVPP22_XLG_INT_MASK); 1126 } 1127 1128 mvpp22_gop_unmask_irq(port); 1129 } 1130 1131 /* Sets the PHY mode of the COMPHY (which configures the serdes lanes). 1132 * 1133 * The PHY mode used by the PPv2 driver comes from the network subsystem, while 1134 * the one given to the COMPHY comes from the generic PHY subsystem. Hence they 1135 * differ. 1136 * 1137 * The COMPHY configures the serdes lanes regardless of the actual use of the 1138 * lanes by the physical layer. This is why configurations like 1139 * "PPv2 (2500BaseX) - COMPHY (2500SGMII)" are valid. 1140 */ 1141 static int mvpp22_comphy_init(struct mvpp2_port *port) 1142 { 1143 enum phy_mode mode; 1144 int ret; 1145 1146 if (!port->comphy) 1147 return 0; 1148 1149 switch (port->phy_interface) { 1150 case PHY_INTERFACE_MODE_SGMII: 1151 case PHY_INTERFACE_MODE_1000BASEX: 1152 mode = PHY_MODE_SGMII; 1153 break; 1154 case PHY_INTERFACE_MODE_2500BASEX: 1155 mode = PHY_MODE_2500SGMII; 1156 break; 1157 case PHY_INTERFACE_MODE_10GKR: 1158 mode = PHY_MODE_10GKR; 1159 break; 1160 default: 1161 return -EINVAL; 1162 } 1163 1164 ret = phy_set_mode(port->comphy, mode); 1165 if (ret) 1166 return ret; 1167 1168 return phy_power_on(port->comphy); 1169 } 1170 1171 static void mvpp2_port_enable(struct mvpp2_port *port) 1172 { 1173 u32 val; 1174 1175 /* Only GOP port 0 has an XLG MAC */ 1176 if (port->gop_id == 0 && 1177 (port->phy_interface == PHY_INTERFACE_MODE_XAUI || 1178 port->phy_interface == PHY_INTERFACE_MODE_10GKR)) { 1179 val = readl(port->base + MVPP22_XLG_CTRL0_REG); 1180 val |= MVPP22_XLG_CTRL0_PORT_EN | 1181 MVPP22_XLG_CTRL0_MAC_RESET_DIS; 1182 val &= ~MVPP22_XLG_CTRL0_MIB_CNT_DIS; 1183 writel(val, port->base + MVPP22_XLG_CTRL0_REG); 1184 } else { 1185 val = readl(port->base + MVPP2_GMAC_CTRL_0_REG); 1186 val |= MVPP2_GMAC_PORT_EN_MASK; 1187 val |= MVPP2_GMAC_MIB_CNTR_EN_MASK; 1188 writel(val, port->base + MVPP2_GMAC_CTRL_0_REG); 1189 } 1190 } 1191 1192 static void mvpp2_port_disable(struct mvpp2_port *port) 1193 { 1194 u32 val; 1195 1196 /* Only GOP port 0 has an XLG MAC */ 1197 if (port->gop_id == 0 && 1198 (port->phy_interface == PHY_INTERFACE_MODE_XAUI || 1199 port->phy_interface == PHY_INTERFACE_MODE_10GKR)) { 1200 val = readl(port->base + MVPP22_XLG_CTRL0_REG); 1201 val &= ~MVPP22_XLG_CTRL0_PORT_EN; 1202 writel(val, port->base + MVPP22_XLG_CTRL0_REG); 1203 1204 /* Disable & reset should be done separately */ 1205 val &= ~MVPP22_XLG_CTRL0_MAC_RESET_DIS; 1206 writel(val, port->base + MVPP22_XLG_CTRL0_REG); 1207 } else { 1208 val = readl(port->base + MVPP2_GMAC_CTRL_0_REG); 1209 val &= ~(MVPP2_GMAC_PORT_EN_MASK); 1210 writel(val, port->base + MVPP2_GMAC_CTRL_0_REG); 1211 } 1212 } 1213 1214 /* Set IEEE 802.3x Flow Control Xon Packet Transmission Mode */ 1215 static void mvpp2_port_periodic_xon_disable(struct mvpp2_port *port) 1216 { 1217 u32 val; 1218 1219 val = readl(port->base + MVPP2_GMAC_CTRL_1_REG) & 1220 ~MVPP2_GMAC_PERIODIC_XON_EN_MASK; 1221 writel(val, port->base + MVPP2_GMAC_CTRL_1_REG); 1222 } 1223 1224 /* Configure loopback port */ 1225 static void mvpp2_port_loopback_set(struct mvpp2_port *port, 1226 const struct phylink_link_state *state) 1227 { 1228 u32 val; 1229 1230 val = readl(port->base + MVPP2_GMAC_CTRL_1_REG); 1231 1232 if (state->speed == 1000) 1233 val |= MVPP2_GMAC_GMII_LB_EN_MASK; 1234 else 1235 val &= ~MVPP2_GMAC_GMII_LB_EN_MASK; 1236 1237 if (port->phy_interface == PHY_INTERFACE_MODE_SGMII || 1238 port->phy_interface == PHY_INTERFACE_MODE_1000BASEX || 1239 port->phy_interface == PHY_INTERFACE_MODE_2500BASEX) 1240 val |= MVPP2_GMAC_PCS_LB_EN_MASK; 1241 else 1242 val &= ~MVPP2_GMAC_PCS_LB_EN_MASK; 1243 1244 writel(val, port->base + MVPP2_GMAC_CTRL_1_REG); 1245 } 1246 1247 struct mvpp2_ethtool_counter { 1248 unsigned int offset; 1249 const char string[ETH_GSTRING_LEN]; 1250 bool reg_is_64b; 1251 }; 1252 1253 static u64 mvpp2_read_count(struct mvpp2_port *port, 1254 const struct mvpp2_ethtool_counter *counter) 1255 { 1256 u64 val; 1257 1258 val = readl(port->stats_base + counter->offset); 1259 if (counter->reg_is_64b) 1260 val += (u64)readl(port->stats_base + counter->offset + 4) << 32; 1261 1262 return val; 1263 } 1264 1265 /* Due to the fact that software statistics and hardware statistics are, by 1266 * design, incremented at different moments in the chain of packet processing, 1267 * it is very likely that incoming packets could have been dropped after being 1268 * counted by hardware but before reaching software statistics (most probably 1269 * multicast packets), and in the oppposite way, during transmission, FCS bytes 1270 * are added in between as well as TSO skb will be split and header bytes added. 1271 * Hence, statistics gathered from userspace with ifconfig (software) and 1272 * ethtool (hardware) cannot be compared. 1273 */ 1274 static const struct mvpp2_ethtool_counter mvpp2_ethtool_regs[] = { 1275 { MVPP2_MIB_GOOD_OCTETS_RCVD, "good_octets_received", true }, 1276 { MVPP2_MIB_BAD_OCTETS_RCVD, "bad_octets_received" }, 1277 { MVPP2_MIB_CRC_ERRORS_SENT, "crc_errors_sent" }, 1278 { MVPP2_MIB_UNICAST_FRAMES_RCVD, "unicast_frames_received" }, 1279 { MVPP2_MIB_BROADCAST_FRAMES_RCVD, "broadcast_frames_received" }, 1280 { MVPP2_MIB_MULTICAST_FRAMES_RCVD, "multicast_frames_received" }, 1281 { MVPP2_MIB_FRAMES_64_OCTETS, "frames_64_octets" }, 1282 { MVPP2_MIB_FRAMES_65_TO_127_OCTETS, "frames_65_to_127_octet" }, 1283 { MVPP2_MIB_FRAMES_128_TO_255_OCTETS, "frames_128_to_255_octet" }, 1284 { MVPP2_MIB_FRAMES_256_TO_511_OCTETS, "frames_256_to_511_octet" }, 1285 { MVPP2_MIB_FRAMES_512_TO_1023_OCTETS, "frames_512_to_1023_octet" }, 1286 { MVPP2_MIB_FRAMES_1024_TO_MAX_OCTETS, "frames_1024_to_max_octet" }, 1287 { MVPP2_MIB_GOOD_OCTETS_SENT, "good_octets_sent", true }, 1288 { MVPP2_MIB_UNICAST_FRAMES_SENT, "unicast_frames_sent" }, 1289 { MVPP2_MIB_MULTICAST_FRAMES_SENT, "multicast_frames_sent" }, 1290 { MVPP2_MIB_BROADCAST_FRAMES_SENT, "broadcast_frames_sent" }, 1291 { MVPP2_MIB_FC_SENT, "fc_sent" }, 1292 { MVPP2_MIB_FC_RCVD, "fc_received" }, 1293 { MVPP2_MIB_RX_FIFO_OVERRUN, "rx_fifo_overrun" }, 1294 { MVPP2_MIB_UNDERSIZE_RCVD, "undersize_received" }, 1295 { MVPP2_MIB_FRAGMENTS_RCVD, "fragments_received" }, 1296 { MVPP2_MIB_OVERSIZE_RCVD, "oversize_received" }, 1297 { MVPP2_MIB_JABBER_RCVD, "jabber_received" }, 1298 { MVPP2_MIB_MAC_RCV_ERROR, "mac_receive_error" }, 1299 { MVPP2_MIB_BAD_CRC_EVENT, "bad_crc_event" }, 1300 { MVPP2_MIB_COLLISION, "collision" }, 1301 { MVPP2_MIB_LATE_COLLISION, "late_collision" }, 1302 }; 1303 1304 static void mvpp2_ethtool_get_strings(struct net_device *netdev, u32 sset, 1305 u8 *data) 1306 { 1307 if (sset == ETH_SS_STATS) { 1308 int i; 1309 1310 for (i = 0; i < ARRAY_SIZE(mvpp2_ethtool_regs); i++) 1311 memcpy(data + i * ETH_GSTRING_LEN, 1312 &mvpp2_ethtool_regs[i].string, ETH_GSTRING_LEN); 1313 } 1314 } 1315 1316 static void mvpp2_gather_hw_statistics(struct work_struct *work) 1317 { 1318 struct delayed_work *del_work = to_delayed_work(work); 1319 struct mvpp2_port *port = container_of(del_work, struct mvpp2_port, 1320 stats_work); 1321 u64 *pstats; 1322 int i; 1323 1324 mutex_lock(&port->gather_stats_lock); 1325 1326 pstats = port->ethtool_stats; 1327 for (i = 0; i < ARRAY_SIZE(mvpp2_ethtool_regs); i++) 1328 *pstats++ += mvpp2_read_count(port, &mvpp2_ethtool_regs[i]); 1329 1330 /* No need to read again the counters right after this function if it 1331 * was called asynchronously by the user (ie. use of ethtool). 1332 */ 1333 cancel_delayed_work(&port->stats_work); 1334 queue_delayed_work(port->priv->stats_queue, &port->stats_work, 1335 MVPP2_MIB_COUNTERS_STATS_DELAY); 1336 1337 mutex_unlock(&port->gather_stats_lock); 1338 } 1339 1340 static void mvpp2_ethtool_get_stats(struct net_device *dev, 1341 struct ethtool_stats *stats, u64 *data) 1342 { 1343 struct mvpp2_port *port = netdev_priv(dev); 1344 1345 /* Update statistics for the given port, then take the lock to avoid 1346 * concurrent accesses on the ethtool_stats structure during its copy. 1347 */ 1348 mvpp2_gather_hw_statistics(&port->stats_work.work); 1349 1350 mutex_lock(&port->gather_stats_lock); 1351 memcpy(data, port->ethtool_stats, 1352 sizeof(u64) * ARRAY_SIZE(mvpp2_ethtool_regs)); 1353 mutex_unlock(&port->gather_stats_lock); 1354 } 1355 1356 static int mvpp2_ethtool_get_sset_count(struct net_device *dev, int sset) 1357 { 1358 if (sset == ETH_SS_STATS) 1359 return ARRAY_SIZE(mvpp2_ethtool_regs); 1360 1361 return -EOPNOTSUPP; 1362 } 1363 1364 static void mvpp2_port_reset(struct mvpp2_port *port) 1365 { 1366 u32 val; 1367 unsigned int i; 1368 1369 /* Read the GOP statistics to reset the hardware counters */ 1370 for (i = 0; i < ARRAY_SIZE(mvpp2_ethtool_regs); i++) 1371 mvpp2_read_count(port, &mvpp2_ethtool_regs[i]); 1372 1373 val = readl(port->base + MVPP2_GMAC_CTRL_2_REG) & 1374 ~MVPP2_GMAC_PORT_RESET_MASK; 1375 writel(val, port->base + MVPP2_GMAC_CTRL_2_REG); 1376 1377 while (readl(port->base + MVPP2_GMAC_CTRL_2_REG) & 1378 MVPP2_GMAC_PORT_RESET_MASK) 1379 continue; 1380 } 1381 1382 /* Change maximum receive size of the port */ 1383 static inline void mvpp2_gmac_max_rx_size_set(struct mvpp2_port *port) 1384 { 1385 u32 val; 1386 1387 val = readl(port->base + MVPP2_GMAC_CTRL_0_REG); 1388 val &= ~MVPP2_GMAC_MAX_RX_SIZE_MASK; 1389 val |= (((port->pkt_size - MVPP2_MH_SIZE) / 2) << 1390 MVPP2_GMAC_MAX_RX_SIZE_OFFS); 1391 writel(val, port->base + MVPP2_GMAC_CTRL_0_REG); 1392 } 1393 1394 /* Change maximum receive size of the port */ 1395 static inline void mvpp2_xlg_max_rx_size_set(struct mvpp2_port *port) 1396 { 1397 u32 val; 1398 1399 val = readl(port->base + MVPP22_XLG_CTRL1_REG); 1400 val &= ~MVPP22_XLG_CTRL1_FRAMESIZELIMIT_MASK; 1401 val |= ((port->pkt_size - MVPP2_MH_SIZE) / 2) << 1402 MVPP22_XLG_CTRL1_FRAMESIZELIMIT_OFFS; 1403 writel(val, port->base + MVPP22_XLG_CTRL1_REG); 1404 } 1405 1406 /* Set defaults to the MVPP2 port */ 1407 static void mvpp2_defaults_set(struct mvpp2_port *port) 1408 { 1409 int tx_port_num, val, queue, ptxq, lrxq; 1410 1411 if (port->priv->hw_version == MVPP21) { 1412 /* Update TX FIFO MIN Threshold */ 1413 val = readl(port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG); 1414 val &= ~MVPP2_GMAC_TX_FIFO_MIN_TH_ALL_MASK; 1415 /* Min. TX threshold must be less than minimal packet length */ 1416 val |= MVPP2_GMAC_TX_FIFO_MIN_TH_MASK(64 - 4 - 2); 1417 writel(val, port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG); 1418 } 1419 1420 /* Disable Legacy WRR, Disable EJP, Release from reset */ 1421 tx_port_num = mvpp2_egress_port(port); 1422 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, 1423 tx_port_num); 1424 mvpp2_write(port->priv, MVPP2_TXP_SCHED_CMD_1_REG, 0); 1425 1426 /* Close bandwidth for all queues */ 1427 for (queue = 0; queue < MVPP2_MAX_TXQ; queue++) { 1428 ptxq = mvpp2_txq_phys(port->id, queue); 1429 mvpp2_write(port->priv, 1430 MVPP2_TXQ_SCHED_TOKEN_CNTR_REG(ptxq), 0); 1431 } 1432 1433 /* Set refill period to 1 usec, refill tokens 1434 * and bucket size to maximum 1435 */ 1436 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PERIOD_REG, 1437 port->priv->tclk / USEC_PER_SEC); 1438 val = mvpp2_read(port->priv, MVPP2_TXP_SCHED_REFILL_REG); 1439 val &= ~MVPP2_TXP_REFILL_PERIOD_ALL_MASK; 1440 val |= MVPP2_TXP_REFILL_PERIOD_MASK(1); 1441 val |= MVPP2_TXP_REFILL_TOKENS_ALL_MASK; 1442 mvpp2_write(port->priv, MVPP2_TXP_SCHED_REFILL_REG, val); 1443 val = MVPP2_TXP_TOKEN_SIZE_MAX; 1444 mvpp2_write(port->priv, MVPP2_TXP_SCHED_TOKEN_SIZE_REG, val); 1445 1446 /* Set MaximumLowLatencyPacketSize value to 256 */ 1447 mvpp2_write(port->priv, MVPP2_RX_CTRL_REG(port->id), 1448 MVPP2_RX_USE_PSEUDO_FOR_CSUM_MASK | 1449 MVPP2_RX_LOW_LATENCY_PKT_SIZE(256)); 1450 1451 /* Enable Rx cache snoop */ 1452 for (lrxq = 0; lrxq < port->nrxqs; lrxq++) { 1453 queue = port->rxqs[lrxq]->id; 1454 val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(queue)); 1455 val |= MVPP2_SNOOP_PKT_SIZE_MASK | 1456 MVPP2_SNOOP_BUF_HDR_MASK; 1457 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(queue), val); 1458 } 1459 1460 /* At default, mask all interrupts to all present cpus */ 1461 mvpp2_interrupts_disable(port); 1462 } 1463 1464 /* Enable/disable receiving packets */ 1465 static void mvpp2_ingress_enable(struct mvpp2_port *port) 1466 { 1467 u32 val; 1468 int lrxq, queue; 1469 1470 for (lrxq = 0; lrxq < port->nrxqs; lrxq++) { 1471 queue = port->rxqs[lrxq]->id; 1472 val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(queue)); 1473 val &= ~MVPP2_RXQ_DISABLE_MASK; 1474 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(queue), val); 1475 } 1476 } 1477 1478 static void mvpp2_ingress_disable(struct mvpp2_port *port) 1479 { 1480 u32 val; 1481 int lrxq, queue; 1482 1483 for (lrxq = 0; lrxq < port->nrxqs; lrxq++) { 1484 queue = port->rxqs[lrxq]->id; 1485 val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(queue)); 1486 val |= MVPP2_RXQ_DISABLE_MASK; 1487 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(queue), val); 1488 } 1489 } 1490 1491 /* Enable transmit via physical egress queue 1492 * - HW starts take descriptors from DRAM 1493 */ 1494 static void mvpp2_egress_enable(struct mvpp2_port *port) 1495 { 1496 u32 qmap; 1497 int queue; 1498 int tx_port_num = mvpp2_egress_port(port); 1499 1500 /* Enable all initialized TXs. */ 1501 qmap = 0; 1502 for (queue = 0; queue < port->ntxqs; queue++) { 1503 struct mvpp2_tx_queue *txq = port->txqs[queue]; 1504 1505 if (txq->descs) 1506 qmap |= (1 << queue); 1507 } 1508 1509 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num); 1510 mvpp2_write(port->priv, MVPP2_TXP_SCHED_Q_CMD_REG, qmap); 1511 } 1512 1513 /* Disable transmit via physical egress queue 1514 * - HW doesn't take descriptors from DRAM 1515 */ 1516 static void mvpp2_egress_disable(struct mvpp2_port *port) 1517 { 1518 u32 reg_data; 1519 int delay; 1520 int tx_port_num = mvpp2_egress_port(port); 1521 1522 /* Issue stop command for active channels only */ 1523 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num); 1524 reg_data = (mvpp2_read(port->priv, MVPP2_TXP_SCHED_Q_CMD_REG)) & 1525 MVPP2_TXP_SCHED_ENQ_MASK; 1526 if (reg_data != 0) 1527 mvpp2_write(port->priv, MVPP2_TXP_SCHED_Q_CMD_REG, 1528 (reg_data << MVPP2_TXP_SCHED_DISQ_OFFSET)); 1529 1530 /* Wait for all Tx activity to terminate. */ 1531 delay = 0; 1532 do { 1533 if (delay >= MVPP2_TX_DISABLE_TIMEOUT_MSEC) { 1534 netdev_warn(port->dev, 1535 "Tx stop timed out, status=0x%08x\n", 1536 reg_data); 1537 break; 1538 } 1539 mdelay(1); 1540 delay++; 1541 1542 /* Check port TX Command register that all 1543 * Tx queues are stopped 1544 */ 1545 reg_data = mvpp2_read(port->priv, MVPP2_TXP_SCHED_Q_CMD_REG); 1546 } while (reg_data & MVPP2_TXP_SCHED_ENQ_MASK); 1547 } 1548 1549 /* Rx descriptors helper methods */ 1550 1551 /* Get number of Rx descriptors occupied by received packets */ 1552 static inline int 1553 mvpp2_rxq_received(struct mvpp2_port *port, int rxq_id) 1554 { 1555 u32 val = mvpp2_read(port->priv, MVPP2_RXQ_STATUS_REG(rxq_id)); 1556 1557 return val & MVPP2_RXQ_OCCUPIED_MASK; 1558 } 1559 1560 /* Update Rx queue status with the number of occupied and available 1561 * Rx descriptor slots. 1562 */ 1563 static inline void 1564 mvpp2_rxq_status_update(struct mvpp2_port *port, int rxq_id, 1565 int used_count, int free_count) 1566 { 1567 /* Decrement the number of used descriptors and increment count 1568 * increment the number of free descriptors. 1569 */ 1570 u32 val = used_count | (free_count << MVPP2_RXQ_NUM_NEW_OFFSET); 1571 1572 mvpp2_write(port->priv, MVPP2_RXQ_STATUS_UPDATE_REG(rxq_id), val); 1573 } 1574 1575 /* Get pointer to next RX descriptor to be processed by SW */ 1576 static inline struct mvpp2_rx_desc * 1577 mvpp2_rxq_next_desc_get(struct mvpp2_rx_queue *rxq) 1578 { 1579 int rx_desc = rxq->next_desc_to_proc; 1580 1581 rxq->next_desc_to_proc = MVPP2_QUEUE_NEXT_DESC(rxq, rx_desc); 1582 prefetch(rxq->descs + rxq->next_desc_to_proc); 1583 return rxq->descs + rx_desc; 1584 } 1585 1586 /* Set rx queue offset */ 1587 static void mvpp2_rxq_offset_set(struct mvpp2_port *port, 1588 int prxq, int offset) 1589 { 1590 u32 val; 1591 1592 /* Convert offset from bytes to units of 32 bytes */ 1593 offset = offset >> 5; 1594 1595 val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(prxq)); 1596 val &= ~MVPP2_RXQ_PACKET_OFFSET_MASK; 1597 1598 /* Offset is in */ 1599 val |= ((offset << MVPP2_RXQ_PACKET_OFFSET_OFFS) & 1600 MVPP2_RXQ_PACKET_OFFSET_MASK); 1601 1602 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(prxq), val); 1603 } 1604 1605 /* Tx descriptors helper methods */ 1606 1607 /* Get pointer to next Tx descriptor to be processed (send) by HW */ 1608 static struct mvpp2_tx_desc * 1609 mvpp2_txq_next_desc_get(struct mvpp2_tx_queue *txq) 1610 { 1611 int tx_desc = txq->next_desc_to_proc; 1612 1613 txq->next_desc_to_proc = MVPP2_QUEUE_NEXT_DESC(txq, tx_desc); 1614 return txq->descs + tx_desc; 1615 } 1616 1617 /* Update HW with number of aggregated Tx descriptors to be sent 1618 * 1619 * Called only from mvpp2_tx(), so migration is disabled, using 1620 * smp_processor_id() is OK. 1621 */ 1622 static void mvpp2_aggr_txq_pend_desc_add(struct mvpp2_port *port, int pending) 1623 { 1624 /* aggregated access - relevant TXQ number is written in TX desc */ 1625 mvpp2_percpu_write(port->priv, smp_processor_id(), 1626 MVPP2_AGGR_TXQ_UPDATE_REG, pending); 1627 } 1628 1629 /* Check if there are enough free descriptors in aggregated txq. 1630 * If not, update the number of occupied descriptors and repeat the check. 1631 * 1632 * Called only from mvpp2_tx(), so migration is disabled, using 1633 * smp_processor_id() is OK. 1634 */ 1635 static int mvpp2_aggr_desc_num_check(struct mvpp2 *priv, 1636 struct mvpp2_tx_queue *aggr_txq, int num) 1637 { 1638 if ((aggr_txq->count + num) > MVPP2_AGGR_TXQ_SIZE) { 1639 /* Update number of occupied aggregated Tx descriptors */ 1640 int cpu = smp_processor_id(); 1641 u32 val = mvpp2_read_relaxed(priv, 1642 MVPP2_AGGR_TXQ_STATUS_REG(cpu)); 1643 1644 aggr_txq->count = val & MVPP2_AGGR_TXQ_PENDING_MASK; 1645 1646 if ((aggr_txq->count + num) > MVPP2_AGGR_TXQ_SIZE) 1647 return -ENOMEM; 1648 } 1649 return 0; 1650 } 1651 1652 /* Reserved Tx descriptors allocation request 1653 * 1654 * Called only from mvpp2_txq_reserved_desc_num_proc(), itself called 1655 * only by mvpp2_tx(), so migration is disabled, using 1656 * smp_processor_id() is OK. 1657 */ 1658 static int mvpp2_txq_alloc_reserved_desc(struct mvpp2 *priv, 1659 struct mvpp2_tx_queue *txq, int num) 1660 { 1661 u32 val; 1662 int cpu = smp_processor_id(); 1663 1664 val = (txq->id << MVPP2_TXQ_RSVD_REQ_Q_OFFSET) | num; 1665 mvpp2_percpu_write_relaxed(priv, cpu, MVPP2_TXQ_RSVD_REQ_REG, val); 1666 1667 val = mvpp2_percpu_read_relaxed(priv, cpu, MVPP2_TXQ_RSVD_RSLT_REG); 1668 1669 return val & MVPP2_TXQ_RSVD_RSLT_MASK; 1670 } 1671 1672 /* Check if there are enough reserved descriptors for transmission. 1673 * If not, request chunk of reserved descriptors and check again. 1674 */ 1675 static int mvpp2_txq_reserved_desc_num_proc(struct mvpp2 *priv, 1676 struct mvpp2_tx_queue *txq, 1677 struct mvpp2_txq_pcpu *txq_pcpu, 1678 int num) 1679 { 1680 int req, cpu, desc_count; 1681 1682 if (txq_pcpu->reserved_num >= num) 1683 return 0; 1684 1685 /* Not enough descriptors reserved! Update the reserved descriptor 1686 * count and check again. 1687 */ 1688 1689 desc_count = 0; 1690 /* Compute total of used descriptors */ 1691 for_each_present_cpu(cpu) { 1692 struct mvpp2_txq_pcpu *txq_pcpu_aux; 1693 1694 txq_pcpu_aux = per_cpu_ptr(txq->pcpu, cpu); 1695 desc_count += txq_pcpu_aux->count; 1696 desc_count += txq_pcpu_aux->reserved_num; 1697 } 1698 1699 req = max(MVPP2_CPU_DESC_CHUNK, num - txq_pcpu->reserved_num); 1700 desc_count += req; 1701 1702 if (desc_count > 1703 (txq->size - (num_present_cpus() * MVPP2_CPU_DESC_CHUNK))) 1704 return -ENOMEM; 1705 1706 txq_pcpu->reserved_num += mvpp2_txq_alloc_reserved_desc(priv, txq, req); 1707 1708 /* OK, the descriptor could have been updated: check again. */ 1709 if (txq_pcpu->reserved_num < num) 1710 return -ENOMEM; 1711 return 0; 1712 } 1713 1714 /* Release the last allocated Tx descriptor. Useful to handle DMA 1715 * mapping failures in the Tx path. 1716 */ 1717 static void mvpp2_txq_desc_put(struct mvpp2_tx_queue *txq) 1718 { 1719 if (txq->next_desc_to_proc == 0) 1720 txq->next_desc_to_proc = txq->last_desc - 1; 1721 else 1722 txq->next_desc_to_proc--; 1723 } 1724 1725 /* Set Tx descriptors fields relevant for CSUM calculation */ 1726 static u32 mvpp2_txq_desc_csum(int l3_offs, int l3_proto, 1727 int ip_hdr_len, int l4_proto) 1728 { 1729 u32 command; 1730 1731 /* fields: L3_offset, IP_hdrlen, L3_type, G_IPv4_chk, 1732 * G_L4_chk, L4_type required only for checksum calculation 1733 */ 1734 command = (l3_offs << MVPP2_TXD_L3_OFF_SHIFT); 1735 command |= (ip_hdr_len << MVPP2_TXD_IP_HLEN_SHIFT); 1736 command |= MVPP2_TXD_IP_CSUM_DISABLE; 1737 1738 if (l3_proto == swab16(ETH_P_IP)) { 1739 command &= ~MVPP2_TXD_IP_CSUM_DISABLE; /* enable IPv4 csum */ 1740 command &= ~MVPP2_TXD_L3_IP6; /* enable IPv4 */ 1741 } else { 1742 command |= MVPP2_TXD_L3_IP6; /* enable IPv6 */ 1743 } 1744 1745 if (l4_proto == IPPROTO_TCP) { 1746 command &= ~MVPP2_TXD_L4_UDP; /* enable TCP */ 1747 command &= ~MVPP2_TXD_L4_CSUM_FRAG; /* generate L4 csum */ 1748 } else if (l4_proto == IPPROTO_UDP) { 1749 command |= MVPP2_TXD_L4_UDP; /* enable UDP */ 1750 command &= ~MVPP2_TXD_L4_CSUM_FRAG; /* generate L4 csum */ 1751 } else { 1752 command |= MVPP2_TXD_L4_CSUM_NOT; 1753 } 1754 1755 return command; 1756 } 1757 1758 /* Get number of sent descriptors and decrement counter. 1759 * The number of sent descriptors is returned. 1760 * Per-CPU access 1761 * 1762 * Called only from mvpp2_txq_done(), called from mvpp2_tx() 1763 * (migration disabled) and from the TX completion tasklet (migration 1764 * disabled) so using smp_processor_id() is OK. 1765 */ 1766 static inline int mvpp2_txq_sent_desc_proc(struct mvpp2_port *port, 1767 struct mvpp2_tx_queue *txq) 1768 { 1769 u32 val; 1770 1771 /* Reading status reg resets transmitted descriptor counter */ 1772 val = mvpp2_percpu_read_relaxed(port->priv, smp_processor_id(), 1773 MVPP2_TXQ_SENT_REG(txq->id)); 1774 1775 return (val & MVPP2_TRANSMITTED_COUNT_MASK) >> 1776 MVPP2_TRANSMITTED_COUNT_OFFSET; 1777 } 1778 1779 /* Called through on_each_cpu(), so runs on all CPUs, with migration 1780 * disabled, therefore using smp_processor_id() is OK. 1781 */ 1782 static void mvpp2_txq_sent_counter_clear(void *arg) 1783 { 1784 struct mvpp2_port *port = arg; 1785 int queue; 1786 1787 for (queue = 0; queue < port->ntxqs; queue++) { 1788 int id = port->txqs[queue]->id; 1789 1790 mvpp2_percpu_read(port->priv, smp_processor_id(), 1791 MVPP2_TXQ_SENT_REG(id)); 1792 } 1793 } 1794 1795 /* Set max sizes for Tx queues */ 1796 static void mvpp2_txp_max_tx_size_set(struct mvpp2_port *port) 1797 { 1798 u32 val, size, mtu; 1799 int txq, tx_port_num; 1800 1801 mtu = port->pkt_size * 8; 1802 if (mtu > MVPP2_TXP_MTU_MAX) 1803 mtu = MVPP2_TXP_MTU_MAX; 1804 1805 /* WA for wrong Token bucket update: Set MTU value = 3*real MTU value */ 1806 mtu = 3 * mtu; 1807 1808 /* Indirect access to registers */ 1809 tx_port_num = mvpp2_egress_port(port); 1810 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num); 1811 1812 /* Set MTU */ 1813 val = mvpp2_read(port->priv, MVPP2_TXP_SCHED_MTU_REG); 1814 val &= ~MVPP2_TXP_MTU_MAX; 1815 val |= mtu; 1816 mvpp2_write(port->priv, MVPP2_TXP_SCHED_MTU_REG, val); 1817 1818 /* TXP token size and all TXQs token size must be larger that MTU */ 1819 val = mvpp2_read(port->priv, MVPP2_TXP_SCHED_TOKEN_SIZE_REG); 1820 size = val & MVPP2_TXP_TOKEN_SIZE_MAX; 1821 if (size < mtu) { 1822 size = mtu; 1823 val &= ~MVPP2_TXP_TOKEN_SIZE_MAX; 1824 val |= size; 1825 mvpp2_write(port->priv, MVPP2_TXP_SCHED_TOKEN_SIZE_REG, val); 1826 } 1827 1828 for (txq = 0; txq < port->ntxqs; txq++) { 1829 val = mvpp2_read(port->priv, 1830 MVPP2_TXQ_SCHED_TOKEN_SIZE_REG(txq)); 1831 size = val & MVPP2_TXQ_TOKEN_SIZE_MAX; 1832 1833 if (size < mtu) { 1834 size = mtu; 1835 val &= ~MVPP2_TXQ_TOKEN_SIZE_MAX; 1836 val |= size; 1837 mvpp2_write(port->priv, 1838 MVPP2_TXQ_SCHED_TOKEN_SIZE_REG(txq), 1839 val); 1840 } 1841 } 1842 } 1843 1844 /* Set the number of packets that will be received before Rx interrupt 1845 * will be generated by HW. 1846 */ 1847 static void mvpp2_rx_pkts_coal_set(struct mvpp2_port *port, 1848 struct mvpp2_rx_queue *rxq) 1849 { 1850 int cpu = get_cpu(); 1851 1852 if (rxq->pkts_coal > MVPP2_OCCUPIED_THRESH_MASK) 1853 rxq->pkts_coal = MVPP2_OCCUPIED_THRESH_MASK; 1854 1855 mvpp2_percpu_write(port->priv, cpu, MVPP2_RXQ_NUM_REG, rxq->id); 1856 mvpp2_percpu_write(port->priv, cpu, MVPP2_RXQ_THRESH_REG, 1857 rxq->pkts_coal); 1858 1859 put_cpu(); 1860 } 1861 1862 /* For some reason in the LSP this is done on each CPU. Why ? */ 1863 static void mvpp2_tx_pkts_coal_set(struct mvpp2_port *port, 1864 struct mvpp2_tx_queue *txq) 1865 { 1866 int cpu = get_cpu(); 1867 u32 val; 1868 1869 if (txq->done_pkts_coal > MVPP2_TXQ_THRESH_MASK) 1870 txq->done_pkts_coal = MVPP2_TXQ_THRESH_MASK; 1871 1872 val = (txq->done_pkts_coal << MVPP2_TXQ_THRESH_OFFSET); 1873 mvpp2_percpu_write(port->priv, cpu, MVPP2_TXQ_NUM_REG, txq->id); 1874 mvpp2_percpu_write(port->priv, cpu, MVPP2_TXQ_THRESH_REG, val); 1875 1876 put_cpu(); 1877 } 1878 1879 static u32 mvpp2_usec_to_cycles(u32 usec, unsigned long clk_hz) 1880 { 1881 u64 tmp = (u64)clk_hz * usec; 1882 1883 do_div(tmp, USEC_PER_SEC); 1884 1885 return tmp > U32_MAX ? U32_MAX : tmp; 1886 } 1887 1888 static u32 mvpp2_cycles_to_usec(u32 cycles, unsigned long clk_hz) 1889 { 1890 u64 tmp = (u64)cycles * USEC_PER_SEC; 1891 1892 do_div(tmp, clk_hz); 1893 1894 return tmp > U32_MAX ? U32_MAX : tmp; 1895 } 1896 1897 /* Set the time delay in usec before Rx interrupt */ 1898 static void mvpp2_rx_time_coal_set(struct mvpp2_port *port, 1899 struct mvpp2_rx_queue *rxq) 1900 { 1901 unsigned long freq = port->priv->tclk; 1902 u32 val = mvpp2_usec_to_cycles(rxq->time_coal, freq); 1903 1904 if (val > MVPP2_MAX_ISR_RX_THRESHOLD) { 1905 rxq->time_coal = 1906 mvpp2_cycles_to_usec(MVPP2_MAX_ISR_RX_THRESHOLD, freq); 1907 1908 /* re-evaluate to get actual register value */ 1909 val = mvpp2_usec_to_cycles(rxq->time_coal, freq); 1910 } 1911 1912 mvpp2_write(port->priv, MVPP2_ISR_RX_THRESHOLD_REG(rxq->id), val); 1913 } 1914 1915 static void mvpp2_tx_time_coal_set(struct mvpp2_port *port) 1916 { 1917 unsigned long freq = port->priv->tclk; 1918 u32 val = mvpp2_usec_to_cycles(port->tx_time_coal, freq); 1919 1920 if (val > MVPP2_MAX_ISR_TX_THRESHOLD) { 1921 port->tx_time_coal = 1922 mvpp2_cycles_to_usec(MVPP2_MAX_ISR_TX_THRESHOLD, freq); 1923 1924 /* re-evaluate to get actual register value */ 1925 val = mvpp2_usec_to_cycles(port->tx_time_coal, freq); 1926 } 1927 1928 mvpp2_write(port->priv, MVPP2_ISR_TX_THRESHOLD_REG(port->id), val); 1929 } 1930 1931 /* Free Tx queue skbuffs */ 1932 static void mvpp2_txq_bufs_free(struct mvpp2_port *port, 1933 struct mvpp2_tx_queue *txq, 1934 struct mvpp2_txq_pcpu *txq_pcpu, int num) 1935 { 1936 int i; 1937 1938 for (i = 0; i < num; i++) { 1939 struct mvpp2_txq_pcpu_buf *tx_buf = 1940 txq_pcpu->buffs + txq_pcpu->txq_get_index; 1941 1942 if (!IS_TSO_HEADER(txq_pcpu, tx_buf->dma)) 1943 dma_unmap_single(port->dev->dev.parent, tx_buf->dma, 1944 tx_buf->size, DMA_TO_DEVICE); 1945 if (tx_buf->skb) 1946 dev_kfree_skb_any(tx_buf->skb); 1947 1948 mvpp2_txq_inc_get(txq_pcpu); 1949 } 1950 } 1951 1952 static inline struct mvpp2_rx_queue *mvpp2_get_rx_queue(struct mvpp2_port *port, 1953 u32 cause) 1954 { 1955 int queue = fls(cause) - 1; 1956 1957 return port->rxqs[queue]; 1958 } 1959 1960 static inline struct mvpp2_tx_queue *mvpp2_get_tx_queue(struct mvpp2_port *port, 1961 u32 cause) 1962 { 1963 int queue = fls(cause) - 1; 1964 1965 return port->txqs[queue]; 1966 } 1967 1968 /* Handle end of transmission */ 1969 static void mvpp2_txq_done(struct mvpp2_port *port, struct mvpp2_tx_queue *txq, 1970 struct mvpp2_txq_pcpu *txq_pcpu) 1971 { 1972 struct netdev_queue *nq = netdev_get_tx_queue(port->dev, txq->log_id); 1973 int tx_done; 1974 1975 if (txq_pcpu->cpu != smp_processor_id()) 1976 netdev_err(port->dev, "wrong cpu on the end of Tx processing\n"); 1977 1978 tx_done = mvpp2_txq_sent_desc_proc(port, txq); 1979 if (!tx_done) 1980 return; 1981 mvpp2_txq_bufs_free(port, txq, txq_pcpu, tx_done); 1982 1983 txq_pcpu->count -= tx_done; 1984 1985 if (netif_tx_queue_stopped(nq)) 1986 if (txq_pcpu->count <= txq_pcpu->wake_threshold) 1987 netif_tx_wake_queue(nq); 1988 } 1989 1990 static unsigned int mvpp2_tx_done(struct mvpp2_port *port, u32 cause, 1991 int cpu) 1992 { 1993 struct mvpp2_tx_queue *txq; 1994 struct mvpp2_txq_pcpu *txq_pcpu; 1995 unsigned int tx_todo = 0; 1996 1997 while (cause) { 1998 txq = mvpp2_get_tx_queue(port, cause); 1999 if (!txq) 2000 break; 2001 2002 txq_pcpu = per_cpu_ptr(txq->pcpu, cpu); 2003 2004 if (txq_pcpu->count) { 2005 mvpp2_txq_done(port, txq, txq_pcpu); 2006 tx_todo += txq_pcpu->count; 2007 } 2008 2009 cause &= ~(1 << txq->log_id); 2010 } 2011 return tx_todo; 2012 } 2013 2014 /* Rx/Tx queue initialization/cleanup methods */ 2015 2016 /* Allocate and initialize descriptors for aggr TXQ */ 2017 static int mvpp2_aggr_txq_init(struct platform_device *pdev, 2018 struct mvpp2_tx_queue *aggr_txq, int cpu, 2019 struct mvpp2 *priv) 2020 { 2021 u32 txq_dma; 2022 2023 /* Allocate memory for TX descriptors */ 2024 aggr_txq->descs = dma_zalloc_coherent(&pdev->dev, 2025 MVPP2_AGGR_TXQ_SIZE * MVPP2_DESC_ALIGNED_SIZE, 2026 &aggr_txq->descs_dma, GFP_KERNEL); 2027 if (!aggr_txq->descs) 2028 return -ENOMEM; 2029 2030 aggr_txq->last_desc = MVPP2_AGGR_TXQ_SIZE - 1; 2031 2032 /* Aggr TXQ no reset WA */ 2033 aggr_txq->next_desc_to_proc = mvpp2_read(priv, 2034 MVPP2_AGGR_TXQ_INDEX_REG(cpu)); 2035 2036 /* Set Tx descriptors queue starting address indirect 2037 * access 2038 */ 2039 if (priv->hw_version == MVPP21) 2040 txq_dma = aggr_txq->descs_dma; 2041 else 2042 txq_dma = aggr_txq->descs_dma >> 2043 MVPP22_AGGR_TXQ_DESC_ADDR_OFFS; 2044 2045 mvpp2_write(priv, MVPP2_AGGR_TXQ_DESC_ADDR_REG(cpu), txq_dma); 2046 mvpp2_write(priv, MVPP2_AGGR_TXQ_DESC_SIZE_REG(cpu), 2047 MVPP2_AGGR_TXQ_SIZE); 2048 2049 return 0; 2050 } 2051 2052 /* Create a specified Rx queue */ 2053 static int mvpp2_rxq_init(struct mvpp2_port *port, 2054 struct mvpp2_rx_queue *rxq) 2055 2056 { 2057 u32 rxq_dma; 2058 int cpu; 2059 2060 rxq->size = port->rx_ring_size; 2061 2062 /* Allocate memory for RX descriptors */ 2063 rxq->descs = dma_alloc_coherent(port->dev->dev.parent, 2064 rxq->size * MVPP2_DESC_ALIGNED_SIZE, 2065 &rxq->descs_dma, GFP_KERNEL); 2066 if (!rxq->descs) 2067 return -ENOMEM; 2068 2069 rxq->last_desc = rxq->size - 1; 2070 2071 /* Zero occupied and non-occupied counters - direct access */ 2072 mvpp2_write(port->priv, MVPP2_RXQ_STATUS_REG(rxq->id), 0); 2073 2074 /* Set Rx descriptors queue starting address - indirect access */ 2075 cpu = get_cpu(); 2076 mvpp2_percpu_write(port->priv, cpu, MVPP2_RXQ_NUM_REG, rxq->id); 2077 if (port->priv->hw_version == MVPP21) 2078 rxq_dma = rxq->descs_dma; 2079 else 2080 rxq_dma = rxq->descs_dma >> MVPP22_DESC_ADDR_OFFS; 2081 mvpp2_percpu_write(port->priv, cpu, MVPP2_RXQ_DESC_ADDR_REG, rxq_dma); 2082 mvpp2_percpu_write(port->priv, cpu, MVPP2_RXQ_DESC_SIZE_REG, rxq->size); 2083 mvpp2_percpu_write(port->priv, cpu, MVPP2_RXQ_INDEX_REG, 0); 2084 put_cpu(); 2085 2086 /* Set Offset */ 2087 mvpp2_rxq_offset_set(port, rxq->id, NET_SKB_PAD); 2088 2089 /* Set coalescing pkts and time */ 2090 mvpp2_rx_pkts_coal_set(port, rxq); 2091 mvpp2_rx_time_coal_set(port, rxq); 2092 2093 /* Add number of descriptors ready for receiving packets */ 2094 mvpp2_rxq_status_update(port, rxq->id, 0, rxq->size); 2095 2096 return 0; 2097 } 2098 2099 /* Push packets received by the RXQ to BM pool */ 2100 static void mvpp2_rxq_drop_pkts(struct mvpp2_port *port, 2101 struct mvpp2_rx_queue *rxq) 2102 { 2103 int rx_received, i; 2104 2105 rx_received = mvpp2_rxq_received(port, rxq->id); 2106 if (!rx_received) 2107 return; 2108 2109 for (i = 0; i < rx_received; i++) { 2110 struct mvpp2_rx_desc *rx_desc = mvpp2_rxq_next_desc_get(rxq); 2111 u32 status = mvpp2_rxdesc_status_get(port, rx_desc); 2112 int pool; 2113 2114 pool = (status & MVPP2_RXD_BM_POOL_ID_MASK) >> 2115 MVPP2_RXD_BM_POOL_ID_OFFS; 2116 2117 mvpp2_bm_pool_put(port, pool, 2118 mvpp2_rxdesc_dma_addr_get(port, rx_desc), 2119 mvpp2_rxdesc_cookie_get(port, rx_desc)); 2120 } 2121 mvpp2_rxq_status_update(port, rxq->id, rx_received, rx_received); 2122 } 2123 2124 /* Cleanup Rx queue */ 2125 static void mvpp2_rxq_deinit(struct mvpp2_port *port, 2126 struct mvpp2_rx_queue *rxq) 2127 { 2128 int cpu; 2129 2130 mvpp2_rxq_drop_pkts(port, rxq); 2131 2132 if (rxq->descs) 2133 dma_free_coherent(port->dev->dev.parent, 2134 rxq->size * MVPP2_DESC_ALIGNED_SIZE, 2135 rxq->descs, 2136 rxq->descs_dma); 2137 2138 rxq->descs = NULL; 2139 rxq->last_desc = 0; 2140 rxq->next_desc_to_proc = 0; 2141 rxq->descs_dma = 0; 2142 2143 /* Clear Rx descriptors queue starting address and size; 2144 * free descriptor number 2145 */ 2146 mvpp2_write(port->priv, MVPP2_RXQ_STATUS_REG(rxq->id), 0); 2147 cpu = get_cpu(); 2148 mvpp2_percpu_write(port->priv, cpu, MVPP2_RXQ_NUM_REG, rxq->id); 2149 mvpp2_percpu_write(port->priv, cpu, MVPP2_RXQ_DESC_ADDR_REG, 0); 2150 mvpp2_percpu_write(port->priv, cpu, MVPP2_RXQ_DESC_SIZE_REG, 0); 2151 put_cpu(); 2152 } 2153 2154 /* Create and initialize a Tx queue */ 2155 static int mvpp2_txq_init(struct mvpp2_port *port, 2156 struct mvpp2_tx_queue *txq) 2157 { 2158 u32 val; 2159 int cpu, desc, desc_per_txq, tx_port_num; 2160 struct mvpp2_txq_pcpu *txq_pcpu; 2161 2162 txq->size = port->tx_ring_size; 2163 2164 /* Allocate memory for Tx descriptors */ 2165 txq->descs = dma_alloc_coherent(port->dev->dev.parent, 2166 txq->size * MVPP2_DESC_ALIGNED_SIZE, 2167 &txq->descs_dma, GFP_KERNEL); 2168 if (!txq->descs) 2169 return -ENOMEM; 2170 2171 txq->last_desc = txq->size - 1; 2172 2173 /* Set Tx descriptors queue starting address - indirect access */ 2174 cpu = get_cpu(); 2175 mvpp2_percpu_write(port->priv, cpu, MVPP2_TXQ_NUM_REG, txq->id); 2176 mvpp2_percpu_write(port->priv, cpu, MVPP2_TXQ_DESC_ADDR_REG, 2177 txq->descs_dma); 2178 mvpp2_percpu_write(port->priv, cpu, MVPP2_TXQ_DESC_SIZE_REG, 2179 txq->size & MVPP2_TXQ_DESC_SIZE_MASK); 2180 mvpp2_percpu_write(port->priv, cpu, MVPP2_TXQ_INDEX_REG, 0); 2181 mvpp2_percpu_write(port->priv, cpu, MVPP2_TXQ_RSVD_CLR_REG, 2182 txq->id << MVPP2_TXQ_RSVD_CLR_OFFSET); 2183 val = mvpp2_percpu_read(port->priv, cpu, MVPP2_TXQ_PENDING_REG); 2184 val &= ~MVPP2_TXQ_PENDING_MASK; 2185 mvpp2_percpu_write(port->priv, cpu, MVPP2_TXQ_PENDING_REG, val); 2186 2187 /* Calculate base address in prefetch buffer. We reserve 16 descriptors 2188 * for each existing TXQ. 2189 * TCONTS for PON port must be continuous from 0 to MVPP2_MAX_TCONT 2190 * GBE ports assumed to be continuous from 0 to MVPP2_MAX_PORTS 2191 */ 2192 desc_per_txq = 16; 2193 desc = (port->id * MVPP2_MAX_TXQ * desc_per_txq) + 2194 (txq->log_id * desc_per_txq); 2195 2196 mvpp2_percpu_write(port->priv, cpu, MVPP2_TXQ_PREF_BUF_REG, 2197 MVPP2_PREF_BUF_PTR(desc) | MVPP2_PREF_BUF_SIZE_16 | 2198 MVPP2_PREF_BUF_THRESH(desc_per_txq / 2)); 2199 put_cpu(); 2200 2201 /* WRR / EJP configuration - indirect access */ 2202 tx_port_num = mvpp2_egress_port(port); 2203 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num); 2204 2205 val = mvpp2_read(port->priv, MVPP2_TXQ_SCHED_REFILL_REG(txq->log_id)); 2206 val &= ~MVPP2_TXQ_REFILL_PERIOD_ALL_MASK; 2207 val |= MVPP2_TXQ_REFILL_PERIOD_MASK(1); 2208 val |= MVPP2_TXQ_REFILL_TOKENS_ALL_MASK; 2209 mvpp2_write(port->priv, MVPP2_TXQ_SCHED_REFILL_REG(txq->log_id), val); 2210 2211 val = MVPP2_TXQ_TOKEN_SIZE_MAX; 2212 mvpp2_write(port->priv, MVPP2_TXQ_SCHED_TOKEN_SIZE_REG(txq->log_id), 2213 val); 2214 2215 for_each_present_cpu(cpu) { 2216 txq_pcpu = per_cpu_ptr(txq->pcpu, cpu); 2217 txq_pcpu->size = txq->size; 2218 txq_pcpu->buffs = kmalloc_array(txq_pcpu->size, 2219 sizeof(*txq_pcpu->buffs), 2220 GFP_KERNEL); 2221 if (!txq_pcpu->buffs) 2222 return -ENOMEM; 2223 2224 txq_pcpu->count = 0; 2225 txq_pcpu->reserved_num = 0; 2226 txq_pcpu->txq_put_index = 0; 2227 txq_pcpu->txq_get_index = 0; 2228 txq_pcpu->tso_headers = NULL; 2229 2230 txq_pcpu->stop_threshold = txq->size - MVPP2_MAX_SKB_DESCS; 2231 txq_pcpu->wake_threshold = txq_pcpu->stop_threshold / 2; 2232 2233 txq_pcpu->tso_headers = 2234 dma_alloc_coherent(port->dev->dev.parent, 2235 txq_pcpu->size * TSO_HEADER_SIZE, 2236 &txq_pcpu->tso_headers_dma, 2237 GFP_KERNEL); 2238 if (!txq_pcpu->tso_headers) 2239 return -ENOMEM; 2240 } 2241 2242 return 0; 2243 } 2244 2245 /* Free allocated TXQ resources */ 2246 static void mvpp2_txq_deinit(struct mvpp2_port *port, 2247 struct mvpp2_tx_queue *txq) 2248 { 2249 struct mvpp2_txq_pcpu *txq_pcpu; 2250 int cpu; 2251 2252 for_each_present_cpu(cpu) { 2253 txq_pcpu = per_cpu_ptr(txq->pcpu, cpu); 2254 kfree(txq_pcpu->buffs); 2255 2256 if (txq_pcpu->tso_headers) 2257 dma_free_coherent(port->dev->dev.parent, 2258 txq_pcpu->size * TSO_HEADER_SIZE, 2259 txq_pcpu->tso_headers, 2260 txq_pcpu->tso_headers_dma); 2261 2262 txq_pcpu->tso_headers = NULL; 2263 } 2264 2265 if (txq->descs) 2266 dma_free_coherent(port->dev->dev.parent, 2267 txq->size * MVPP2_DESC_ALIGNED_SIZE, 2268 txq->descs, txq->descs_dma); 2269 2270 txq->descs = NULL; 2271 txq->last_desc = 0; 2272 txq->next_desc_to_proc = 0; 2273 txq->descs_dma = 0; 2274 2275 /* Set minimum bandwidth for disabled TXQs */ 2276 mvpp2_write(port->priv, MVPP2_TXQ_SCHED_TOKEN_CNTR_REG(txq->id), 0); 2277 2278 /* Set Tx descriptors queue starting address and size */ 2279 cpu = get_cpu(); 2280 mvpp2_percpu_write(port->priv, cpu, MVPP2_TXQ_NUM_REG, txq->id); 2281 mvpp2_percpu_write(port->priv, cpu, MVPP2_TXQ_DESC_ADDR_REG, 0); 2282 mvpp2_percpu_write(port->priv, cpu, MVPP2_TXQ_DESC_SIZE_REG, 0); 2283 put_cpu(); 2284 } 2285 2286 /* Cleanup Tx ports */ 2287 static void mvpp2_txq_clean(struct mvpp2_port *port, struct mvpp2_tx_queue *txq) 2288 { 2289 struct mvpp2_txq_pcpu *txq_pcpu; 2290 int delay, pending, cpu; 2291 u32 val; 2292 2293 cpu = get_cpu(); 2294 mvpp2_percpu_write(port->priv, cpu, MVPP2_TXQ_NUM_REG, txq->id); 2295 val = mvpp2_percpu_read(port->priv, cpu, MVPP2_TXQ_PREF_BUF_REG); 2296 val |= MVPP2_TXQ_DRAIN_EN_MASK; 2297 mvpp2_percpu_write(port->priv, cpu, MVPP2_TXQ_PREF_BUF_REG, val); 2298 2299 /* The napi queue has been stopped so wait for all packets 2300 * to be transmitted. 2301 */ 2302 delay = 0; 2303 do { 2304 if (delay >= MVPP2_TX_PENDING_TIMEOUT_MSEC) { 2305 netdev_warn(port->dev, 2306 "port %d: cleaning queue %d timed out\n", 2307 port->id, txq->log_id); 2308 break; 2309 } 2310 mdelay(1); 2311 delay++; 2312 2313 pending = mvpp2_percpu_read(port->priv, cpu, 2314 MVPP2_TXQ_PENDING_REG); 2315 pending &= MVPP2_TXQ_PENDING_MASK; 2316 } while (pending); 2317 2318 val &= ~MVPP2_TXQ_DRAIN_EN_MASK; 2319 mvpp2_percpu_write(port->priv, cpu, MVPP2_TXQ_PREF_BUF_REG, val); 2320 put_cpu(); 2321 2322 for_each_present_cpu(cpu) { 2323 txq_pcpu = per_cpu_ptr(txq->pcpu, cpu); 2324 2325 /* Release all packets */ 2326 mvpp2_txq_bufs_free(port, txq, txq_pcpu, txq_pcpu->count); 2327 2328 /* Reset queue */ 2329 txq_pcpu->count = 0; 2330 txq_pcpu->txq_put_index = 0; 2331 txq_pcpu->txq_get_index = 0; 2332 } 2333 } 2334 2335 /* Cleanup all Tx queues */ 2336 static void mvpp2_cleanup_txqs(struct mvpp2_port *port) 2337 { 2338 struct mvpp2_tx_queue *txq; 2339 int queue; 2340 u32 val; 2341 2342 val = mvpp2_read(port->priv, MVPP2_TX_PORT_FLUSH_REG); 2343 2344 /* Reset Tx ports and delete Tx queues */ 2345 val |= MVPP2_TX_PORT_FLUSH_MASK(port->id); 2346 mvpp2_write(port->priv, MVPP2_TX_PORT_FLUSH_REG, val); 2347 2348 for (queue = 0; queue < port->ntxqs; queue++) { 2349 txq = port->txqs[queue]; 2350 mvpp2_txq_clean(port, txq); 2351 mvpp2_txq_deinit(port, txq); 2352 } 2353 2354 on_each_cpu(mvpp2_txq_sent_counter_clear, port, 1); 2355 2356 val &= ~MVPP2_TX_PORT_FLUSH_MASK(port->id); 2357 mvpp2_write(port->priv, MVPP2_TX_PORT_FLUSH_REG, val); 2358 } 2359 2360 /* Cleanup all Rx queues */ 2361 static void mvpp2_cleanup_rxqs(struct mvpp2_port *port) 2362 { 2363 int queue; 2364 2365 for (queue = 0; queue < port->nrxqs; queue++) 2366 mvpp2_rxq_deinit(port, port->rxqs[queue]); 2367 } 2368 2369 /* Init all Rx queues for port */ 2370 static int mvpp2_setup_rxqs(struct mvpp2_port *port) 2371 { 2372 int queue, err; 2373 2374 for (queue = 0; queue < port->nrxqs; queue++) { 2375 err = mvpp2_rxq_init(port, port->rxqs[queue]); 2376 if (err) 2377 goto err_cleanup; 2378 } 2379 return 0; 2380 2381 err_cleanup: 2382 mvpp2_cleanup_rxqs(port); 2383 return err; 2384 } 2385 2386 /* Init all tx queues for port */ 2387 static int mvpp2_setup_txqs(struct mvpp2_port *port) 2388 { 2389 struct mvpp2_tx_queue *txq; 2390 int queue, err; 2391 2392 for (queue = 0; queue < port->ntxqs; queue++) { 2393 txq = port->txqs[queue]; 2394 err = mvpp2_txq_init(port, txq); 2395 if (err) 2396 goto err_cleanup; 2397 } 2398 2399 if (port->has_tx_irqs) { 2400 mvpp2_tx_time_coal_set(port); 2401 for (queue = 0; queue < port->ntxqs; queue++) { 2402 txq = port->txqs[queue]; 2403 mvpp2_tx_pkts_coal_set(port, txq); 2404 } 2405 } 2406 2407 on_each_cpu(mvpp2_txq_sent_counter_clear, port, 1); 2408 return 0; 2409 2410 err_cleanup: 2411 mvpp2_cleanup_txqs(port); 2412 return err; 2413 } 2414 2415 /* The callback for per-port interrupt */ 2416 static irqreturn_t mvpp2_isr(int irq, void *dev_id) 2417 { 2418 struct mvpp2_queue_vector *qv = dev_id; 2419 2420 mvpp2_qvec_interrupt_disable(qv); 2421 2422 napi_schedule(&qv->napi); 2423 2424 return IRQ_HANDLED; 2425 } 2426 2427 /* Per-port interrupt for link status changes */ 2428 static irqreturn_t mvpp2_link_status_isr(int irq, void *dev_id) 2429 { 2430 struct mvpp2_port *port = (struct mvpp2_port *)dev_id; 2431 struct net_device *dev = port->dev; 2432 bool event = false, link = false; 2433 u32 val; 2434 2435 mvpp22_gop_mask_irq(port); 2436 2437 if (port->gop_id == 0 && 2438 port->phy_interface == PHY_INTERFACE_MODE_10GKR) { 2439 val = readl(port->base + MVPP22_XLG_INT_STAT); 2440 if (val & MVPP22_XLG_INT_STAT_LINK) { 2441 event = true; 2442 val = readl(port->base + MVPP22_XLG_STATUS); 2443 if (val & MVPP22_XLG_STATUS_LINK_UP) 2444 link = true; 2445 } 2446 } else if (phy_interface_mode_is_rgmii(port->phy_interface) || 2447 port->phy_interface == PHY_INTERFACE_MODE_SGMII || 2448 port->phy_interface == PHY_INTERFACE_MODE_1000BASEX || 2449 port->phy_interface == PHY_INTERFACE_MODE_2500BASEX) { 2450 val = readl(port->base + MVPP22_GMAC_INT_STAT); 2451 if (val & MVPP22_GMAC_INT_STAT_LINK) { 2452 event = true; 2453 val = readl(port->base + MVPP2_GMAC_STATUS0); 2454 if (val & MVPP2_GMAC_STATUS0_LINK_UP) 2455 link = true; 2456 } 2457 } 2458 2459 if (port->phylink) { 2460 phylink_mac_change(port->phylink, link); 2461 goto handled; 2462 } 2463 2464 if (!netif_running(dev) || !event) 2465 goto handled; 2466 2467 if (link) { 2468 mvpp2_interrupts_enable(port); 2469 2470 mvpp2_egress_enable(port); 2471 mvpp2_ingress_enable(port); 2472 netif_carrier_on(dev); 2473 netif_tx_wake_all_queues(dev); 2474 } else { 2475 netif_tx_stop_all_queues(dev); 2476 netif_carrier_off(dev); 2477 mvpp2_ingress_disable(port); 2478 mvpp2_egress_disable(port); 2479 2480 mvpp2_interrupts_disable(port); 2481 } 2482 2483 handled: 2484 mvpp22_gop_unmask_irq(port); 2485 return IRQ_HANDLED; 2486 } 2487 2488 static void mvpp2_timer_set(struct mvpp2_port_pcpu *port_pcpu) 2489 { 2490 ktime_t interval; 2491 2492 if (!port_pcpu->timer_scheduled) { 2493 port_pcpu->timer_scheduled = true; 2494 interval = MVPP2_TXDONE_HRTIMER_PERIOD_NS; 2495 hrtimer_start(&port_pcpu->tx_done_timer, interval, 2496 HRTIMER_MODE_REL_PINNED); 2497 } 2498 } 2499 2500 static void mvpp2_tx_proc_cb(unsigned long data) 2501 { 2502 struct net_device *dev = (struct net_device *)data; 2503 struct mvpp2_port *port = netdev_priv(dev); 2504 struct mvpp2_port_pcpu *port_pcpu = this_cpu_ptr(port->pcpu); 2505 unsigned int tx_todo, cause; 2506 2507 if (!netif_running(dev)) 2508 return; 2509 port_pcpu->timer_scheduled = false; 2510 2511 /* Process all the Tx queues */ 2512 cause = (1 << port->ntxqs) - 1; 2513 tx_todo = mvpp2_tx_done(port, cause, smp_processor_id()); 2514 2515 /* Set the timer in case not all the packets were processed */ 2516 if (tx_todo) 2517 mvpp2_timer_set(port_pcpu); 2518 } 2519 2520 static enum hrtimer_restart mvpp2_hr_timer_cb(struct hrtimer *timer) 2521 { 2522 struct mvpp2_port_pcpu *port_pcpu = container_of(timer, 2523 struct mvpp2_port_pcpu, 2524 tx_done_timer); 2525 2526 tasklet_schedule(&port_pcpu->tx_done_tasklet); 2527 2528 return HRTIMER_NORESTART; 2529 } 2530 2531 /* Main RX/TX processing routines */ 2532 2533 /* Display more error info */ 2534 static void mvpp2_rx_error(struct mvpp2_port *port, 2535 struct mvpp2_rx_desc *rx_desc) 2536 { 2537 u32 status = mvpp2_rxdesc_status_get(port, rx_desc); 2538 size_t sz = mvpp2_rxdesc_size_get(port, rx_desc); 2539 char *err_str = NULL; 2540 2541 switch (status & MVPP2_RXD_ERR_CODE_MASK) { 2542 case MVPP2_RXD_ERR_CRC: 2543 err_str = "crc"; 2544 break; 2545 case MVPP2_RXD_ERR_OVERRUN: 2546 err_str = "overrun"; 2547 break; 2548 case MVPP2_RXD_ERR_RESOURCE: 2549 err_str = "resource"; 2550 break; 2551 } 2552 if (err_str && net_ratelimit()) 2553 netdev_err(port->dev, 2554 "bad rx status %08x (%s error), size=%zu\n", 2555 status, err_str, sz); 2556 } 2557 2558 /* Handle RX checksum offload */ 2559 static void mvpp2_rx_csum(struct mvpp2_port *port, u32 status, 2560 struct sk_buff *skb) 2561 { 2562 if (((status & MVPP2_RXD_L3_IP4) && 2563 !(status & MVPP2_RXD_IP4_HEADER_ERR)) || 2564 (status & MVPP2_RXD_L3_IP6)) 2565 if (((status & MVPP2_RXD_L4_UDP) || 2566 (status & MVPP2_RXD_L4_TCP)) && 2567 (status & MVPP2_RXD_L4_CSUM_OK)) { 2568 skb->csum = 0; 2569 skb->ip_summed = CHECKSUM_UNNECESSARY; 2570 return; 2571 } 2572 2573 skb->ip_summed = CHECKSUM_NONE; 2574 } 2575 2576 /* Reuse skb if possible, or allocate a new skb and add it to BM pool */ 2577 static int mvpp2_rx_refill(struct mvpp2_port *port, 2578 struct mvpp2_bm_pool *bm_pool, int pool) 2579 { 2580 dma_addr_t dma_addr; 2581 phys_addr_t phys_addr; 2582 void *buf; 2583 2584 /* No recycle or too many buffers are in use, so allocate a new skb */ 2585 buf = mvpp2_buf_alloc(port, bm_pool, &dma_addr, &phys_addr, 2586 GFP_ATOMIC); 2587 if (!buf) 2588 return -ENOMEM; 2589 2590 mvpp2_bm_pool_put(port, pool, dma_addr, phys_addr); 2591 2592 return 0; 2593 } 2594 2595 /* Handle tx checksum */ 2596 static u32 mvpp2_skb_tx_csum(struct mvpp2_port *port, struct sk_buff *skb) 2597 { 2598 if (skb->ip_summed == CHECKSUM_PARTIAL) { 2599 int ip_hdr_len = 0; 2600 u8 l4_proto; 2601 2602 if (skb->protocol == htons(ETH_P_IP)) { 2603 struct iphdr *ip4h = ip_hdr(skb); 2604 2605 /* Calculate IPv4 checksum and L4 checksum */ 2606 ip_hdr_len = ip4h->ihl; 2607 l4_proto = ip4h->protocol; 2608 } else if (skb->protocol == htons(ETH_P_IPV6)) { 2609 struct ipv6hdr *ip6h = ipv6_hdr(skb); 2610 2611 /* Read l4_protocol from one of IPv6 extra headers */ 2612 if (skb_network_header_len(skb) > 0) 2613 ip_hdr_len = (skb_network_header_len(skb) >> 2); 2614 l4_proto = ip6h->nexthdr; 2615 } else { 2616 return MVPP2_TXD_L4_CSUM_NOT; 2617 } 2618 2619 return mvpp2_txq_desc_csum(skb_network_offset(skb), 2620 skb->protocol, ip_hdr_len, l4_proto); 2621 } 2622 2623 return MVPP2_TXD_L4_CSUM_NOT | MVPP2_TXD_IP_CSUM_DISABLE; 2624 } 2625 2626 /* Main rx processing */ 2627 static int mvpp2_rx(struct mvpp2_port *port, struct napi_struct *napi, 2628 int rx_todo, struct mvpp2_rx_queue *rxq) 2629 { 2630 struct net_device *dev = port->dev; 2631 int rx_received; 2632 int rx_done = 0; 2633 u32 rcvd_pkts = 0; 2634 u32 rcvd_bytes = 0; 2635 2636 /* Get number of received packets and clamp the to-do */ 2637 rx_received = mvpp2_rxq_received(port, rxq->id); 2638 if (rx_todo > rx_received) 2639 rx_todo = rx_received; 2640 2641 while (rx_done < rx_todo) { 2642 struct mvpp2_rx_desc *rx_desc = mvpp2_rxq_next_desc_get(rxq); 2643 struct mvpp2_bm_pool *bm_pool; 2644 struct sk_buff *skb; 2645 unsigned int frag_size; 2646 dma_addr_t dma_addr; 2647 phys_addr_t phys_addr; 2648 u32 rx_status; 2649 int pool, rx_bytes, err; 2650 void *data; 2651 2652 rx_done++; 2653 rx_status = mvpp2_rxdesc_status_get(port, rx_desc); 2654 rx_bytes = mvpp2_rxdesc_size_get(port, rx_desc); 2655 rx_bytes -= MVPP2_MH_SIZE; 2656 dma_addr = mvpp2_rxdesc_dma_addr_get(port, rx_desc); 2657 phys_addr = mvpp2_rxdesc_cookie_get(port, rx_desc); 2658 data = (void *)phys_to_virt(phys_addr); 2659 2660 pool = (rx_status & MVPP2_RXD_BM_POOL_ID_MASK) >> 2661 MVPP2_RXD_BM_POOL_ID_OFFS; 2662 bm_pool = &port->priv->bm_pools[pool]; 2663 2664 /* In case of an error, release the requested buffer pointer 2665 * to the Buffer Manager. This request process is controlled 2666 * by the hardware, and the information about the buffer is 2667 * comprised by the RX descriptor. 2668 */ 2669 if (rx_status & MVPP2_RXD_ERR_SUMMARY) { 2670 err_drop_frame: 2671 dev->stats.rx_errors++; 2672 mvpp2_rx_error(port, rx_desc); 2673 /* Return the buffer to the pool */ 2674 mvpp2_bm_pool_put(port, pool, dma_addr, phys_addr); 2675 continue; 2676 } 2677 2678 if (bm_pool->frag_size > PAGE_SIZE) 2679 frag_size = 0; 2680 else 2681 frag_size = bm_pool->frag_size; 2682 2683 skb = build_skb(data, frag_size); 2684 if (!skb) { 2685 netdev_warn(port->dev, "skb build failed\n"); 2686 goto err_drop_frame; 2687 } 2688 2689 err = mvpp2_rx_refill(port, bm_pool, pool); 2690 if (err) { 2691 netdev_err(port->dev, "failed to refill BM pools\n"); 2692 goto err_drop_frame; 2693 } 2694 2695 dma_unmap_single(dev->dev.parent, dma_addr, 2696 bm_pool->buf_size, DMA_FROM_DEVICE); 2697 2698 rcvd_pkts++; 2699 rcvd_bytes += rx_bytes; 2700 2701 skb_reserve(skb, MVPP2_MH_SIZE + NET_SKB_PAD); 2702 skb_put(skb, rx_bytes); 2703 skb->protocol = eth_type_trans(skb, dev); 2704 mvpp2_rx_csum(port, rx_status, skb); 2705 2706 napi_gro_receive(napi, skb); 2707 } 2708 2709 if (rcvd_pkts) { 2710 struct mvpp2_pcpu_stats *stats = this_cpu_ptr(port->stats); 2711 2712 u64_stats_update_begin(&stats->syncp); 2713 stats->rx_packets += rcvd_pkts; 2714 stats->rx_bytes += rcvd_bytes; 2715 u64_stats_update_end(&stats->syncp); 2716 } 2717 2718 /* Update Rx queue management counters */ 2719 wmb(); 2720 mvpp2_rxq_status_update(port, rxq->id, rx_done, rx_done); 2721 2722 return rx_todo; 2723 } 2724 2725 static inline void 2726 tx_desc_unmap_put(struct mvpp2_port *port, struct mvpp2_tx_queue *txq, 2727 struct mvpp2_tx_desc *desc) 2728 { 2729 struct mvpp2_txq_pcpu *txq_pcpu = this_cpu_ptr(txq->pcpu); 2730 2731 dma_addr_t buf_dma_addr = 2732 mvpp2_txdesc_dma_addr_get(port, desc); 2733 size_t buf_sz = 2734 mvpp2_txdesc_size_get(port, desc); 2735 if (!IS_TSO_HEADER(txq_pcpu, buf_dma_addr)) 2736 dma_unmap_single(port->dev->dev.parent, buf_dma_addr, 2737 buf_sz, DMA_TO_DEVICE); 2738 mvpp2_txq_desc_put(txq); 2739 } 2740 2741 /* Handle tx fragmentation processing */ 2742 static int mvpp2_tx_frag_process(struct mvpp2_port *port, struct sk_buff *skb, 2743 struct mvpp2_tx_queue *aggr_txq, 2744 struct mvpp2_tx_queue *txq) 2745 { 2746 struct mvpp2_txq_pcpu *txq_pcpu = this_cpu_ptr(txq->pcpu); 2747 struct mvpp2_tx_desc *tx_desc; 2748 int i; 2749 dma_addr_t buf_dma_addr; 2750 2751 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { 2752 skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 2753 void *addr = page_address(frag->page.p) + frag->page_offset; 2754 2755 tx_desc = mvpp2_txq_next_desc_get(aggr_txq); 2756 mvpp2_txdesc_txq_set(port, tx_desc, txq->id); 2757 mvpp2_txdesc_size_set(port, tx_desc, frag->size); 2758 2759 buf_dma_addr = dma_map_single(port->dev->dev.parent, addr, 2760 frag->size, DMA_TO_DEVICE); 2761 if (dma_mapping_error(port->dev->dev.parent, buf_dma_addr)) { 2762 mvpp2_txq_desc_put(txq); 2763 goto cleanup; 2764 } 2765 2766 mvpp2_txdesc_dma_addr_set(port, tx_desc, buf_dma_addr); 2767 2768 if (i == (skb_shinfo(skb)->nr_frags - 1)) { 2769 /* Last descriptor */ 2770 mvpp2_txdesc_cmd_set(port, tx_desc, 2771 MVPP2_TXD_L_DESC); 2772 mvpp2_txq_inc_put(port, txq_pcpu, skb, tx_desc); 2773 } else { 2774 /* Descriptor in the middle: Not First, Not Last */ 2775 mvpp2_txdesc_cmd_set(port, tx_desc, 0); 2776 mvpp2_txq_inc_put(port, txq_pcpu, NULL, tx_desc); 2777 } 2778 } 2779 2780 return 0; 2781 cleanup: 2782 /* Release all descriptors that were used to map fragments of 2783 * this packet, as well as the corresponding DMA mappings 2784 */ 2785 for (i = i - 1; i >= 0; i--) { 2786 tx_desc = txq->descs + i; 2787 tx_desc_unmap_put(port, txq, tx_desc); 2788 } 2789 2790 return -ENOMEM; 2791 } 2792 2793 static inline void mvpp2_tso_put_hdr(struct sk_buff *skb, 2794 struct net_device *dev, 2795 struct mvpp2_tx_queue *txq, 2796 struct mvpp2_tx_queue *aggr_txq, 2797 struct mvpp2_txq_pcpu *txq_pcpu, 2798 int hdr_sz) 2799 { 2800 struct mvpp2_port *port = netdev_priv(dev); 2801 struct mvpp2_tx_desc *tx_desc = mvpp2_txq_next_desc_get(aggr_txq); 2802 dma_addr_t addr; 2803 2804 mvpp2_txdesc_txq_set(port, tx_desc, txq->id); 2805 mvpp2_txdesc_size_set(port, tx_desc, hdr_sz); 2806 2807 addr = txq_pcpu->tso_headers_dma + 2808 txq_pcpu->txq_put_index * TSO_HEADER_SIZE; 2809 mvpp2_txdesc_dma_addr_set(port, tx_desc, addr); 2810 2811 mvpp2_txdesc_cmd_set(port, tx_desc, mvpp2_skb_tx_csum(port, skb) | 2812 MVPP2_TXD_F_DESC | 2813 MVPP2_TXD_PADDING_DISABLE); 2814 mvpp2_txq_inc_put(port, txq_pcpu, NULL, tx_desc); 2815 } 2816 2817 static inline int mvpp2_tso_put_data(struct sk_buff *skb, 2818 struct net_device *dev, struct tso_t *tso, 2819 struct mvpp2_tx_queue *txq, 2820 struct mvpp2_tx_queue *aggr_txq, 2821 struct mvpp2_txq_pcpu *txq_pcpu, 2822 int sz, bool left, bool last) 2823 { 2824 struct mvpp2_port *port = netdev_priv(dev); 2825 struct mvpp2_tx_desc *tx_desc = mvpp2_txq_next_desc_get(aggr_txq); 2826 dma_addr_t buf_dma_addr; 2827 2828 mvpp2_txdesc_txq_set(port, tx_desc, txq->id); 2829 mvpp2_txdesc_size_set(port, tx_desc, sz); 2830 2831 buf_dma_addr = dma_map_single(dev->dev.parent, tso->data, sz, 2832 DMA_TO_DEVICE); 2833 if (unlikely(dma_mapping_error(dev->dev.parent, buf_dma_addr))) { 2834 mvpp2_txq_desc_put(txq); 2835 return -ENOMEM; 2836 } 2837 2838 mvpp2_txdesc_dma_addr_set(port, tx_desc, buf_dma_addr); 2839 2840 if (!left) { 2841 mvpp2_txdesc_cmd_set(port, tx_desc, MVPP2_TXD_L_DESC); 2842 if (last) { 2843 mvpp2_txq_inc_put(port, txq_pcpu, skb, tx_desc); 2844 return 0; 2845 } 2846 } else { 2847 mvpp2_txdesc_cmd_set(port, tx_desc, 0); 2848 } 2849 2850 mvpp2_txq_inc_put(port, txq_pcpu, NULL, tx_desc); 2851 return 0; 2852 } 2853 2854 static int mvpp2_tx_tso(struct sk_buff *skb, struct net_device *dev, 2855 struct mvpp2_tx_queue *txq, 2856 struct mvpp2_tx_queue *aggr_txq, 2857 struct mvpp2_txq_pcpu *txq_pcpu) 2858 { 2859 struct mvpp2_port *port = netdev_priv(dev); 2860 struct tso_t tso; 2861 int hdr_sz = skb_transport_offset(skb) + tcp_hdrlen(skb); 2862 int i, len, descs = 0; 2863 2864 /* Check number of available descriptors */ 2865 if (mvpp2_aggr_desc_num_check(port->priv, aggr_txq, 2866 tso_count_descs(skb)) || 2867 mvpp2_txq_reserved_desc_num_proc(port->priv, txq, txq_pcpu, 2868 tso_count_descs(skb))) 2869 return 0; 2870 2871 tso_start(skb, &tso); 2872 len = skb->len - hdr_sz; 2873 while (len > 0) { 2874 int left = min_t(int, skb_shinfo(skb)->gso_size, len); 2875 char *hdr = txq_pcpu->tso_headers + 2876 txq_pcpu->txq_put_index * TSO_HEADER_SIZE; 2877 2878 len -= left; 2879 descs++; 2880 2881 tso_build_hdr(skb, hdr, &tso, left, len == 0); 2882 mvpp2_tso_put_hdr(skb, dev, txq, aggr_txq, txq_pcpu, hdr_sz); 2883 2884 while (left > 0) { 2885 int sz = min_t(int, tso.size, left); 2886 left -= sz; 2887 descs++; 2888 2889 if (mvpp2_tso_put_data(skb, dev, &tso, txq, aggr_txq, 2890 txq_pcpu, sz, left, len == 0)) 2891 goto release; 2892 tso_build_data(skb, &tso, sz); 2893 } 2894 } 2895 2896 return descs; 2897 2898 release: 2899 for (i = descs - 1; i >= 0; i--) { 2900 struct mvpp2_tx_desc *tx_desc = txq->descs + i; 2901 tx_desc_unmap_put(port, txq, tx_desc); 2902 } 2903 return 0; 2904 } 2905 2906 /* Main tx processing */ 2907 static int mvpp2_tx(struct sk_buff *skb, struct net_device *dev) 2908 { 2909 struct mvpp2_port *port = netdev_priv(dev); 2910 struct mvpp2_tx_queue *txq, *aggr_txq; 2911 struct mvpp2_txq_pcpu *txq_pcpu; 2912 struct mvpp2_tx_desc *tx_desc; 2913 dma_addr_t buf_dma_addr; 2914 int frags = 0; 2915 u16 txq_id; 2916 u32 tx_cmd; 2917 2918 txq_id = skb_get_queue_mapping(skb); 2919 txq = port->txqs[txq_id]; 2920 txq_pcpu = this_cpu_ptr(txq->pcpu); 2921 aggr_txq = &port->priv->aggr_txqs[smp_processor_id()]; 2922 2923 if (skb_is_gso(skb)) { 2924 frags = mvpp2_tx_tso(skb, dev, txq, aggr_txq, txq_pcpu); 2925 goto out; 2926 } 2927 frags = skb_shinfo(skb)->nr_frags + 1; 2928 2929 /* Check number of available descriptors */ 2930 if (mvpp2_aggr_desc_num_check(port->priv, aggr_txq, frags) || 2931 mvpp2_txq_reserved_desc_num_proc(port->priv, txq, 2932 txq_pcpu, frags)) { 2933 frags = 0; 2934 goto out; 2935 } 2936 2937 /* Get a descriptor for the first part of the packet */ 2938 tx_desc = mvpp2_txq_next_desc_get(aggr_txq); 2939 mvpp2_txdesc_txq_set(port, tx_desc, txq->id); 2940 mvpp2_txdesc_size_set(port, tx_desc, skb_headlen(skb)); 2941 2942 buf_dma_addr = dma_map_single(dev->dev.parent, skb->data, 2943 skb_headlen(skb), DMA_TO_DEVICE); 2944 if (unlikely(dma_mapping_error(dev->dev.parent, buf_dma_addr))) { 2945 mvpp2_txq_desc_put(txq); 2946 frags = 0; 2947 goto out; 2948 } 2949 2950 mvpp2_txdesc_dma_addr_set(port, tx_desc, buf_dma_addr); 2951 2952 tx_cmd = mvpp2_skb_tx_csum(port, skb); 2953 2954 if (frags == 1) { 2955 /* First and Last descriptor */ 2956 tx_cmd |= MVPP2_TXD_F_DESC | MVPP2_TXD_L_DESC; 2957 mvpp2_txdesc_cmd_set(port, tx_desc, tx_cmd); 2958 mvpp2_txq_inc_put(port, txq_pcpu, skb, tx_desc); 2959 } else { 2960 /* First but not Last */ 2961 tx_cmd |= MVPP2_TXD_F_DESC | MVPP2_TXD_PADDING_DISABLE; 2962 mvpp2_txdesc_cmd_set(port, tx_desc, tx_cmd); 2963 mvpp2_txq_inc_put(port, txq_pcpu, NULL, tx_desc); 2964 2965 /* Continue with other skb fragments */ 2966 if (mvpp2_tx_frag_process(port, skb, aggr_txq, txq)) { 2967 tx_desc_unmap_put(port, txq, tx_desc); 2968 frags = 0; 2969 } 2970 } 2971 2972 out: 2973 if (frags > 0) { 2974 struct mvpp2_pcpu_stats *stats = this_cpu_ptr(port->stats); 2975 struct netdev_queue *nq = netdev_get_tx_queue(dev, txq_id); 2976 2977 txq_pcpu->reserved_num -= frags; 2978 txq_pcpu->count += frags; 2979 aggr_txq->count += frags; 2980 2981 /* Enable transmit */ 2982 wmb(); 2983 mvpp2_aggr_txq_pend_desc_add(port, frags); 2984 2985 if (txq_pcpu->count >= txq_pcpu->stop_threshold) 2986 netif_tx_stop_queue(nq); 2987 2988 u64_stats_update_begin(&stats->syncp); 2989 stats->tx_packets++; 2990 stats->tx_bytes += skb->len; 2991 u64_stats_update_end(&stats->syncp); 2992 } else { 2993 dev->stats.tx_dropped++; 2994 dev_kfree_skb_any(skb); 2995 } 2996 2997 /* Finalize TX processing */ 2998 if (!port->has_tx_irqs && txq_pcpu->count >= txq->done_pkts_coal) 2999 mvpp2_txq_done(port, txq, txq_pcpu); 3000 3001 /* Set the timer in case not all frags were processed */ 3002 if (!port->has_tx_irqs && txq_pcpu->count <= frags && 3003 txq_pcpu->count > 0) { 3004 struct mvpp2_port_pcpu *port_pcpu = this_cpu_ptr(port->pcpu); 3005 3006 mvpp2_timer_set(port_pcpu); 3007 } 3008 3009 return NETDEV_TX_OK; 3010 } 3011 3012 static inline void mvpp2_cause_error(struct net_device *dev, int cause) 3013 { 3014 if (cause & MVPP2_CAUSE_FCS_ERR_MASK) 3015 netdev_err(dev, "FCS error\n"); 3016 if (cause & MVPP2_CAUSE_RX_FIFO_OVERRUN_MASK) 3017 netdev_err(dev, "rx fifo overrun error\n"); 3018 if (cause & MVPP2_CAUSE_TX_FIFO_UNDERRUN_MASK) 3019 netdev_err(dev, "tx fifo underrun error\n"); 3020 } 3021 3022 static int mvpp2_poll(struct napi_struct *napi, int budget) 3023 { 3024 u32 cause_rx_tx, cause_rx, cause_tx, cause_misc; 3025 int rx_done = 0; 3026 struct mvpp2_port *port = netdev_priv(napi->dev); 3027 struct mvpp2_queue_vector *qv; 3028 int cpu = smp_processor_id(); 3029 3030 qv = container_of(napi, struct mvpp2_queue_vector, napi); 3031 3032 /* Rx/Tx cause register 3033 * 3034 * Bits 0-15: each bit indicates received packets on the Rx queue 3035 * (bit 0 is for Rx queue 0). 3036 * 3037 * Bits 16-23: each bit indicates transmitted packets on the Tx queue 3038 * (bit 16 is for Tx queue 0). 3039 * 3040 * Each CPU has its own Rx/Tx cause register 3041 */ 3042 cause_rx_tx = mvpp2_percpu_read_relaxed(port->priv, qv->sw_thread_id, 3043 MVPP2_ISR_RX_TX_CAUSE_REG(port->id)); 3044 3045 cause_misc = cause_rx_tx & MVPP2_CAUSE_MISC_SUM_MASK; 3046 if (cause_misc) { 3047 mvpp2_cause_error(port->dev, cause_misc); 3048 3049 /* Clear the cause register */ 3050 mvpp2_write(port->priv, MVPP2_ISR_MISC_CAUSE_REG, 0); 3051 mvpp2_percpu_write(port->priv, cpu, 3052 MVPP2_ISR_RX_TX_CAUSE_REG(port->id), 3053 cause_rx_tx & ~MVPP2_CAUSE_MISC_SUM_MASK); 3054 } 3055 3056 cause_tx = cause_rx_tx & MVPP2_CAUSE_TXQ_OCCUP_DESC_ALL_MASK; 3057 if (cause_tx) { 3058 cause_tx >>= MVPP2_CAUSE_TXQ_OCCUP_DESC_ALL_OFFSET; 3059 mvpp2_tx_done(port, cause_tx, qv->sw_thread_id); 3060 } 3061 3062 /* Process RX packets */ 3063 cause_rx = cause_rx_tx & MVPP2_CAUSE_RXQ_OCCUP_DESC_ALL_MASK; 3064 cause_rx <<= qv->first_rxq; 3065 cause_rx |= qv->pending_cause_rx; 3066 while (cause_rx && budget > 0) { 3067 int count; 3068 struct mvpp2_rx_queue *rxq; 3069 3070 rxq = mvpp2_get_rx_queue(port, cause_rx); 3071 if (!rxq) 3072 break; 3073 3074 count = mvpp2_rx(port, napi, budget, rxq); 3075 rx_done += count; 3076 budget -= count; 3077 if (budget > 0) { 3078 /* Clear the bit associated to this Rx queue 3079 * so that next iteration will continue from 3080 * the next Rx queue. 3081 */ 3082 cause_rx &= ~(1 << rxq->logic_rxq); 3083 } 3084 } 3085 3086 if (budget > 0) { 3087 cause_rx = 0; 3088 napi_complete_done(napi, rx_done); 3089 3090 mvpp2_qvec_interrupt_enable(qv); 3091 } 3092 qv->pending_cause_rx = cause_rx; 3093 return rx_done; 3094 } 3095 3096 static void mvpp22_mode_reconfigure(struct mvpp2_port *port) 3097 { 3098 u32 ctrl3; 3099 3100 /* comphy reconfiguration */ 3101 mvpp22_comphy_init(port); 3102 3103 /* gop reconfiguration */ 3104 mvpp22_gop_init(port); 3105 3106 /* Only GOP port 0 has an XLG MAC */ 3107 if (port->gop_id == 0) { 3108 ctrl3 = readl(port->base + MVPP22_XLG_CTRL3_REG); 3109 ctrl3 &= ~MVPP22_XLG_CTRL3_MACMODESELECT_MASK; 3110 3111 if (port->phy_interface == PHY_INTERFACE_MODE_XAUI || 3112 port->phy_interface == PHY_INTERFACE_MODE_10GKR) 3113 ctrl3 |= MVPP22_XLG_CTRL3_MACMODESELECT_10G; 3114 else 3115 ctrl3 |= MVPP22_XLG_CTRL3_MACMODESELECT_GMAC; 3116 3117 writel(ctrl3, port->base + MVPP22_XLG_CTRL3_REG); 3118 } 3119 3120 if (port->gop_id == 0 && 3121 (port->phy_interface == PHY_INTERFACE_MODE_XAUI || 3122 port->phy_interface == PHY_INTERFACE_MODE_10GKR)) 3123 mvpp2_xlg_max_rx_size_set(port); 3124 else 3125 mvpp2_gmac_max_rx_size_set(port); 3126 } 3127 3128 /* Set hw internals when starting port */ 3129 static void mvpp2_start_dev(struct mvpp2_port *port) 3130 { 3131 int i; 3132 3133 mvpp2_txp_max_tx_size_set(port); 3134 3135 for (i = 0; i < port->nqvecs; i++) 3136 napi_enable(&port->qvecs[i].napi); 3137 3138 /* Enable interrupts on all CPUs */ 3139 mvpp2_interrupts_enable(port); 3140 3141 if (port->priv->hw_version == MVPP22) 3142 mvpp22_mode_reconfigure(port); 3143 3144 if (port->phylink) { 3145 phylink_start(port->phylink); 3146 } else { 3147 /* Phylink isn't used as of now for ACPI, so the MAC has to be 3148 * configured manually when the interface is started. This will 3149 * be removed as soon as the phylink ACPI support lands in. 3150 */ 3151 struct phylink_link_state state = { 3152 .interface = port->phy_interface, 3153 .link = 1, 3154 }; 3155 mvpp2_mac_config(port->dev, MLO_AN_INBAND, &state); 3156 } 3157 3158 netif_tx_start_all_queues(port->dev); 3159 } 3160 3161 /* Set hw internals when stopping port */ 3162 static void mvpp2_stop_dev(struct mvpp2_port *port) 3163 { 3164 int i; 3165 3166 /* Disable interrupts on all CPUs */ 3167 mvpp2_interrupts_disable(port); 3168 3169 for (i = 0; i < port->nqvecs; i++) 3170 napi_disable(&port->qvecs[i].napi); 3171 3172 if (port->phylink) 3173 phylink_stop(port->phylink); 3174 phy_power_off(port->comphy); 3175 } 3176 3177 static int mvpp2_check_ringparam_valid(struct net_device *dev, 3178 struct ethtool_ringparam *ring) 3179 { 3180 u16 new_rx_pending = ring->rx_pending; 3181 u16 new_tx_pending = ring->tx_pending; 3182 3183 if (ring->rx_pending == 0 || ring->tx_pending == 0) 3184 return -EINVAL; 3185 3186 if (ring->rx_pending > MVPP2_MAX_RXD_MAX) 3187 new_rx_pending = MVPP2_MAX_RXD_MAX; 3188 else if (!IS_ALIGNED(ring->rx_pending, 16)) 3189 new_rx_pending = ALIGN(ring->rx_pending, 16); 3190 3191 if (ring->tx_pending > MVPP2_MAX_TXD_MAX) 3192 new_tx_pending = MVPP2_MAX_TXD_MAX; 3193 else if (!IS_ALIGNED(ring->tx_pending, 32)) 3194 new_tx_pending = ALIGN(ring->tx_pending, 32); 3195 3196 /* The Tx ring size cannot be smaller than the minimum number of 3197 * descriptors needed for TSO. 3198 */ 3199 if (new_tx_pending < MVPP2_MAX_SKB_DESCS) 3200 new_tx_pending = ALIGN(MVPP2_MAX_SKB_DESCS, 32); 3201 3202 if (ring->rx_pending != new_rx_pending) { 3203 netdev_info(dev, "illegal Rx ring size value %d, round to %d\n", 3204 ring->rx_pending, new_rx_pending); 3205 ring->rx_pending = new_rx_pending; 3206 } 3207 3208 if (ring->tx_pending != new_tx_pending) { 3209 netdev_info(dev, "illegal Tx ring size value %d, round to %d\n", 3210 ring->tx_pending, new_tx_pending); 3211 ring->tx_pending = new_tx_pending; 3212 } 3213 3214 return 0; 3215 } 3216 3217 static void mvpp21_get_mac_address(struct mvpp2_port *port, unsigned char *addr) 3218 { 3219 u32 mac_addr_l, mac_addr_m, mac_addr_h; 3220 3221 mac_addr_l = readl(port->base + MVPP2_GMAC_CTRL_1_REG); 3222 mac_addr_m = readl(port->priv->lms_base + MVPP2_SRC_ADDR_MIDDLE); 3223 mac_addr_h = readl(port->priv->lms_base + MVPP2_SRC_ADDR_HIGH); 3224 addr[0] = (mac_addr_h >> 24) & 0xFF; 3225 addr[1] = (mac_addr_h >> 16) & 0xFF; 3226 addr[2] = (mac_addr_h >> 8) & 0xFF; 3227 addr[3] = mac_addr_h & 0xFF; 3228 addr[4] = mac_addr_m & 0xFF; 3229 addr[5] = (mac_addr_l >> MVPP2_GMAC_SA_LOW_OFFS) & 0xFF; 3230 } 3231 3232 static int mvpp2_irqs_init(struct mvpp2_port *port) 3233 { 3234 int err, i; 3235 3236 for (i = 0; i < port->nqvecs; i++) { 3237 struct mvpp2_queue_vector *qv = port->qvecs + i; 3238 3239 if (qv->type == MVPP2_QUEUE_VECTOR_PRIVATE) 3240 irq_set_status_flags(qv->irq, IRQ_NO_BALANCING); 3241 3242 err = request_irq(qv->irq, mvpp2_isr, 0, port->dev->name, qv); 3243 if (err) 3244 goto err; 3245 3246 if (qv->type == MVPP2_QUEUE_VECTOR_PRIVATE) 3247 irq_set_affinity_hint(qv->irq, 3248 cpumask_of(qv->sw_thread_id)); 3249 } 3250 3251 return 0; 3252 err: 3253 for (i = 0; i < port->nqvecs; i++) { 3254 struct mvpp2_queue_vector *qv = port->qvecs + i; 3255 3256 irq_set_affinity_hint(qv->irq, NULL); 3257 free_irq(qv->irq, qv); 3258 } 3259 3260 return err; 3261 } 3262 3263 static void mvpp2_irqs_deinit(struct mvpp2_port *port) 3264 { 3265 int i; 3266 3267 for (i = 0; i < port->nqvecs; i++) { 3268 struct mvpp2_queue_vector *qv = port->qvecs + i; 3269 3270 irq_set_affinity_hint(qv->irq, NULL); 3271 irq_clear_status_flags(qv->irq, IRQ_NO_BALANCING); 3272 free_irq(qv->irq, qv); 3273 } 3274 } 3275 3276 static int mvpp2_open(struct net_device *dev) 3277 { 3278 struct mvpp2_port *port = netdev_priv(dev); 3279 struct mvpp2 *priv = port->priv; 3280 unsigned char mac_bcast[ETH_ALEN] = { 3281 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }; 3282 bool valid = false; 3283 int err; 3284 3285 err = mvpp2_prs_mac_da_accept(port, mac_bcast, true); 3286 if (err) { 3287 netdev_err(dev, "mvpp2_prs_mac_da_accept BC failed\n"); 3288 return err; 3289 } 3290 err = mvpp2_prs_mac_da_accept(port, dev->dev_addr, true); 3291 if (err) { 3292 netdev_err(dev, "mvpp2_prs_mac_da_accept own addr failed\n"); 3293 return err; 3294 } 3295 err = mvpp2_prs_tag_mode_set(port->priv, port->id, MVPP2_TAG_TYPE_MH); 3296 if (err) { 3297 netdev_err(dev, "mvpp2_prs_tag_mode_set failed\n"); 3298 return err; 3299 } 3300 err = mvpp2_prs_def_flow(port); 3301 if (err) { 3302 netdev_err(dev, "mvpp2_prs_def_flow failed\n"); 3303 return err; 3304 } 3305 3306 /* Allocate the Rx/Tx queues */ 3307 err = mvpp2_setup_rxqs(port); 3308 if (err) { 3309 netdev_err(port->dev, "cannot allocate Rx queues\n"); 3310 return err; 3311 } 3312 3313 err = mvpp2_setup_txqs(port); 3314 if (err) { 3315 netdev_err(port->dev, "cannot allocate Tx queues\n"); 3316 goto err_cleanup_rxqs; 3317 } 3318 3319 err = mvpp2_irqs_init(port); 3320 if (err) { 3321 netdev_err(port->dev, "cannot init IRQs\n"); 3322 goto err_cleanup_txqs; 3323 } 3324 3325 /* Phylink isn't supported yet in ACPI mode */ 3326 if (port->of_node) { 3327 err = phylink_of_phy_connect(port->phylink, port->of_node, 0); 3328 if (err) { 3329 netdev_err(port->dev, "could not attach PHY (%d)\n", 3330 err); 3331 goto err_free_irq; 3332 } 3333 3334 valid = true; 3335 } 3336 3337 if (priv->hw_version == MVPP22 && port->link_irq && !port->phylink) { 3338 err = request_irq(port->link_irq, mvpp2_link_status_isr, 0, 3339 dev->name, port); 3340 if (err) { 3341 netdev_err(port->dev, "cannot request link IRQ %d\n", 3342 port->link_irq); 3343 goto err_free_irq; 3344 } 3345 3346 mvpp22_gop_setup_irq(port); 3347 3348 /* In default link is down */ 3349 netif_carrier_off(port->dev); 3350 3351 valid = true; 3352 } else { 3353 port->link_irq = 0; 3354 } 3355 3356 if (!valid) { 3357 netdev_err(port->dev, 3358 "invalid configuration: no dt or link IRQ"); 3359 goto err_free_irq; 3360 } 3361 3362 /* Unmask interrupts on all CPUs */ 3363 on_each_cpu(mvpp2_interrupts_unmask, port, 1); 3364 mvpp2_shared_interrupt_mask_unmask(port, false); 3365 3366 mvpp2_start_dev(port); 3367 3368 if (priv->hw_version == MVPP22) 3369 mvpp22_init_rss(port); 3370 3371 /* Start hardware statistics gathering */ 3372 queue_delayed_work(priv->stats_queue, &port->stats_work, 3373 MVPP2_MIB_COUNTERS_STATS_DELAY); 3374 3375 return 0; 3376 3377 err_free_irq: 3378 mvpp2_irqs_deinit(port); 3379 err_cleanup_txqs: 3380 mvpp2_cleanup_txqs(port); 3381 err_cleanup_rxqs: 3382 mvpp2_cleanup_rxqs(port); 3383 return err; 3384 } 3385 3386 static int mvpp2_stop(struct net_device *dev) 3387 { 3388 struct mvpp2_port *port = netdev_priv(dev); 3389 struct mvpp2_port_pcpu *port_pcpu; 3390 int cpu; 3391 3392 mvpp2_stop_dev(port); 3393 3394 /* Mask interrupts on all CPUs */ 3395 on_each_cpu(mvpp2_interrupts_mask, port, 1); 3396 mvpp2_shared_interrupt_mask_unmask(port, true); 3397 3398 if (port->phylink) 3399 phylink_disconnect_phy(port->phylink); 3400 if (port->link_irq) 3401 free_irq(port->link_irq, port); 3402 3403 mvpp2_irqs_deinit(port); 3404 if (!port->has_tx_irqs) { 3405 for_each_present_cpu(cpu) { 3406 port_pcpu = per_cpu_ptr(port->pcpu, cpu); 3407 3408 hrtimer_cancel(&port_pcpu->tx_done_timer); 3409 port_pcpu->timer_scheduled = false; 3410 tasklet_kill(&port_pcpu->tx_done_tasklet); 3411 } 3412 } 3413 mvpp2_cleanup_rxqs(port); 3414 mvpp2_cleanup_txqs(port); 3415 3416 cancel_delayed_work_sync(&port->stats_work); 3417 3418 return 0; 3419 } 3420 3421 static int mvpp2_prs_mac_da_accept_list(struct mvpp2_port *port, 3422 struct netdev_hw_addr_list *list) 3423 { 3424 struct netdev_hw_addr *ha; 3425 int ret; 3426 3427 netdev_hw_addr_list_for_each(ha, list) { 3428 ret = mvpp2_prs_mac_da_accept(port, ha->addr, true); 3429 if (ret) 3430 return ret; 3431 } 3432 3433 return 0; 3434 } 3435 3436 static void mvpp2_set_rx_promisc(struct mvpp2_port *port, bool enable) 3437 { 3438 if (!enable && (port->dev->features & NETIF_F_HW_VLAN_CTAG_FILTER)) 3439 mvpp2_prs_vid_enable_filtering(port); 3440 else 3441 mvpp2_prs_vid_disable_filtering(port); 3442 3443 mvpp2_prs_mac_promisc_set(port->priv, port->id, 3444 MVPP2_PRS_L2_UNI_CAST, enable); 3445 3446 mvpp2_prs_mac_promisc_set(port->priv, port->id, 3447 MVPP2_PRS_L2_MULTI_CAST, enable); 3448 } 3449 3450 static void mvpp2_set_rx_mode(struct net_device *dev) 3451 { 3452 struct mvpp2_port *port = netdev_priv(dev); 3453 3454 /* Clear the whole UC and MC list */ 3455 mvpp2_prs_mac_del_all(port); 3456 3457 if (dev->flags & IFF_PROMISC) { 3458 mvpp2_set_rx_promisc(port, true); 3459 return; 3460 } 3461 3462 mvpp2_set_rx_promisc(port, false); 3463 3464 if (netdev_uc_count(dev) > MVPP2_PRS_MAC_UC_FILT_MAX || 3465 mvpp2_prs_mac_da_accept_list(port, &dev->uc)) 3466 mvpp2_prs_mac_promisc_set(port->priv, port->id, 3467 MVPP2_PRS_L2_UNI_CAST, true); 3468 3469 if (dev->flags & IFF_ALLMULTI) { 3470 mvpp2_prs_mac_promisc_set(port->priv, port->id, 3471 MVPP2_PRS_L2_MULTI_CAST, true); 3472 return; 3473 } 3474 3475 if (netdev_mc_count(dev) > MVPP2_PRS_MAC_MC_FILT_MAX || 3476 mvpp2_prs_mac_da_accept_list(port, &dev->mc)) 3477 mvpp2_prs_mac_promisc_set(port->priv, port->id, 3478 MVPP2_PRS_L2_MULTI_CAST, true); 3479 } 3480 3481 static int mvpp2_set_mac_address(struct net_device *dev, void *p) 3482 { 3483 const struct sockaddr *addr = p; 3484 int err; 3485 3486 if (!is_valid_ether_addr(addr->sa_data)) 3487 return -EADDRNOTAVAIL; 3488 3489 err = mvpp2_prs_update_mac_da(dev, addr->sa_data); 3490 if (err) { 3491 /* Reconfigure parser accept the original MAC address */ 3492 mvpp2_prs_update_mac_da(dev, dev->dev_addr); 3493 netdev_err(dev, "failed to change MAC address\n"); 3494 } 3495 return err; 3496 } 3497 3498 static int mvpp2_change_mtu(struct net_device *dev, int mtu) 3499 { 3500 struct mvpp2_port *port = netdev_priv(dev); 3501 int err; 3502 3503 if (!IS_ALIGNED(MVPP2_RX_PKT_SIZE(mtu), 8)) { 3504 netdev_info(dev, "illegal MTU value %d, round to %d\n", mtu, 3505 ALIGN(MVPP2_RX_PKT_SIZE(mtu), 8)); 3506 mtu = ALIGN(MVPP2_RX_PKT_SIZE(mtu), 8); 3507 } 3508 3509 if (!netif_running(dev)) { 3510 err = mvpp2_bm_update_mtu(dev, mtu); 3511 if (!err) { 3512 port->pkt_size = MVPP2_RX_PKT_SIZE(mtu); 3513 return 0; 3514 } 3515 3516 /* Reconfigure BM to the original MTU */ 3517 err = mvpp2_bm_update_mtu(dev, dev->mtu); 3518 if (err) 3519 goto log_error; 3520 } 3521 3522 mvpp2_stop_dev(port); 3523 3524 err = mvpp2_bm_update_mtu(dev, mtu); 3525 if (!err) { 3526 port->pkt_size = MVPP2_RX_PKT_SIZE(mtu); 3527 goto out_start; 3528 } 3529 3530 /* Reconfigure BM to the original MTU */ 3531 err = mvpp2_bm_update_mtu(dev, dev->mtu); 3532 if (err) 3533 goto log_error; 3534 3535 out_start: 3536 mvpp2_start_dev(port); 3537 mvpp2_egress_enable(port); 3538 mvpp2_ingress_enable(port); 3539 3540 return 0; 3541 log_error: 3542 netdev_err(dev, "failed to change MTU\n"); 3543 return err; 3544 } 3545 3546 static void 3547 mvpp2_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats) 3548 { 3549 struct mvpp2_port *port = netdev_priv(dev); 3550 unsigned int start; 3551 int cpu; 3552 3553 for_each_possible_cpu(cpu) { 3554 struct mvpp2_pcpu_stats *cpu_stats; 3555 u64 rx_packets; 3556 u64 rx_bytes; 3557 u64 tx_packets; 3558 u64 tx_bytes; 3559 3560 cpu_stats = per_cpu_ptr(port->stats, cpu); 3561 do { 3562 start = u64_stats_fetch_begin_irq(&cpu_stats->syncp); 3563 rx_packets = cpu_stats->rx_packets; 3564 rx_bytes = cpu_stats->rx_bytes; 3565 tx_packets = cpu_stats->tx_packets; 3566 tx_bytes = cpu_stats->tx_bytes; 3567 } while (u64_stats_fetch_retry_irq(&cpu_stats->syncp, start)); 3568 3569 stats->rx_packets += rx_packets; 3570 stats->rx_bytes += rx_bytes; 3571 stats->tx_packets += tx_packets; 3572 stats->tx_bytes += tx_bytes; 3573 } 3574 3575 stats->rx_errors = dev->stats.rx_errors; 3576 stats->rx_dropped = dev->stats.rx_dropped; 3577 stats->tx_dropped = dev->stats.tx_dropped; 3578 } 3579 3580 static int mvpp2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) 3581 { 3582 struct mvpp2_port *port = netdev_priv(dev); 3583 3584 if (!port->phylink) 3585 return -ENOTSUPP; 3586 3587 return phylink_mii_ioctl(port->phylink, ifr, cmd); 3588 } 3589 3590 static int mvpp2_vlan_rx_add_vid(struct net_device *dev, __be16 proto, u16 vid) 3591 { 3592 struct mvpp2_port *port = netdev_priv(dev); 3593 int ret; 3594 3595 ret = mvpp2_prs_vid_entry_add(port, vid); 3596 if (ret) 3597 netdev_err(dev, "rx-vlan-filter offloading cannot accept more than %d VIDs per port\n", 3598 MVPP2_PRS_VLAN_FILT_MAX - 1); 3599 return ret; 3600 } 3601 3602 static int mvpp2_vlan_rx_kill_vid(struct net_device *dev, __be16 proto, u16 vid) 3603 { 3604 struct mvpp2_port *port = netdev_priv(dev); 3605 3606 mvpp2_prs_vid_entry_remove(port, vid); 3607 return 0; 3608 } 3609 3610 static int mvpp2_set_features(struct net_device *dev, 3611 netdev_features_t features) 3612 { 3613 netdev_features_t changed = dev->features ^ features; 3614 struct mvpp2_port *port = netdev_priv(dev); 3615 3616 if (changed & NETIF_F_HW_VLAN_CTAG_FILTER) { 3617 if (features & NETIF_F_HW_VLAN_CTAG_FILTER) { 3618 mvpp2_prs_vid_enable_filtering(port); 3619 } else { 3620 /* Invalidate all registered VID filters for this 3621 * port 3622 */ 3623 mvpp2_prs_vid_remove_all(port); 3624 3625 mvpp2_prs_vid_disable_filtering(port); 3626 } 3627 } 3628 3629 return 0; 3630 } 3631 3632 /* Ethtool methods */ 3633 3634 static int mvpp2_ethtool_nway_reset(struct net_device *dev) 3635 { 3636 struct mvpp2_port *port = netdev_priv(dev); 3637 3638 if (!port->phylink) 3639 return -ENOTSUPP; 3640 3641 return phylink_ethtool_nway_reset(port->phylink); 3642 } 3643 3644 /* Set interrupt coalescing for ethtools */ 3645 static int mvpp2_ethtool_set_coalesce(struct net_device *dev, 3646 struct ethtool_coalesce *c) 3647 { 3648 struct mvpp2_port *port = netdev_priv(dev); 3649 int queue; 3650 3651 for (queue = 0; queue < port->nrxqs; queue++) { 3652 struct mvpp2_rx_queue *rxq = port->rxqs[queue]; 3653 3654 rxq->time_coal = c->rx_coalesce_usecs; 3655 rxq->pkts_coal = c->rx_max_coalesced_frames; 3656 mvpp2_rx_pkts_coal_set(port, rxq); 3657 mvpp2_rx_time_coal_set(port, rxq); 3658 } 3659 3660 if (port->has_tx_irqs) { 3661 port->tx_time_coal = c->tx_coalesce_usecs; 3662 mvpp2_tx_time_coal_set(port); 3663 } 3664 3665 for (queue = 0; queue < port->ntxqs; queue++) { 3666 struct mvpp2_tx_queue *txq = port->txqs[queue]; 3667 3668 txq->done_pkts_coal = c->tx_max_coalesced_frames; 3669 3670 if (port->has_tx_irqs) 3671 mvpp2_tx_pkts_coal_set(port, txq); 3672 } 3673 3674 return 0; 3675 } 3676 3677 /* get coalescing for ethtools */ 3678 static int mvpp2_ethtool_get_coalesce(struct net_device *dev, 3679 struct ethtool_coalesce *c) 3680 { 3681 struct mvpp2_port *port = netdev_priv(dev); 3682 3683 c->rx_coalesce_usecs = port->rxqs[0]->time_coal; 3684 c->rx_max_coalesced_frames = port->rxqs[0]->pkts_coal; 3685 c->tx_max_coalesced_frames = port->txqs[0]->done_pkts_coal; 3686 c->tx_coalesce_usecs = port->tx_time_coal; 3687 return 0; 3688 } 3689 3690 static void mvpp2_ethtool_get_drvinfo(struct net_device *dev, 3691 struct ethtool_drvinfo *drvinfo) 3692 { 3693 strlcpy(drvinfo->driver, MVPP2_DRIVER_NAME, 3694 sizeof(drvinfo->driver)); 3695 strlcpy(drvinfo->version, MVPP2_DRIVER_VERSION, 3696 sizeof(drvinfo->version)); 3697 strlcpy(drvinfo->bus_info, dev_name(&dev->dev), 3698 sizeof(drvinfo->bus_info)); 3699 } 3700 3701 static void mvpp2_ethtool_get_ringparam(struct net_device *dev, 3702 struct ethtool_ringparam *ring) 3703 { 3704 struct mvpp2_port *port = netdev_priv(dev); 3705 3706 ring->rx_max_pending = MVPP2_MAX_RXD_MAX; 3707 ring->tx_max_pending = MVPP2_MAX_TXD_MAX; 3708 ring->rx_pending = port->rx_ring_size; 3709 ring->tx_pending = port->tx_ring_size; 3710 } 3711 3712 static int mvpp2_ethtool_set_ringparam(struct net_device *dev, 3713 struct ethtool_ringparam *ring) 3714 { 3715 struct mvpp2_port *port = netdev_priv(dev); 3716 u16 prev_rx_ring_size = port->rx_ring_size; 3717 u16 prev_tx_ring_size = port->tx_ring_size; 3718 int err; 3719 3720 err = mvpp2_check_ringparam_valid(dev, ring); 3721 if (err) 3722 return err; 3723 3724 if (!netif_running(dev)) { 3725 port->rx_ring_size = ring->rx_pending; 3726 port->tx_ring_size = ring->tx_pending; 3727 return 0; 3728 } 3729 3730 /* The interface is running, so we have to force a 3731 * reallocation of the queues 3732 */ 3733 mvpp2_stop_dev(port); 3734 mvpp2_cleanup_rxqs(port); 3735 mvpp2_cleanup_txqs(port); 3736 3737 port->rx_ring_size = ring->rx_pending; 3738 port->tx_ring_size = ring->tx_pending; 3739 3740 err = mvpp2_setup_rxqs(port); 3741 if (err) { 3742 /* Reallocate Rx queues with the original ring size */ 3743 port->rx_ring_size = prev_rx_ring_size; 3744 ring->rx_pending = prev_rx_ring_size; 3745 err = mvpp2_setup_rxqs(port); 3746 if (err) 3747 goto err_out; 3748 } 3749 err = mvpp2_setup_txqs(port); 3750 if (err) { 3751 /* Reallocate Tx queues with the original ring size */ 3752 port->tx_ring_size = prev_tx_ring_size; 3753 ring->tx_pending = prev_tx_ring_size; 3754 err = mvpp2_setup_txqs(port); 3755 if (err) 3756 goto err_clean_rxqs; 3757 } 3758 3759 mvpp2_start_dev(port); 3760 mvpp2_egress_enable(port); 3761 mvpp2_ingress_enable(port); 3762 3763 return 0; 3764 3765 err_clean_rxqs: 3766 mvpp2_cleanup_rxqs(port); 3767 err_out: 3768 netdev_err(dev, "failed to change ring parameters"); 3769 return err; 3770 } 3771 3772 static void mvpp2_ethtool_get_pause_param(struct net_device *dev, 3773 struct ethtool_pauseparam *pause) 3774 { 3775 struct mvpp2_port *port = netdev_priv(dev); 3776 3777 if (!port->phylink) 3778 return; 3779 3780 phylink_ethtool_get_pauseparam(port->phylink, pause); 3781 } 3782 3783 static int mvpp2_ethtool_set_pause_param(struct net_device *dev, 3784 struct ethtool_pauseparam *pause) 3785 { 3786 struct mvpp2_port *port = netdev_priv(dev); 3787 3788 if (!port->phylink) 3789 return -ENOTSUPP; 3790 3791 return phylink_ethtool_set_pauseparam(port->phylink, pause); 3792 } 3793 3794 static int mvpp2_ethtool_get_link_ksettings(struct net_device *dev, 3795 struct ethtool_link_ksettings *cmd) 3796 { 3797 struct mvpp2_port *port = netdev_priv(dev); 3798 3799 if (!port->phylink) 3800 return -ENOTSUPP; 3801 3802 return phylink_ethtool_ksettings_get(port->phylink, cmd); 3803 } 3804 3805 static int mvpp2_ethtool_set_link_ksettings(struct net_device *dev, 3806 const struct ethtool_link_ksettings *cmd) 3807 { 3808 struct mvpp2_port *port = netdev_priv(dev); 3809 3810 if (!port->phylink) 3811 return -ENOTSUPP; 3812 3813 return phylink_ethtool_ksettings_set(port->phylink, cmd); 3814 } 3815 3816 /* Device ops */ 3817 3818 static const struct net_device_ops mvpp2_netdev_ops = { 3819 .ndo_open = mvpp2_open, 3820 .ndo_stop = mvpp2_stop, 3821 .ndo_start_xmit = mvpp2_tx, 3822 .ndo_set_rx_mode = mvpp2_set_rx_mode, 3823 .ndo_set_mac_address = mvpp2_set_mac_address, 3824 .ndo_change_mtu = mvpp2_change_mtu, 3825 .ndo_get_stats64 = mvpp2_get_stats64, 3826 .ndo_do_ioctl = mvpp2_ioctl, 3827 .ndo_vlan_rx_add_vid = mvpp2_vlan_rx_add_vid, 3828 .ndo_vlan_rx_kill_vid = mvpp2_vlan_rx_kill_vid, 3829 .ndo_set_features = mvpp2_set_features, 3830 }; 3831 3832 static const struct ethtool_ops mvpp2_eth_tool_ops = { 3833 .nway_reset = mvpp2_ethtool_nway_reset, 3834 .get_link = ethtool_op_get_link, 3835 .set_coalesce = mvpp2_ethtool_set_coalesce, 3836 .get_coalesce = mvpp2_ethtool_get_coalesce, 3837 .get_drvinfo = mvpp2_ethtool_get_drvinfo, 3838 .get_ringparam = mvpp2_ethtool_get_ringparam, 3839 .set_ringparam = mvpp2_ethtool_set_ringparam, 3840 .get_strings = mvpp2_ethtool_get_strings, 3841 .get_ethtool_stats = mvpp2_ethtool_get_stats, 3842 .get_sset_count = mvpp2_ethtool_get_sset_count, 3843 .get_pauseparam = mvpp2_ethtool_get_pause_param, 3844 .set_pauseparam = mvpp2_ethtool_set_pause_param, 3845 .get_link_ksettings = mvpp2_ethtool_get_link_ksettings, 3846 .set_link_ksettings = mvpp2_ethtool_set_link_ksettings, 3847 }; 3848 3849 /* Used for PPv2.1, or PPv2.2 with the old Device Tree binding that 3850 * had a single IRQ defined per-port. 3851 */ 3852 static int mvpp2_simple_queue_vectors_init(struct mvpp2_port *port, 3853 struct device_node *port_node) 3854 { 3855 struct mvpp2_queue_vector *v = &port->qvecs[0]; 3856 3857 v->first_rxq = 0; 3858 v->nrxqs = port->nrxqs; 3859 v->type = MVPP2_QUEUE_VECTOR_SHARED; 3860 v->sw_thread_id = 0; 3861 v->sw_thread_mask = *cpumask_bits(cpu_online_mask); 3862 v->port = port; 3863 v->irq = irq_of_parse_and_map(port_node, 0); 3864 if (v->irq <= 0) 3865 return -EINVAL; 3866 netif_napi_add(port->dev, &v->napi, mvpp2_poll, 3867 NAPI_POLL_WEIGHT); 3868 3869 port->nqvecs = 1; 3870 3871 return 0; 3872 } 3873 3874 static int mvpp2_multi_queue_vectors_init(struct mvpp2_port *port, 3875 struct device_node *port_node) 3876 { 3877 struct mvpp2_queue_vector *v; 3878 int i, ret; 3879 3880 port->nqvecs = num_possible_cpus(); 3881 if (queue_mode == MVPP2_QDIST_SINGLE_MODE) 3882 port->nqvecs += 1; 3883 3884 for (i = 0; i < port->nqvecs; i++) { 3885 char irqname[16]; 3886 3887 v = port->qvecs + i; 3888 3889 v->port = port; 3890 v->type = MVPP2_QUEUE_VECTOR_PRIVATE; 3891 v->sw_thread_id = i; 3892 v->sw_thread_mask = BIT(i); 3893 3894 snprintf(irqname, sizeof(irqname), "tx-cpu%d", i); 3895 3896 if (queue_mode == MVPP2_QDIST_MULTI_MODE) { 3897 v->first_rxq = i * MVPP2_DEFAULT_RXQ; 3898 v->nrxqs = MVPP2_DEFAULT_RXQ; 3899 } else if (queue_mode == MVPP2_QDIST_SINGLE_MODE && 3900 i == (port->nqvecs - 1)) { 3901 v->first_rxq = 0; 3902 v->nrxqs = port->nrxqs; 3903 v->type = MVPP2_QUEUE_VECTOR_SHARED; 3904 strncpy(irqname, "rx-shared", sizeof(irqname)); 3905 } 3906 3907 if (port_node) 3908 v->irq = of_irq_get_byname(port_node, irqname); 3909 else 3910 v->irq = fwnode_irq_get(port->fwnode, i); 3911 if (v->irq <= 0) { 3912 ret = -EINVAL; 3913 goto err; 3914 } 3915 3916 netif_napi_add(port->dev, &v->napi, mvpp2_poll, 3917 NAPI_POLL_WEIGHT); 3918 } 3919 3920 return 0; 3921 3922 err: 3923 for (i = 0; i < port->nqvecs; i++) 3924 irq_dispose_mapping(port->qvecs[i].irq); 3925 return ret; 3926 } 3927 3928 static int mvpp2_queue_vectors_init(struct mvpp2_port *port, 3929 struct device_node *port_node) 3930 { 3931 if (port->has_tx_irqs) 3932 return mvpp2_multi_queue_vectors_init(port, port_node); 3933 else 3934 return mvpp2_simple_queue_vectors_init(port, port_node); 3935 } 3936 3937 static void mvpp2_queue_vectors_deinit(struct mvpp2_port *port) 3938 { 3939 int i; 3940 3941 for (i = 0; i < port->nqvecs; i++) 3942 irq_dispose_mapping(port->qvecs[i].irq); 3943 } 3944 3945 /* Configure Rx queue group interrupt for this port */ 3946 static void mvpp2_rx_irqs_setup(struct mvpp2_port *port) 3947 { 3948 struct mvpp2 *priv = port->priv; 3949 u32 val; 3950 int i; 3951 3952 if (priv->hw_version == MVPP21) { 3953 mvpp2_write(priv, MVPP21_ISR_RXQ_GROUP_REG(port->id), 3954 port->nrxqs); 3955 return; 3956 } 3957 3958 /* Handle the more complicated PPv2.2 case */ 3959 for (i = 0; i < port->nqvecs; i++) { 3960 struct mvpp2_queue_vector *qv = port->qvecs + i; 3961 3962 if (!qv->nrxqs) 3963 continue; 3964 3965 val = qv->sw_thread_id; 3966 val |= port->id << MVPP22_ISR_RXQ_GROUP_INDEX_GROUP_OFFSET; 3967 mvpp2_write(priv, MVPP22_ISR_RXQ_GROUP_INDEX_REG, val); 3968 3969 val = qv->first_rxq; 3970 val |= qv->nrxqs << MVPP22_ISR_RXQ_SUB_GROUP_SIZE_OFFSET; 3971 mvpp2_write(priv, MVPP22_ISR_RXQ_SUB_GROUP_CONFIG_REG, val); 3972 } 3973 } 3974 3975 /* Initialize port HW */ 3976 static int mvpp2_port_init(struct mvpp2_port *port) 3977 { 3978 struct device *dev = port->dev->dev.parent; 3979 struct mvpp2 *priv = port->priv; 3980 struct mvpp2_txq_pcpu *txq_pcpu; 3981 int queue, cpu, err; 3982 3983 /* Checks for hardware constraints */ 3984 if (port->first_rxq + port->nrxqs > 3985 MVPP2_MAX_PORTS * priv->max_port_rxqs) 3986 return -EINVAL; 3987 3988 if (port->nrxqs % 4 || (port->nrxqs > priv->max_port_rxqs) || 3989 (port->ntxqs > MVPP2_MAX_TXQ)) 3990 return -EINVAL; 3991 3992 /* Disable port */ 3993 mvpp2_egress_disable(port); 3994 mvpp2_port_disable(port); 3995 3996 port->tx_time_coal = MVPP2_TXDONE_COAL_USEC; 3997 3998 port->txqs = devm_kcalloc(dev, port->ntxqs, sizeof(*port->txqs), 3999 GFP_KERNEL); 4000 if (!port->txqs) 4001 return -ENOMEM; 4002 4003 /* Associate physical Tx queues to this port and initialize. 4004 * The mapping is predefined. 4005 */ 4006 for (queue = 0; queue < port->ntxqs; queue++) { 4007 int queue_phy_id = mvpp2_txq_phys(port->id, queue); 4008 struct mvpp2_tx_queue *txq; 4009 4010 txq = devm_kzalloc(dev, sizeof(*txq), GFP_KERNEL); 4011 if (!txq) { 4012 err = -ENOMEM; 4013 goto err_free_percpu; 4014 } 4015 4016 txq->pcpu = alloc_percpu(struct mvpp2_txq_pcpu); 4017 if (!txq->pcpu) { 4018 err = -ENOMEM; 4019 goto err_free_percpu; 4020 } 4021 4022 txq->id = queue_phy_id; 4023 txq->log_id = queue; 4024 txq->done_pkts_coal = MVPP2_TXDONE_COAL_PKTS_THRESH; 4025 for_each_present_cpu(cpu) { 4026 txq_pcpu = per_cpu_ptr(txq->pcpu, cpu); 4027 txq_pcpu->cpu = cpu; 4028 } 4029 4030 port->txqs[queue] = txq; 4031 } 4032 4033 port->rxqs = devm_kcalloc(dev, port->nrxqs, sizeof(*port->rxqs), 4034 GFP_KERNEL); 4035 if (!port->rxqs) { 4036 err = -ENOMEM; 4037 goto err_free_percpu; 4038 } 4039 4040 /* Allocate and initialize Rx queue for this port */ 4041 for (queue = 0; queue < port->nrxqs; queue++) { 4042 struct mvpp2_rx_queue *rxq; 4043 4044 /* Map physical Rx queue to port's logical Rx queue */ 4045 rxq = devm_kzalloc(dev, sizeof(*rxq), GFP_KERNEL); 4046 if (!rxq) { 4047 err = -ENOMEM; 4048 goto err_free_percpu; 4049 } 4050 /* Map this Rx queue to a physical queue */ 4051 rxq->id = port->first_rxq + queue; 4052 rxq->port = port->id; 4053 rxq->logic_rxq = queue; 4054 4055 port->rxqs[queue] = rxq; 4056 } 4057 4058 mvpp2_rx_irqs_setup(port); 4059 4060 /* Create Rx descriptor rings */ 4061 for (queue = 0; queue < port->nrxqs; queue++) { 4062 struct mvpp2_rx_queue *rxq = port->rxqs[queue]; 4063 4064 rxq->size = port->rx_ring_size; 4065 rxq->pkts_coal = MVPP2_RX_COAL_PKTS; 4066 rxq->time_coal = MVPP2_RX_COAL_USEC; 4067 } 4068 4069 mvpp2_ingress_disable(port); 4070 4071 /* Port default configuration */ 4072 mvpp2_defaults_set(port); 4073 4074 /* Port's classifier configuration */ 4075 mvpp2_cls_oversize_rxq_set(port); 4076 mvpp2_cls_port_config(port); 4077 4078 /* Provide an initial Rx packet size */ 4079 port->pkt_size = MVPP2_RX_PKT_SIZE(port->dev->mtu); 4080 4081 /* Initialize pools for swf */ 4082 err = mvpp2_swf_bm_pool_init(port); 4083 if (err) 4084 goto err_free_percpu; 4085 4086 return 0; 4087 4088 err_free_percpu: 4089 for (queue = 0; queue < port->ntxqs; queue++) { 4090 if (!port->txqs[queue]) 4091 continue; 4092 free_percpu(port->txqs[queue]->pcpu); 4093 } 4094 return err; 4095 } 4096 4097 /* Checks if the port DT description has the TX interrupts 4098 * described. On PPv2.1, there are no such interrupts. On PPv2.2, 4099 * there are available, but we need to keep support for old DTs. 4100 */ 4101 static bool mvpp2_port_has_tx_irqs(struct mvpp2 *priv, 4102 struct device_node *port_node) 4103 { 4104 char *irqs[5] = { "rx-shared", "tx-cpu0", "tx-cpu1", 4105 "tx-cpu2", "tx-cpu3" }; 4106 int ret, i; 4107 4108 if (priv->hw_version == MVPP21) 4109 return false; 4110 4111 for (i = 0; i < 5; i++) { 4112 ret = of_property_match_string(port_node, "interrupt-names", 4113 irqs[i]); 4114 if (ret < 0) 4115 return false; 4116 } 4117 4118 return true; 4119 } 4120 4121 static void mvpp2_port_copy_mac_addr(struct net_device *dev, struct mvpp2 *priv, 4122 struct fwnode_handle *fwnode, 4123 char **mac_from) 4124 { 4125 struct mvpp2_port *port = netdev_priv(dev); 4126 char hw_mac_addr[ETH_ALEN] = {0}; 4127 char fw_mac_addr[ETH_ALEN]; 4128 4129 if (fwnode_get_mac_address(fwnode, fw_mac_addr, ETH_ALEN)) { 4130 *mac_from = "firmware node"; 4131 ether_addr_copy(dev->dev_addr, fw_mac_addr); 4132 return; 4133 } 4134 4135 if (priv->hw_version == MVPP21) { 4136 mvpp21_get_mac_address(port, hw_mac_addr); 4137 if (is_valid_ether_addr(hw_mac_addr)) { 4138 *mac_from = "hardware"; 4139 ether_addr_copy(dev->dev_addr, hw_mac_addr); 4140 return; 4141 } 4142 } 4143 4144 *mac_from = "random"; 4145 eth_hw_addr_random(dev); 4146 } 4147 4148 static void mvpp2_phylink_validate(struct net_device *dev, 4149 unsigned long *supported, 4150 struct phylink_link_state *state) 4151 { 4152 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, }; 4153 4154 phylink_set(mask, Autoneg); 4155 phylink_set_port_modes(mask); 4156 phylink_set(mask, Pause); 4157 phylink_set(mask, Asym_Pause); 4158 4159 switch (state->interface) { 4160 case PHY_INTERFACE_MODE_10GKR: 4161 phylink_set(mask, 10000baseCR_Full); 4162 phylink_set(mask, 10000baseSR_Full); 4163 phylink_set(mask, 10000baseLR_Full); 4164 phylink_set(mask, 10000baseLRM_Full); 4165 phylink_set(mask, 10000baseER_Full); 4166 phylink_set(mask, 10000baseKR_Full); 4167 /* Fall-through */ 4168 default: 4169 phylink_set(mask, 10baseT_Half); 4170 phylink_set(mask, 10baseT_Full); 4171 phylink_set(mask, 100baseT_Half); 4172 phylink_set(mask, 100baseT_Full); 4173 phylink_set(mask, 10000baseT_Full); 4174 /* Fall-through */ 4175 case PHY_INTERFACE_MODE_1000BASEX: 4176 case PHY_INTERFACE_MODE_2500BASEX: 4177 phylink_set(mask, 1000baseT_Full); 4178 phylink_set(mask, 1000baseX_Full); 4179 phylink_set(mask, 2500baseX_Full); 4180 } 4181 4182 bitmap_and(supported, supported, mask, __ETHTOOL_LINK_MODE_MASK_NBITS); 4183 bitmap_and(state->advertising, state->advertising, mask, 4184 __ETHTOOL_LINK_MODE_MASK_NBITS); 4185 } 4186 4187 static void mvpp22_xlg_link_state(struct mvpp2_port *port, 4188 struct phylink_link_state *state) 4189 { 4190 u32 val; 4191 4192 state->speed = SPEED_10000; 4193 state->duplex = 1; 4194 state->an_complete = 1; 4195 4196 val = readl(port->base + MVPP22_XLG_STATUS); 4197 state->link = !!(val & MVPP22_XLG_STATUS_LINK_UP); 4198 4199 state->pause = 0; 4200 val = readl(port->base + MVPP22_XLG_CTRL0_REG); 4201 if (val & MVPP22_XLG_CTRL0_TX_FLOW_CTRL_EN) 4202 state->pause |= MLO_PAUSE_TX; 4203 if (val & MVPP22_XLG_CTRL0_RX_FLOW_CTRL_EN) 4204 state->pause |= MLO_PAUSE_RX; 4205 } 4206 4207 static void mvpp2_gmac_link_state(struct mvpp2_port *port, 4208 struct phylink_link_state *state) 4209 { 4210 u32 val; 4211 4212 val = readl(port->base + MVPP2_GMAC_STATUS0); 4213 4214 state->an_complete = !!(val & MVPP2_GMAC_STATUS0_AN_COMPLETE); 4215 state->link = !!(val & MVPP2_GMAC_STATUS0_LINK_UP); 4216 state->duplex = !!(val & MVPP2_GMAC_STATUS0_FULL_DUPLEX); 4217 4218 switch (port->phy_interface) { 4219 case PHY_INTERFACE_MODE_1000BASEX: 4220 state->speed = SPEED_1000; 4221 break; 4222 case PHY_INTERFACE_MODE_2500BASEX: 4223 state->speed = SPEED_2500; 4224 break; 4225 default: 4226 if (val & MVPP2_GMAC_STATUS0_GMII_SPEED) 4227 state->speed = SPEED_1000; 4228 else if (val & MVPP2_GMAC_STATUS0_MII_SPEED) 4229 state->speed = SPEED_100; 4230 else 4231 state->speed = SPEED_10; 4232 } 4233 4234 state->pause = 0; 4235 if (val & MVPP2_GMAC_STATUS0_RX_PAUSE) 4236 state->pause |= MLO_PAUSE_RX; 4237 if (val & MVPP2_GMAC_STATUS0_TX_PAUSE) 4238 state->pause |= MLO_PAUSE_TX; 4239 } 4240 4241 static int mvpp2_phylink_mac_link_state(struct net_device *dev, 4242 struct phylink_link_state *state) 4243 { 4244 struct mvpp2_port *port = netdev_priv(dev); 4245 4246 if (port->priv->hw_version == MVPP22 && port->gop_id == 0) { 4247 u32 mode = readl(port->base + MVPP22_XLG_CTRL3_REG); 4248 mode &= MVPP22_XLG_CTRL3_MACMODESELECT_MASK; 4249 4250 if (mode == MVPP22_XLG_CTRL3_MACMODESELECT_10G) { 4251 mvpp22_xlg_link_state(port, state); 4252 return 1; 4253 } 4254 } 4255 4256 mvpp2_gmac_link_state(port, state); 4257 return 1; 4258 } 4259 4260 static void mvpp2_mac_an_restart(struct net_device *dev) 4261 { 4262 struct mvpp2_port *port = netdev_priv(dev); 4263 u32 val; 4264 4265 if (port->phy_interface != PHY_INTERFACE_MODE_SGMII) 4266 return; 4267 4268 val = readl(port->base + MVPP2_GMAC_AUTONEG_CONFIG); 4269 /* The RESTART_AN bit is cleared by the h/w after restarting the AN 4270 * process. 4271 */ 4272 val |= MVPP2_GMAC_IN_BAND_RESTART_AN | MVPP2_GMAC_IN_BAND_AUTONEG; 4273 writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG); 4274 } 4275 4276 static void mvpp2_xlg_config(struct mvpp2_port *port, unsigned int mode, 4277 const struct phylink_link_state *state) 4278 { 4279 u32 ctrl0, ctrl4; 4280 4281 ctrl0 = readl(port->base + MVPP22_XLG_CTRL0_REG); 4282 ctrl4 = readl(port->base + MVPP22_XLG_CTRL4_REG); 4283 4284 if (state->pause & MLO_PAUSE_TX) 4285 ctrl0 |= MVPP22_XLG_CTRL0_TX_FLOW_CTRL_EN; 4286 if (state->pause & MLO_PAUSE_RX) 4287 ctrl0 |= MVPP22_XLG_CTRL0_RX_FLOW_CTRL_EN; 4288 4289 ctrl4 &= ~MVPP22_XLG_CTRL4_MACMODSELECT_GMAC; 4290 ctrl4 |= MVPP22_XLG_CTRL4_FWD_FC | MVPP22_XLG_CTRL4_FWD_PFC | 4291 MVPP22_XLG_CTRL4_EN_IDLE_CHECK; 4292 4293 writel(ctrl0, port->base + MVPP22_XLG_CTRL0_REG); 4294 writel(ctrl4, port->base + MVPP22_XLG_CTRL4_REG); 4295 } 4296 4297 static void mvpp2_gmac_config(struct mvpp2_port *port, unsigned int mode, 4298 const struct phylink_link_state *state) 4299 { 4300 u32 an, ctrl0, ctrl2, ctrl4; 4301 4302 an = readl(port->base + MVPP2_GMAC_AUTONEG_CONFIG); 4303 ctrl0 = readl(port->base + MVPP2_GMAC_CTRL_0_REG); 4304 ctrl2 = readl(port->base + MVPP2_GMAC_CTRL_2_REG); 4305 ctrl4 = readl(port->base + MVPP22_GMAC_CTRL_4_REG); 4306 4307 /* Force link down */ 4308 an &= ~MVPP2_GMAC_FORCE_LINK_PASS; 4309 an |= MVPP2_GMAC_FORCE_LINK_DOWN; 4310 writel(an, port->base + MVPP2_GMAC_AUTONEG_CONFIG); 4311 4312 /* Set the GMAC in a reset state */ 4313 ctrl2 |= MVPP2_GMAC_PORT_RESET_MASK; 4314 writel(ctrl2, port->base + MVPP2_GMAC_CTRL_2_REG); 4315 4316 an &= ~(MVPP2_GMAC_CONFIG_MII_SPEED | MVPP2_GMAC_CONFIG_GMII_SPEED | 4317 MVPP2_GMAC_AN_SPEED_EN | MVPP2_GMAC_FC_ADV_EN | 4318 MVPP2_GMAC_FC_ADV_ASM_EN | MVPP2_GMAC_FLOW_CTRL_AUTONEG | 4319 MVPP2_GMAC_CONFIG_FULL_DUPLEX | MVPP2_GMAC_AN_DUPLEX_EN | 4320 MVPP2_GMAC_FORCE_LINK_DOWN); 4321 ctrl0 &= ~MVPP2_GMAC_PORT_TYPE_MASK; 4322 ctrl2 &= ~(MVPP2_GMAC_PORT_RESET_MASK | MVPP2_GMAC_PCS_ENABLE_MASK); 4323 4324 if (state->interface == PHY_INTERFACE_MODE_1000BASEX || 4325 state->interface == PHY_INTERFACE_MODE_2500BASEX) { 4326 /* 1000BaseX and 2500BaseX ports cannot negotiate speed nor can 4327 * they negotiate duplex: they are always operating with a fixed 4328 * speed of 1000/2500Mbps in full duplex, so force 1000/2500 4329 * speed and full duplex here. 4330 */ 4331 ctrl0 |= MVPP2_GMAC_PORT_TYPE_MASK; 4332 an |= MVPP2_GMAC_CONFIG_GMII_SPEED | 4333 MVPP2_GMAC_CONFIG_FULL_DUPLEX; 4334 } else if (!phy_interface_mode_is_rgmii(state->interface)) { 4335 an |= MVPP2_GMAC_AN_SPEED_EN | MVPP2_GMAC_FLOW_CTRL_AUTONEG; 4336 } 4337 4338 if (state->duplex) 4339 an |= MVPP2_GMAC_CONFIG_FULL_DUPLEX; 4340 if (phylink_test(state->advertising, Pause)) 4341 an |= MVPP2_GMAC_FC_ADV_EN; 4342 if (phylink_test(state->advertising, Asym_Pause)) 4343 an |= MVPP2_GMAC_FC_ADV_ASM_EN; 4344 4345 if (state->interface == PHY_INTERFACE_MODE_SGMII || 4346 state->interface == PHY_INTERFACE_MODE_1000BASEX || 4347 state->interface == PHY_INTERFACE_MODE_2500BASEX) { 4348 an |= MVPP2_GMAC_IN_BAND_AUTONEG; 4349 ctrl2 |= MVPP2_GMAC_INBAND_AN_MASK | MVPP2_GMAC_PCS_ENABLE_MASK; 4350 4351 ctrl4 &= ~(MVPP22_CTRL4_EXT_PIN_GMII_SEL | 4352 MVPP22_CTRL4_RX_FC_EN | MVPP22_CTRL4_TX_FC_EN); 4353 ctrl4 |= MVPP22_CTRL4_SYNC_BYPASS_DIS | 4354 MVPP22_CTRL4_DP_CLK_SEL | 4355 MVPP22_CTRL4_QSGMII_BYPASS_ACTIVE; 4356 4357 if (state->pause & MLO_PAUSE_TX) 4358 ctrl4 |= MVPP22_CTRL4_TX_FC_EN; 4359 if (state->pause & MLO_PAUSE_RX) 4360 ctrl4 |= MVPP22_CTRL4_RX_FC_EN; 4361 } else if (phy_interface_mode_is_rgmii(state->interface)) { 4362 an |= MVPP2_GMAC_IN_BAND_AUTONEG_BYPASS; 4363 4364 if (state->speed == SPEED_1000) 4365 an |= MVPP2_GMAC_CONFIG_GMII_SPEED; 4366 else if (state->speed == SPEED_100) 4367 an |= MVPP2_GMAC_CONFIG_MII_SPEED; 4368 4369 ctrl4 &= ~MVPP22_CTRL4_DP_CLK_SEL; 4370 ctrl4 |= MVPP22_CTRL4_EXT_PIN_GMII_SEL | 4371 MVPP22_CTRL4_SYNC_BYPASS_DIS | 4372 MVPP22_CTRL4_QSGMII_BYPASS_ACTIVE; 4373 } 4374 4375 writel(ctrl0, port->base + MVPP2_GMAC_CTRL_0_REG); 4376 writel(ctrl2, port->base + MVPP2_GMAC_CTRL_2_REG); 4377 writel(ctrl4, port->base + MVPP22_GMAC_CTRL_4_REG); 4378 writel(an, port->base + MVPP2_GMAC_AUTONEG_CONFIG); 4379 } 4380 4381 static void mvpp2_mac_config(struct net_device *dev, unsigned int mode, 4382 const struct phylink_link_state *state) 4383 { 4384 struct mvpp2_port *port = netdev_priv(dev); 4385 4386 /* Check for invalid configuration */ 4387 if (state->interface == PHY_INTERFACE_MODE_10GKR && port->gop_id != 0) { 4388 netdev_err(dev, "Invalid mode on %s\n", dev->name); 4389 return; 4390 } 4391 4392 netif_tx_stop_all_queues(port->dev); 4393 if (!port->has_phy) 4394 netif_carrier_off(port->dev); 4395 4396 /* Make sure the port is disabled when reconfiguring the mode */ 4397 mvpp2_port_disable(port); 4398 4399 if (port->priv->hw_version == MVPP22 && 4400 port->phy_interface != state->interface) { 4401 port->phy_interface = state->interface; 4402 4403 /* Reconfigure the serdes lanes */ 4404 phy_power_off(port->comphy); 4405 mvpp22_mode_reconfigure(port); 4406 } 4407 4408 /* mac (re)configuration */ 4409 if (state->interface == PHY_INTERFACE_MODE_10GKR) 4410 mvpp2_xlg_config(port, mode, state); 4411 else if (phy_interface_mode_is_rgmii(state->interface) || 4412 state->interface == PHY_INTERFACE_MODE_SGMII || 4413 state->interface == PHY_INTERFACE_MODE_1000BASEX || 4414 state->interface == PHY_INTERFACE_MODE_2500BASEX) 4415 mvpp2_gmac_config(port, mode, state); 4416 4417 if (port->priv->hw_version == MVPP21 && port->flags & MVPP2_F_LOOPBACK) 4418 mvpp2_port_loopback_set(port, state); 4419 4420 /* If the port already was up, make sure it's still in the same state */ 4421 if (state->link || !port->has_phy) { 4422 mvpp2_port_enable(port); 4423 4424 mvpp2_egress_enable(port); 4425 mvpp2_ingress_enable(port); 4426 if (!port->has_phy) 4427 netif_carrier_on(dev); 4428 netif_tx_wake_all_queues(dev); 4429 } 4430 } 4431 4432 static void mvpp2_mac_link_up(struct net_device *dev, unsigned int mode, 4433 phy_interface_t interface, struct phy_device *phy) 4434 { 4435 struct mvpp2_port *port = netdev_priv(dev); 4436 u32 val; 4437 4438 if (!phylink_autoneg_inband(mode) && 4439 interface != PHY_INTERFACE_MODE_10GKR) { 4440 val = readl(port->base + MVPP2_GMAC_AUTONEG_CONFIG); 4441 val &= ~MVPP2_GMAC_FORCE_LINK_DOWN; 4442 if (phy_interface_mode_is_rgmii(interface)) 4443 val |= MVPP2_GMAC_FORCE_LINK_PASS; 4444 writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG); 4445 } 4446 4447 mvpp2_port_enable(port); 4448 4449 mvpp2_egress_enable(port); 4450 mvpp2_ingress_enable(port); 4451 netif_tx_wake_all_queues(dev); 4452 } 4453 4454 static void mvpp2_mac_link_down(struct net_device *dev, unsigned int mode, 4455 phy_interface_t interface) 4456 { 4457 struct mvpp2_port *port = netdev_priv(dev); 4458 u32 val; 4459 4460 if (!phylink_autoneg_inband(mode) && 4461 interface != PHY_INTERFACE_MODE_10GKR) { 4462 val = readl(port->base + MVPP2_GMAC_AUTONEG_CONFIG); 4463 val &= ~MVPP2_GMAC_FORCE_LINK_PASS; 4464 val |= MVPP2_GMAC_FORCE_LINK_DOWN; 4465 writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG); 4466 } 4467 4468 netif_tx_stop_all_queues(dev); 4469 mvpp2_egress_disable(port); 4470 mvpp2_ingress_disable(port); 4471 4472 /* When using link interrupts to notify phylink of a MAC state change, 4473 * we do not want the port to be disabled (we want to receive further 4474 * interrupts, to be notified when the port will have a link later). 4475 */ 4476 if (!port->has_phy) 4477 return; 4478 4479 mvpp2_port_disable(port); 4480 } 4481 4482 static const struct phylink_mac_ops mvpp2_phylink_ops = { 4483 .validate = mvpp2_phylink_validate, 4484 .mac_link_state = mvpp2_phylink_mac_link_state, 4485 .mac_an_restart = mvpp2_mac_an_restart, 4486 .mac_config = mvpp2_mac_config, 4487 .mac_link_up = mvpp2_mac_link_up, 4488 .mac_link_down = mvpp2_mac_link_down, 4489 }; 4490 4491 /* Ports initialization */ 4492 static int mvpp2_port_probe(struct platform_device *pdev, 4493 struct fwnode_handle *port_fwnode, 4494 struct mvpp2 *priv) 4495 { 4496 struct phy *comphy = NULL; 4497 struct mvpp2_port *port; 4498 struct mvpp2_port_pcpu *port_pcpu; 4499 struct device_node *port_node = to_of_node(port_fwnode); 4500 struct net_device *dev; 4501 struct resource *res; 4502 struct phylink *phylink; 4503 char *mac_from = ""; 4504 unsigned int ntxqs, nrxqs; 4505 bool has_tx_irqs; 4506 u32 id; 4507 int features; 4508 int phy_mode; 4509 int err, i, cpu; 4510 4511 if (port_node) { 4512 has_tx_irqs = mvpp2_port_has_tx_irqs(priv, port_node); 4513 } else { 4514 has_tx_irqs = true; 4515 queue_mode = MVPP2_QDIST_MULTI_MODE; 4516 } 4517 4518 if (!has_tx_irqs) 4519 queue_mode = MVPP2_QDIST_SINGLE_MODE; 4520 4521 ntxqs = MVPP2_MAX_TXQ; 4522 if (priv->hw_version == MVPP22 && queue_mode == MVPP2_QDIST_MULTI_MODE) 4523 nrxqs = MVPP2_DEFAULT_RXQ * num_possible_cpus(); 4524 else 4525 nrxqs = MVPP2_DEFAULT_RXQ; 4526 4527 dev = alloc_etherdev_mqs(sizeof(*port), ntxqs, nrxqs); 4528 if (!dev) 4529 return -ENOMEM; 4530 4531 phy_mode = fwnode_get_phy_mode(port_fwnode); 4532 if (phy_mode < 0) { 4533 dev_err(&pdev->dev, "incorrect phy mode\n"); 4534 err = phy_mode; 4535 goto err_free_netdev; 4536 } 4537 4538 if (port_node) { 4539 comphy = devm_of_phy_get(&pdev->dev, port_node, NULL); 4540 if (IS_ERR(comphy)) { 4541 if (PTR_ERR(comphy) == -EPROBE_DEFER) { 4542 err = -EPROBE_DEFER; 4543 goto err_free_netdev; 4544 } 4545 comphy = NULL; 4546 } 4547 } 4548 4549 if (fwnode_property_read_u32(port_fwnode, "port-id", &id)) { 4550 err = -EINVAL; 4551 dev_err(&pdev->dev, "missing port-id value\n"); 4552 goto err_free_netdev; 4553 } 4554 4555 dev->tx_queue_len = MVPP2_MAX_TXD_MAX; 4556 dev->watchdog_timeo = 5 * HZ; 4557 dev->netdev_ops = &mvpp2_netdev_ops; 4558 dev->ethtool_ops = &mvpp2_eth_tool_ops; 4559 4560 port = netdev_priv(dev); 4561 port->dev = dev; 4562 port->fwnode = port_fwnode; 4563 port->has_phy = !!of_find_property(port_node, "phy", NULL); 4564 port->ntxqs = ntxqs; 4565 port->nrxqs = nrxqs; 4566 port->priv = priv; 4567 port->has_tx_irqs = has_tx_irqs; 4568 4569 err = mvpp2_queue_vectors_init(port, port_node); 4570 if (err) 4571 goto err_free_netdev; 4572 4573 if (port_node) 4574 port->link_irq = of_irq_get_byname(port_node, "link"); 4575 else 4576 port->link_irq = fwnode_irq_get(port_fwnode, port->nqvecs + 1); 4577 if (port->link_irq == -EPROBE_DEFER) { 4578 err = -EPROBE_DEFER; 4579 goto err_deinit_qvecs; 4580 } 4581 if (port->link_irq <= 0) 4582 /* the link irq is optional */ 4583 port->link_irq = 0; 4584 4585 if (fwnode_property_read_bool(port_fwnode, "marvell,loopback")) 4586 port->flags |= MVPP2_F_LOOPBACK; 4587 4588 port->id = id; 4589 if (priv->hw_version == MVPP21) 4590 port->first_rxq = port->id * port->nrxqs; 4591 else 4592 port->first_rxq = port->id * priv->max_port_rxqs; 4593 4594 port->of_node = port_node; 4595 port->phy_interface = phy_mode; 4596 port->comphy = comphy; 4597 4598 if (priv->hw_version == MVPP21) { 4599 res = platform_get_resource(pdev, IORESOURCE_MEM, 2 + id); 4600 port->base = devm_ioremap_resource(&pdev->dev, res); 4601 if (IS_ERR(port->base)) { 4602 err = PTR_ERR(port->base); 4603 goto err_free_irq; 4604 } 4605 4606 port->stats_base = port->priv->lms_base + 4607 MVPP21_MIB_COUNTERS_OFFSET + 4608 port->gop_id * MVPP21_MIB_COUNTERS_PORT_SZ; 4609 } else { 4610 if (fwnode_property_read_u32(port_fwnode, "gop-port-id", 4611 &port->gop_id)) { 4612 err = -EINVAL; 4613 dev_err(&pdev->dev, "missing gop-port-id value\n"); 4614 goto err_deinit_qvecs; 4615 } 4616 4617 port->base = priv->iface_base + MVPP22_GMAC_BASE(port->gop_id); 4618 port->stats_base = port->priv->iface_base + 4619 MVPP22_MIB_COUNTERS_OFFSET + 4620 port->gop_id * MVPP22_MIB_COUNTERS_PORT_SZ; 4621 } 4622 4623 /* Alloc per-cpu and ethtool stats */ 4624 port->stats = netdev_alloc_pcpu_stats(struct mvpp2_pcpu_stats); 4625 if (!port->stats) { 4626 err = -ENOMEM; 4627 goto err_free_irq; 4628 } 4629 4630 port->ethtool_stats = devm_kcalloc(&pdev->dev, 4631 ARRAY_SIZE(mvpp2_ethtool_regs), 4632 sizeof(u64), GFP_KERNEL); 4633 if (!port->ethtool_stats) { 4634 err = -ENOMEM; 4635 goto err_free_stats; 4636 } 4637 4638 mutex_init(&port->gather_stats_lock); 4639 INIT_DELAYED_WORK(&port->stats_work, mvpp2_gather_hw_statistics); 4640 4641 mvpp2_port_copy_mac_addr(dev, priv, port_fwnode, &mac_from); 4642 4643 port->tx_ring_size = MVPP2_MAX_TXD_DFLT; 4644 port->rx_ring_size = MVPP2_MAX_RXD_DFLT; 4645 SET_NETDEV_DEV(dev, &pdev->dev); 4646 4647 err = mvpp2_port_init(port); 4648 if (err < 0) { 4649 dev_err(&pdev->dev, "failed to init port %d\n", id); 4650 goto err_free_stats; 4651 } 4652 4653 mvpp2_port_periodic_xon_disable(port); 4654 4655 mvpp2_port_reset(port); 4656 4657 port->pcpu = alloc_percpu(struct mvpp2_port_pcpu); 4658 if (!port->pcpu) { 4659 err = -ENOMEM; 4660 goto err_free_txq_pcpu; 4661 } 4662 4663 if (!port->has_tx_irqs) { 4664 for_each_present_cpu(cpu) { 4665 port_pcpu = per_cpu_ptr(port->pcpu, cpu); 4666 4667 hrtimer_init(&port_pcpu->tx_done_timer, CLOCK_MONOTONIC, 4668 HRTIMER_MODE_REL_PINNED); 4669 port_pcpu->tx_done_timer.function = mvpp2_hr_timer_cb; 4670 port_pcpu->timer_scheduled = false; 4671 4672 tasklet_init(&port_pcpu->tx_done_tasklet, 4673 mvpp2_tx_proc_cb, 4674 (unsigned long)dev); 4675 } 4676 } 4677 4678 features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | 4679 NETIF_F_TSO; 4680 dev->features = features | NETIF_F_RXCSUM; 4681 dev->hw_features |= features | NETIF_F_RXCSUM | NETIF_F_GRO | 4682 NETIF_F_HW_VLAN_CTAG_FILTER; 4683 4684 if (port->pool_long->id == MVPP2_BM_JUMBO && port->id != 0) { 4685 dev->features &= ~(NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM); 4686 dev->hw_features &= ~(NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM); 4687 } 4688 4689 dev->vlan_features |= features; 4690 dev->gso_max_segs = MVPP2_MAX_TSO_SEGS; 4691 dev->priv_flags |= IFF_UNICAST_FLT; 4692 4693 /* MTU range: 68 - 9704 */ 4694 dev->min_mtu = ETH_MIN_MTU; 4695 /* 9704 == 9728 - 20 and rounding to 8 */ 4696 dev->max_mtu = MVPP2_BM_JUMBO_PKT_SIZE; 4697 4698 /* Phylink isn't used w/ ACPI as of now */ 4699 if (port_node) { 4700 phylink = phylink_create(dev, port_fwnode, phy_mode, 4701 &mvpp2_phylink_ops); 4702 if (IS_ERR(phylink)) { 4703 err = PTR_ERR(phylink); 4704 goto err_free_port_pcpu; 4705 } 4706 port->phylink = phylink; 4707 } else { 4708 port->phylink = NULL; 4709 } 4710 4711 err = register_netdev(dev); 4712 if (err < 0) { 4713 dev_err(&pdev->dev, "failed to register netdev\n"); 4714 goto err_phylink; 4715 } 4716 netdev_info(dev, "Using %s mac address %pM\n", mac_from, dev->dev_addr); 4717 4718 priv->port_list[priv->port_count++] = port; 4719 4720 return 0; 4721 4722 err_phylink: 4723 if (port->phylink) 4724 phylink_destroy(port->phylink); 4725 err_free_port_pcpu: 4726 free_percpu(port->pcpu); 4727 err_free_txq_pcpu: 4728 for (i = 0; i < port->ntxqs; i++) 4729 free_percpu(port->txqs[i]->pcpu); 4730 err_free_stats: 4731 free_percpu(port->stats); 4732 err_free_irq: 4733 if (port->link_irq) 4734 irq_dispose_mapping(port->link_irq); 4735 err_deinit_qvecs: 4736 mvpp2_queue_vectors_deinit(port); 4737 err_free_netdev: 4738 free_netdev(dev); 4739 return err; 4740 } 4741 4742 /* Ports removal routine */ 4743 static void mvpp2_port_remove(struct mvpp2_port *port) 4744 { 4745 int i; 4746 4747 unregister_netdev(port->dev); 4748 if (port->phylink) 4749 phylink_destroy(port->phylink); 4750 free_percpu(port->pcpu); 4751 free_percpu(port->stats); 4752 for (i = 0; i < port->ntxqs; i++) 4753 free_percpu(port->txqs[i]->pcpu); 4754 mvpp2_queue_vectors_deinit(port); 4755 if (port->link_irq) 4756 irq_dispose_mapping(port->link_irq); 4757 free_netdev(port->dev); 4758 } 4759 4760 /* Initialize decoding windows */ 4761 static void mvpp2_conf_mbus_windows(const struct mbus_dram_target_info *dram, 4762 struct mvpp2 *priv) 4763 { 4764 u32 win_enable; 4765 int i; 4766 4767 for (i = 0; i < 6; i++) { 4768 mvpp2_write(priv, MVPP2_WIN_BASE(i), 0); 4769 mvpp2_write(priv, MVPP2_WIN_SIZE(i), 0); 4770 4771 if (i < 4) 4772 mvpp2_write(priv, MVPP2_WIN_REMAP(i), 0); 4773 } 4774 4775 win_enable = 0; 4776 4777 for (i = 0; i < dram->num_cs; i++) { 4778 const struct mbus_dram_window *cs = dram->cs + i; 4779 4780 mvpp2_write(priv, MVPP2_WIN_BASE(i), 4781 (cs->base & 0xffff0000) | (cs->mbus_attr << 8) | 4782 dram->mbus_dram_target_id); 4783 4784 mvpp2_write(priv, MVPP2_WIN_SIZE(i), 4785 (cs->size - 1) & 0xffff0000); 4786 4787 win_enable |= (1 << i); 4788 } 4789 4790 mvpp2_write(priv, MVPP2_BASE_ADDR_ENABLE, win_enable); 4791 } 4792 4793 /* Initialize Rx FIFO's */ 4794 static void mvpp2_rx_fifo_init(struct mvpp2 *priv) 4795 { 4796 int port; 4797 4798 for (port = 0; port < MVPP2_MAX_PORTS; port++) { 4799 mvpp2_write(priv, MVPP2_RX_DATA_FIFO_SIZE_REG(port), 4800 MVPP2_RX_FIFO_PORT_DATA_SIZE_4KB); 4801 mvpp2_write(priv, MVPP2_RX_ATTR_FIFO_SIZE_REG(port), 4802 MVPP2_RX_FIFO_PORT_ATTR_SIZE_4KB); 4803 } 4804 4805 mvpp2_write(priv, MVPP2_RX_MIN_PKT_SIZE_REG, 4806 MVPP2_RX_FIFO_PORT_MIN_PKT); 4807 mvpp2_write(priv, MVPP2_RX_FIFO_INIT_REG, 0x1); 4808 } 4809 4810 static void mvpp22_rx_fifo_init(struct mvpp2 *priv) 4811 { 4812 int port; 4813 4814 /* The FIFO size parameters are set depending on the maximum speed a 4815 * given port can handle: 4816 * - Port 0: 10Gbps 4817 * - Port 1: 2.5Gbps 4818 * - Ports 2 and 3: 1Gbps 4819 */ 4820 4821 mvpp2_write(priv, MVPP2_RX_DATA_FIFO_SIZE_REG(0), 4822 MVPP2_RX_FIFO_PORT_DATA_SIZE_32KB); 4823 mvpp2_write(priv, MVPP2_RX_ATTR_FIFO_SIZE_REG(0), 4824 MVPP2_RX_FIFO_PORT_ATTR_SIZE_32KB); 4825 4826 mvpp2_write(priv, MVPP2_RX_DATA_FIFO_SIZE_REG(1), 4827 MVPP2_RX_FIFO_PORT_DATA_SIZE_8KB); 4828 mvpp2_write(priv, MVPP2_RX_ATTR_FIFO_SIZE_REG(1), 4829 MVPP2_RX_FIFO_PORT_ATTR_SIZE_8KB); 4830 4831 for (port = 2; port < MVPP2_MAX_PORTS; port++) { 4832 mvpp2_write(priv, MVPP2_RX_DATA_FIFO_SIZE_REG(port), 4833 MVPP2_RX_FIFO_PORT_DATA_SIZE_4KB); 4834 mvpp2_write(priv, MVPP2_RX_ATTR_FIFO_SIZE_REG(port), 4835 MVPP2_RX_FIFO_PORT_ATTR_SIZE_4KB); 4836 } 4837 4838 mvpp2_write(priv, MVPP2_RX_MIN_PKT_SIZE_REG, 4839 MVPP2_RX_FIFO_PORT_MIN_PKT); 4840 mvpp2_write(priv, MVPP2_RX_FIFO_INIT_REG, 0x1); 4841 } 4842 4843 /* Initialize Tx FIFO's: the total FIFO size is 19kB on PPv2.2 and 10G 4844 * interfaces must have a Tx FIFO size of 10kB. As only port 0 can do 10G, 4845 * configure its Tx FIFO size to 10kB and the others ports Tx FIFO size to 3kB. 4846 */ 4847 static void mvpp22_tx_fifo_init(struct mvpp2 *priv) 4848 { 4849 int port, size, thrs; 4850 4851 for (port = 0; port < MVPP2_MAX_PORTS; port++) { 4852 if (port == 0) { 4853 size = MVPP22_TX_FIFO_DATA_SIZE_10KB; 4854 thrs = MVPP2_TX_FIFO_THRESHOLD_10KB; 4855 } else { 4856 size = MVPP22_TX_FIFO_DATA_SIZE_3KB; 4857 thrs = MVPP2_TX_FIFO_THRESHOLD_3KB; 4858 } 4859 mvpp2_write(priv, MVPP22_TX_FIFO_SIZE_REG(port), size); 4860 mvpp2_write(priv, MVPP22_TX_FIFO_THRESH_REG(port), thrs); 4861 } 4862 } 4863 4864 static void mvpp2_axi_init(struct mvpp2 *priv) 4865 { 4866 u32 val, rdval, wrval; 4867 4868 mvpp2_write(priv, MVPP22_BM_ADDR_HIGH_RLS_REG, 0x0); 4869 4870 /* AXI Bridge Configuration */ 4871 4872 rdval = MVPP22_AXI_CODE_CACHE_RD_CACHE 4873 << MVPP22_AXI_ATTR_CACHE_OFFS; 4874 rdval |= MVPP22_AXI_CODE_DOMAIN_OUTER_DOM 4875 << MVPP22_AXI_ATTR_DOMAIN_OFFS; 4876 4877 wrval = MVPP22_AXI_CODE_CACHE_WR_CACHE 4878 << MVPP22_AXI_ATTR_CACHE_OFFS; 4879 wrval |= MVPP22_AXI_CODE_DOMAIN_OUTER_DOM 4880 << MVPP22_AXI_ATTR_DOMAIN_OFFS; 4881 4882 /* BM */ 4883 mvpp2_write(priv, MVPP22_AXI_BM_WR_ATTR_REG, wrval); 4884 mvpp2_write(priv, MVPP22_AXI_BM_RD_ATTR_REG, rdval); 4885 4886 /* Descriptors */ 4887 mvpp2_write(priv, MVPP22_AXI_AGGRQ_DESCR_RD_ATTR_REG, rdval); 4888 mvpp2_write(priv, MVPP22_AXI_TXQ_DESCR_WR_ATTR_REG, wrval); 4889 mvpp2_write(priv, MVPP22_AXI_TXQ_DESCR_RD_ATTR_REG, rdval); 4890 mvpp2_write(priv, MVPP22_AXI_RXQ_DESCR_WR_ATTR_REG, wrval); 4891 4892 /* Buffer Data */ 4893 mvpp2_write(priv, MVPP22_AXI_TX_DATA_RD_ATTR_REG, rdval); 4894 mvpp2_write(priv, MVPP22_AXI_RX_DATA_WR_ATTR_REG, wrval); 4895 4896 val = MVPP22_AXI_CODE_CACHE_NON_CACHE 4897 << MVPP22_AXI_CODE_CACHE_OFFS; 4898 val |= MVPP22_AXI_CODE_DOMAIN_SYSTEM 4899 << MVPP22_AXI_CODE_DOMAIN_OFFS; 4900 mvpp2_write(priv, MVPP22_AXI_RD_NORMAL_CODE_REG, val); 4901 mvpp2_write(priv, MVPP22_AXI_WR_NORMAL_CODE_REG, val); 4902 4903 val = MVPP22_AXI_CODE_CACHE_RD_CACHE 4904 << MVPP22_AXI_CODE_CACHE_OFFS; 4905 val |= MVPP22_AXI_CODE_DOMAIN_OUTER_DOM 4906 << MVPP22_AXI_CODE_DOMAIN_OFFS; 4907 4908 mvpp2_write(priv, MVPP22_AXI_RD_SNOOP_CODE_REG, val); 4909 4910 val = MVPP22_AXI_CODE_CACHE_WR_CACHE 4911 << MVPP22_AXI_CODE_CACHE_OFFS; 4912 val |= MVPP22_AXI_CODE_DOMAIN_OUTER_DOM 4913 << MVPP22_AXI_CODE_DOMAIN_OFFS; 4914 4915 mvpp2_write(priv, MVPP22_AXI_WR_SNOOP_CODE_REG, val); 4916 } 4917 4918 /* Initialize network controller common part HW */ 4919 static int mvpp2_init(struct platform_device *pdev, struct mvpp2 *priv) 4920 { 4921 const struct mbus_dram_target_info *dram_target_info; 4922 int err, i; 4923 u32 val; 4924 4925 /* MBUS windows configuration */ 4926 dram_target_info = mv_mbus_dram_info(); 4927 if (dram_target_info) 4928 mvpp2_conf_mbus_windows(dram_target_info, priv); 4929 4930 if (priv->hw_version == MVPP22) 4931 mvpp2_axi_init(priv); 4932 4933 /* Disable HW PHY polling */ 4934 if (priv->hw_version == MVPP21) { 4935 val = readl(priv->lms_base + MVPP2_PHY_AN_CFG0_REG); 4936 val |= MVPP2_PHY_AN_STOP_SMI0_MASK; 4937 writel(val, priv->lms_base + MVPP2_PHY_AN_CFG0_REG); 4938 } else { 4939 val = readl(priv->iface_base + MVPP22_SMI_MISC_CFG_REG); 4940 val &= ~MVPP22_SMI_POLLING_EN; 4941 writel(val, priv->iface_base + MVPP22_SMI_MISC_CFG_REG); 4942 } 4943 4944 /* Allocate and initialize aggregated TXQs */ 4945 priv->aggr_txqs = devm_kcalloc(&pdev->dev, num_present_cpus(), 4946 sizeof(*priv->aggr_txqs), 4947 GFP_KERNEL); 4948 if (!priv->aggr_txqs) 4949 return -ENOMEM; 4950 4951 for_each_present_cpu(i) { 4952 priv->aggr_txqs[i].id = i; 4953 priv->aggr_txqs[i].size = MVPP2_AGGR_TXQ_SIZE; 4954 err = mvpp2_aggr_txq_init(pdev, &priv->aggr_txqs[i], i, priv); 4955 if (err < 0) 4956 return err; 4957 } 4958 4959 /* Fifo Init */ 4960 if (priv->hw_version == MVPP21) { 4961 mvpp2_rx_fifo_init(priv); 4962 } else { 4963 mvpp22_rx_fifo_init(priv); 4964 mvpp22_tx_fifo_init(priv); 4965 } 4966 4967 if (priv->hw_version == MVPP21) 4968 writel(MVPP2_EXT_GLOBAL_CTRL_DEFAULT, 4969 priv->lms_base + MVPP2_MNG_EXTENDED_GLOBAL_CTRL_REG); 4970 4971 /* Allow cache snoop when transmiting packets */ 4972 mvpp2_write(priv, MVPP2_TX_SNOOP_REG, 0x1); 4973 4974 /* Buffer Manager initialization */ 4975 err = mvpp2_bm_init(pdev, priv); 4976 if (err < 0) 4977 return err; 4978 4979 /* Parser default initialization */ 4980 err = mvpp2_prs_default_init(pdev, priv); 4981 if (err < 0) 4982 return err; 4983 4984 /* Classifier default initialization */ 4985 mvpp2_cls_init(priv); 4986 4987 return 0; 4988 } 4989 4990 static int mvpp2_probe(struct platform_device *pdev) 4991 { 4992 const struct acpi_device_id *acpi_id; 4993 struct fwnode_handle *fwnode = pdev->dev.fwnode; 4994 struct fwnode_handle *port_fwnode; 4995 struct mvpp2 *priv; 4996 struct resource *res; 4997 void __iomem *base; 4998 int i; 4999 int err; 5000 5001 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); 5002 if (!priv) 5003 return -ENOMEM; 5004 5005 if (has_acpi_companion(&pdev->dev)) { 5006 acpi_id = acpi_match_device(pdev->dev.driver->acpi_match_table, 5007 &pdev->dev); 5008 priv->hw_version = (unsigned long)acpi_id->driver_data; 5009 } else { 5010 priv->hw_version = 5011 (unsigned long)of_device_get_match_data(&pdev->dev); 5012 } 5013 5014 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 5015 base = devm_ioremap_resource(&pdev->dev, res); 5016 if (IS_ERR(base)) 5017 return PTR_ERR(base); 5018 5019 if (priv->hw_version == MVPP21) { 5020 res = platform_get_resource(pdev, IORESOURCE_MEM, 1); 5021 priv->lms_base = devm_ioremap_resource(&pdev->dev, res); 5022 if (IS_ERR(priv->lms_base)) 5023 return PTR_ERR(priv->lms_base); 5024 } else { 5025 res = platform_get_resource(pdev, IORESOURCE_MEM, 1); 5026 if (has_acpi_companion(&pdev->dev)) { 5027 /* In case the MDIO memory region is declared in 5028 * the ACPI, it can already appear as 'in-use' 5029 * in the OS. Because it is overlapped by second 5030 * region of the network controller, make 5031 * sure it is released, before requesting it again. 5032 * The care is taken by mvpp2 driver to avoid 5033 * concurrent access to this memory region. 5034 */ 5035 release_resource(res); 5036 } 5037 priv->iface_base = devm_ioremap_resource(&pdev->dev, res); 5038 if (IS_ERR(priv->iface_base)) 5039 return PTR_ERR(priv->iface_base); 5040 } 5041 5042 if (priv->hw_version == MVPP22 && dev_of_node(&pdev->dev)) { 5043 priv->sysctrl_base = 5044 syscon_regmap_lookup_by_phandle(pdev->dev.of_node, 5045 "marvell,system-controller"); 5046 if (IS_ERR(priv->sysctrl_base)) 5047 /* The system controller regmap is optional for dt 5048 * compatibility reasons. When not provided, the 5049 * configuration of the GoP relies on the 5050 * firmware/bootloader. 5051 */ 5052 priv->sysctrl_base = NULL; 5053 } 5054 5055 mvpp2_setup_bm_pool(); 5056 5057 for (i = 0; i < MVPP2_MAX_THREADS; i++) { 5058 u32 addr_space_sz; 5059 5060 addr_space_sz = (priv->hw_version == MVPP21 ? 5061 MVPP21_ADDR_SPACE_SZ : MVPP22_ADDR_SPACE_SZ); 5062 priv->swth_base[i] = base + i * addr_space_sz; 5063 } 5064 5065 if (priv->hw_version == MVPP21) 5066 priv->max_port_rxqs = 8; 5067 else 5068 priv->max_port_rxqs = 32; 5069 5070 if (dev_of_node(&pdev->dev)) { 5071 priv->pp_clk = devm_clk_get(&pdev->dev, "pp_clk"); 5072 if (IS_ERR(priv->pp_clk)) 5073 return PTR_ERR(priv->pp_clk); 5074 err = clk_prepare_enable(priv->pp_clk); 5075 if (err < 0) 5076 return err; 5077 5078 priv->gop_clk = devm_clk_get(&pdev->dev, "gop_clk"); 5079 if (IS_ERR(priv->gop_clk)) { 5080 err = PTR_ERR(priv->gop_clk); 5081 goto err_pp_clk; 5082 } 5083 err = clk_prepare_enable(priv->gop_clk); 5084 if (err < 0) 5085 goto err_pp_clk; 5086 5087 if (priv->hw_version == MVPP22) { 5088 priv->mg_clk = devm_clk_get(&pdev->dev, "mg_clk"); 5089 if (IS_ERR(priv->mg_clk)) { 5090 err = PTR_ERR(priv->mg_clk); 5091 goto err_gop_clk; 5092 } 5093 5094 err = clk_prepare_enable(priv->mg_clk); 5095 if (err < 0) 5096 goto err_gop_clk; 5097 5098 priv->mg_core_clk = devm_clk_get(&pdev->dev, "mg_core_clk"); 5099 if (IS_ERR(priv->mg_core_clk)) { 5100 priv->mg_core_clk = NULL; 5101 } else { 5102 err = clk_prepare_enable(priv->mg_core_clk); 5103 if (err < 0) 5104 goto err_mg_clk; 5105 } 5106 } 5107 5108 priv->axi_clk = devm_clk_get(&pdev->dev, "axi_clk"); 5109 if (IS_ERR(priv->axi_clk)) { 5110 err = PTR_ERR(priv->axi_clk); 5111 if (err == -EPROBE_DEFER) 5112 goto err_mg_core_clk; 5113 priv->axi_clk = NULL; 5114 } else { 5115 err = clk_prepare_enable(priv->axi_clk); 5116 if (err < 0) 5117 goto err_mg_core_clk; 5118 } 5119 5120 /* Get system's tclk rate */ 5121 priv->tclk = clk_get_rate(priv->pp_clk); 5122 } else if (device_property_read_u32(&pdev->dev, "clock-frequency", 5123 &priv->tclk)) { 5124 dev_err(&pdev->dev, "missing clock-frequency value\n"); 5125 return -EINVAL; 5126 } 5127 5128 if (priv->hw_version == MVPP22) { 5129 err = dma_set_mask(&pdev->dev, MVPP2_DESC_DMA_MASK); 5130 if (err) 5131 goto err_axi_clk; 5132 /* Sadly, the BM pools all share the same register to 5133 * store the high 32 bits of their address. So they 5134 * must all have the same high 32 bits, which forces 5135 * us to restrict coherent memory to DMA_BIT_MASK(32). 5136 */ 5137 err = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32)); 5138 if (err) 5139 goto err_axi_clk; 5140 } 5141 5142 /* Initialize network controller */ 5143 err = mvpp2_init(pdev, priv); 5144 if (err < 0) { 5145 dev_err(&pdev->dev, "failed to initialize controller\n"); 5146 goto err_axi_clk; 5147 } 5148 5149 /* Initialize ports */ 5150 fwnode_for_each_available_child_node(fwnode, port_fwnode) { 5151 err = mvpp2_port_probe(pdev, port_fwnode, priv); 5152 if (err < 0) 5153 goto err_port_probe; 5154 } 5155 5156 if (priv->port_count == 0) { 5157 dev_err(&pdev->dev, "no ports enabled\n"); 5158 err = -ENODEV; 5159 goto err_axi_clk; 5160 } 5161 5162 /* Statistics must be gathered regularly because some of them (like 5163 * packets counters) are 32-bit registers and could overflow quite 5164 * quickly. For instance, a 10Gb link used at full bandwidth with the 5165 * smallest packets (64B) will overflow a 32-bit counter in less than 5166 * 30 seconds. Then, use a workqueue to fill 64-bit counters. 5167 */ 5168 snprintf(priv->queue_name, sizeof(priv->queue_name), 5169 "stats-wq-%s%s", netdev_name(priv->port_list[0]->dev), 5170 priv->port_count > 1 ? "+" : ""); 5171 priv->stats_queue = create_singlethread_workqueue(priv->queue_name); 5172 if (!priv->stats_queue) { 5173 err = -ENOMEM; 5174 goto err_port_probe; 5175 } 5176 5177 platform_set_drvdata(pdev, priv); 5178 return 0; 5179 5180 err_port_probe: 5181 i = 0; 5182 fwnode_for_each_available_child_node(fwnode, port_fwnode) { 5183 if (priv->port_list[i]) 5184 mvpp2_port_remove(priv->port_list[i]); 5185 i++; 5186 } 5187 err_axi_clk: 5188 clk_disable_unprepare(priv->axi_clk); 5189 5190 err_mg_core_clk: 5191 if (priv->hw_version == MVPP22) 5192 clk_disable_unprepare(priv->mg_core_clk); 5193 err_mg_clk: 5194 if (priv->hw_version == MVPP22) 5195 clk_disable_unprepare(priv->mg_clk); 5196 err_gop_clk: 5197 clk_disable_unprepare(priv->gop_clk); 5198 err_pp_clk: 5199 clk_disable_unprepare(priv->pp_clk); 5200 return err; 5201 } 5202 5203 static int mvpp2_remove(struct platform_device *pdev) 5204 { 5205 struct mvpp2 *priv = platform_get_drvdata(pdev); 5206 struct fwnode_handle *fwnode = pdev->dev.fwnode; 5207 struct fwnode_handle *port_fwnode; 5208 int i = 0; 5209 5210 flush_workqueue(priv->stats_queue); 5211 destroy_workqueue(priv->stats_queue); 5212 5213 fwnode_for_each_available_child_node(fwnode, port_fwnode) { 5214 if (priv->port_list[i]) { 5215 mutex_destroy(&priv->port_list[i]->gather_stats_lock); 5216 mvpp2_port_remove(priv->port_list[i]); 5217 } 5218 i++; 5219 } 5220 5221 for (i = 0; i < MVPP2_BM_POOLS_NUM; i++) { 5222 struct mvpp2_bm_pool *bm_pool = &priv->bm_pools[i]; 5223 5224 mvpp2_bm_pool_destroy(pdev, priv, bm_pool); 5225 } 5226 5227 for_each_present_cpu(i) { 5228 struct mvpp2_tx_queue *aggr_txq = &priv->aggr_txqs[i]; 5229 5230 dma_free_coherent(&pdev->dev, 5231 MVPP2_AGGR_TXQ_SIZE * MVPP2_DESC_ALIGNED_SIZE, 5232 aggr_txq->descs, 5233 aggr_txq->descs_dma); 5234 } 5235 5236 if (is_acpi_node(port_fwnode)) 5237 return 0; 5238 5239 clk_disable_unprepare(priv->axi_clk); 5240 clk_disable_unprepare(priv->mg_core_clk); 5241 clk_disable_unprepare(priv->mg_clk); 5242 clk_disable_unprepare(priv->pp_clk); 5243 clk_disable_unprepare(priv->gop_clk); 5244 5245 return 0; 5246 } 5247 5248 static const struct of_device_id mvpp2_match[] = { 5249 { 5250 .compatible = "marvell,armada-375-pp2", 5251 .data = (void *)MVPP21, 5252 }, 5253 { 5254 .compatible = "marvell,armada-7k-pp22", 5255 .data = (void *)MVPP22, 5256 }, 5257 { } 5258 }; 5259 MODULE_DEVICE_TABLE(of, mvpp2_match); 5260 5261 static const struct acpi_device_id mvpp2_acpi_match[] = { 5262 { "MRVL0110", MVPP22 }, 5263 { }, 5264 }; 5265 MODULE_DEVICE_TABLE(acpi, mvpp2_acpi_match); 5266 5267 static struct platform_driver mvpp2_driver = { 5268 .probe = mvpp2_probe, 5269 .remove = mvpp2_remove, 5270 .driver = { 5271 .name = MVPP2_DRIVER_NAME, 5272 .of_match_table = mvpp2_match, 5273 .acpi_match_table = ACPI_PTR(mvpp2_acpi_match), 5274 }, 5275 }; 5276 5277 module_platform_driver(mvpp2_driver); 5278 5279 MODULE_DESCRIPTION("Marvell PPv2 Ethernet Driver - www.marvell.com"); 5280 MODULE_AUTHOR("Marcin Wojtas <mw@semihalf.com>"); 5281 MODULE_LICENSE("GPL v2"); 5282