1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Driver for Marvell PPv2 network controller for Armada 375 SoC. 4 * 5 * Copyright (C) 2014 Marvell 6 * 7 * Marcin Wojtas <mw@semihalf.com> 8 */ 9 10 #include <linux/acpi.h> 11 #include <linux/kernel.h> 12 #include <linux/netdevice.h> 13 #include <linux/etherdevice.h> 14 #include <linux/platform_device.h> 15 #include <linux/skbuff.h> 16 #include <linux/inetdevice.h> 17 #include <linux/mbus.h> 18 #include <linux/module.h> 19 #include <linux/mfd/syscon.h> 20 #include <linux/interrupt.h> 21 #include <linux/cpumask.h> 22 #include <linux/of.h> 23 #include <linux/of_irq.h> 24 #include <linux/of_mdio.h> 25 #include <linux/of_net.h> 26 #include <linux/of_address.h> 27 #include <linux/of_device.h> 28 #include <linux/phy.h> 29 #include <linux/phylink.h> 30 #include <linux/phy/phy.h> 31 #include <linux/ptp_classify.h> 32 #include <linux/clk.h> 33 #include <linux/hrtimer.h> 34 #include <linux/ktime.h> 35 #include <linux/regmap.h> 36 #include <uapi/linux/ppp_defs.h> 37 #include <net/ip.h> 38 #include <net/ipv6.h> 39 #include <net/tso.h> 40 #include <linux/bpf_trace.h> 41 42 #include "mvpp2.h" 43 #include "mvpp2_prs.h" 44 #include "mvpp2_cls.h" 45 46 enum mvpp2_bm_pool_log_num { 47 MVPP2_BM_SHORT, 48 MVPP2_BM_LONG, 49 MVPP2_BM_JUMBO, 50 MVPP2_BM_POOLS_NUM 51 }; 52 53 static struct { 54 int pkt_size; 55 int buf_num; 56 } mvpp2_pools[MVPP2_BM_POOLS_NUM]; 57 58 /* The prototype is added here to be used in start_dev when using ACPI. This 59 * will be removed once phylink is used for all modes (dt+ACPI). 60 */ 61 static void mvpp2_acpi_start(struct mvpp2_port *port); 62 63 /* Queue modes */ 64 #define MVPP2_QDIST_SINGLE_MODE 0 65 #define MVPP2_QDIST_MULTI_MODE 1 66 67 static int queue_mode = MVPP2_QDIST_MULTI_MODE; 68 69 module_param(queue_mode, int, 0444); 70 MODULE_PARM_DESC(queue_mode, "Set queue_mode (single=0, multi=1)"); 71 72 /* Utility/helper methods */ 73 74 void mvpp2_write(struct mvpp2 *priv, u32 offset, u32 data) 75 { 76 writel(data, priv->swth_base[0] + offset); 77 } 78 79 u32 mvpp2_read(struct mvpp2 *priv, u32 offset) 80 { 81 return readl(priv->swth_base[0] + offset); 82 } 83 84 static u32 mvpp2_read_relaxed(struct mvpp2 *priv, u32 offset) 85 { 86 return readl_relaxed(priv->swth_base[0] + offset); 87 } 88 89 static inline u32 mvpp2_cpu_to_thread(struct mvpp2 *priv, int cpu) 90 { 91 return cpu % priv->nthreads; 92 } 93 94 static void mvpp2_cm3_write(struct mvpp2 *priv, u32 offset, u32 data) 95 { 96 writel(data, priv->cm3_base + offset); 97 } 98 99 static u32 mvpp2_cm3_read(struct mvpp2 *priv, u32 offset) 100 { 101 return readl(priv->cm3_base + offset); 102 } 103 104 static struct page_pool * 105 mvpp2_create_page_pool(struct device *dev, int num, int len, 106 enum dma_data_direction dma_dir) 107 { 108 struct page_pool_params pp_params = { 109 /* internal DMA mapping in page_pool */ 110 .flags = PP_FLAG_DMA_MAP | PP_FLAG_DMA_SYNC_DEV, 111 .pool_size = num, 112 .nid = NUMA_NO_NODE, 113 .dev = dev, 114 .dma_dir = dma_dir, 115 .offset = MVPP2_SKB_HEADROOM, 116 .max_len = len, 117 }; 118 119 return page_pool_create(&pp_params); 120 } 121 122 /* These accessors should be used to access: 123 * 124 * - per-thread registers, where each thread has its own copy of the 125 * register. 126 * 127 * MVPP2_BM_VIRT_ALLOC_REG 128 * MVPP2_BM_ADDR_HIGH_ALLOC 129 * MVPP22_BM_ADDR_HIGH_RLS_REG 130 * MVPP2_BM_VIRT_RLS_REG 131 * MVPP2_ISR_RX_TX_CAUSE_REG 132 * MVPP2_ISR_RX_TX_MASK_REG 133 * MVPP2_TXQ_NUM_REG 134 * MVPP2_AGGR_TXQ_UPDATE_REG 135 * MVPP2_TXQ_RSVD_REQ_REG 136 * MVPP2_TXQ_RSVD_RSLT_REG 137 * MVPP2_TXQ_SENT_REG 138 * MVPP2_RXQ_NUM_REG 139 * 140 * - global registers that must be accessed through a specific thread 141 * window, because they are related to an access to a per-thread 142 * register 143 * 144 * MVPP2_BM_PHY_ALLOC_REG (related to MVPP2_BM_VIRT_ALLOC_REG) 145 * MVPP2_BM_PHY_RLS_REG (related to MVPP2_BM_VIRT_RLS_REG) 146 * MVPP2_RXQ_THRESH_REG (related to MVPP2_RXQ_NUM_REG) 147 * MVPP2_RXQ_DESC_ADDR_REG (related to MVPP2_RXQ_NUM_REG) 148 * MVPP2_RXQ_DESC_SIZE_REG (related to MVPP2_RXQ_NUM_REG) 149 * MVPP2_RXQ_INDEX_REG (related to MVPP2_RXQ_NUM_REG) 150 * MVPP2_TXQ_PENDING_REG (related to MVPP2_TXQ_NUM_REG) 151 * MVPP2_TXQ_DESC_ADDR_REG (related to MVPP2_TXQ_NUM_REG) 152 * MVPP2_TXQ_DESC_SIZE_REG (related to MVPP2_TXQ_NUM_REG) 153 * MVPP2_TXQ_INDEX_REG (related to MVPP2_TXQ_NUM_REG) 154 * MVPP2_TXQ_PENDING_REG (related to MVPP2_TXQ_NUM_REG) 155 * MVPP2_TXQ_PREF_BUF_REG (related to MVPP2_TXQ_NUM_REG) 156 * MVPP2_TXQ_PREF_BUF_REG (related to MVPP2_TXQ_NUM_REG) 157 */ 158 static void mvpp2_thread_write(struct mvpp2 *priv, unsigned int thread, 159 u32 offset, u32 data) 160 { 161 writel(data, priv->swth_base[thread] + offset); 162 } 163 164 static u32 mvpp2_thread_read(struct mvpp2 *priv, unsigned int thread, 165 u32 offset) 166 { 167 return readl(priv->swth_base[thread] + offset); 168 } 169 170 static void mvpp2_thread_write_relaxed(struct mvpp2 *priv, unsigned int thread, 171 u32 offset, u32 data) 172 { 173 writel_relaxed(data, priv->swth_base[thread] + offset); 174 } 175 176 static u32 mvpp2_thread_read_relaxed(struct mvpp2 *priv, unsigned int thread, 177 u32 offset) 178 { 179 return readl_relaxed(priv->swth_base[thread] + offset); 180 } 181 182 static dma_addr_t mvpp2_txdesc_dma_addr_get(struct mvpp2_port *port, 183 struct mvpp2_tx_desc *tx_desc) 184 { 185 if (port->priv->hw_version == MVPP21) 186 return le32_to_cpu(tx_desc->pp21.buf_dma_addr); 187 else 188 return le64_to_cpu(tx_desc->pp22.buf_dma_addr_ptp) & 189 MVPP2_DESC_DMA_MASK; 190 } 191 192 static void mvpp2_txdesc_dma_addr_set(struct mvpp2_port *port, 193 struct mvpp2_tx_desc *tx_desc, 194 dma_addr_t dma_addr) 195 { 196 dma_addr_t addr, offset; 197 198 addr = dma_addr & ~MVPP2_TX_DESC_ALIGN; 199 offset = dma_addr & MVPP2_TX_DESC_ALIGN; 200 201 if (port->priv->hw_version == MVPP21) { 202 tx_desc->pp21.buf_dma_addr = cpu_to_le32(addr); 203 tx_desc->pp21.packet_offset = offset; 204 } else { 205 __le64 val = cpu_to_le64(addr); 206 207 tx_desc->pp22.buf_dma_addr_ptp &= ~cpu_to_le64(MVPP2_DESC_DMA_MASK); 208 tx_desc->pp22.buf_dma_addr_ptp |= val; 209 tx_desc->pp22.packet_offset = offset; 210 } 211 } 212 213 static size_t mvpp2_txdesc_size_get(struct mvpp2_port *port, 214 struct mvpp2_tx_desc *tx_desc) 215 { 216 if (port->priv->hw_version == MVPP21) 217 return le16_to_cpu(tx_desc->pp21.data_size); 218 else 219 return le16_to_cpu(tx_desc->pp22.data_size); 220 } 221 222 static void mvpp2_txdesc_size_set(struct mvpp2_port *port, 223 struct mvpp2_tx_desc *tx_desc, 224 size_t size) 225 { 226 if (port->priv->hw_version == MVPP21) 227 tx_desc->pp21.data_size = cpu_to_le16(size); 228 else 229 tx_desc->pp22.data_size = cpu_to_le16(size); 230 } 231 232 static void mvpp2_txdesc_txq_set(struct mvpp2_port *port, 233 struct mvpp2_tx_desc *tx_desc, 234 unsigned int txq) 235 { 236 if (port->priv->hw_version == MVPP21) 237 tx_desc->pp21.phys_txq = txq; 238 else 239 tx_desc->pp22.phys_txq = txq; 240 } 241 242 static void mvpp2_txdesc_cmd_set(struct mvpp2_port *port, 243 struct mvpp2_tx_desc *tx_desc, 244 unsigned int command) 245 { 246 if (port->priv->hw_version == MVPP21) 247 tx_desc->pp21.command = cpu_to_le32(command); 248 else 249 tx_desc->pp22.command = cpu_to_le32(command); 250 } 251 252 static unsigned int mvpp2_txdesc_offset_get(struct mvpp2_port *port, 253 struct mvpp2_tx_desc *tx_desc) 254 { 255 if (port->priv->hw_version == MVPP21) 256 return tx_desc->pp21.packet_offset; 257 else 258 return tx_desc->pp22.packet_offset; 259 } 260 261 static dma_addr_t mvpp2_rxdesc_dma_addr_get(struct mvpp2_port *port, 262 struct mvpp2_rx_desc *rx_desc) 263 { 264 if (port->priv->hw_version == MVPP21) 265 return le32_to_cpu(rx_desc->pp21.buf_dma_addr); 266 else 267 return le64_to_cpu(rx_desc->pp22.buf_dma_addr_key_hash) & 268 MVPP2_DESC_DMA_MASK; 269 } 270 271 static unsigned long mvpp2_rxdesc_cookie_get(struct mvpp2_port *port, 272 struct mvpp2_rx_desc *rx_desc) 273 { 274 if (port->priv->hw_version == MVPP21) 275 return le32_to_cpu(rx_desc->pp21.buf_cookie); 276 else 277 return le64_to_cpu(rx_desc->pp22.buf_cookie_misc) & 278 MVPP2_DESC_DMA_MASK; 279 } 280 281 static size_t mvpp2_rxdesc_size_get(struct mvpp2_port *port, 282 struct mvpp2_rx_desc *rx_desc) 283 { 284 if (port->priv->hw_version == MVPP21) 285 return le16_to_cpu(rx_desc->pp21.data_size); 286 else 287 return le16_to_cpu(rx_desc->pp22.data_size); 288 } 289 290 static u32 mvpp2_rxdesc_status_get(struct mvpp2_port *port, 291 struct mvpp2_rx_desc *rx_desc) 292 { 293 if (port->priv->hw_version == MVPP21) 294 return le32_to_cpu(rx_desc->pp21.status); 295 else 296 return le32_to_cpu(rx_desc->pp22.status); 297 } 298 299 static void mvpp2_txq_inc_get(struct mvpp2_txq_pcpu *txq_pcpu) 300 { 301 txq_pcpu->txq_get_index++; 302 if (txq_pcpu->txq_get_index == txq_pcpu->size) 303 txq_pcpu->txq_get_index = 0; 304 } 305 306 static void mvpp2_txq_inc_put(struct mvpp2_port *port, 307 struct mvpp2_txq_pcpu *txq_pcpu, 308 void *data, 309 struct mvpp2_tx_desc *tx_desc, 310 enum mvpp2_tx_buf_type buf_type) 311 { 312 struct mvpp2_txq_pcpu_buf *tx_buf = 313 txq_pcpu->buffs + txq_pcpu->txq_put_index; 314 tx_buf->type = buf_type; 315 if (buf_type == MVPP2_TYPE_SKB) 316 tx_buf->skb = data; 317 else 318 tx_buf->xdpf = data; 319 tx_buf->size = mvpp2_txdesc_size_get(port, tx_desc); 320 tx_buf->dma = mvpp2_txdesc_dma_addr_get(port, tx_desc) + 321 mvpp2_txdesc_offset_get(port, tx_desc); 322 txq_pcpu->txq_put_index++; 323 if (txq_pcpu->txq_put_index == txq_pcpu->size) 324 txq_pcpu->txq_put_index = 0; 325 } 326 327 /* Get number of maximum RXQ */ 328 static int mvpp2_get_nrxqs(struct mvpp2 *priv) 329 { 330 unsigned int nrxqs; 331 332 if (priv->hw_version != MVPP21 && queue_mode == MVPP2_QDIST_SINGLE_MODE) 333 return 1; 334 335 /* According to the PPv2.2 datasheet and our experiments on 336 * PPv2.1, RX queues have an allocation granularity of 4 (when 337 * more than a single one on PPv2.2). 338 * Round up to nearest multiple of 4. 339 */ 340 nrxqs = (num_possible_cpus() + 3) & ~0x3; 341 if (nrxqs > MVPP2_PORT_MAX_RXQ) 342 nrxqs = MVPP2_PORT_MAX_RXQ; 343 344 return nrxqs; 345 } 346 347 /* Get number of physical egress port */ 348 static inline int mvpp2_egress_port(struct mvpp2_port *port) 349 { 350 return MVPP2_MAX_TCONT + port->id; 351 } 352 353 /* Get number of physical TXQ */ 354 static inline int mvpp2_txq_phys(int port, int txq) 355 { 356 return (MVPP2_MAX_TCONT + port) * MVPP2_MAX_TXQ + txq; 357 } 358 359 /* Returns a struct page if page_pool is set, otherwise a buffer */ 360 static void *mvpp2_frag_alloc(const struct mvpp2_bm_pool *pool, 361 struct page_pool *page_pool) 362 { 363 if (page_pool) 364 return page_pool_dev_alloc_pages(page_pool); 365 366 if (likely(pool->frag_size <= PAGE_SIZE)) 367 return netdev_alloc_frag(pool->frag_size); 368 369 return kmalloc(pool->frag_size, GFP_ATOMIC); 370 } 371 372 static void mvpp2_frag_free(const struct mvpp2_bm_pool *pool, 373 struct page_pool *page_pool, void *data) 374 { 375 if (page_pool) 376 page_pool_put_full_page(page_pool, virt_to_head_page(data), false); 377 else if (likely(pool->frag_size <= PAGE_SIZE)) 378 skb_free_frag(data); 379 else 380 kfree(data); 381 } 382 383 /* Buffer Manager configuration routines */ 384 385 /* Create pool */ 386 static int mvpp2_bm_pool_create(struct device *dev, struct mvpp2 *priv, 387 struct mvpp2_bm_pool *bm_pool, int size) 388 { 389 u32 val; 390 391 /* Number of buffer pointers must be a multiple of 16, as per 392 * hardware constraints 393 */ 394 if (!IS_ALIGNED(size, 16)) 395 return -EINVAL; 396 397 /* PPv2.1 needs 8 bytes per buffer pointer, PPv2.2 and PPv2.3 needs 16 398 * bytes per buffer pointer 399 */ 400 if (priv->hw_version == MVPP21) 401 bm_pool->size_bytes = 2 * sizeof(u32) * size; 402 else 403 bm_pool->size_bytes = 2 * sizeof(u64) * size; 404 405 bm_pool->virt_addr = dma_alloc_coherent(dev, bm_pool->size_bytes, 406 &bm_pool->dma_addr, 407 GFP_KERNEL); 408 if (!bm_pool->virt_addr) 409 return -ENOMEM; 410 411 if (!IS_ALIGNED((unsigned long)bm_pool->virt_addr, 412 MVPP2_BM_POOL_PTR_ALIGN)) { 413 dma_free_coherent(dev, bm_pool->size_bytes, 414 bm_pool->virt_addr, bm_pool->dma_addr); 415 dev_err(dev, "BM pool %d is not %d bytes aligned\n", 416 bm_pool->id, MVPP2_BM_POOL_PTR_ALIGN); 417 return -ENOMEM; 418 } 419 420 mvpp2_write(priv, MVPP2_BM_POOL_BASE_REG(bm_pool->id), 421 lower_32_bits(bm_pool->dma_addr)); 422 mvpp2_write(priv, MVPP2_BM_POOL_SIZE_REG(bm_pool->id), size); 423 424 val = mvpp2_read(priv, MVPP2_BM_POOL_CTRL_REG(bm_pool->id)); 425 val |= MVPP2_BM_START_MASK; 426 427 val &= ~MVPP2_BM_LOW_THRESH_MASK; 428 val &= ~MVPP2_BM_HIGH_THRESH_MASK; 429 430 /* Set 8 Pools BPPI threshold for MVPP23 */ 431 if (priv->hw_version == MVPP23) { 432 val |= MVPP2_BM_LOW_THRESH_VALUE(MVPP23_BM_BPPI_LOW_THRESH); 433 val |= MVPP2_BM_HIGH_THRESH_VALUE(MVPP23_BM_BPPI_HIGH_THRESH); 434 } else { 435 val |= MVPP2_BM_LOW_THRESH_VALUE(MVPP2_BM_BPPI_LOW_THRESH); 436 val |= MVPP2_BM_HIGH_THRESH_VALUE(MVPP2_BM_BPPI_HIGH_THRESH); 437 } 438 439 mvpp2_write(priv, MVPP2_BM_POOL_CTRL_REG(bm_pool->id), val); 440 441 bm_pool->size = size; 442 bm_pool->pkt_size = 0; 443 bm_pool->buf_num = 0; 444 445 return 0; 446 } 447 448 /* Set pool buffer size */ 449 static void mvpp2_bm_pool_bufsize_set(struct mvpp2 *priv, 450 struct mvpp2_bm_pool *bm_pool, 451 int buf_size) 452 { 453 u32 val; 454 455 bm_pool->buf_size = buf_size; 456 457 val = ALIGN(buf_size, 1 << MVPP2_POOL_BUF_SIZE_OFFSET); 458 mvpp2_write(priv, MVPP2_POOL_BUF_SIZE_REG(bm_pool->id), val); 459 } 460 461 static void mvpp2_bm_bufs_get_addrs(struct device *dev, struct mvpp2 *priv, 462 struct mvpp2_bm_pool *bm_pool, 463 dma_addr_t *dma_addr, 464 phys_addr_t *phys_addr) 465 { 466 unsigned int thread = mvpp2_cpu_to_thread(priv, get_cpu()); 467 468 *dma_addr = mvpp2_thread_read(priv, thread, 469 MVPP2_BM_PHY_ALLOC_REG(bm_pool->id)); 470 *phys_addr = mvpp2_thread_read(priv, thread, MVPP2_BM_VIRT_ALLOC_REG); 471 472 if (priv->hw_version != MVPP21) { 473 u32 val; 474 u32 dma_addr_highbits, phys_addr_highbits; 475 476 val = mvpp2_thread_read(priv, thread, MVPP22_BM_ADDR_HIGH_ALLOC); 477 dma_addr_highbits = (val & MVPP22_BM_ADDR_HIGH_PHYS_MASK); 478 phys_addr_highbits = (val & MVPP22_BM_ADDR_HIGH_VIRT_MASK) >> 479 MVPP22_BM_ADDR_HIGH_VIRT_SHIFT; 480 481 if (sizeof(dma_addr_t) == 8) 482 *dma_addr |= (u64)dma_addr_highbits << 32; 483 484 if (sizeof(phys_addr_t) == 8) 485 *phys_addr |= (u64)phys_addr_highbits << 32; 486 } 487 488 put_cpu(); 489 } 490 491 /* Free all buffers from the pool */ 492 static void mvpp2_bm_bufs_free(struct device *dev, struct mvpp2 *priv, 493 struct mvpp2_bm_pool *bm_pool, int buf_num) 494 { 495 struct page_pool *pp = NULL; 496 int i; 497 498 if (buf_num > bm_pool->buf_num) { 499 WARN(1, "Pool does not have so many bufs pool(%d) bufs(%d)\n", 500 bm_pool->id, buf_num); 501 buf_num = bm_pool->buf_num; 502 } 503 504 if (priv->percpu_pools) 505 pp = priv->page_pool[bm_pool->id]; 506 507 for (i = 0; i < buf_num; i++) { 508 dma_addr_t buf_dma_addr; 509 phys_addr_t buf_phys_addr; 510 void *data; 511 512 mvpp2_bm_bufs_get_addrs(dev, priv, bm_pool, 513 &buf_dma_addr, &buf_phys_addr); 514 515 if (!pp) 516 dma_unmap_single(dev, buf_dma_addr, 517 bm_pool->buf_size, DMA_FROM_DEVICE); 518 519 data = (void *)phys_to_virt(buf_phys_addr); 520 if (!data) 521 break; 522 523 mvpp2_frag_free(bm_pool, pp, data); 524 } 525 526 /* Update BM driver with number of buffers removed from pool */ 527 bm_pool->buf_num -= i; 528 } 529 530 /* Check number of buffers in BM pool */ 531 static int mvpp2_check_hw_buf_num(struct mvpp2 *priv, struct mvpp2_bm_pool *bm_pool) 532 { 533 int buf_num = 0; 534 535 buf_num += mvpp2_read(priv, MVPP2_BM_POOL_PTRS_NUM_REG(bm_pool->id)) & 536 MVPP22_BM_POOL_PTRS_NUM_MASK; 537 buf_num += mvpp2_read(priv, MVPP2_BM_BPPI_PTRS_NUM_REG(bm_pool->id)) & 538 MVPP2_BM_BPPI_PTR_NUM_MASK; 539 540 /* HW has one buffer ready which is not reflected in the counters */ 541 if (buf_num) 542 buf_num += 1; 543 544 return buf_num; 545 } 546 547 /* Cleanup pool */ 548 static int mvpp2_bm_pool_destroy(struct device *dev, struct mvpp2 *priv, 549 struct mvpp2_bm_pool *bm_pool) 550 { 551 int buf_num; 552 u32 val; 553 554 buf_num = mvpp2_check_hw_buf_num(priv, bm_pool); 555 mvpp2_bm_bufs_free(dev, priv, bm_pool, buf_num); 556 557 /* Check buffer counters after free */ 558 buf_num = mvpp2_check_hw_buf_num(priv, bm_pool); 559 if (buf_num) { 560 WARN(1, "cannot free all buffers in pool %d, buf_num left %d\n", 561 bm_pool->id, bm_pool->buf_num); 562 return 0; 563 } 564 565 val = mvpp2_read(priv, MVPP2_BM_POOL_CTRL_REG(bm_pool->id)); 566 val |= MVPP2_BM_STOP_MASK; 567 mvpp2_write(priv, MVPP2_BM_POOL_CTRL_REG(bm_pool->id), val); 568 569 if (priv->percpu_pools) { 570 page_pool_destroy(priv->page_pool[bm_pool->id]); 571 priv->page_pool[bm_pool->id] = NULL; 572 } 573 574 dma_free_coherent(dev, bm_pool->size_bytes, 575 bm_pool->virt_addr, 576 bm_pool->dma_addr); 577 return 0; 578 } 579 580 static int mvpp2_bm_pools_init(struct device *dev, struct mvpp2 *priv) 581 { 582 int i, err, size, poolnum = MVPP2_BM_POOLS_NUM; 583 struct mvpp2_bm_pool *bm_pool; 584 585 if (priv->percpu_pools) 586 poolnum = mvpp2_get_nrxqs(priv) * 2; 587 588 /* Create all pools with maximum size */ 589 size = MVPP2_BM_POOL_SIZE_MAX; 590 for (i = 0; i < poolnum; i++) { 591 bm_pool = &priv->bm_pools[i]; 592 bm_pool->id = i; 593 err = mvpp2_bm_pool_create(dev, priv, bm_pool, size); 594 if (err) 595 goto err_unroll_pools; 596 mvpp2_bm_pool_bufsize_set(priv, bm_pool, 0); 597 } 598 return 0; 599 600 err_unroll_pools: 601 dev_err(dev, "failed to create BM pool %d, size %d\n", i, size); 602 for (i = i - 1; i >= 0; i--) 603 mvpp2_bm_pool_destroy(dev, priv, &priv->bm_pools[i]); 604 return err; 605 } 606 607 /* Routine enable PPv23 8 pool mode */ 608 static void mvpp23_bm_set_8pool_mode(struct mvpp2 *priv) 609 { 610 int val; 611 612 val = mvpp2_read(priv, MVPP22_BM_POOL_BASE_ADDR_HIGH_REG); 613 val |= MVPP23_BM_8POOL_MODE; 614 mvpp2_write(priv, MVPP22_BM_POOL_BASE_ADDR_HIGH_REG, val); 615 } 616 617 static int mvpp2_bm_init(struct device *dev, struct mvpp2 *priv) 618 { 619 enum dma_data_direction dma_dir = DMA_FROM_DEVICE; 620 int i, err, poolnum = MVPP2_BM_POOLS_NUM; 621 struct mvpp2_port *port; 622 623 if (priv->percpu_pools) { 624 for (i = 0; i < priv->port_count; i++) { 625 port = priv->port_list[i]; 626 if (port->xdp_prog) { 627 dma_dir = DMA_BIDIRECTIONAL; 628 break; 629 } 630 } 631 632 poolnum = mvpp2_get_nrxqs(priv) * 2; 633 for (i = 0; i < poolnum; i++) { 634 /* the pool in use */ 635 int pn = i / (poolnum / 2); 636 637 priv->page_pool[i] = 638 mvpp2_create_page_pool(dev, 639 mvpp2_pools[pn].buf_num, 640 mvpp2_pools[pn].pkt_size, 641 dma_dir); 642 if (IS_ERR(priv->page_pool[i])) { 643 int j; 644 645 for (j = 0; j < i; j++) { 646 page_pool_destroy(priv->page_pool[j]); 647 priv->page_pool[j] = NULL; 648 } 649 return PTR_ERR(priv->page_pool[i]); 650 } 651 } 652 } 653 654 dev_info(dev, "using %d %s buffers\n", poolnum, 655 priv->percpu_pools ? "per-cpu" : "shared"); 656 657 for (i = 0; i < poolnum; i++) { 658 /* Mask BM all interrupts */ 659 mvpp2_write(priv, MVPP2_BM_INTR_MASK_REG(i), 0); 660 /* Clear BM cause register */ 661 mvpp2_write(priv, MVPP2_BM_INTR_CAUSE_REG(i), 0); 662 } 663 664 /* Allocate and initialize BM pools */ 665 priv->bm_pools = devm_kcalloc(dev, poolnum, 666 sizeof(*priv->bm_pools), GFP_KERNEL); 667 if (!priv->bm_pools) 668 return -ENOMEM; 669 670 if (priv->hw_version == MVPP23) 671 mvpp23_bm_set_8pool_mode(priv); 672 673 err = mvpp2_bm_pools_init(dev, priv); 674 if (err < 0) 675 return err; 676 return 0; 677 } 678 679 static void mvpp2_setup_bm_pool(void) 680 { 681 /* Short pool */ 682 mvpp2_pools[MVPP2_BM_SHORT].buf_num = MVPP2_BM_SHORT_BUF_NUM; 683 mvpp2_pools[MVPP2_BM_SHORT].pkt_size = MVPP2_BM_SHORT_PKT_SIZE; 684 685 /* Long pool */ 686 mvpp2_pools[MVPP2_BM_LONG].buf_num = MVPP2_BM_LONG_BUF_NUM; 687 mvpp2_pools[MVPP2_BM_LONG].pkt_size = MVPP2_BM_LONG_PKT_SIZE; 688 689 /* Jumbo pool */ 690 mvpp2_pools[MVPP2_BM_JUMBO].buf_num = MVPP2_BM_JUMBO_BUF_NUM; 691 mvpp2_pools[MVPP2_BM_JUMBO].pkt_size = MVPP2_BM_JUMBO_PKT_SIZE; 692 } 693 694 /* Attach long pool to rxq */ 695 static void mvpp2_rxq_long_pool_set(struct mvpp2_port *port, 696 int lrxq, int long_pool) 697 { 698 u32 val, mask; 699 int prxq; 700 701 /* Get queue physical ID */ 702 prxq = port->rxqs[lrxq]->id; 703 704 if (port->priv->hw_version == MVPP21) 705 mask = MVPP21_RXQ_POOL_LONG_MASK; 706 else 707 mask = MVPP22_RXQ_POOL_LONG_MASK; 708 709 val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(prxq)); 710 val &= ~mask; 711 val |= (long_pool << MVPP2_RXQ_POOL_LONG_OFFS) & mask; 712 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(prxq), val); 713 } 714 715 /* Attach short pool to rxq */ 716 static void mvpp2_rxq_short_pool_set(struct mvpp2_port *port, 717 int lrxq, int short_pool) 718 { 719 u32 val, mask; 720 int prxq; 721 722 /* Get queue physical ID */ 723 prxq = port->rxqs[lrxq]->id; 724 725 if (port->priv->hw_version == MVPP21) 726 mask = MVPP21_RXQ_POOL_SHORT_MASK; 727 else 728 mask = MVPP22_RXQ_POOL_SHORT_MASK; 729 730 val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(prxq)); 731 val &= ~mask; 732 val |= (short_pool << MVPP2_RXQ_POOL_SHORT_OFFS) & mask; 733 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(prxq), val); 734 } 735 736 static void *mvpp2_buf_alloc(struct mvpp2_port *port, 737 struct mvpp2_bm_pool *bm_pool, 738 struct page_pool *page_pool, 739 dma_addr_t *buf_dma_addr, 740 phys_addr_t *buf_phys_addr, 741 gfp_t gfp_mask) 742 { 743 dma_addr_t dma_addr; 744 struct page *page; 745 void *data; 746 747 data = mvpp2_frag_alloc(bm_pool, page_pool); 748 if (!data) 749 return NULL; 750 751 if (page_pool) { 752 page = (struct page *)data; 753 dma_addr = page_pool_get_dma_addr(page); 754 data = page_to_virt(page); 755 } else { 756 dma_addr = dma_map_single(port->dev->dev.parent, data, 757 MVPP2_RX_BUF_SIZE(bm_pool->pkt_size), 758 DMA_FROM_DEVICE); 759 if (unlikely(dma_mapping_error(port->dev->dev.parent, dma_addr))) { 760 mvpp2_frag_free(bm_pool, NULL, data); 761 return NULL; 762 } 763 } 764 *buf_dma_addr = dma_addr; 765 *buf_phys_addr = virt_to_phys(data); 766 767 return data; 768 } 769 770 /* Routine enable flow control for RXQs condition */ 771 static void mvpp2_rxq_enable_fc(struct mvpp2_port *port) 772 { 773 int val, cm3_state, host_id, q; 774 int fq = port->first_rxq; 775 unsigned long flags; 776 777 spin_lock_irqsave(&port->priv->mss_spinlock, flags); 778 779 /* Remove Flow control enable bit to prevent race between FW and Kernel 780 * If Flow control was enabled, it would be re-enabled. 781 */ 782 val = mvpp2_cm3_read(port->priv, MSS_FC_COM_REG); 783 cm3_state = (val & FLOW_CONTROL_ENABLE_BIT); 784 val &= ~FLOW_CONTROL_ENABLE_BIT; 785 mvpp2_cm3_write(port->priv, MSS_FC_COM_REG, val); 786 787 /* Set same Flow control for all RXQs */ 788 for (q = 0; q < port->nrxqs; q++) { 789 /* Set stop and start Flow control RXQ thresholds */ 790 val = MSS_THRESHOLD_START; 791 val |= (MSS_THRESHOLD_STOP << MSS_RXQ_TRESH_STOP_OFFS); 792 mvpp2_cm3_write(port->priv, MSS_RXQ_TRESH_REG(q, fq), val); 793 794 val = mvpp2_cm3_read(port->priv, MSS_RXQ_ASS_REG(q, fq)); 795 /* Set RXQ port ID */ 796 val &= ~(MSS_RXQ_ASS_PORTID_MASK << MSS_RXQ_ASS_Q_BASE(q, fq)); 797 val |= (port->id << MSS_RXQ_ASS_Q_BASE(q, fq)); 798 val &= ~(MSS_RXQ_ASS_HOSTID_MASK << (MSS_RXQ_ASS_Q_BASE(q, fq) 799 + MSS_RXQ_ASS_HOSTID_OFFS)); 800 801 /* Calculate RXQ host ID: 802 * In Single queue mode: Host ID equal to Host ID used for 803 * shared RX interrupt 804 * In Multi queue mode: Host ID equal to number of 805 * RXQ ID / number of CoS queues 806 * In Single resource mode: Host ID always equal to 0 807 */ 808 if (queue_mode == MVPP2_QDIST_SINGLE_MODE) 809 host_id = port->nqvecs; 810 else if (queue_mode == MVPP2_QDIST_MULTI_MODE) 811 host_id = q; 812 else 813 host_id = 0; 814 815 /* Set RXQ host ID */ 816 val |= (host_id << (MSS_RXQ_ASS_Q_BASE(q, fq) 817 + MSS_RXQ_ASS_HOSTID_OFFS)); 818 819 mvpp2_cm3_write(port->priv, MSS_RXQ_ASS_REG(q, fq), val); 820 } 821 822 /* Notify Firmware that Flow control config space ready for update */ 823 val = mvpp2_cm3_read(port->priv, MSS_FC_COM_REG); 824 val |= FLOW_CONTROL_UPDATE_COMMAND_BIT; 825 val |= cm3_state; 826 mvpp2_cm3_write(port->priv, MSS_FC_COM_REG, val); 827 828 spin_unlock_irqrestore(&port->priv->mss_spinlock, flags); 829 } 830 831 /* Routine disable flow control for RXQs condition */ 832 static void mvpp2_rxq_disable_fc(struct mvpp2_port *port) 833 { 834 int val, cm3_state, q; 835 unsigned long flags; 836 int fq = port->first_rxq; 837 838 spin_lock_irqsave(&port->priv->mss_spinlock, flags); 839 840 /* Remove Flow control enable bit to prevent race between FW and Kernel 841 * If Flow control was enabled, it would be re-enabled. 842 */ 843 val = mvpp2_cm3_read(port->priv, MSS_FC_COM_REG); 844 cm3_state = (val & FLOW_CONTROL_ENABLE_BIT); 845 val &= ~FLOW_CONTROL_ENABLE_BIT; 846 mvpp2_cm3_write(port->priv, MSS_FC_COM_REG, val); 847 848 /* Disable Flow control for all RXQs */ 849 for (q = 0; q < port->nrxqs; q++) { 850 /* Set threshold 0 to disable Flow control */ 851 val = 0; 852 val |= (0 << MSS_RXQ_TRESH_STOP_OFFS); 853 mvpp2_cm3_write(port->priv, MSS_RXQ_TRESH_REG(q, fq), val); 854 855 val = mvpp2_cm3_read(port->priv, MSS_RXQ_ASS_REG(q, fq)); 856 857 val &= ~(MSS_RXQ_ASS_PORTID_MASK << MSS_RXQ_ASS_Q_BASE(q, fq)); 858 859 val &= ~(MSS_RXQ_ASS_HOSTID_MASK << (MSS_RXQ_ASS_Q_BASE(q, fq) 860 + MSS_RXQ_ASS_HOSTID_OFFS)); 861 862 mvpp2_cm3_write(port->priv, MSS_RXQ_ASS_REG(q, fq), val); 863 } 864 865 /* Notify Firmware that Flow control config space ready for update */ 866 val = mvpp2_cm3_read(port->priv, MSS_FC_COM_REG); 867 val |= FLOW_CONTROL_UPDATE_COMMAND_BIT; 868 val |= cm3_state; 869 mvpp2_cm3_write(port->priv, MSS_FC_COM_REG, val); 870 871 spin_unlock_irqrestore(&port->priv->mss_spinlock, flags); 872 } 873 874 /* Routine disable/enable flow control for BM pool condition */ 875 static void mvpp2_bm_pool_update_fc(struct mvpp2_port *port, 876 struct mvpp2_bm_pool *pool, 877 bool en) 878 { 879 int val, cm3_state; 880 unsigned long flags; 881 882 spin_lock_irqsave(&port->priv->mss_spinlock, flags); 883 884 /* Remove Flow control enable bit to prevent race between FW and Kernel 885 * If Flow control were enabled, it would be re-enabled. 886 */ 887 val = mvpp2_cm3_read(port->priv, MSS_FC_COM_REG); 888 cm3_state = (val & FLOW_CONTROL_ENABLE_BIT); 889 val &= ~FLOW_CONTROL_ENABLE_BIT; 890 mvpp2_cm3_write(port->priv, MSS_FC_COM_REG, val); 891 892 /* Check if BM pool should be enabled/disable */ 893 if (en) { 894 /* Set BM pool start and stop thresholds per port */ 895 val = mvpp2_cm3_read(port->priv, MSS_BUF_POOL_REG(pool->id)); 896 val |= MSS_BUF_POOL_PORT_OFFS(port->id); 897 val &= ~MSS_BUF_POOL_START_MASK; 898 val |= (MSS_THRESHOLD_START << MSS_BUF_POOL_START_OFFS); 899 val &= ~MSS_BUF_POOL_STOP_MASK; 900 val |= MSS_THRESHOLD_STOP; 901 mvpp2_cm3_write(port->priv, MSS_BUF_POOL_REG(pool->id), val); 902 } else { 903 /* Remove BM pool from the port */ 904 val = mvpp2_cm3_read(port->priv, MSS_BUF_POOL_REG(pool->id)); 905 val &= ~MSS_BUF_POOL_PORT_OFFS(port->id); 906 907 /* Zero BM pool start and stop thresholds to disable pool 908 * flow control if pool empty (not used by any port) 909 */ 910 if (!pool->buf_num) { 911 val &= ~MSS_BUF_POOL_START_MASK; 912 val &= ~MSS_BUF_POOL_STOP_MASK; 913 } 914 915 mvpp2_cm3_write(port->priv, MSS_BUF_POOL_REG(pool->id), val); 916 } 917 918 /* Notify Firmware that Flow control config space ready for update */ 919 val = mvpp2_cm3_read(port->priv, MSS_FC_COM_REG); 920 val |= FLOW_CONTROL_UPDATE_COMMAND_BIT; 921 val |= cm3_state; 922 mvpp2_cm3_write(port->priv, MSS_FC_COM_REG, val); 923 924 spin_unlock_irqrestore(&port->priv->mss_spinlock, flags); 925 } 926 927 static int mvpp2_enable_global_fc(struct mvpp2 *priv) 928 { 929 int val, timeout = 0; 930 931 /* Enable global flow control. In this stage global 932 * flow control enabled, but still disabled per port. 933 */ 934 val = mvpp2_cm3_read(priv, MSS_FC_COM_REG); 935 val |= FLOW_CONTROL_ENABLE_BIT; 936 mvpp2_cm3_write(priv, MSS_FC_COM_REG, val); 937 938 /* Check if Firmware running and disable FC if not*/ 939 val |= FLOW_CONTROL_UPDATE_COMMAND_BIT; 940 mvpp2_cm3_write(priv, MSS_FC_COM_REG, val); 941 942 while (timeout < MSS_FC_MAX_TIMEOUT) { 943 val = mvpp2_cm3_read(priv, MSS_FC_COM_REG); 944 945 if (!(val & FLOW_CONTROL_UPDATE_COMMAND_BIT)) 946 return 0; 947 usleep_range(10, 20); 948 timeout++; 949 } 950 951 priv->global_tx_fc = false; 952 return -EOPNOTSUPP; 953 } 954 955 /* Release buffer to BM */ 956 static inline void mvpp2_bm_pool_put(struct mvpp2_port *port, int pool, 957 dma_addr_t buf_dma_addr, 958 phys_addr_t buf_phys_addr) 959 { 960 unsigned int thread = mvpp2_cpu_to_thread(port->priv, get_cpu()); 961 unsigned long flags = 0; 962 963 if (test_bit(thread, &port->priv->lock_map)) 964 spin_lock_irqsave(&port->bm_lock[thread], flags); 965 966 if (port->priv->hw_version != MVPP21) { 967 u32 val = 0; 968 969 if (sizeof(dma_addr_t) == 8) 970 val |= upper_32_bits(buf_dma_addr) & 971 MVPP22_BM_ADDR_HIGH_PHYS_RLS_MASK; 972 973 if (sizeof(phys_addr_t) == 8) 974 val |= (upper_32_bits(buf_phys_addr) 975 << MVPP22_BM_ADDR_HIGH_VIRT_RLS_SHIFT) & 976 MVPP22_BM_ADDR_HIGH_VIRT_RLS_MASK; 977 978 mvpp2_thread_write_relaxed(port->priv, thread, 979 MVPP22_BM_ADDR_HIGH_RLS_REG, val); 980 } 981 982 /* MVPP2_BM_VIRT_RLS_REG is not interpreted by HW, and simply 983 * returned in the "cookie" field of the RX 984 * descriptor. Instead of storing the virtual address, we 985 * store the physical address 986 */ 987 mvpp2_thread_write_relaxed(port->priv, thread, 988 MVPP2_BM_VIRT_RLS_REG, buf_phys_addr); 989 mvpp2_thread_write_relaxed(port->priv, thread, 990 MVPP2_BM_PHY_RLS_REG(pool), buf_dma_addr); 991 992 if (test_bit(thread, &port->priv->lock_map)) 993 spin_unlock_irqrestore(&port->bm_lock[thread], flags); 994 995 put_cpu(); 996 } 997 998 /* Allocate buffers for the pool */ 999 static int mvpp2_bm_bufs_add(struct mvpp2_port *port, 1000 struct mvpp2_bm_pool *bm_pool, int buf_num) 1001 { 1002 int i, buf_size, total_size; 1003 dma_addr_t dma_addr; 1004 phys_addr_t phys_addr; 1005 struct page_pool *pp = NULL; 1006 void *buf; 1007 1008 if (port->priv->percpu_pools && 1009 bm_pool->pkt_size > MVPP2_BM_LONG_PKT_SIZE) { 1010 netdev_err(port->dev, 1011 "attempted to use jumbo frames with per-cpu pools"); 1012 return 0; 1013 } 1014 1015 buf_size = MVPP2_RX_BUF_SIZE(bm_pool->pkt_size); 1016 total_size = MVPP2_RX_TOTAL_SIZE(buf_size); 1017 1018 if (buf_num < 0 || 1019 (buf_num + bm_pool->buf_num > bm_pool->size)) { 1020 netdev_err(port->dev, 1021 "cannot allocate %d buffers for pool %d\n", 1022 buf_num, bm_pool->id); 1023 return 0; 1024 } 1025 1026 if (port->priv->percpu_pools) 1027 pp = port->priv->page_pool[bm_pool->id]; 1028 for (i = 0; i < buf_num; i++) { 1029 buf = mvpp2_buf_alloc(port, bm_pool, pp, &dma_addr, 1030 &phys_addr, GFP_KERNEL); 1031 if (!buf) 1032 break; 1033 1034 mvpp2_bm_pool_put(port, bm_pool->id, dma_addr, 1035 phys_addr); 1036 } 1037 1038 /* Update BM driver with number of buffers added to pool */ 1039 bm_pool->buf_num += i; 1040 1041 netdev_dbg(port->dev, 1042 "pool %d: pkt_size=%4d, buf_size=%4d, total_size=%4d\n", 1043 bm_pool->id, bm_pool->pkt_size, buf_size, total_size); 1044 1045 netdev_dbg(port->dev, 1046 "pool %d: %d of %d buffers added\n", 1047 bm_pool->id, i, buf_num); 1048 return i; 1049 } 1050 1051 /* Notify the driver that BM pool is being used as specific type and return the 1052 * pool pointer on success 1053 */ 1054 static struct mvpp2_bm_pool * 1055 mvpp2_bm_pool_use(struct mvpp2_port *port, unsigned pool, int pkt_size) 1056 { 1057 struct mvpp2_bm_pool *new_pool = &port->priv->bm_pools[pool]; 1058 int num; 1059 1060 if ((port->priv->percpu_pools && pool > mvpp2_get_nrxqs(port->priv) * 2) || 1061 (!port->priv->percpu_pools && pool >= MVPP2_BM_POOLS_NUM)) { 1062 netdev_err(port->dev, "Invalid pool %d\n", pool); 1063 return NULL; 1064 } 1065 1066 /* Allocate buffers in case BM pool is used as long pool, but packet 1067 * size doesn't match MTU or BM pool hasn't being used yet 1068 */ 1069 if (new_pool->pkt_size == 0) { 1070 int pkts_num; 1071 1072 /* Set default buffer number or free all the buffers in case 1073 * the pool is not empty 1074 */ 1075 pkts_num = new_pool->buf_num; 1076 if (pkts_num == 0) { 1077 if (port->priv->percpu_pools) { 1078 if (pool < port->nrxqs) 1079 pkts_num = mvpp2_pools[MVPP2_BM_SHORT].buf_num; 1080 else 1081 pkts_num = mvpp2_pools[MVPP2_BM_LONG].buf_num; 1082 } else { 1083 pkts_num = mvpp2_pools[pool].buf_num; 1084 } 1085 } else { 1086 mvpp2_bm_bufs_free(port->dev->dev.parent, 1087 port->priv, new_pool, pkts_num); 1088 } 1089 1090 new_pool->pkt_size = pkt_size; 1091 new_pool->frag_size = 1092 SKB_DATA_ALIGN(MVPP2_RX_BUF_SIZE(pkt_size)) + 1093 MVPP2_SKB_SHINFO_SIZE; 1094 1095 /* Allocate buffers for this pool */ 1096 num = mvpp2_bm_bufs_add(port, new_pool, pkts_num); 1097 if (num != pkts_num) { 1098 WARN(1, "pool %d: %d of %d allocated\n", 1099 new_pool->id, num, pkts_num); 1100 return NULL; 1101 } 1102 } 1103 1104 mvpp2_bm_pool_bufsize_set(port->priv, new_pool, 1105 MVPP2_RX_BUF_SIZE(new_pool->pkt_size)); 1106 1107 return new_pool; 1108 } 1109 1110 static struct mvpp2_bm_pool * 1111 mvpp2_bm_pool_use_percpu(struct mvpp2_port *port, int type, 1112 unsigned int pool, int pkt_size) 1113 { 1114 struct mvpp2_bm_pool *new_pool = &port->priv->bm_pools[pool]; 1115 int num; 1116 1117 if (pool > port->nrxqs * 2) { 1118 netdev_err(port->dev, "Invalid pool %d\n", pool); 1119 return NULL; 1120 } 1121 1122 /* Allocate buffers in case BM pool is used as long pool, but packet 1123 * size doesn't match MTU or BM pool hasn't being used yet 1124 */ 1125 if (new_pool->pkt_size == 0) { 1126 int pkts_num; 1127 1128 /* Set default buffer number or free all the buffers in case 1129 * the pool is not empty 1130 */ 1131 pkts_num = new_pool->buf_num; 1132 if (pkts_num == 0) 1133 pkts_num = mvpp2_pools[type].buf_num; 1134 else 1135 mvpp2_bm_bufs_free(port->dev->dev.parent, 1136 port->priv, new_pool, pkts_num); 1137 1138 new_pool->pkt_size = pkt_size; 1139 new_pool->frag_size = 1140 SKB_DATA_ALIGN(MVPP2_RX_BUF_SIZE(pkt_size)) + 1141 MVPP2_SKB_SHINFO_SIZE; 1142 1143 /* Allocate buffers for this pool */ 1144 num = mvpp2_bm_bufs_add(port, new_pool, pkts_num); 1145 if (num != pkts_num) { 1146 WARN(1, "pool %d: %d of %d allocated\n", 1147 new_pool->id, num, pkts_num); 1148 return NULL; 1149 } 1150 } 1151 1152 mvpp2_bm_pool_bufsize_set(port->priv, new_pool, 1153 MVPP2_RX_BUF_SIZE(new_pool->pkt_size)); 1154 1155 return new_pool; 1156 } 1157 1158 /* Initialize pools for swf, shared buffers variant */ 1159 static int mvpp2_swf_bm_pool_init_shared(struct mvpp2_port *port) 1160 { 1161 enum mvpp2_bm_pool_log_num long_log_pool, short_log_pool; 1162 int rxq; 1163 1164 /* If port pkt_size is higher than 1518B: 1165 * HW Long pool - SW Jumbo pool, HW Short pool - SW Long pool 1166 * else: HW Long pool - SW Long pool, HW Short pool - SW Short pool 1167 */ 1168 if (port->pkt_size > MVPP2_BM_LONG_PKT_SIZE) { 1169 long_log_pool = MVPP2_BM_JUMBO; 1170 short_log_pool = MVPP2_BM_LONG; 1171 } else { 1172 long_log_pool = MVPP2_BM_LONG; 1173 short_log_pool = MVPP2_BM_SHORT; 1174 } 1175 1176 if (!port->pool_long) { 1177 port->pool_long = 1178 mvpp2_bm_pool_use(port, long_log_pool, 1179 mvpp2_pools[long_log_pool].pkt_size); 1180 if (!port->pool_long) 1181 return -ENOMEM; 1182 1183 port->pool_long->port_map |= BIT(port->id); 1184 1185 for (rxq = 0; rxq < port->nrxqs; rxq++) 1186 mvpp2_rxq_long_pool_set(port, rxq, port->pool_long->id); 1187 } 1188 1189 if (!port->pool_short) { 1190 port->pool_short = 1191 mvpp2_bm_pool_use(port, short_log_pool, 1192 mvpp2_pools[short_log_pool].pkt_size); 1193 if (!port->pool_short) 1194 return -ENOMEM; 1195 1196 port->pool_short->port_map |= BIT(port->id); 1197 1198 for (rxq = 0; rxq < port->nrxqs; rxq++) 1199 mvpp2_rxq_short_pool_set(port, rxq, 1200 port->pool_short->id); 1201 } 1202 1203 return 0; 1204 } 1205 1206 /* Initialize pools for swf, percpu buffers variant */ 1207 static int mvpp2_swf_bm_pool_init_percpu(struct mvpp2_port *port) 1208 { 1209 struct mvpp2_bm_pool *bm_pool; 1210 int i; 1211 1212 for (i = 0; i < port->nrxqs; i++) { 1213 bm_pool = mvpp2_bm_pool_use_percpu(port, MVPP2_BM_SHORT, i, 1214 mvpp2_pools[MVPP2_BM_SHORT].pkt_size); 1215 if (!bm_pool) 1216 return -ENOMEM; 1217 1218 bm_pool->port_map |= BIT(port->id); 1219 mvpp2_rxq_short_pool_set(port, i, bm_pool->id); 1220 } 1221 1222 for (i = 0; i < port->nrxqs; i++) { 1223 bm_pool = mvpp2_bm_pool_use_percpu(port, MVPP2_BM_LONG, i + port->nrxqs, 1224 mvpp2_pools[MVPP2_BM_LONG].pkt_size); 1225 if (!bm_pool) 1226 return -ENOMEM; 1227 1228 bm_pool->port_map |= BIT(port->id); 1229 mvpp2_rxq_long_pool_set(port, i, bm_pool->id); 1230 } 1231 1232 port->pool_long = NULL; 1233 port->pool_short = NULL; 1234 1235 return 0; 1236 } 1237 1238 static int mvpp2_swf_bm_pool_init(struct mvpp2_port *port) 1239 { 1240 if (port->priv->percpu_pools) 1241 return mvpp2_swf_bm_pool_init_percpu(port); 1242 else 1243 return mvpp2_swf_bm_pool_init_shared(port); 1244 } 1245 1246 static void mvpp2_set_hw_csum(struct mvpp2_port *port, 1247 enum mvpp2_bm_pool_log_num new_long_pool) 1248 { 1249 const netdev_features_t csums = NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM; 1250 1251 /* Update L4 checksum when jumbo enable/disable on port. 1252 * Only port 0 supports hardware checksum offload due to 1253 * the Tx FIFO size limitation. 1254 * Also, don't set NETIF_F_HW_CSUM because L3_offset in TX descriptor 1255 * has 7 bits, so the maximum L3 offset is 128. 1256 */ 1257 if (new_long_pool == MVPP2_BM_JUMBO && port->id != 0) { 1258 port->dev->features &= ~csums; 1259 port->dev->hw_features &= ~csums; 1260 } else { 1261 port->dev->features |= csums; 1262 port->dev->hw_features |= csums; 1263 } 1264 } 1265 1266 static int mvpp2_bm_update_mtu(struct net_device *dev, int mtu) 1267 { 1268 struct mvpp2_port *port = netdev_priv(dev); 1269 enum mvpp2_bm_pool_log_num new_long_pool; 1270 int pkt_size = MVPP2_RX_PKT_SIZE(mtu); 1271 1272 if (port->priv->percpu_pools) 1273 goto out_set; 1274 1275 /* If port MTU is higher than 1518B: 1276 * HW Long pool - SW Jumbo pool, HW Short pool - SW Long pool 1277 * else: HW Long pool - SW Long pool, HW Short pool - SW Short pool 1278 */ 1279 if (pkt_size > MVPP2_BM_LONG_PKT_SIZE) 1280 new_long_pool = MVPP2_BM_JUMBO; 1281 else 1282 new_long_pool = MVPP2_BM_LONG; 1283 1284 if (new_long_pool != port->pool_long->id) { 1285 if (port->tx_fc) { 1286 if (pkt_size > MVPP2_BM_LONG_PKT_SIZE) 1287 mvpp2_bm_pool_update_fc(port, 1288 port->pool_short, 1289 false); 1290 else 1291 mvpp2_bm_pool_update_fc(port, port->pool_long, 1292 false); 1293 } 1294 1295 /* Remove port from old short & long pool */ 1296 port->pool_long = mvpp2_bm_pool_use(port, port->pool_long->id, 1297 port->pool_long->pkt_size); 1298 port->pool_long->port_map &= ~BIT(port->id); 1299 port->pool_long = NULL; 1300 1301 port->pool_short = mvpp2_bm_pool_use(port, port->pool_short->id, 1302 port->pool_short->pkt_size); 1303 port->pool_short->port_map &= ~BIT(port->id); 1304 port->pool_short = NULL; 1305 1306 port->pkt_size = pkt_size; 1307 1308 /* Add port to new short & long pool */ 1309 mvpp2_swf_bm_pool_init(port); 1310 1311 mvpp2_set_hw_csum(port, new_long_pool); 1312 1313 if (port->tx_fc) { 1314 if (pkt_size > MVPP2_BM_LONG_PKT_SIZE) 1315 mvpp2_bm_pool_update_fc(port, port->pool_long, 1316 true); 1317 else 1318 mvpp2_bm_pool_update_fc(port, port->pool_short, 1319 true); 1320 } 1321 1322 /* Update L4 checksum when jumbo enable/disable on port */ 1323 if (new_long_pool == MVPP2_BM_JUMBO && port->id != 0) { 1324 dev->features &= ~(NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM); 1325 dev->hw_features &= ~(NETIF_F_IP_CSUM | 1326 NETIF_F_IPV6_CSUM); 1327 } else { 1328 dev->features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM; 1329 dev->hw_features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM; 1330 } 1331 } 1332 1333 out_set: 1334 dev->mtu = mtu; 1335 dev->wanted_features = dev->features; 1336 1337 netdev_update_features(dev); 1338 return 0; 1339 } 1340 1341 static inline void mvpp2_interrupts_enable(struct mvpp2_port *port) 1342 { 1343 int i, sw_thread_mask = 0; 1344 1345 for (i = 0; i < port->nqvecs; i++) 1346 sw_thread_mask |= port->qvecs[i].sw_thread_mask; 1347 1348 mvpp2_write(port->priv, MVPP2_ISR_ENABLE_REG(port->id), 1349 MVPP2_ISR_ENABLE_INTERRUPT(sw_thread_mask)); 1350 } 1351 1352 static inline void mvpp2_interrupts_disable(struct mvpp2_port *port) 1353 { 1354 int i, sw_thread_mask = 0; 1355 1356 for (i = 0; i < port->nqvecs; i++) 1357 sw_thread_mask |= port->qvecs[i].sw_thread_mask; 1358 1359 mvpp2_write(port->priv, MVPP2_ISR_ENABLE_REG(port->id), 1360 MVPP2_ISR_DISABLE_INTERRUPT(sw_thread_mask)); 1361 } 1362 1363 static inline void mvpp2_qvec_interrupt_enable(struct mvpp2_queue_vector *qvec) 1364 { 1365 struct mvpp2_port *port = qvec->port; 1366 1367 mvpp2_write(port->priv, MVPP2_ISR_ENABLE_REG(port->id), 1368 MVPP2_ISR_ENABLE_INTERRUPT(qvec->sw_thread_mask)); 1369 } 1370 1371 static inline void mvpp2_qvec_interrupt_disable(struct mvpp2_queue_vector *qvec) 1372 { 1373 struct mvpp2_port *port = qvec->port; 1374 1375 mvpp2_write(port->priv, MVPP2_ISR_ENABLE_REG(port->id), 1376 MVPP2_ISR_DISABLE_INTERRUPT(qvec->sw_thread_mask)); 1377 } 1378 1379 /* Mask the current thread's Rx/Tx interrupts 1380 * Called by on_each_cpu(), guaranteed to run with migration disabled, 1381 * using smp_processor_id() is OK. 1382 */ 1383 static void mvpp2_interrupts_mask(void *arg) 1384 { 1385 struct mvpp2_port *port = arg; 1386 int cpu = smp_processor_id(); 1387 u32 thread; 1388 1389 /* If the thread isn't used, don't do anything */ 1390 if (cpu > port->priv->nthreads) 1391 return; 1392 1393 thread = mvpp2_cpu_to_thread(port->priv, cpu); 1394 1395 mvpp2_thread_write(port->priv, thread, 1396 MVPP2_ISR_RX_TX_MASK_REG(port->id), 0); 1397 mvpp2_thread_write(port->priv, thread, 1398 MVPP2_ISR_RX_ERR_CAUSE_REG(port->id), 0); 1399 } 1400 1401 /* Unmask the current thread's Rx/Tx interrupts. 1402 * Called by on_each_cpu(), guaranteed to run with migration disabled, 1403 * using smp_processor_id() is OK. 1404 */ 1405 static void mvpp2_interrupts_unmask(void *arg) 1406 { 1407 struct mvpp2_port *port = arg; 1408 int cpu = smp_processor_id(); 1409 u32 val, thread; 1410 1411 /* If the thread isn't used, don't do anything */ 1412 if (cpu > port->priv->nthreads) 1413 return; 1414 1415 thread = mvpp2_cpu_to_thread(port->priv, cpu); 1416 1417 val = MVPP2_CAUSE_MISC_SUM_MASK | 1418 MVPP2_CAUSE_RXQ_OCCUP_DESC_ALL_MASK(port->priv->hw_version); 1419 if (port->has_tx_irqs) 1420 val |= MVPP2_CAUSE_TXQ_OCCUP_DESC_ALL_MASK; 1421 1422 mvpp2_thread_write(port->priv, thread, 1423 MVPP2_ISR_RX_TX_MASK_REG(port->id), val); 1424 mvpp2_thread_write(port->priv, thread, 1425 MVPP2_ISR_RX_ERR_CAUSE_REG(port->id), 1426 MVPP2_ISR_RX_ERR_CAUSE_NONOCC_MASK); 1427 } 1428 1429 static void 1430 mvpp2_shared_interrupt_mask_unmask(struct mvpp2_port *port, bool mask) 1431 { 1432 u32 val; 1433 int i; 1434 1435 if (port->priv->hw_version == MVPP21) 1436 return; 1437 1438 if (mask) 1439 val = 0; 1440 else 1441 val = MVPP2_CAUSE_RXQ_OCCUP_DESC_ALL_MASK(MVPP22); 1442 1443 for (i = 0; i < port->nqvecs; i++) { 1444 struct mvpp2_queue_vector *v = port->qvecs + i; 1445 1446 if (v->type != MVPP2_QUEUE_VECTOR_SHARED) 1447 continue; 1448 1449 mvpp2_thread_write(port->priv, v->sw_thread_id, 1450 MVPP2_ISR_RX_TX_MASK_REG(port->id), val); 1451 mvpp2_thread_write(port->priv, v->sw_thread_id, 1452 MVPP2_ISR_RX_ERR_CAUSE_REG(port->id), 1453 MVPP2_ISR_RX_ERR_CAUSE_NONOCC_MASK); 1454 } 1455 } 1456 1457 /* Only GOP port 0 has an XLG MAC */ 1458 static bool mvpp2_port_supports_xlg(struct mvpp2_port *port) 1459 { 1460 return port->gop_id == 0; 1461 } 1462 1463 static bool mvpp2_port_supports_rgmii(struct mvpp2_port *port) 1464 { 1465 return !(port->priv->hw_version != MVPP21 && port->gop_id == 0); 1466 } 1467 1468 /* Port configuration routines */ 1469 static bool mvpp2_is_xlg(phy_interface_t interface) 1470 { 1471 return interface == PHY_INTERFACE_MODE_10GBASER || 1472 interface == PHY_INTERFACE_MODE_XAUI; 1473 } 1474 1475 static void mvpp2_modify(void __iomem *ptr, u32 mask, u32 set) 1476 { 1477 u32 old, val; 1478 1479 old = val = readl(ptr); 1480 val &= ~mask; 1481 val |= set; 1482 if (old != val) 1483 writel(val, ptr); 1484 } 1485 1486 static void mvpp22_gop_init_rgmii(struct mvpp2_port *port) 1487 { 1488 struct mvpp2 *priv = port->priv; 1489 u32 val; 1490 1491 regmap_read(priv->sysctrl_base, GENCONF_PORT_CTRL0, &val); 1492 val |= GENCONF_PORT_CTRL0_BUS_WIDTH_SELECT; 1493 regmap_write(priv->sysctrl_base, GENCONF_PORT_CTRL0, val); 1494 1495 regmap_read(priv->sysctrl_base, GENCONF_CTRL0, &val); 1496 if (port->gop_id == 2) 1497 val |= GENCONF_CTRL0_PORT0_RGMII; 1498 else if (port->gop_id == 3) 1499 val |= GENCONF_CTRL0_PORT1_RGMII_MII; 1500 regmap_write(priv->sysctrl_base, GENCONF_CTRL0, val); 1501 } 1502 1503 static void mvpp22_gop_init_sgmii(struct mvpp2_port *port) 1504 { 1505 struct mvpp2 *priv = port->priv; 1506 u32 val; 1507 1508 regmap_read(priv->sysctrl_base, GENCONF_PORT_CTRL0, &val); 1509 val |= GENCONF_PORT_CTRL0_BUS_WIDTH_SELECT | 1510 GENCONF_PORT_CTRL0_RX_DATA_SAMPLE; 1511 regmap_write(priv->sysctrl_base, GENCONF_PORT_CTRL0, val); 1512 1513 if (port->gop_id > 1) { 1514 regmap_read(priv->sysctrl_base, GENCONF_CTRL0, &val); 1515 if (port->gop_id == 2) 1516 val &= ~GENCONF_CTRL0_PORT0_RGMII; 1517 else if (port->gop_id == 3) 1518 val &= ~GENCONF_CTRL0_PORT1_RGMII_MII; 1519 regmap_write(priv->sysctrl_base, GENCONF_CTRL0, val); 1520 } 1521 } 1522 1523 static void mvpp22_gop_init_10gkr(struct mvpp2_port *port) 1524 { 1525 struct mvpp2 *priv = port->priv; 1526 void __iomem *mpcs = priv->iface_base + MVPP22_MPCS_BASE(port->gop_id); 1527 void __iomem *xpcs = priv->iface_base + MVPP22_XPCS_BASE(port->gop_id); 1528 u32 val; 1529 1530 val = readl(xpcs + MVPP22_XPCS_CFG0); 1531 val &= ~(MVPP22_XPCS_CFG0_PCS_MODE(0x3) | 1532 MVPP22_XPCS_CFG0_ACTIVE_LANE(0x3)); 1533 val |= MVPP22_XPCS_CFG0_ACTIVE_LANE(2); 1534 writel(val, xpcs + MVPP22_XPCS_CFG0); 1535 1536 val = readl(mpcs + MVPP22_MPCS_CTRL); 1537 val &= ~MVPP22_MPCS_CTRL_FWD_ERR_CONN; 1538 writel(val, mpcs + MVPP22_MPCS_CTRL); 1539 1540 val = readl(mpcs + MVPP22_MPCS_CLK_RESET); 1541 val &= ~MVPP22_MPCS_CLK_RESET_DIV_RATIO(0x7); 1542 val |= MVPP22_MPCS_CLK_RESET_DIV_RATIO(1); 1543 writel(val, mpcs + MVPP22_MPCS_CLK_RESET); 1544 } 1545 1546 static void mvpp22_gop_fca_enable_periodic(struct mvpp2_port *port, bool en) 1547 { 1548 struct mvpp2 *priv = port->priv; 1549 void __iomem *fca = priv->iface_base + MVPP22_FCA_BASE(port->gop_id); 1550 u32 val; 1551 1552 val = readl(fca + MVPP22_FCA_CONTROL_REG); 1553 val &= ~MVPP22_FCA_ENABLE_PERIODIC; 1554 if (en) 1555 val |= MVPP22_FCA_ENABLE_PERIODIC; 1556 writel(val, fca + MVPP22_FCA_CONTROL_REG); 1557 } 1558 1559 static void mvpp22_gop_fca_set_timer(struct mvpp2_port *port, u32 timer) 1560 { 1561 struct mvpp2 *priv = port->priv; 1562 void __iomem *fca = priv->iface_base + MVPP22_FCA_BASE(port->gop_id); 1563 u32 lsb, msb; 1564 1565 lsb = timer & MVPP22_FCA_REG_MASK; 1566 msb = timer >> MVPP22_FCA_REG_SIZE; 1567 1568 writel(lsb, fca + MVPP22_PERIODIC_COUNTER_LSB_REG); 1569 writel(msb, fca + MVPP22_PERIODIC_COUNTER_MSB_REG); 1570 } 1571 1572 /* Set Flow Control timer x100 faster than pause quanta to ensure that link 1573 * partner won't send traffic if port is in XOFF mode. 1574 */ 1575 static void mvpp22_gop_fca_set_periodic_timer(struct mvpp2_port *port) 1576 { 1577 u32 timer; 1578 1579 timer = (port->priv->tclk / (USEC_PER_SEC * FC_CLK_DIVIDER)) 1580 * FC_QUANTA; 1581 1582 mvpp22_gop_fca_enable_periodic(port, false); 1583 1584 mvpp22_gop_fca_set_timer(port, timer); 1585 1586 mvpp22_gop_fca_enable_periodic(port, true); 1587 } 1588 1589 static int mvpp22_gop_init(struct mvpp2_port *port) 1590 { 1591 struct mvpp2 *priv = port->priv; 1592 u32 val; 1593 1594 if (!priv->sysctrl_base) 1595 return 0; 1596 1597 switch (port->phy_interface) { 1598 case PHY_INTERFACE_MODE_RGMII: 1599 case PHY_INTERFACE_MODE_RGMII_ID: 1600 case PHY_INTERFACE_MODE_RGMII_RXID: 1601 case PHY_INTERFACE_MODE_RGMII_TXID: 1602 if (!mvpp2_port_supports_rgmii(port)) 1603 goto invalid_conf; 1604 mvpp22_gop_init_rgmii(port); 1605 break; 1606 case PHY_INTERFACE_MODE_SGMII: 1607 case PHY_INTERFACE_MODE_1000BASEX: 1608 case PHY_INTERFACE_MODE_2500BASEX: 1609 mvpp22_gop_init_sgmii(port); 1610 break; 1611 case PHY_INTERFACE_MODE_10GBASER: 1612 if (!mvpp2_port_supports_xlg(port)) 1613 goto invalid_conf; 1614 mvpp22_gop_init_10gkr(port); 1615 break; 1616 default: 1617 goto unsupported_conf; 1618 } 1619 1620 regmap_read(priv->sysctrl_base, GENCONF_PORT_CTRL1, &val); 1621 val |= GENCONF_PORT_CTRL1_RESET(port->gop_id) | 1622 GENCONF_PORT_CTRL1_EN(port->gop_id); 1623 regmap_write(priv->sysctrl_base, GENCONF_PORT_CTRL1, val); 1624 1625 regmap_read(priv->sysctrl_base, GENCONF_PORT_CTRL0, &val); 1626 val |= GENCONF_PORT_CTRL0_CLK_DIV_PHASE_CLR; 1627 regmap_write(priv->sysctrl_base, GENCONF_PORT_CTRL0, val); 1628 1629 regmap_read(priv->sysctrl_base, GENCONF_SOFT_RESET1, &val); 1630 val |= GENCONF_SOFT_RESET1_GOP; 1631 regmap_write(priv->sysctrl_base, GENCONF_SOFT_RESET1, val); 1632 1633 mvpp22_gop_fca_set_periodic_timer(port); 1634 1635 unsupported_conf: 1636 return 0; 1637 1638 invalid_conf: 1639 netdev_err(port->dev, "Invalid port configuration\n"); 1640 return -EINVAL; 1641 } 1642 1643 static void mvpp22_gop_unmask_irq(struct mvpp2_port *port) 1644 { 1645 u32 val; 1646 1647 if (phy_interface_mode_is_rgmii(port->phy_interface) || 1648 phy_interface_mode_is_8023z(port->phy_interface) || 1649 port->phy_interface == PHY_INTERFACE_MODE_SGMII) { 1650 /* Enable the GMAC link status irq for this port */ 1651 val = readl(port->base + MVPP22_GMAC_INT_SUM_MASK); 1652 val |= MVPP22_GMAC_INT_SUM_MASK_LINK_STAT; 1653 writel(val, port->base + MVPP22_GMAC_INT_SUM_MASK); 1654 } 1655 1656 if (mvpp2_port_supports_xlg(port)) { 1657 /* Enable the XLG/GIG irqs for this port */ 1658 val = readl(port->base + MVPP22_XLG_EXT_INT_MASK); 1659 if (mvpp2_is_xlg(port->phy_interface)) 1660 val |= MVPP22_XLG_EXT_INT_MASK_XLG; 1661 else 1662 val |= MVPP22_XLG_EXT_INT_MASK_GIG; 1663 writel(val, port->base + MVPP22_XLG_EXT_INT_MASK); 1664 } 1665 } 1666 1667 static void mvpp22_gop_mask_irq(struct mvpp2_port *port) 1668 { 1669 u32 val; 1670 1671 if (mvpp2_port_supports_xlg(port)) { 1672 val = readl(port->base + MVPP22_XLG_EXT_INT_MASK); 1673 val &= ~(MVPP22_XLG_EXT_INT_MASK_XLG | 1674 MVPP22_XLG_EXT_INT_MASK_GIG); 1675 writel(val, port->base + MVPP22_XLG_EXT_INT_MASK); 1676 } 1677 1678 if (phy_interface_mode_is_rgmii(port->phy_interface) || 1679 phy_interface_mode_is_8023z(port->phy_interface) || 1680 port->phy_interface == PHY_INTERFACE_MODE_SGMII) { 1681 val = readl(port->base + MVPP22_GMAC_INT_SUM_MASK); 1682 val &= ~MVPP22_GMAC_INT_SUM_MASK_LINK_STAT; 1683 writel(val, port->base + MVPP22_GMAC_INT_SUM_MASK); 1684 } 1685 } 1686 1687 static void mvpp22_gop_setup_irq(struct mvpp2_port *port) 1688 { 1689 u32 val; 1690 1691 mvpp2_modify(port->base + MVPP22_GMAC_INT_SUM_MASK, 1692 MVPP22_GMAC_INT_SUM_MASK_PTP, 1693 MVPP22_GMAC_INT_SUM_MASK_PTP); 1694 1695 if (port->phylink || 1696 phy_interface_mode_is_rgmii(port->phy_interface) || 1697 phy_interface_mode_is_8023z(port->phy_interface) || 1698 port->phy_interface == PHY_INTERFACE_MODE_SGMII) { 1699 val = readl(port->base + MVPP22_GMAC_INT_MASK); 1700 val |= MVPP22_GMAC_INT_MASK_LINK_STAT; 1701 writel(val, port->base + MVPP22_GMAC_INT_MASK); 1702 } 1703 1704 if (mvpp2_port_supports_xlg(port)) { 1705 val = readl(port->base + MVPP22_XLG_INT_MASK); 1706 val |= MVPP22_XLG_INT_MASK_LINK; 1707 writel(val, port->base + MVPP22_XLG_INT_MASK); 1708 1709 mvpp2_modify(port->base + MVPP22_XLG_EXT_INT_MASK, 1710 MVPP22_XLG_EXT_INT_MASK_PTP, 1711 MVPP22_XLG_EXT_INT_MASK_PTP); 1712 } 1713 1714 mvpp22_gop_unmask_irq(port); 1715 } 1716 1717 /* Sets the PHY mode of the COMPHY (which configures the serdes lanes). 1718 * 1719 * The PHY mode used by the PPv2 driver comes from the network subsystem, while 1720 * the one given to the COMPHY comes from the generic PHY subsystem. Hence they 1721 * differ. 1722 * 1723 * The COMPHY configures the serdes lanes regardless of the actual use of the 1724 * lanes by the physical layer. This is why configurations like 1725 * "PPv2 (2500BaseX) - COMPHY (2500SGMII)" are valid. 1726 */ 1727 static int mvpp22_comphy_init(struct mvpp2_port *port) 1728 { 1729 int ret; 1730 1731 if (!port->comphy) 1732 return 0; 1733 1734 ret = phy_set_mode_ext(port->comphy, PHY_MODE_ETHERNET, 1735 port->phy_interface); 1736 if (ret) 1737 return ret; 1738 1739 return phy_power_on(port->comphy); 1740 } 1741 1742 static void mvpp2_port_enable(struct mvpp2_port *port) 1743 { 1744 u32 val; 1745 1746 if (mvpp2_port_supports_xlg(port) && 1747 mvpp2_is_xlg(port->phy_interface)) { 1748 val = readl(port->base + MVPP22_XLG_CTRL0_REG); 1749 val |= MVPP22_XLG_CTRL0_PORT_EN; 1750 val &= ~MVPP22_XLG_CTRL0_MIB_CNT_DIS; 1751 writel(val, port->base + MVPP22_XLG_CTRL0_REG); 1752 } else { 1753 val = readl(port->base + MVPP2_GMAC_CTRL_0_REG); 1754 val |= MVPP2_GMAC_PORT_EN_MASK; 1755 val |= MVPP2_GMAC_MIB_CNTR_EN_MASK; 1756 writel(val, port->base + MVPP2_GMAC_CTRL_0_REG); 1757 } 1758 } 1759 1760 static void mvpp2_port_disable(struct mvpp2_port *port) 1761 { 1762 u32 val; 1763 1764 if (mvpp2_port_supports_xlg(port) && 1765 mvpp2_is_xlg(port->phy_interface)) { 1766 val = readl(port->base + MVPP22_XLG_CTRL0_REG); 1767 val &= ~MVPP22_XLG_CTRL0_PORT_EN; 1768 writel(val, port->base + MVPP22_XLG_CTRL0_REG); 1769 } 1770 1771 val = readl(port->base + MVPP2_GMAC_CTRL_0_REG); 1772 val &= ~(MVPP2_GMAC_PORT_EN_MASK); 1773 writel(val, port->base + MVPP2_GMAC_CTRL_0_REG); 1774 } 1775 1776 /* Set IEEE 802.3x Flow Control Xon Packet Transmission Mode */ 1777 static void mvpp2_port_periodic_xon_disable(struct mvpp2_port *port) 1778 { 1779 u32 val; 1780 1781 val = readl(port->base + MVPP2_GMAC_CTRL_1_REG) & 1782 ~MVPP2_GMAC_PERIODIC_XON_EN_MASK; 1783 writel(val, port->base + MVPP2_GMAC_CTRL_1_REG); 1784 } 1785 1786 /* Configure loopback port */ 1787 static void mvpp2_port_loopback_set(struct mvpp2_port *port, 1788 const struct phylink_link_state *state) 1789 { 1790 u32 val; 1791 1792 val = readl(port->base + MVPP2_GMAC_CTRL_1_REG); 1793 1794 if (state->speed == 1000) 1795 val |= MVPP2_GMAC_GMII_LB_EN_MASK; 1796 else 1797 val &= ~MVPP2_GMAC_GMII_LB_EN_MASK; 1798 1799 if (phy_interface_mode_is_8023z(state->interface) || 1800 state->interface == PHY_INTERFACE_MODE_SGMII) 1801 val |= MVPP2_GMAC_PCS_LB_EN_MASK; 1802 else 1803 val &= ~MVPP2_GMAC_PCS_LB_EN_MASK; 1804 1805 writel(val, port->base + MVPP2_GMAC_CTRL_1_REG); 1806 } 1807 1808 enum { 1809 ETHTOOL_XDP_REDIRECT, 1810 ETHTOOL_XDP_PASS, 1811 ETHTOOL_XDP_DROP, 1812 ETHTOOL_XDP_TX, 1813 ETHTOOL_XDP_TX_ERR, 1814 ETHTOOL_XDP_XMIT, 1815 ETHTOOL_XDP_XMIT_ERR, 1816 }; 1817 1818 struct mvpp2_ethtool_counter { 1819 unsigned int offset; 1820 const char string[ETH_GSTRING_LEN]; 1821 bool reg_is_64b; 1822 }; 1823 1824 static u64 mvpp2_read_count(struct mvpp2_port *port, 1825 const struct mvpp2_ethtool_counter *counter) 1826 { 1827 u64 val; 1828 1829 val = readl(port->stats_base + counter->offset); 1830 if (counter->reg_is_64b) 1831 val += (u64)readl(port->stats_base + counter->offset + 4) << 32; 1832 1833 return val; 1834 } 1835 1836 /* Some counters are accessed indirectly by first writing an index to 1837 * MVPP2_CTRS_IDX. The index can represent various resources depending on the 1838 * register we access, it can be a hit counter for some classification tables, 1839 * a counter specific to a rxq, a txq or a buffer pool. 1840 */ 1841 static u32 mvpp2_read_index(struct mvpp2 *priv, u32 index, u32 reg) 1842 { 1843 mvpp2_write(priv, MVPP2_CTRS_IDX, index); 1844 return mvpp2_read(priv, reg); 1845 } 1846 1847 /* Due to the fact that software statistics and hardware statistics are, by 1848 * design, incremented at different moments in the chain of packet processing, 1849 * it is very likely that incoming packets could have been dropped after being 1850 * counted by hardware but before reaching software statistics (most probably 1851 * multicast packets), and in the oppposite way, during transmission, FCS bytes 1852 * are added in between as well as TSO skb will be split and header bytes added. 1853 * Hence, statistics gathered from userspace with ifconfig (software) and 1854 * ethtool (hardware) cannot be compared. 1855 */ 1856 static const struct mvpp2_ethtool_counter mvpp2_ethtool_mib_regs[] = { 1857 { MVPP2_MIB_GOOD_OCTETS_RCVD, "good_octets_received", true }, 1858 { MVPP2_MIB_BAD_OCTETS_RCVD, "bad_octets_received" }, 1859 { MVPP2_MIB_CRC_ERRORS_SENT, "crc_errors_sent" }, 1860 { MVPP2_MIB_UNICAST_FRAMES_RCVD, "unicast_frames_received" }, 1861 { MVPP2_MIB_BROADCAST_FRAMES_RCVD, "broadcast_frames_received" }, 1862 { MVPP2_MIB_MULTICAST_FRAMES_RCVD, "multicast_frames_received" }, 1863 { MVPP2_MIB_FRAMES_64_OCTETS, "frames_64_octets" }, 1864 { MVPP2_MIB_FRAMES_65_TO_127_OCTETS, "frames_65_to_127_octet" }, 1865 { MVPP2_MIB_FRAMES_128_TO_255_OCTETS, "frames_128_to_255_octet" }, 1866 { MVPP2_MIB_FRAMES_256_TO_511_OCTETS, "frames_256_to_511_octet" }, 1867 { MVPP2_MIB_FRAMES_512_TO_1023_OCTETS, "frames_512_to_1023_octet" }, 1868 { MVPP2_MIB_FRAMES_1024_TO_MAX_OCTETS, "frames_1024_to_max_octet" }, 1869 { MVPP2_MIB_GOOD_OCTETS_SENT, "good_octets_sent", true }, 1870 { MVPP2_MIB_UNICAST_FRAMES_SENT, "unicast_frames_sent" }, 1871 { MVPP2_MIB_MULTICAST_FRAMES_SENT, "multicast_frames_sent" }, 1872 { MVPP2_MIB_BROADCAST_FRAMES_SENT, "broadcast_frames_sent" }, 1873 { MVPP2_MIB_FC_SENT, "fc_sent" }, 1874 { MVPP2_MIB_FC_RCVD, "fc_received" }, 1875 { MVPP2_MIB_RX_FIFO_OVERRUN, "rx_fifo_overrun" }, 1876 { MVPP2_MIB_UNDERSIZE_RCVD, "undersize_received" }, 1877 { MVPP2_MIB_FRAGMENTS_RCVD, "fragments_received" }, 1878 { MVPP2_MIB_OVERSIZE_RCVD, "oversize_received" }, 1879 { MVPP2_MIB_JABBER_RCVD, "jabber_received" }, 1880 { MVPP2_MIB_MAC_RCV_ERROR, "mac_receive_error" }, 1881 { MVPP2_MIB_BAD_CRC_EVENT, "bad_crc_event" }, 1882 { MVPP2_MIB_COLLISION, "collision" }, 1883 { MVPP2_MIB_LATE_COLLISION, "late_collision" }, 1884 }; 1885 1886 static const struct mvpp2_ethtool_counter mvpp2_ethtool_port_regs[] = { 1887 { MVPP2_OVERRUN_ETH_DROP, "rx_fifo_or_parser_overrun_drops" }, 1888 { MVPP2_CLS_ETH_DROP, "rx_classifier_drops" }, 1889 }; 1890 1891 static const struct mvpp2_ethtool_counter mvpp2_ethtool_txq_regs[] = { 1892 { MVPP2_TX_DESC_ENQ_CTR, "txq_%d_desc_enqueue" }, 1893 { MVPP2_TX_DESC_ENQ_TO_DDR_CTR, "txq_%d_desc_enqueue_to_ddr" }, 1894 { MVPP2_TX_BUFF_ENQ_TO_DDR_CTR, "txq_%d_buff_euqueue_to_ddr" }, 1895 { MVPP2_TX_DESC_ENQ_HW_FWD_CTR, "txq_%d_desc_hardware_forwarded" }, 1896 { MVPP2_TX_PKTS_DEQ_CTR, "txq_%d_packets_dequeued" }, 1897 { MVPP2_TX_PKTS_FULL_QUEUE_DROP_CTR, "txq_%d_queue_full_drops" }, 1898 { MVPP2_TX_PKTS_EARLY_DROP_CTR, "txq_%d_packets_early_drops" }, 1899 { MVPP2_TX_PKTS_BM_DROP_CTR, "txq_%d_packets_bm_drops" }, 1900 { MVPP2_TX_PKTS_BM_MC_DROP_CTR, "txq_%d_packets_rep_bm_drops" }, 1901 }; 1902 1903 static const struct mvpp2_ethtool_counter mvpp2_ethtool_rxq_regs[] = { 1904 { MVPP2_RX_DESC_ENQ_CTR, "rxq_%d_desc_enqueue" }, 1905 { MVPP2_RX_PKTS_FULL_QUEUE_DROP_CTR, "rxq_%d_queue_full_drops" }, 1906 { MVPP2_RX_PKTS_EARLY_DROP_CTR, "rxq_%d_packets_early_drops" }, 1907 { MVPP2_RX_PKTS_BM_DROP_CTR, "rxq_%d_packets_bm_drops" }, 1908 }; 1909 1910 static const struct mvpp2_ethtool_counter mvpp2_ethtool_xdp[] = { 1911 { ETHTOOL_XDP_REDIRECT, "rx_xdp_redirect", }, 1912 { ETHTOOL_XDP_PASS, "rx_xdp_pass", }, 1913 { ETHTOOL_XDP_DROP, "rx_xdp_drop", }, 1914 { ETHTOOL_XDP_TX, "rx_xdp_tx", }, 1915 { ETHTOOL_XDP_TX_ERR, "rx_xdp_tx_errors", }, 1916 { ETHTOOL_XDP_XMIT, "tx_xdp_xmit", }, 1917 { ETHTOOL_XDP_XMIT_ERR, "tx_xdp_xmit_errors", }, 1918 }; 1919 1920 #define MVPP2_N_ETHTOOL_STATS(ntxqs, nrxqs) (ARRAY_SIZE(mvpp2_ethtool_mib_regs) + \ 1921 ARRAY_SIZE(mvpp2_ethtool_port_regs) + \ 1922 (ARRAY_SIZE(mvpp2_ethtool_txq_regs) * (ntxqs)) + \ 1923 (ARRAY_SIZE(mvpp2_ethtool_rxq_regs) * (nrxqs)) + \ 1924 ARRAY_SIZE(mvpp2_ethtool_xdp)) 1925 1926 static void mvpp2_ethtool_get_strings(struct net_device *netdev, u32 sset, 1927 u8 *data) 1928 { 1929 struct mvpp2_port *port = netdev_priv(netdev); 1930 int i, q; 1931 1932 if (sset != ETH_SS_STATS) 1933 return; 1934 1935 for (i = 0; i < ARRAY_SIZE(mvpp2_ethtool_mib_regs); i++) { 1936 strscpy(data, mvpp2_ethtool_mib_regs[i].string, 1937 ETH_GSTRING_LEN); 1938 data += ETH_GSTRING_LEN; 1939 } 1940 1941 for (i = 0; i < ARRAY_SIZE(mvpp2_ethtool_port_regs); i++) { 1942 strscpy(data, mvpp2_ethtool_port_regs[i].string, 1943 ETH_GSTRING_LEN); 1944 data += ETH_GSTRING_LEN; 1945 } 1946 1947 for (q = 0; q < port->ntxqs; q++) { 1948 for (i = 0; i < ARRAY_SIZE(mvpp2_ethtool_txq_regs); i++) { 1949 snprintf(data, ETH_GSTRING_LEN, 1950 mvpp2_ethtool_txq_regs[i].string, q); 1951 data += ETH_GSTRING_LEN; 1952 } 1953 } 1954 1955 for (q = 0; q < port->nrxqs; q++) { 1956 for (i = 0; i < ARRAY_SIZE(mvpp2_ethtool_rxq_regs); i++) { 1957 snprintf(data, ETH_GSTRING_LEN, 1958 mvpp2_ethtool_rxq_regs[i].string, 1959 q); 1960 data += ETH_GSTRING_LEN; 1961 } 1962 } 1963 1964 for (i = 0; i < ARRAY_SIZE(mvpp2_ethtool_xdp); i++) { 1965 strscpy(data, mvpp2_ethtool_xdp[i].string, 1966 ETH_GSTRING_LEN); 1967 data += ETH_GSTRING_LEN; 1968 } 1969 } 1970 1971 static void 1972 mvpp2_get_xdp_stats(struct mvpp2_port *port, struct mvpp2_pcpu_stats *xdp_stats) 1973 { 1974 unsigned int start; 1975 unsigned int cpu; 1976 1977 /* Gather XDP Statistics */ 1978 for_each_possible_cpu(cpu) { 1979 struct mvpp2_pcpu_stats *cpu_stats; 1980 u64 xdp_redirect; 1981 u64 xdp_pass; 1982 u64 xdp_drop; 1983 u64 xdp_xmit; 1984 u64 xdp_xmit_err; 1985 u64 xdp_tx; 1986 u64 xdp_tx_err; 1987 1988 cpu_stats = per_cpu_ptr(port->stats, cpu); 1989 do { 1990 start = u64_stats_fetch_begin_irq(&cpu_stats->syncp); 1991 xdp_redirect = cpu_stats->xdp_redirect; 1992 xdp_pass = cpu_stats->xdp_pass; 1993 xdp_drop = cpu_stats->xdp_drop; 1994 xdp_xmit = cpu_stats->xdp_xmit; 1995 xdp_xmit_err = cpu_stats->xdp_xmit_err; 1996 xdp_tx = cpu_stats->xdp_tx; 1997 xdp_tx_err = cpu_stats->xdp_tx_err; 1998 } while (u64_stats_fetch_retry_irq(&cpu_stats->syncp, start)); 1999 2000 xdp_stats->xdp_redirect += xdp_redirect; 2001 xdp_stats->xdp_pass += xdp_pass; 2002 xdp_stats->xdp_drop += xdp_drop; 2003 xdp_stats->xdp_xmit += xdp_xmit; 2004 xdp_stats->xdp_xmit_err += xdp_xmit_err; 2005 xdp_stats->xdp_tx += xdp_tx; 2006 xdp_stats->xdp_tx_err += xdp_tx_err; 2007 } 2008 } 2009 2010 static void mvpp2_read_stats(struct mvpp2_port *port) 2011 { 2012 struct mvpp2_pcpu_stats xdp_stats = {}; 2013 const struct mvpp2_ethtool_counter *s; 2014 u64 *pstats; 2015 int i, q; 2016 2017 pstats = port->ethtool_stats; 2018 2019 for (i = 0; i < ARRAY_SIZE(mvpp2_ethtool_mib_regs); i++) 2020 *pstats++ += mvpp2_read_count(port, &mvpp2_ethtool_mib_regs[i]); 2021 2022 for (i = 0; i < ARRAY_SIZE(mvpp2_ethtool_port_regs); i++) 2023 *pstats++ += mvpp2_read(port->priv, 2024 mvpp2_ethtool_port_regs[i].offset + 2025 4 * port->id); 2026 2027 for (q = 0; q < port->ntxqs; q++) 2028 for (i = 0; i < ARRAY_SIZE(mvpp2_ethtool_txq_regs); i++) 2029 *pstats++ += mvpp2_read_index(port->priv, 2030 MVPP22_CTRS_TX_CTR(port->id, q), 2031 mvpp2_ethtool_txq_regs[i].offset); 2032 2033 /* Rxqs are numbered from 0 from the user standpoint, but not from the 2034 * driver's. We need to add the port->first_rxq offset. 2035 */ 2036 for (q = 0; q < port->nrxqs; q++) 2037 for (i = 0; i < ARRAY_SIZE(mvpp2_ethtool_rxq_regs); i++) 2038 *pstats++ += mvpp2_read_index(port->priv, 2039 port->first_rxq + q, 2040 mvpp2_ethtool_rxq_regs[i].offset); 2041 2042 /* Gather XDP Statistics */ 2043 mvpp2_get_xdp_stats(port, &xdp_stats); 2044 2045 for (i = 0, s = mvpp2_ethtool_xdp; 2046 s < mvpp2_ethtool_xdp + ARRAY_SIZE(mvpp2_ethtool_xdp); 2047 s++, i++) { 2048 switch (s->offset) { 2049 case ETHTOOL_XDP_REDIRECT: 2050 *pstats++ = xdp_stats.xdp_redirect; 2051 break; 2052 case ETHTOOL_XDP_PASS: 2053 *pstats++ = xdp_stats.xdp_pass; 2054 break; 2055 case ETHTOOL_XDP_DROP: 2056 *pstats++ = xdp_stats.xdp_drop; 2057 break; 2058 case ETHTOOL_XDP_TX: 2059 *pstats++ = xdp_stats.xdp_tx; 2060 break; 2061 case ETHTOOL_XDP_TX_ERR: 2062 *pstats++ = xdp_stats.xdp_tx_err; 2063 break; 2064 case ETHTOOL_XDP_XMIT: 2065 *pstats++ = xdp_stats.xdp_xmit; 2066 break; 2067 case ETHTOOL_XDP_XMIT_ERR: 2068 *pstats++ = xdp_stats.xdp_xmit_err; 2069 break; 2070 } 2071 } 2072 } 2073 2074 static void mvpp2_gather_hw_statistics(struct work_struct *work) 2075 { 2076 struct delayed_work *del_work = to_delayed_work(work); 2077 struct mvpp2_port *port = container_of(del_work, struct mvpp2_port, 2078 stats_work); 2079 2080 mutex_lock(&port->gather_stats_lock); 2081 2082 mvpp2_read_stats(port); 2083 2084 /* No need to read again the counters right after this function if it 2085 * was called asynchronously by the user (ie. use of ethtool). 2086 */ 2087 cancel_delayed_work(&port->stats_work); 2088 queue_delayed_work(port->priv->stats_queue, &port->stats_work, 2089 MVPP2_MIB_COUNTERS_STATS_DELAY); 2090 2091 mutex_unlock(&port->gather_stats_lock); 2092 } 2093 2094 static void mvpp2_ethtool_get_stats(struct net_device *dev, 2095 struct ethtool_stats *stats, u64 *data) 2096 { 2097 struct mvpp2_port *port = netdev_priv(dev); 2098 2099 /* Update statistics for the given port, then take the lock to avoid 2100 * concurrent accesses on the ethtool_stats structure during its copy. 2101 */ 2102 mvpp2_gather_hw_statistics(&port->stats_work.work); 2103 2104 mutex_lock(&port->gather_stats_lock); 2105 memcpy(data, port->ethtool_stats, 2106 sizeof(u64) * MVPP2_N_ETHTOOL_STATS(port->ntxqs, port->nrxqs)); 2107 mutex_unlock(&port->gather_stats_lock); 2108 } 2109 2110 static int mvpp2_ethtool_get_sset_count(struct net_device *dev, int sset) 2111 { 2112 struct mvpp2_port *port = netdev_priv(dev); 2113 2114 if (sset == ETH_SS_STATS) 2115 return MVPP2_N_ETHTOOL_STATS(port->ntxqs, port->nrxqs); 2116 2117 return -EOPNOTSUPP; 2118 } 2119 2120 static void mvpp2_mac_reset_assert(struct mvpp2_port *port) 2121 { 2122 u32 val; 2123 2124 val = readl(port->base + MVPP2_GMAC_CTRL_2_REG) | 2125 MVPP2_GMAC_PORT_RESET_MASK; 2126 writel(val, port->base + MVPP2_GMAC_CTRL_2_REG); 2127 2128 if (port->priv->hw_version != MVPP21 && port->gop_id == 0) { 2129 val = readl(port->base + MVPP22_XLG_CTRL0_REG) & 2130 ~MVPP22_XLG_CTRL0_MAC_RESET_DIS; 2131 writel(val, port->base + MVPP22_XLG_CTRL0_REG); 2132 } 2133 } 2134 2135 static void mvpp22_pcs_reset_assert(struct mvpp2_port *port) 2136 { 2137 struct mvpp2 *priv = port->priv; 2138 void __iomem *mpcs, *xpcs; 2139 u32 val; 2140 2141 if (port->priv->hw_version == MVPP21 || port->gop_id != 0) 2142 return; 2143 2144 mpcs = priv->iface_base + MVPP22_MPCS_BASE(port->gop_id); 2145 xpcs = priv->iface_base + MVPP22_XPCS_BASE(port->gop_id); 2146 2147 val = readl(mpcs + MVPP22_MPCS_CLK_RESET); 2148 val &= ~(MAC_CLK_RESET_MAC | MAC_CLK_RESET_SD_RX | MAC_CLK_RESET_SD_TX); 2149 val |= MVPP22_MPCS_CLK_RESET_DIV_SET; 2150 writel(val, mpcs + MVPP22_MPCS_CLK_RESET); 2151 2152 val = readl(xpcs + MVPP22_XPCS_CFG0); 2153 writel(val & ~MVPP22_XPCS_CFG0_RESET_DIS, xpcs + MVPP22_XPCS_CFG0); 2154 } 2155 2156 static void mvpp22_pcs_reset_deassert(struct mvpp2_port *port) 2157 { 2158 struct mvpp2 *priv = port->priv; 2159 void __iomem *mpcs, *xpcs; 2160 u32 val; 2161 2162 if (port->priv->hw_version == MVPP21 || port->gop_id != 0) 2163 return; 2164 2165 mpcs = priv->iface_base + MVPP22_MPCS_BASE(port->gop_id); 2166 xpcs = priv->iface_base + MVPP22_XPCS_BASE(port->gop_id); 2167 2168 switch (port->phy_interface) { 2169 case PHY_INTERFACE_MODE_10GBASER: 2170 val = readl(mpcs + MVPP22_MPCS_CLK_RESET); 2171 val |= MAC_CLK_RESET_MAC | MAC_CLK_RESET_SD_RX | 2172 MAC_CLK_RESET_SD_TX; 2173 val &= ~MVPP22_MPCS_CLK_RESET_DIV_SET; 2174 writel(val, mpcs + MVPP22_MPCS_CLK_RESET); 2175 break; 2176 case PHY_INTERFACE_MODE_XAUI: 2177 case PHY_INTERFACE_MODE_RXAUI: 2178 val = readl(xpcs + MVPP22_XPCS_CFG0); 2179 writel(val | MVPP22_XPCS_CFG0_RESET_DIS, xpcs + MVPP22_XPCS_CFG0); 2180 break; 2181 default: 2182 break; 2183 } 2184 } 2185 2186 /* Change maximum receive size of the port */ 2187 static inline void mvpp2_gmac_max_rx_size_set(struct mvpp2_port *port) 2188 { 2189 u32 val; 2190 2191 val = readl(port->base + MVPP2_GMAC_CTRL_0_REG); 2192 val &= ~MVPP2_GMAC_MAX_RX_SIZE_MASK; 2193 val |= (((port->pkt_size - MVPP2_MH_SIZE) / 2) << 2194 MVPP2_GMAC_MAX_RX_SIZE_OFFS); 2195 writel(val, port->base + MVPP2_GMAC_CTRL_0_REG); 2196 } 2197 2198 /* Change maximum receive size of the port */ 2199 static inline void mvpp2_xlg_max_rx_size_set(struct mvpp2_port *port) 2200 { 2201 u32 val; 2202 2203 val = readl(port->base + MVPP22_XLG_CTRL1_REG); 2204 val &= ~MVPP22_XLG_CTRL1_FRAMESIZELIMIT_MASK; 2205 val |= ((port->pkt_size - MVPP2_MH_SIZE) / 2) << 2206 MVPP22_XLG_CTRL1_FRAMESIZELIMIT_OFFS; 2207 writel(val, port->base + MVPP22_XLG_CTRL1_REG); 2208 } 2209 2210 /* Set defaults to the MVPP2 port */ 2211 static void mvpp2_defaults_set(struct mvpp2_port *port) 2212 { 2213 int tx_port_num, val, queue, lrxq; 2214 2215 if (port->priv->hw_version == MVPP21) { 2216 /* Update TX FIFO MIN Threshold */ 2217 val = readl(port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG); 2218 val &= ~MVPP2_GMAC_TX_FIFO_MIN_TH_ALL_MASK; 2219 /* Min. TX threshold must be less than minimal packet length */ 2220 val |= MVPP2_GMAC_TX_FIFO_MIN_TH_MASK(64 - 4 - 2); 2221 writel(val, port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG); 2222 } 2223 2224 /* Disable Legacy WRR, Disable EJP, Release from reset */ 2225 tx_port_num = mvpp2_egress_port(port); 2226 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, 2227 tx_port_num); 2228 mvpp2_write(port->priv, MVPP2_TXP_SCHED_CMD_1_REG, 0); 2229 2230 /* Set TXQ scheduling to Round-Robin */ 2231 mvpp2_write(port->priv, MVPP2_TXP_SCHED_FIXED_PRIO_REG, 0); 2232 2233 /* Close bandwidth for all queues */ 2234 for (queue = 0; queue < MVPP2_MAX_TXQ; queue++) 2235 mvpp2_write(port->priv, 2236 MVPP2_TXQ_SCHED_TOKEN_CNTR_REG(queue), 0); 2237 2238 /* Set refill period to 1 usec, refill tokens 2239 * and bucket size to maximum 2240 */ 2241 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PERIOD_REG, 2242 port->priv->tclk / USEC_PER_SEC); 2243 val = mvpp2_read(port->priv, MVPP2_TXP_SCHED_REFILL_REG); 2244 val &= ~MVPP2_TXP_REFILL_PERIOD_ALL_MASK; 2245 val |= MVPP2_TXP_REFILL_PERIOD_MASK(1); 2246 val |= MVPP2_TXP_REFILL_TOKENS_ALL_MASK; 2247 mvpp2_write(port->priv, MVPP2_TXP_SCHED_REFILL_REG, val); 2248 val = MVPP2_TXP_TOKEN_SIZE_MAX; 2249 mvpp2_write(port->priv, MVPP2_TXP_SCHED_TOKEN_SIZE_REG, val); 2250 2251 /* Set MaximumLowLatencyPacketSize value to 256 */ 2252 mvpp2_write(port->priv, MVPP2_RX_CTRL_REG(port->id), 2253 MVPP2_RX_USE_PSEUDO_FOR_CSUM_MASK | 2254 MVPP2_RX_LOW_LATENCY_PKT_SIZE(256)); 2255 2256 /* Enable Rx cache snoop */ 2257 for (lrxq = 0; lrxq < port->nrxqs; lrxq++) { 2258 queue = port->rxqs[lrxq]->id; 2259 val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(queue)); 2260 val |= MVPP2_SNOOP_PKT_SIZE_MASK | 2261 MVPP2_SNOOP_BUF_HDR_MASK; 2262 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(queue), val); 2263 } 2264 2265 /* At default, mask all interrupts to all present cpus */ 2266 mvpp2_interrupts_disable(port); 2267 } 2268 2269 /* Enable/disable receiving packets */ 2270 static void mvpp2_ingress_enable(struct mvpp2_port *port) 2271 { 2272 u32 val; 2273 int lrxq, queue; 2274 2275 for (lrxq = 0; lrxq < port->nrxqs; lrxq++) { 2276 queue = port->rxqs[lrxq]->id; 2277 val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(queue)); 2278 val &= ~MVPP2_RXQ_DISABLE_MASK; 2279 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(queue), val); 2280 } 2281 } 2282 2283 static void mvpp2_ingress_disable(struct mvpp2_port *port) 2284 { 2285 u32 val; 2286 int lrxq, queue; 2287 2288 for (lrxq = 0; lrxq < port->nrxqs; lrxq++) { 2289 queue = port->rxqs[lrxq]->id; 2290 val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(queue)); 2291 val |= MVPP2_RXQ_DISABLE_MASK; 2292 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(queue), val); 2293 } 2294 } 2295 2296 /* Enable transmit via physical egress queue 2297 * - HW starts take descriptors from DRAM 2298 */ 2299 static void mvpp2_egress_enable(struct mvpp2_port *port) 2300 { 2301 u32 qmap; 2302 int queue; 2303 int tx_port_num = mvpp2_egress_port(port); 2304 2305 /* Enable all initialized TXs. */ 2306 qmap = 0; 2307 for (queue = 0; queue < port->ntxqs; queue++) { 2308 struct mvpp2_tx_queue *txq = port->txqs[queue]; 2309 2310 if (txq->descs) 2311 qmap |= (1 << queue); 2312 } 2313 2314 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num); 2315 mvpp2_write(port->priv, MVPP2_TXP_SCHED_Q_CMD_REG, qmap); 2316 } 2317 2318 /* Disable transmit via physical egress queue 2319 * - HW doesn't take descriptors from DRAM 2320 */ 2321 static void mvpp2_egress_disable(struct mvpp2_port *port) 2322 { 2323 u32 reg_data; 2324 int delay; 2325 int tx_port_num = mvpp2_egress_port(port); 2326 2327 /* Issue stop command for active channels only */ 2328 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num); 2329 reg_data = (mvpp2_read(port->priv, MVPP2_TXP_SCHED_Q_CMD_REG)) & 2330 MVPP2_TXP_SCHED_ENQ_MASK; 2331 if (reg_data != 0) 2332 mvpp2_write(port->priv, MVPP2_TXP_SCHED_Q_CMD_REG, 2333 (reg_data << MVPP2_TXP_SCHED_DISQ_OFFSET)); 2334 2335 /* Wait for all Tx activity to terminate. */ 2336 delay = 0; 2337 do { 2338 if (delay >= MVPP2_TX_DISABLE_TIMEOUT_MSEC) { 2339 netdev_warn(port->dev, 2340 "Tx stop timed out, status=0x%08x\n", 2341 reg_data); 2342 break; 2343 } 2344 mdelay(1); 2345 delay++; 2346 2347 /* Check port TX Command register that all 2348 * Tx queues are stopped 2349 */ 2350 reg_data = mvpp2_read(port->priv, MVPP2_TXP_SCHED_Q_CMD_REG); 2351 } while (reg_data & MVPP2_TXP_SCHED_ENQ_MASK); 2352 } 2353 2354 /* Rx descriptors helper methods */ 2355 2356 /* Get number of Rx descriptors occupied by received packets */ 2357 static inline int 2358 mvpp2_rxq_received(struct mvpp2_port *port, int rxq_id) 2359 { 2360 u32 val = mvpp2_read(port->priv, MVPP2_RXQ_STATUS_REG(rxq_id)); 2361 2362 return val & MVPP2_RXQ_OCCUPIED_MASK; 2363 } 2364 2365 /* Update Rx queue status with the number of occupied and available 2366 * Rx descriptor slots. 2367 */ 2368 static inline void 2369 mvpp2_rxq_status_update(struct mvpp2_port *port, int rxq_id, 2370 int used_count, int free_count) 2371 { 2372 /* Decrement the number of used descriptors and increment count 2373 * increment the number of free descriptors. 2374 */ 2375 u32 val = used_count | (free_count << MVPP2_RXQ_NUM_NEW_OFFSET); 2376 2377 mvpp2_write(port->priv, MVPP2_RXQ_STATUS_UPDATE_REG(rxq_id), val); 2378 } 2379 2380 /* Get pointer to next RX descriptor to be processed by SW */ 2381 static inline struct mvpp2_rx_desc * 2382 mvpp2_rxq_next_desc_get(struct mvpp2_rx_queue *rxq) 2383 { 2384 int rx_desc = rxq->next_desc_to_proc; 2385 2386 rxq->next_desc_to_proc = MVPP2_QUEUE_NEXT_DESC(rxq, rx_desc); 2387 prefetch(rxq->descs + rxq->next_desc_to_proc); 2388 return rxq->descs + rx_desc; 2389 } 2390 2391 /* Set rx queue offset */ 2392 static void mvpp2_rxq_offset_set(struct mvpp2_port *port, 2393 int prxq, int offset) 2394 { 2395 u32 val; 2396 2397 /* Convert offset from bytes to units of 32 bytes */ 2398 offset = offset >> 5; 2399 2400 val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(prxq)); 2401 val &= ~MVPP2_RXQ_PACKET_OFFSET_MASK; 2402 2403 /* Offset is in */ 2404 val |= ((offset << MVPP2_RXQ_PACKET_OFFSET_OFFS) & 2405 MVPP2_RXQ_PACKET_OFFSET_MASK); 2406 2407 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(prxq), val); 2408 } 2409 2410 /* Tx descriptors helper methods */ 2411 2412 /* Get pointer to next Tx descriptor to be processed (send) by HW */ 2413 static struct mvpp2_tx_desc * 2414 mvpp2_txq_next_desc_get(struct mvpp2_tx_queue *txq) 2415 { 2416 int tx_desc = txq->next_desc_to_proc; 2417 2418 txq->next_desc_to_proc = MVPP2_QUEUE_NEXT_DESC(txq, tx_desc); 2419 return txq->descs + tx_desc; 2420 } 2421 2422 /* Update HW with number of aggregated Tx descriptors to be sent 2423 * 2424 * Called only from mvpp2_tx(), so migration is disabled, using 2425 * smp_processor_id() is OK. 2426 */ 2427 static void mvpp2_aggr_txq_pend_desc_add(struct mvpp2_port *port, int pending) 2428 { 2429 /* aggregated access - relevant TXQ number is written in TX desc */ 2430 mvpp2_thread_write(port->priv, 2431 mvpp2_cpu_to_thread(port->priv, smp_processor_id()), 2432 MVPP2_AGGR_TXQ_UPDATE_REG, pending); 2433 } 2434 2435 /* Check if there are enough free descriptors in aggregated txq. 2436 * If not, update the number of occupied descriptors and repeat the check. 2437 * 2438 * Called only from mvpp2_tx(), so migration is disabled, using 2439 * smp_processor_id() is OK. 2440 */ 2441 static int mvpp2_aggr_desc_num_check(struct mvpp2_port *port, 2442 struct mvpp2_tx_queue *aggr_txq, int num) 2443 { 2444 if ((aggr_txq->count + num) > MVPP2_AGGR_TXQ_SIZE) { 2445 /* Update number of occupied aggregated Tx descriptors */ 2446 unsigned int thread = 2447 mvpp2_cpu_to_thread(port->priv, smp_processor_id()); 2448 u32 val = mvpp2_read_relaxed(port->priv, 2449 MVPP2_AGGR_TXQ_STATUS_REG(thread)); 2450 2451 aggr_txq->count = val & MVPP2_AGGR_TXQ_PENDING_MASK; 2452 2453 if ((aggr_txq->count + num) > MVPP2_AGGR_TXQ_SIZE) 2454 return -ENOMEM; 2455 } 2456 return 0; 2457 } 2458 2459 /* Reserved Tx descriptors allocation request 2460 * 2461 * Called only from mvpp2_txq_reserved_desc_num_proc(), itself called 2462 * only by mvpp2_tx(), so migration is disabled, using 2463 * smp_processor_id() is OK. 2464 */ 2465 static int mvpp2_txq_alloc_reserved_desc(struct mvpp2_port *port, 2466 struct mvpp2_tx_queue *txq, int num) 2467 { 2468 unsigned int thread = mvpp2_cpu_to_thread(port->priv, smp_processor_id()); 2469 struct mvpp2 *priv = port->priv; 2470 u32 val; 2471 2472 val = (txq->id << MVPP2_TXQ_RSVD_REQ_Q_OFFSET) | num; 2473 mvpp2_thread_write_relaxed(priv, thread, MVPP2_TXQ_RSVD_REQ_REG, val); 2474 2475 val = mvpp2_thread_read_relaxed(priv, thread, MVPP2_TXQ_RSVD_RSLT_REG); 2476 2477 return val & MVPP2_TXQ_RSVD_RSLT_MASK; 2478 } 2479 2480 /* Check if there are enough reserved descriptors for transmission. 2481 * If not, request chunk of reserved descriptors and check again. 2482 */ 2483 static int mvpp2_txq_reserved_desc_num_proc(struct mvpp2_port *port, 2484 struct mvpp2_tx_queue *txq, 2485 struct mvpp2_txq_pcpu *txq_pcpu, 2486 int num) 2487 { 2488 int req, desc_count; 2489 unsigned int thread; 2490 2491 if (txq_pcpu->reserved_num >= num) 2492 return 0; 2493 2494 /* Not enough descriptors reserved! Update the reserved descriptor 2495 * count and check again. 2496 */ 2497 2498 desc_count = 0; 2499 /* Compute total of used descriptors */ 2500 for (thread = 0; thread < port->priv->nthreads; thread++) { 2501 struct mvpp2_txq_pcpu *txq_pcpu_aux; 2502 2503 txq_pcpu_aux = per_cpu_ptr(txq->pcpu, thread); 2504 desc_count += txq_pcpu_aux->count; 2505 desc_count += txq_pcpu_aux->reserved_num; 2506 } 2507 2508 req = max(MVPP2_CPU_DESC_CHUNK, num - txq_pcpu->reserved_num); 2509 desc_count += req; 2510 2511 if (desc_count > 2512 (txq->size - (MVPP2_MAX_THREADS * MVPP2_CPU_DESC_CHUNK))) 2513 return -ENOMEM; 2514 2515 txq_pcpu->reserved_num += mvpp2_txq_alloc_reserved_desc(port, txq, req); 2516 2517 /* OK, the descriptor could have been updated: check again. */ 2518 if (txq_pcpu->reserved_num < num) 2519 return -ENOMEM; 2520 return 0; 2521 } 2522 2523 /* Release the last allocated Tx descriptor. Useful to handle DMA 2524 * mapping failures in the Tx path. 2525 */ 2526 static void mvpp2_txq_desc_put(struct mvpp2_tx_queue *txq) 2527 { 2528 if (txq->next_desc_to_proc == 0) 2529 txq->next_desc_to_proc = txq->last_desc - 1; 2530 else 2531 txq->next_desc_to_proc--; 2532 } 2533 2534 /* Set Tx descriptors fields relevant for CSUM calculation */ 2535 static u32 mvpp2_txq_desc_csum(int l3_offs, __be16 l3_proto, 2536 int ip_hdr_len, int l4_proto) 2537 { 2538 u32 command; 2539 2540 /* fields: L3_offset, IP_hdrlen, L3_type, G_IPv4_chk, 2541 * G_L4_chk, L4_type required only for checksum calculation 2542 */ 2543 command = (l3_offs << MVPP2_TXD_L3_OFF_SHIFT); 2544 command |= (ip_hdr_len << MVPP2_TXD_IP_HLEN_SHIFT); 2545 command |= MVPP2_TXD_IP_CSUM_DISABLE; 2546 2547 if (l3_proto == htons(ETH_P_IP)) { 2548 command &= ~MVPP2_TXD_IP_CSUM_DISABLE; /* enable IPv4 csum */ 2549 command &= ~MVPP2_TXD_L3_IP6; /* enable IPv4 */ 2550 } else { 2551 command |= MVPP2_TXD_L3_IP6; /* enable IPv6 */ 2552 } 2553 2554 if (l4_proto == IPPROTO_TCP) { 2555 command &= ~MVPP2_TXD_L4_UDP; /* enable TCP */ 2556 command &= ~MVPP2_TXD_L4_CSUM_FRAG; /* generate L4 csum */ 2557 } else if (l4_proto == IPPROTO_UDP) { 2558 command |= MVPP2_TXD_L4_UDP; /* enable UDP */ 2559 command &= ~MVPP2_TXD_L4_CSUM_FRAG; /* generate L4 csum */ 2560 } else { 2561 command |= MVPP2_TXD_L4_CSUM_NOT; 2562 } 2563 2564 return command; 2565 } 2566 2567 /* Get number of sent descriptors and decrement counter. 2568 * The number of sent descriptors is returned. 2569 * Per-thread access 2570 * 2571 * Called only from mvpp2_txq_done(), called from mvpp2_tx() 2572 * (migration disabled) and from the TX completion tasklet (migration 2573 * disabled) so using smp_processor_id() is OK. 2574 */ 2575 static inline int mvpp2_txq_sent_desc_proc(struct mvpp2_port *port, 2576 struct mvpp2_tx_queue *txq) 2577 { 2578 u32 val; 2579 2580 /* Reading status reg resets transmitted descriptor counter */ 2581 val = mvpp2_thread_read_relaxed(port->priv, 2582 mvpp2_cpu_to_thread(port->priv, smp_processor_id()), 2583 MVPP2_TXQ_SENT_REG(txq->id)); 2584 2585 return (val & MVPP2_TRANSMITTED_COUNT_MASK) >> 2586 MVPP2_TRANSMITTED_COUNT_OFFSET; 2587 } 2588 2589 /* Called through on_each_cpu(), so runs on all CPUs, with migration 2590 * disabled, therefore using smp_processor_id() is OK. 2591 */ 2592 static void mvpp2_txq_sent_counter_clear(void *arg) 2593 { 2594 struct mvpp2_port *port = arg; 2595 int queue; 2596 2597 /* If the thread isn't used, don't do anything */ 2598 if (smp_processor_id() > port->priv->nthreads) 2599 return; 2600 2601 for (queue = 0; queue < port->ntxqs; queue++) { 2602 int id = port->txqs[queue]->id; 2603 2604 mvpp2_thread_read(port->priv, 2605 mvpp2_cpu_to_thread(port->priv, smp_processor_id()), 2606 MVPP2_TXQ_SENT_REG(id)); 2607 } 2608 } 2609 2610 /* Set max sizes for Tx queues */ 2611 static void mvpp2_txp_max_tx_size_set(struct mvpp2_port *port) 2612 { 2613 u32 val, size, mtu; 2614 int txq, tx_port_num; 2615 2616 mtu = port->pkt_size * 8; 2617 if (mtu > MVPP2_TXP_MTU_MAX) 2618 mtu = MVPP2_TXP_MTU_MAX; 2619 2620 /* WA for wrong Token bucket update: Set MTU value = 3*real MTU value */ 2621 mtu = 3 * mtu; 2622 2623 /* Indirect access to registers */ 2624 tx_port_num = mvpp2_egress_port(port); 2625 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num); 2626 2627 /* Set MTU */ 2628 val = mvpp2_read(port->priv, MVPP2_TXP_SCHED_MTU_REG); 2629 val &= ~MVPP2_TXP_MTU_MAX; 2630 val |= mtu; 2631 mvpp2_write(port->priv, MVPP2_TXP_SCHED_MTU_REG, val); 2632 2633 /* TXP token size and all TXQs token size must be larger that MTU */ 2634 val = mvpp2_read(port->priv, MVPP2_TXP_SCHED_TOKEN_SIZE_REG); 2635 size = val & MVPP2_TXP_TOKEN_SIZE_MAX; 2636 if (size < mtu) { 2637 size = mtu; 2638 val &= ~MVPP2_TXP_TOKEN_SIZE_MAX; 2639 val |= size; 2640 mvpp2_write(port->priv, MVPP2_TXP_SCHED_TOKEN_SIZE_REG, val); 2641 } 2642 2643 for (txq = 0; txq < port->ntxqs; txq++) { 2644 val = mvpp2_read(port->priv, 2645 MVPP2_TXQ_SCHED_TOKEN_SIZE_REG(txq)); 2646 size = val & MVPP2_TXQ_TOKEN_SIZE_MAX; 2647 2648 if (size < mtu) { 2649 size = mtu; 2650 val &= ~MVPP2_TXQ_TOKEN_SIZE_MAX; 2651 val |= size; 2652 mvpp2_write(port->priv, 2653 MVPP2_TXQ_SCHED_TOKEN_SIZE_REG(txq), 2654 val); 2655 } 2656 } 2657 } 2658 2659 /* Set the number of non-occupied descriptors threshold */ 2660 static void mvpp2_set_rxq_free_tresh(struct mvpp2_port *port, 2661 struct mvpp2_rx_queue *rxq) 2662 { 2663 u32 val; 2664 2665 mvpp2_write(port->priv, MVPP2_RXQ_NUM_REG, rxq->id); 2666 2667 val = mvpp2_read(port->priv, MVPP2_RXQ_THRESH_REG); 2668 val &= ~MVPP2_RXQ_NON_OCCUPIED_MASK; 2669 val |= MSS_THRESHOLD_STOP << MVPP2_RXQ_NON_OCCUPIED_OFFSET; 2670 mvpp2_write(port->priv, MVPP2_RXQ_THRESH_REG, val); 2671 } 2672 2673 /* Set the number of packets that will be received before Rx interrupt 2674 * will be generated by HW. 2675 */ 2676 static void mvpp2_rx_pkts_coal_set(struct mvpp2_port *port, 2677 struct mvpp2_rx_queue *rxq) 2678 { 2679 unsigned int thread = mvpp2_cpu_to_thread(port->priv, get_cpu()); 2680 2681 if (rxq->pkts_coal > MVPP2_OCCUPIED_THRESH_MASK) 2682 rxq->pkts_coal = MVPP2_OCCUPIED_THRESH_MASK; 2683 2684 mvpp2_thread_write(port->priv, thread, MVPP2_RXQ_NUM_REG, rxq->id); 2685 mvpp2_thread_write(port->priv, thread, MVPP2_RXQ_THRESH_REG, 2686 rxq->pkts_coal); 2687 2688 put_cpu(); 2689 } 2690 2691 /* For some reason in the LSP this is done on each CPU. Why ? */ 2692 static void mvpp2_tx_pkts_coal_set(struct mvpp2_port *port, 2693 struct mvpp2_tx_queue *txq) 2694 { 2695 unsigned int thread; 2696 u32 val; 2697 2698 if (txq->done_pkts_coal > MVPP2_TXQ_THRESH_MASK) 2699 txq->done_pkts_coal = MVPP2_TXQ_THRESH_MASK; 2700 2701 val = (txq->done_pkts_coal << MVPP2_TXQ_THRESH_OFFSET); 2702 /* PKT-coalescing registers are per-queue + per-thread */ 2703 for (thread = 0; thread < MVPP2_MAX_THREADS; thread++) { 2704 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_NUM_REG, txq->id); 2705 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_THRESH_REG, val); 2706 } 2707 } 2708 2709 static u32 mvpp2_usec_to_cycles(u32 usec, unsigned long clk_hz) 2710 { 2711 u64 tmp = (u64)clk_hz * usec; 2712 2713 do_div(tmp, USEC_PER_SEC); 2714 2715 return tmp > U32_MAX ? U32_MAX : tmp; 2716 } 2717 2718 static u32 mvpp2_cycles_to_usec(u32 cycles, unsigned long clk_hz) 2719 { 2720 u64 tmp = (u64)cycles * USEC_PER_SEC; 2721 2722 do_div(tmp, clk_hz); 2723 2724 return tmp > U32_MAX ? U32_MAX : tmp; 2725 } 2726 2727 /* Set the time delay in usec before Rx interrupt */ 2728 static void mvpp2_rx_time_coal_set(struct mvpp2_port *port, 2729 struct mvpp2_rx_queue *rxq) 2730 { 2731 unsigned long freq = port->priv->tclk; 2732 u32 val = mvpp2_usec_to_cycles(rxq->time_coal, freq); 2733 2734 if (val > MVPP2_MAX_ISR_RX_THRESHOLD) { 2735 rxq->time_coal = 2736 mvpp2_cycles_to_usec(MVPP2_MAX_ISR_RX_THRESHOLD, freq); 2737 2738 /* re-evaluate to get actual register value */ 2739 val = mvpp2_usec_to_cycles(rxq->time_coal, freq); 2740 } 2741 2742 mvpp2_write(port->priv, MVPP2_ISR_RX_THRESHOLD_REG(rxq->id), val); 2743 } 2744 2745 static void mvpp2_tx_time_coal_set(struct mvpp2_port *port) 2746 { 2747 unsigned long freq = port->priv->tclk; 2748 u32 val = mvpp2_usec_to_cycles(port->tx_time_coal, freq); 2749 2750 if (val > MVPP2_MAX_ISR_TX_THRESHOLD) { 2751 port->tx_time_coal = 2752 mvpp2_cycles_to_usec(MVPP2_MAX_ISR_TX_THRESHOLD, freq); 2753 2754 /* re-evaluate to get actual register value */ 2755 val = mvpp2_usec_to_cycles(port->tx_time_coal, freq); 2756 } 2757 2758 mvpp2_write(port->priv, MVPP2_ISR_TX_THRESHOLD_REG(port->id), val); 2759 } 2760 2761 /* Free Tx queue skbuffs */ 2762 static void mvpp2_txq_bufs_free(struct mvpp2_port *port, 2763 struct mvpp2_tx_queue *txq, 2764 struct mvpp2_txq_pcpu *txq_pcpu, int num) 2765 { 2766 struct xdp_frame_bulk bq; 2767 int i; 2768 2769 xdp_frame_bulk_init(&bq); 2770 2771 rcu_read_lock(); /* need for xdp_return_frame_bulk */ 2772 2773 for (i = 0; i < num; i++) { 2774 struct mvpp2_txq_pcpu_buf *tx_buf = 2775 txq_pcpu->buffs + txq_pcpu->txq_get_index; 2776 2777 if (!IS_TSO_HEADER(txq_pcpu, tx_buf->dma) && 2778 tx_buf->type != MVPP2_TYPE_XDP_TX) 2779 dma_unmap_single(port->dev->dev.parent, tx_buf->dma, 2780 tx_buf->size, DMA_TO_DEVICE); 2781 if (tx_buf->type == MVPP2_TYPE_SKB && tx_buf->skb) 2782 dev_kfree_skb_any(tx_buf->skb); 2783 else if (tx_buf->type == MVPP2_TYPE_XDP_TX || 2784 tx_buf->type == MVPP2_TYPE_XDP_NDO) 2785 xdp_return_frame_bulk(tx_buf->xdpf, &bq); 2786 2787 mvpp2_txq_inc_get(txq_pcpu); 2788 } 2789 xdp_flush_frame_bulk(&bq); 2790 2791 rcu_read_unlock(); 2792 } 2793 2794 static inline struct mvpp2_rx_queue *mvpp2_get_rx_queue(struct mvpp2_port *port, 2795 u32 cause) 2796 { 2797 int queue = fls(cause) - 1; 2798 2799 return port->rxqs[queue]; 2800 } 2801 2802 static inline struct mvpp2_tx_queue *mvpp2_get_tx_queue(struct mvpp2_port *port, 2803 u32 cause) 2804 { 2805 int queue = fls(cause) - 1; 2806 2807 return port->txqs[queue]; 2808 } 2809 2810 /* Handle end of transmission */ 2811 static void mvpp2_txq_done(struct mvpp2_port *port, struct mvpp2_tx_queue *txq, 2812 struct mvpp2_txq_pcpu *txq_pcpu) 2813 { 2814 struct netdev_queue *nq = netdev_get_tx_queue(port->dev, txq->log_id); 2815 int tx_done; 2816 2817 if (txq_pcpu->thread != mvpp2_cpu_to_thread(port->priv, smp_processor_id())) 2818 netdev_err(port->dev, "wrong cpu on the end of Tx processing\n"); 2819 2820 tx_done = mvpp2_txq_sent_desc_proc(port, txq); 2821 if (!tx_done) 2822 return; 2823 mvpp2_txq_bufs_free(port, txq, txq_pcpu, tx_done); 2824 2825 txq_pcpu->count -= tx_done; 2826 2827 if (netif_tx_queue_stopped(nq)) 2828 if (txq_pcpu->count <= txq_pcpu->wake_threshold) 2829 netif_tx_wake_queue(nq); 2830 } 2831 2832 static unsigned int mvpp2_tx_done(struct mvpp2_port *port, u32 cause, 2833 unsigned int thread) 2834 { 2835 struct mvpp2_tx_queue *txq; 2836 struct mvpp2_txq_pcpu *txq_pcpu; 2837 unsigned int tx_todo = 0; 2838 2839 while (cause) { 2840 txq = mvpp2_get_tx_queue(port, cause); 2841 if (!txq) 2842 break; 2843 2844 txq_pcpu = per_cpu_ptr(txq->pcpu, thread); 2845 2846 if (txq_pcpu->count) { 2847 mvpp2_txq_done(port, txq, txq_pcpu); 2848 tx_todo += txq_pcpu->count; 2849 } 2850 2851 cause &= ~(1 << txq->log_id); 2852 } 2853 return tx_todo; 2854 } 2855 2856 /* Rx/Tx queue initialization/cleanup methods */ 2857 2858 /* Allocate and initialize descriptors for aggr TXQ */ 2859 static int mvpp2_aggr_txq_init(struct platform_device *pdev, 2860 struct mvpp2_tx_queue *aggr_txq, 2861 unsigned int thread, struct mvpp2 *priv) 2862 { 2863 u32 txq_dma; 2864 2865 /* Allocate memory for TX descriptors */ 2866 aggr_txq->descs = dma_alloc_coherent(&pdev->dev, 2867 MVPP2_AGGR_TXQ_SIZE * MVPP2_DESC_ALIGNED_SIZE, 2868 &aggr_txq->descs_dma, GFP_KERNEL); 2869 if (!aggr_txq->descs) 2870 return -ENOMEM; 2871 2872 aggr_txq->last_desc = MVPP2_AGGR_TXQ_SIZE - 1; 2873 2874 /* Aggr TXQ no reset WA */ 2875 aggr_txq->next_desc_to_proc = mvpp2_read(priv, 2876 MVPP2_AGGR_TXQ_INDEX_REG(thread)); 2877 2878 /* Set Tx descriptors queue starting address indirect 2879 * access 2880 */ 2881 if (priv->hw_version == MVPP21) 2882 txq_dma = aggr_txq->descs_dma; 2883 else 2884 txq_dma = aggr_txq->descs_dma >> 2885 MVPP22_AGGR_TXQ_DESC_ADDR_OFFS; 2886 2887 mvpp2_write(priv, MVPP2_AGGR_TXQ_DESC_ADDR_REG(thread), txq_dma); 2888 mvpp2_write(priv, MVPP2_AGGR_TXQ_DESC_SIZE_REG(thread), 2889 MVPP2_AGGR_TXQ_SIZE); 2890 2891 return 0; 2892 } 2893 2894 /* Create a specified Rx queue */ 2895 static int mvpp2_rxq_init(struct mvpp2_port *port, 2896 struct mvpp2_rx_queue *rxq) 2897 { 2898 struct mvpp2 *priv = port->priv; 2899 unsigned int thread; 2900 u32 rxq_dma; 2901 int err; 2902 2903 rxq->size = port->rx_ring_size; 2904 2905 /* Allocate memory for RX descriptors */ 2906 rxq->descs = dma_alloc_coherent(port->dev->dev.parent, 2907 rxq->size * MVPP2_DESC_ALIGNED_SIZE, 2908 &rxq->descs_dma, GFP_KERNEL); 2909 if (!rxq->descs) 2910 return -ENOMEM; 2911 2912 rxq->last_desc = rxq->size - 1; 2913 2914 /* Zero occupied and non-occupied counters - direct access */ 2915 mvpp2_write(port->priv, MVPP2_RXQ_STATUS_REG(rxq->id), 0); 2916 2917 /* Set Rx descriptors queue starting address - indirect access */ 2918 thread = mvpp2_cpu_to_thread(port->priv, get_cpu()); 2919 mvpp2_thread_write(port->priv, thread, MVPP2_RXQ_NUM_REG, rxq->id); 2920 if (port->priv->hw_version == MVPP21) 2921 rxq_dma = rxq->descs_dma; 2922 else 2923 rxq_dma = rxq->descs_dma >> MVPP22_DESC_ADDR_OFFS; 2924 mvpp2_thread_write(port->priv, thread, MVPP2_RXQ_DESC_ADDR_REG, rxq_dma); 2925 mvpp2_thread_write(port->priv, thread, MVPP2_RXQ_DESC_SIZE_REG, rxq->size); 2926 mvpp2_thread_write(port->priv, thread, MVPP2_RXQ_INDEX_REG, 0); 2927 put_cpu(); 2928 2929 /* Set Offset */ 2930 mvpp2_rxq_offset_set(port, rxq->id, MVPP2_SKB_HEADROOM); 2931 2932 /* Set coalescing pkts and time */ 2933 mvpp2_rx_pkts_coal_set(port, rxq); 2934 mvpp2_rx_time_coal_set(port, rxq); 2935 2936 /* Set the number of non occupied descriptors threshold */ 2937 mvpp2_set_rxq_free_tresh(port, rxq); 2938 2939 /* Add number of descriptors ready for receiving packets */ 2940 mvpp2_rxq_status_update(port, rxq->id, 0, rxq->size); 2941 2942 if (priv->percpu_pools) { 2943 err = xdp_rxq_info_reg(&rxq->xdp_rxq_short, port->dev, rxq->id, 0); 2944 if (err < 0) 2945 goto err_free_dma; 2946 2947 err = xdp_rxq_info_reg(&rxq->xdp_rxq_long, port->dev, rxq->id, 0); 2948 if (err < 0) 2949 goto err_unregister_rxq_short; 2950 2951 /* Every RXQ has a pool for short and another for long packets */ 2952 err = xdp_rxq_info_reg_mem_model(&rxq->xdp_rxq_short, 2953 MEM_TYPE_PAGE_POOL, 2954 priv->page_pool[rxq->logic_rxq]); 2955 if (err < 0) 2956 goto err_unregister_rxq_long; 2957 2958 err = xdp_rxq_info_reg_mem_model(&rxq->xdp_rxq_long, 2959 MEM_TYPE_PAGE_POOL, 2960 priv->page_pool[rxq->logic_rxq + 2961 port->nrxqs]); 2962 if (err < 0) 2963 goto err_unregister_mem_rxq_short; 2964 } 2965 2966 return 0; 2967 2968 err_unregister_mem_rxq_short: 2969 xdp_rxq_info_unreg_mem_model(&rxq->xdp_rxq_short); 2970 err_unregister_rxq_long: 2971 xdp_rxq_info_unreg(&rxq->xdp_rxq_long); 2972 err_unregister_rxq_short: 2973 xdp_rxq_info_unreg(&rxq->xdp_rxq_short); 2974 err_free_dma: 2975 dma_free_coherent(port->dev->dev.parent, 2976 rxq->size * MVPP2_DESC_ALIGNED_SIZE, 2977 rxq->descs, rxq->descs_dma); 2978 return err; 2979 } 2980 2981 /* Push packets received by the RXQ to BM pool */ 2982 static void mvpp2_rxq_drop_pkts(struct mvpp2_port *port, 2983 struct mvpp2_rx_queue *rxq) 2984 { 2985 int rx_received, i; 2986 2987 rx_received = mvpp2_rxq_received(port, rxq->id); 2988 if (!rx_received) 2989 return; 2990 2991 for (i = 0; i < rx_received; i++) { 2992 struct mvpp2_rx_desc *rx_desc = mvpp2_rxq_next_desc_get(rxq); 2993 u32 status = mvpp2_rxdesc_status_get(port, rx_desc); 2994 int pool; 2995 2996 pool = (status & MVPP2_RXD_BM_POOL_ID_MASK) >> 2997 MVPP2_RXD_BM_POOL_ID_OFFS; 2998 2999 mvpp2_bm_pool_put(port, pool, 3000 mvpp2_rxdesc_dma_addr_get(port, rx_desc), 3001 mvpp2_rxdesc_cookie_get(port, rx_desc)); 3002 } 3003 mvpp2_rxq_status_update(port, rxq->id, rx_received, rx_received); 3004 } 3005 3006 /* Cleanup Rx queue */ 3007 static void mvpp2_rxq_deinit(struct mvpp2_port *port, 3008 struct mvpp2_rx_queue *rxq) 3009 { 3010 unsigned int thread; 3011 3012 if (xdp_rxq_info_is_reg(&rxq->xdp_rxq_short)) 3013 xdp_rxq_info_unreg(&rxq->xdp_rxq_short); 3014 3015 if (xdp_rxq_info_is_reg(&rxq->xdp_rxq_long)) 3016 xdp_rxq_info_unreg(&rxq->xdp_rxq_long); 3017 3018 mvpp2_rxq_drop_pkts(port, rxq); 3019 3020 if (rxq->descs) 3021 dma_free_coherent(port->dev->dev.parent, 3022 rxq->size * MVPP2_DESC_ALIGNED_SIZE, 3023 rxq->descs, 3024 rxq->descs_dma); 3025 3026 rxq->descs = NULL; 3027 rxq->last_desc = 0; 3028 rxq->next_desc_to_proc = 0; 3029 rxq->descs_dma = 0; 3030 3031 /* Clear Rx descriptors queue starting address and size; 3032 * free descriptor number 3033 */ 3034 mvpp2_write(port->priv, MVPP2_RXQ_STATUS_REG(rxq->id), 0); 3035 thread = mvpp2_cpu_to_thread(port->priv, get_cpu()); 3036 mvpp2_thread_write(port->priv, thread, MVPP2_RXQ_NUM_REG, rxq->id); 3037 mvpp2_thread_write(port->priv, thread, MVPP2_RXQ_DESC_ADDR_REG, 0); 3038 mvpp2_thread_write(port->priv, thread, MVPP2_RXQ_DESC_SIZE_REG, 0); 3039 put_cpu(); 3040 } 3041 3042 /* Create and initialize a Tx queue */ 3043 static int mvpp2_txq_init(struct mvpp2_port *port, 3044 struct mvpp2_tx_queue *txq) 3045 { 3046 u32 val; 3047 unsigned int thread; 3048 int desc, desc_per_txq, tx_port_num; 3049 struct mvpp2_txq_pcpu *txq_pcpu; 3050 3051 txq->size = port->tx_ring_size; 3052 3053 /* Allocate memory for Tx descriptors */ 3054 txq->descs = dma_alloc_coherent(port->dev->dev.parent, 3055 txq->size * MVPP2_DESC_ALIGNED_SIZE, 3056 &txq->descs_dma, GFP_KERNEL); 3057 if (!txq->descs) 3058 return -ENOMEM; 3059 3060 txq->last_desc = txq->size - 1; 3061 3062 /* Set Tx descriptors queue starting address - indirect access */ 3063 thread = mvpp2_cpu_to_thread(port->priv, get_cpu()); 3064 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_NUM_REG, txq->id); 3065 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_DESC_ADDR_REG, 3066 txq->descs_dma); 3067 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_DESC_SIZE_REG, 3068 txq->size & MVPP2_TXQ_DESC_SIZE_MASK); 3069 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_INDEX_REG, 0); 3070 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_RSVD_CLR_REG, 3071 txq->id << MVPP2_TXQ_RSVD_CLR_OFFSET); 3072 val = mvpp2_thread_read(port->priv, thread, MVPP2_TXQ_PENDING_REG); 3073 val &= ~MVPP2_TXQ_PENDING_MASK; 3074 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_PENDING_REG, val); 3075 3076 /* Calculate base address in prefetch buffer. We reserve 16 descriptors 3077 * for each existing TXQ. 3078 * TCONTS for PON port must be continuous from 0 to MVPP2_MAX_TCONT 3079 * GBE ports assumed to be continuous from 0 to MVPP2_MAX_PORTS 3080 */ 3081 desc_per_txq = 16; 3082 desc = (port->id * MVPP2_MAX_TXQ * desc_per_txq) + 3083 (txq->log_id * desc_per_txq); 3084 3085 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_PREF_BUF_REG, 3086 MVPP2_PREF_BUF_PTR(desc) | MVPP2_PREF_BUF_SIZE_16 | 3087 MVPP2_PREF_BUF_THRESH(desc_per_txq / 2)); 3088 put_cpu(); 3089 3090 /* WRR / EJP configuration - indirect access */ 3091 tx_port_num = mvpp2_egress_port(port); 3092 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num); 3093 3094 val = mvpp2_read(port->priv, MVPP2_TXQ_SCHED_REFILL_REG(txq->log_id)); 3095 val &= ~MVPP2_TXQ_REFILL_PERIOD_ALL_MASK; 3096 val |= MVPP2_TXQ_REFILL_PERIOD_MASK(1); 3097 val |= MVPP2_TXQ_REFILL_TOKENS_ALL_MASK; 3098 mvpp2_write(port->priv, MVPP2_TXQ_SCHED_REFILL_REG(txq->log_id), val); 3099 3100 val = MVPP2_TXQ_TOKEN_SIZE_MAX; 3101 mvpp2_write(port->priv, MVPP2_TXQ_SCHED_TOKEN_SIZE_REG(txq->log_id), 3102 val); 3103 3104 for (thread = 0; thread < port->priv->nthreads; thread++) { 3105 txq_pcpu = per_cpu_ptr(txq->pcpu, thread); 3106 txq_pcpu->size = txq->size; 3107 txq_pcpu->buffs = kmalloc_array(txq_pcpu->size, 3108 sizeof(*txq_pcpu->buffs), 3109 GFP_KERNEL); 3110 if (!txq_pcpu->buffs) 3111 return -ENOMEM; 3112 3113 txq_pcpu->count = 0; 3114 txq_pcpu->reserved_num = 0; 3115 txq_pcpu->txq_put_index = 0; 3116 txq_pcpu->txq_get_index = 0; 3117 txq_pcpu->tso_headers = NULL; 3118 3119 txq_pcpu->stop_threshold = txq->size - MVPP2_MAX_SKB_DESCS; 3120 txq_pcpu->wake_threshold = txq_pcpu->stop_threshold / 2; 3121 3122 txq_pcpu->tso_headers = 3123 dma_alloc_coherent(port->dev->dev.parent, 3124 txq_pcpu->size * TSO_HEADER_SIZE, 3125 &txq_pcpu->tso_headers_dma, 3126 GFP_KERNEL); 3127 if (!txq_pcpu->tso_headers) 3128 return -ENOMEM; 3129 } 3130 3131 return 0; 3132 } 3133 3134 /* Free allocated TXQ resources */ 3135 static void mvpp2_txq_deinit(struct mvpp2_port *port, 3136 struct mvpp2_tx_queue *txq) 3137 { 3138 struct mvpp2_txq_pcpu *txq_pcpu; 3139 unsigned int thread; 3140 3141 for (thread = 0; thread < port->priv->nthreads; thread++) { 3142 txq_pcpu = per_cpu_ptr(txq->pcpu, thread); 3143 kfree(txq_pcpu->buffs); 3144 3145 if (txq_pcpu->tso_headers) 3146 dma_free_coherent(port->dev->dev.parent, 3147 txq_pcpu->size * TSO_HEADER_SIZE, 3148 txq_pcpu->tso_headers, 3149 txq_pcpu->tso_headers_dma); 3150 3151 txq_pcpu->tso_headers = NULL; 3152 } 3153 3154 if (txq->descs) 3155 dma_free_coherent(port->dev->dev.parent, 3156 txq->size * MVPP2_DESC_ALIGNED_SIZE, 3157 txq->descs, txq->descs_dma); 3158 3159 txq->descs = NULL; 3160 txq->last_desc = 0; 3161 txq->next_desc_to_proc = 0; 3162 txq->descs_dma = 0; 3163 3164 /* Set minimum bandwidth for disabled TXQs */ 3165 mvpp2_write(port->priv, MVPP2_TXQ_SCHED_TOKEN_CNTR_REG(txq->log_id), 0); 3166 3167 /* Set Tx descriptors queue starting address and size */ 3168 thread = mvpp2_cpu_to_thread(port->priv, get_cpu()); 3169 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_NUM_REG, txq->id); 3170 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_DESC_ADDR_REG, 0); 3171 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_DESC_SIZE_REG, 0); 3172 put_cpu(); 3173 } 3174 3175 /* Cleanup Tx ports */ 3176 static void mvpp2_txq_clean(struct mvpp2_port *port, struct mvpp2_tx_queue *txq) 3177 { 3178 struct mvpp2_txq_pcpu *txq_pcpu; 3179 int delay, pending; 3180 unsigned int thread = mvpp2_cpu_to_thread(port->priv, get_cpu()); 3181 u32 val; 3182 3183 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_NUM_REG, txq->id); 3184 val = mvpp2_thread_read(port->priv, thread, MVPP2_TXQ_PREF_BUF_REG); 3185 val |= MVPP2_TXQ_DRAIN_EN_MASK; 3186 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_PREF_BUF_REG, val); 3187 3188 /* The napi queue has been stopped so wait for all packets 3189 * to be transmitted. 3190 */ 3191 delay = 0; 3192 do { 3193 if (delay >= MVPP2_TX_PENDING_TIMEOUT_MSEC) { 3194 netdev_warn(port->dev, 3195 "port %d: cleaning queue %d timed out\n", 3196 port->id, txq->log_id); 3197 break; 3198 } 3199 mdelay(1); 3200 delay++; 3201 3202 pending = mvpp2_thread_read(port->priv, thread, 3203 MVPP2_TXQ_PENDING_REG); 3204 pending &= MVPP2_TXQ_PENDING_MASK; 3205 } while (pending); 3206 3207 val &= ~MVPP2_TXQ_DRAIN_EN_MASK; 3208 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_PREF_BUF_REG, val); 3209 put_cpu(); 3210 3211 for (thread = 0; thread < port->priv->nthreads; thread++) { 3212 txq_pcpu = per_cpu_ptr(txq->pcpu, thread); 3213 3214 /* Release all packets */ 3215 mvpp2_txq_bufs_free(port, txq, txq_pcpu, txq_pcpu->count); 3216 3217 /* Reset queue */ 3218 txq_pcpu->count = 0; 3219 txq_pcpu->txq_put_index = 0; 3220 txq_pcpu->txq_get_index = 0; 3221 } 3222 } 3223 3224 /* Cleanup all Tx queues */ 3225 static void mvpp2_cleanup_txqs(struct mvpp2_port *port) 3226 { 3227 struct mvpp2_tx_queue *txq; 3228 int queue; 3229 u32 val; 3230 3231 val = mvpp2_read(port->priv, MVPP2_TX_PORT_FLUSH_REG); 3232 3233 /* Reset Tx ports and delete Tx queues */ 3234 val |= MVPP2_TX_PORT_FLUSH_MASK(port->id); 3235 mvpp2_write(port->priv, MVPP2_TX_PORT_FLUSH_REG, val); 3236 3237 for (queue = 0; queue < port->ntxqs; queue++) { 3238 txq = port->txqs[queue]; 3239 mvpp2_txq_clean(port, txq); 3240 mvpp2_txq_deinit(port, txq); 3241 } 3242 3243 on_each_cpu(mvpp2_txq_sent_counter_clear, port, 1); 3244 3245 val &= ~MVPP2_TX_PORT_FLUSH_MASK(port->id); 3246 mvpp2_write(port->priv, MVPP2_TX_PORT_FLUSH_REG, val); 3247 } 3248 3249 /* Cleanup all Rx queues */ 3250 static void mvpp2_cleanup_rxqs(struct mvpp2_port *port) 3251 { 3252 int queue; 3253 3254 for (queue = 0; queue < port->nrxqs; queue++) 3255 mvpp2_rxq_deinit(port, port->rxqs[queue]); 3256 3257 if (port->tx_fc) 3258 mvpp2_rxq_disable_fc(port); 3259 } 3260 3261 /* Init all Rx queues for port */ 3262 static int mvpp2_setup_rxqs(struct mvpp2_port *port) 3263 { 3264 int queue, err; 3265 3266 for (queue = 0; queue < port->nrxqs; queue++) { 3267 err = mvpp2_rxq_init(port, port->rxqs[queue]); 3268 if (err) 3269 goto err_cleanup; 3270 } 3271 3272 if (port->tx_fc) 3273 mvpp2_rxq_enable_fc(port); 3274 3275 return 0; 3276 3277 err_cleanup: 3278 mvpp2_cleanup_rxqs(port); 3279 return err; 3280 } 3281 3282 /* Init all tx queues for port */ 3283 static int mvpp2_setup_txqs(struct mvpp2_port *port) 3284 { 3285 struct mvpp2_tx_queue *txq; 3286 int queue, err; 3287 3288 for (queue = 0; queue < port->ntxqs; queue++) { 3289 txq = port->txqs[queue]; 3290 err = mvpp2_txq_init(port, txq); 3291 if (err) 3292 goto err_cleanup; 3293 3294 /* Assign this queue to a CPU */ 3295 if (queue < num_possible_cpus()) 3296 netif_set_xps_queue(port->dev, cpumask_of(queue), queue); 3297 } 3298 3299 if (port->has_tx_irqs) { 3300 mvpp2_tx_time_coal_set(port); 3301 for (queue = 0; queue < port->ntxqs; queue++) { 3302 txq = port->txqs[queue]; 3303 mvpp2_tx_pkts_coal_set(port, txq); 3304 } 3305 } 3306 3307 on_each_cpu(mvpp2_txq_sent_counter_clear, port, 1); 3308 return 0; 3309 3310 err_cleanup: 3311 mvpp2_cleanup_txqs(port); 3312 return err; 3313 } 3314 3315 /* The callback for per-port interrupt */ 3316 static irqreturn_t mvpp2_isr(int irq, void *dev_id) 3317 { 3318 struct mvpp2_queue_vector *qv = dev_id; 3319 3320 mvpp2_qvec_interrupt_disable(qv); 3321 3322 napi_schedule(&qv->napi); 3323 3324 return IRQ_HANDLED; 3325 } 3326 3327 static void mvpp2_isr_handle_ptp_queue(struct mvpp2_port *port, int nq) 3328 { 3329 struct skb_shared_hwtstamps shhwtstamps; 3330 struct mvpp2_hwtstamp_queue *queue; 3331 struct sk_buff *skb; 3332 void __iomem *ptp_q; 3333 unsigned int id; 3334 u32 r0, r1, r2; 3335 3336 ptp_q = port->priv->iface_base + MVPP22_PTP_BASE(port->gop_id); 3337 if (nq) 3338 ptp_q += MVPP22_PTP_TX_Q1_R0 - MVPP22_PTP_TX_Q0_R0; 3339 3340 queue = &port->tx_hwtstamp_queue[nq]; 3341 3342 while (1) { 3343 r0 = readl_relaxed(ptp_q + MVPP22_PTP_TX_Q0_R0) & 0xffff; 3344 if (!r0) 3345 break; 3346 3347 r1 = readl_relaxed(ptp_q + MVPP22_PTP_TX_Q0_R1) & 0xffff; 3348 r2 = readl_relaxed(ptp_q + MVPP22_PTP_TX_Q0_R2) & 0xffff; 3349 3350 id = (r0 >> 1) & 31; 3351 3352 skb = queue->skb[id]; 3353 queue->skb[id] = NULL; 3354 if (skb) { 3355 u32 ts = r2 << 19 | r1 << 3 | r0 >> 13; 3356 3357 mvpp22_tai_tstamp(port->priv->tai, ts, &shhwtstamps); 3358 skb_tstamp_tx(skb, &shhwtstamps); 3359 dev_kfree_skb_any(skb); 3360 } 3361 } 3362 } 3363 3364 static void mvpp2_isr_handle_ptp(struct mvpp2_port *port) 3365 { 3366 void __iomem *ptp; 3367 u32 val; 3368 3369 ptp = port->priv->iface_base + MVPP22_PTP_BASE(port->gop_id); 3370 val = readl(ptp + MVPP22_PTP_INT_CAUSE); 3371 if (val & MVPP22_PTP_INT_CAUSE_QUEUE0) 3372 mvpp2_isr_handle_ptp_queue(port, 0); 3373 if (val & MVPP22_PTP_INT_CAUSE_QUEUE1) 3374 mvpp2_isr_handle_ptp_queue(port, 1); 3375 } 3376 3377 static void mvpp2_isr_handle_link(struct mvpp2_port *port, bool link) 3378 { 3379 struct net_device *dev = port->dev; 3380 3381 if (port->phylink) { 3382 phylink_mac_change(port->phylink, link); 3383 return; 3384 } 3385 3386 if (!netif_running(dev)) 3387 return; 3388 3389 if (link) { 3390 mvpp2_interrupts_enable(port); 3391 3392 mvpp2_egress_enable(port); 3393 mvpp2_ingress_enable(port); 3394 netif_carrier_on(dev); 3395 netif_tx_wake_all_queues(dev); 3396 } else { 3397 netif_tx_stop_all_queues(dev); 3398 netif_carrier_off(dev); 3399 mvpp2_ingress_disable(port); 3400 mvpp2_egress_disable(port); 3401 3402 mvpp2_interrupts_disable(port); 3403 } 3404 } 3405 3406 static void mvpp2_isr_handle_xlg(struct mvpp2_port *port) 3407 { 3408 bool link; 3409 u32 val; 3410 3411 val = readl(port->base + MVPP22_XLG_INT_STAT); 3412 if (val & MVPP22_XLG_INT_STAT_LINK) { 3413 val = readl(port->base + MVPP22_XLG_STATUS); 3414 link = (val & MVPP22_XLG_STATUS_LINK_UP); 3415 mvpp2_isr_handle_link(port, link); 3416 } 3417 } 3418 3419 static void mvpp2_isr_handle_gmac_internal(struct mvpp2_port *port) 3420 { 3421 bool link; 3422 u32 val; 3423 3424 if (phy_interface_mode_is_rgmii(port->phy_interface) || 3425 phy_interface_mode_is_8023z(port->phy_interface) || 3426 port->phy_interface == PHY_INTERFACE_MODE_SGMII) { 3427 val = readl(port->base + MVPP22_GMAC_INT_STAT); 3428 if (val & MVPP22_GMAC_INT_STAT_LINK) { 3429 val = readl(port->base + MVPP2_GMAC_STATUS0); 3430 link = (val & MVPP2_GMAC_STATUS0_LINK_UP); 3431 mvpp2_isr_handle_link(port, link); 3432 } 3433 } 3434 } 3435 3436 /* Per-port interrupt for link status changes */ 3437 static irqreturn_t mvpp2_port_isr(int irq, void *dev_id) 3438 { 3439 struct mvpp2_port *port = (struct mvpp2_port *)dev_id; 3440 u32 val; 3441 3442 mvpp22_gop_mask_irq(port); 3443 3444 if (mvpp2_port_supports_xlg(port) && 3445 mvpp2_is_xlg(port->phy_interface)) { 3446 /* Check the external status register */ 3447 val = readl(port->base + MVPP22_XLG_EXT_INT_STAT); 3448 if (val & MVPP22_XLG_EXT_INT_STAT_XLG) 3449 mvpp2_isr_handle_xlg(port); 3450 if (val & MVPP22_XLG_EXT_INT_STAT_PTP) 3451 mvpp2_isr_handle_ptp(port); 3452 } else { 3453 /* If it's not the XLG, we must be using the GMAC. 3454 * Check the summary status. 3455 */ 3456 val = readl(port->base + MVPP22_GMAC_INT_SUM_STAT); 3457 if (val & MVPP22_GMAC_INT_SUM_STAT_INTERNAL) 3458 mvpp2_isr_handle_gmac_internal(port); 3459 if (val & MVPP22_GMAC_INT_SUM_STAT_PTP) 3460 mvpp2_isr_handle_ptp(port); 3461 } 3462 3463 mvpp22_gop_unmask_irq(port); 3464 return IRQ_HANDLED; 3465 } 3466 3467 static enum hrtimer_restart mvpp2_hr_timer_cb(struct hrtimer *timer) 3468 { 3469 struct net_device *dev; 3470 struct mvpp2_port *port; 3471 struct mvpp2_port_pcpu *port_pcpu; 3472 unsigned int tx_todo, cause; 3473 3474 port_pcpu = container_of(timer, struct mvpp2_port_pcpu, tx_done_timer); 3475 dev = port_pcpu->dev; 3476 3477 if (!netif_running(dev)) 3478 return HRTIMER_NORESTART; 3479 3480 port_pcpu->timer_scheduled = false; 3481 port = netdev_priv(dev); 3482 3483 /* Process all the Tx queues */ 3484 cause = (1 << port->ntxqs) - 1; 3485 tx_todo = mvpp2_tx_done(port, cause, 3486 mvpp2_cpu_to_thread(port->priv, smp_processor_id())); 3487 3488 /* Set the timer in case not all the packets were processed */ 3489 if (tx_todo && !port_pcpu->timer_scheduled) { 3490 port_pcpu->timer_scheduled = true; 3491 hrtimer_forward_now(&port_pcpu->tx_done_timer, 3492 MVPP2_TXDONE_HRTIMER_PERIOD_NS); 3493 3494 return HRTIMER_RESTART; 3495 } 3496 return HRTIMER_NORESTART; 3497 } 3498 3499 /* Main RX/TX processing routines */ 3500 3501 /* Display more error info */ 3502 static void mvpp2_rx_error(struct mvpp2_port *port, 3503 struct mvpp2_rx_desc *rx_desc) 3504 { 3505 u32 status = mvpp2_rxdesc_status_get(port, rx_desc); 3506 size_t sz = mvpp2_rxdesc_size_get(port, rx_desc); 3507 char *err_str = NULL; 3508 3509 switch (status & MVPP2_RXD_ERR_CODE_MASK) { 3510 case MVPP2_RXD_ERR_CRC: 3511 err_str = "crc"; 3512 break; 3513 case MVPP2_RXD_ERR_OVERRUN: 3514 err_str = "overrun"; 3515 break; 3516 case MVPP2_RXD_ERR_RESOURCE: 3517 err_str = "resource"; 3518 break; 3519 } 3520 if (err_str && net_ratelimit()) 3521 netdev_err(port->dev, 3522 "bad rx status %08x (%s error), size=%zu\n", 3523 status, err_str, sz); 3524 } 3525 3526 /* Handle RX checksum offload */ 3527 static void mvpp2_rx_csum(struct mvpp2_port *port, u32 status, 3528 struct sk_buff *skb) 3529 { 3530 if (((status & MVPP2_RXD_L3_IP4) && 3531 !(status & MVPP2_RXD_IP4_HEADER_ERR)) || 3532 (status & MVPP2_RXD_L3_IP6)) 3533 if (((status & MVPP2_RXD_L4_UDP) || 3534 (status & MVPP2_RXD_L4_TCP)) && 3535 (status & MVPP2_RXD_L4_CSUM_OK)) { 3536 skb->csum = 0; 3537 skb->ip_summed = CHECKSUM_UNNECESSARY; 3538 return; 3539 } 3540 3541 skb->ip_summed = CHECKSUM_NONE; 3542 } 3543 3544 /* Allocate a new skb and add it to BM pool */ 3545 static int mvpp2_rx_refill(struct mvpp2_port *port, 3546 struct mvpp2_bm_pool *bm_pool, 3547 struct page_pool *page_pool, int pool) 3548 { 3549 dma_addr_t dma_addr; 3550 phys_addr_t phys_addr; 3551 void *buf; 3552 3553 buf = mvpp2_buf_alloc(port, bm_pool, page_pool, 3554 &dma_addr, &phys_addr, GFP_ATOMIC); 3555 if (!buf) 3556 return -ENOMEM; 3557 3558 mvpp2_bm_pool_put(port, pool, dma_addr, phys_addr); 3559 3560 return 0; 3561 } 3562 3563 /* Handle tx checksum */ 3564 static u32 mvpp2_skb_tx_csum(struct mvpp2_port *port, struct sk_buff *skb) 3565 { 3566 if (skb->ip_summed == CHECKSUM_PARTIAL) { 3567 int ip_hdr_len = 0; 3568 u8 l4_proto; 3569 __be16 l3_proto = vlan_get_protocol(skb); 3570 3571 if (l3_proto == htons(ETH_P_IP)) { 3572 struct iphdr *ip4h = ip_hdr(skb); 3573 3574 /* Calculate IPv4 checksum and L4 checksum */ 3575 ip_hdr_len = ip4h->ihl; 3576 l4_proto = ip4h->protocol; 3577 } else if (l3_proto == htons(ETH_P_IPV6)) { 3578 struct ipv6hdr *ip6h = ipv6_hdr(skb); 3579 3580 /* Read l4_protocol from one of IPv6 extra headers */ 3581 if (skb_network_header_len(skb) > 0) 3582 ip_hdr_len = (skb_network_header_len(skb) >> 2); 3583 l4_proto = ip6h->nexthdr; 3584 } else { 3585 return MVPP2_TXD_L4_CSUM_NOT; 3586 } 3587 3588 return mvpp2_txq_desc_csum(skb_network_offset(skb), 3589 l3_proto, ip_hdr_len, l4_proto); 3590 } 3591 3592 return MVPP2_TXD_L4_CSUM_NOT | MVPP2_TXD_IP_CSUM_DISABLE; 3593 } 3594 3595 static void mvpp2_xdp_finish_tx(struct mvpp2_port *port, u16 txq_id, int nxmit, int nxmit_byte) 3596 { 3597 unsigned int thread = mvpp2_cpu_to_thread(port->priv, smp_processor_id()); 3598 struct mvpp2_tx_queue *aggr_txq; 3599 struct mvpp2_txq_pcpu *txq_pcpu; 3600 struct mvpp2_tx_queue *txq; 3601 struct netdev_queue *nq; 3602 3603 txq = port->txqs[txq_id]; 3604 txq_pcpu = per_cpu_ptr(txq->pcpu, thread); 3605 nq = netdev_get_tx_queue(port->dev, txq_id); 3606 aggr_txq = &port->priv->aggr_txqs[thread]; 3607 3608 txq_pcpu->reserved_num -= nxmit; 3609 txq_pcpu->count += nxmit; 3610 aggr_txq->count += nxmit; 3611 3612 /* Enable transmit */ 3613 wmb(); 3614 mvpp2_aggr_txq_pend_desc_add(port, nxmit); 3615 3616 if (txq_pcpu->count >= txq_pcpu->stop_threshold) 3617 netif_tx_stop_queue(nq); 3618 3619 /* Finalize TX processing */ 3620 if (!port->has_tx_irqs && txq_pcpu->count >= txq->done_pkts_coal) 3621 mvpp2_txq_done(port, txq, txq_pcpu); 3622 } 3623 3624 static int 3625 mvpp2_xdp_submit_frame(struct mvpp2_port *port, u16 txq_id, 3626 struct xdp_frame *xdpf, bool dma_map) 3627 { 3628 unsigned int thread = mvpp2_cpu_to_thread(port->priv, smp_processor_id()); 3629 u32 tx_cmd = MVPP2_TXD_L4_CSUM_NOT | MVPP2_TXD_IP_CSUM_DISABLE | 3630 MVPP2_TXD_F_DESC | MVPP2_TXD_L_DESC; 3631 enum mvpp2_tx_buf_type buf_type; 3632 struct mvpp2_txq_pcpu *txq_pcpu; 3633 struct mvpp2_tx_queue *aggr_txq; 3634 struct mvpp2_tx_desc *tx_desc; 3635 struct mvpp2_tx_queue *txq; 3636 int ret = MVPP2_XDP_TX; 3637 dma_addr_t dma_addr; 3638 3639 txq = port->txqs[txq_id]; 3640 txq_pcpu = per_cpu_ptr(txq->pcpu, thread); 3641 aggr_txq = &port->priv->aggr_txqs[thread]; 3642 3643 /* Check number of available descriptors */ 3644 if (mvpp2_aggr_desc_num_check(port, aggr_txq, 1) || 3645 mvpp2_txq_reserved_desc_num_proc(port, txq, txq_pcpu, 1)) { 3646 ret = MVPP2_XDP_DROPPED; 3647 goto out; 3648 } 3649 3650 /* Get a descriptor for the first part of the packet */ 3651 tx_desc = mvpp2_txq_next_desc_get(aggr_txq); 3652 mvpp2_txdesc_txq_set(port, tx_desc, txq->id); 3653 mvpp2_txdesc_size_set(port, tx_desc, xdpf->len); 3654 3655 if (dma_map) { 3656 /* XDP_REDIRECT or AF_XDP */ 3657 dma_addr = dma_map_single(port->dev->dev.parent, xdpf->data, 3658 xdpf->len, DMA_TO_DEVICE); 3659 3660 if (unlikely(dma_mapping_error(port->dev->dev.parent, dma_addr))) { 3661 mvpp2_txq_desc_put(txq); 3662 ret = MVPP2_XDP_DROPPED; 3663 goto out; 3664 } 3665 3666 buf_type = MVPP2_TYPE_XDP_NDO; 3667 } else { 3668 /* XDP_TX */ 3669 struct page *page = virt_to_page(xdpf->data); 3670 3671 dma_addr = page_pool_get_dma_addr(page) + 3672 sizeof(*xdpf) + xdpf->headroom; 3673 dma_sync_single_for_device(port->dev->dev.parent, dma_addr, 3674 xdpf->len, DMA_BIDIRECTIONAL); 3675 3676 buf_type = MVPP2_TYPE_XDP_TX; 3677 } 3678 3679 mvpp2_txdesc_dma_addr_set(port, tx_desc, dma_addr); 3680 3681 mvpp2_txdesc_cmd_set(port, tx_desc, tx_cmd); 3682 mvpp2_txq_inc_put(port, txq_pcpu, xdpf, tx_desc, buf_type); 3683 3684 out: 3685 return ret; 3686 } 3687 3688 static int 3689 mvpp2_xdp_xmit_back(struct mvpp2_port *port, struct xdp_buff *xdp) 3690 { 3691 struct mvpp2_pcpu_stats *stats = this_cpu_ptr(port->stats); 3692 struct xdp_frame *xdpf; 3693 u16 txq_id; 3694 int ret; 3695 3696 xdpf = xdp_convert_buff_to_frame(xdp); 3697 if (unlikely(!xdpf)) 3698 return MVPP2_XDP_DROPPED; 3699 3700 /* The first of the TX queues are used for XPS, 3701 * the second half for XDP_TX 3702 */ 3703 txq_id = mvpp2_cpu_to_thread(port->priv, smp_processor_id()) + (port->ntxqs / 2); 3704 3705 ret = mvpp2_xdp_submit_frame(port, txq_id, xdpf, false); 3706 if (ret == MVPP2_XDP_TX) { 3707 u64_stats_update_begin(&stats->syncp); 3708 stats->tx_bytes += xdpf->len; 3709 stats->tx_packets++; 3710 stats->xdp_tx++; 3711 u64_stats_update_end(&stats->syncp); 3712 3713 mvpp2_xdp_finish_tx(port, txq_id, 1, xdpf->len); 3714 } else { 3715 u64_stats_update_begin(&stats->syncp); 3716 stats->xdp_tx_err++; 3717 u64_stats_update_end(&stats->syncp); 3718 } 3719 3720 return ret; 3721 } 3722 3723 static int 3724 mvpp2_xdp_xmit(struct net_device *dev, int num_frame, 3725 struct xdp_frame **frames, u32 flags) 3726 { 3727 struct mvpp2_port *port = netdev_priv(dev); 3728 int i, nxmit_byte = 0, nxmit = num_frame; 3729 struct mvpp2_pcpu_stats *stats; 3730 u16 txq_id; 3731 u32 ret; 3732 3733 if (unlikely(test_bit(0, &port->state))) 3734 return -ENETDOWN; 3735 3736 if (unlikely(flags & ~XDP_XMIT_FLAGS_MASK)) 3737 return -EINVAL; 3738 3739 /* The first of the TX queues are used for XPS, 3740 * the second half for XDP_TX 3741 */ 3742 txq_id = mvpp2_cpu_to_thread(port->priv, smp_processor_id()) + (port->ntxqs / 2); 3743 3744 for (i = 0; i < num_frame; i++) { 3745 ret = mvpp2_xdp_submit_frame(port, txq_id, frames[i], true); 3746 if (ret == MVPP2_XDP_TX) { 3747 nxmit_byte += frames[i]->len; 3748 } else { 3749 xdp_return_frame_rx_napi(frames[i]); 3750 nxmit--; 3751 } 3752 } 3753 3754 if (likely(nxmit > 0)) 3755 mvpp2_xdp_finish_tx(port, txq_id, nxmit, nxmit_byte); 3756 3757 stats = this_cpu_ptr(port->stats); 3758 u64_stats_update_begin(&stats->syncp); 3759 stats->tx_bytes += nxmit_byte; 3760 stats->tx_packets += nxmit; 3761 stats->xdp_xmit += nxmit; 3762 stats->xdp_xmit_err += num_frame - nxmit; 3763 u64_stats_update_end(&stats->syncp); 3764 3765 return nxmit; 3766 } 3767 3768 static int 3769 mvpp2_run_xdp(struct mvpp2_port *port, struct mvpp2_rx_queue *rxq, 3770 struct bpf_prog *prog, struct xdp_buff *xdp, 3771 struct page_pool *pp, struct mvpp2_pcpu_stats *stats) 3772 { 3773 unsigned int len, sync, err; 3774 struct page *page; 3775 u32 ret, act; 3776 3777 len = xdp->data_end - xdp->data_hard_start - MVPP2_SKB_HEADROOM; 3778 act = bpf_prog_run_xdp(prog, xdp); 3779 3780 /* Due xdp_adjust_tail: DMA sync for_device cover max len CPU touch */ 3781 sync = xdp->data_end - xdp->data_hard_start - MVPP2_SKB_HEADROOM; 3782 sync = max(sync, len); 3783 3784 switch (act) { 3785 case XDP_PASS: 3786 stats->xdp_pass++; 3787 ret = MVPP2_XDP_PASS; 3788 break; 3789 case XDP_REDIRECT: 3790 err = xdp_do_redirect(port->dev, xdp, prog); 3791 if (unlikely(err)) { 3792 ret = MVPP2_XDP_DROPPED; 3793 page = virt_to_head_page(xdp->data); 3794 page_pool_put_page(pp, page, sync, true); 3795 } else { 3796 ret = MVPP2_XDP_REDIR; 3797 stats->xdp_redirect++; 3798 } 3799 break; 3800 case XDP_TX: 3801 ret = mvpp2_xdp_xmit_back(port, xdp); 3802 if (ret != MVPP2_XDP_TX) { 3803 page = virt_to_head_page(xdp->data); 3804 page_pool_put_page(pp, page, sync, true); 3805 } 3806 break; 3807 default: 3808 bpf_warn_invalid_xdp_action(act); 3809 fallthrough; 3810 case XDP_ABORTED: 3811 trace_xdp_exception(port->dev, prog, act); 3812 fallthrough; 3813 case XDP_DROP: 3814 page = virt_to_head_page(xdp->data); 3815 page_pool_put_page(pp, page, sync, true); 3816 ret = MVPP2_XDP_DROPPED; 3817 stats->xdp_drop++; 3818 break; 3819 } 3820 3821 return ret; 3822 } 3823 3824 /* Main rx processing */ 3825 static int mvpp2_rx(struct mvpp2_port *port, struct napi_struct *napi, 3826 int rx_todo, struct mvpp2_rx_queue *rxq) 3827 { 3828 struct net_device *dev = port->dev; 3829 struct mvpp2_pcpu_stats ps = {}; 3830 enum dma_data_direction dma_dir; 3831 struct bpf_prog *xdp_prog; 3832 struct xdp_buff xdp; 3833 int rx_received; 3834 int rx_done = 0; 3835 u32 xdp_ret = 0; 3836 3837 rcu_read_lock(); 3838 3839 xdp_prog = READ_ONCE(port->xdp_prog); 3840 3841 /* Get number of received packets and clamp the to-do */ 3842 rx_received = mvpp2_rxq_received(port, rxq->id); 3843 if (rx_todo > rx_received) 3844 rx_todo = rx_received; 3845 3846 while (rx_done < rx_todo) { 3847 struct mvpp2_rx_desc *rx_desc = mvpp2_rxq_next_desc_get(rxq); 3848 struct mvpp2_bm_pool *bm_pool; 3849 struct page_pool *pp = NULL; 3850 struct sk_buff *skb; 3851 unsigned int frag_size; 3852 dma_addr_t dma_addr; 3853 phys_addr_t phys_addr; 3854 u32 rx_status, timestamp; 3855 int pool, rx_bytes, err, ret; 3856 void *data; 3857 3858 rx_done++; 3859 rx_status = mvpp2_rxdesc_status_get(port, rx_desc); 3860 rx_bytes = mvpp2_rxdesc_size_get(port, rx_desc); 3861 rx_bytes -= MVPP2_MH_SIZE; 3862 dma_addr = mvpp2_rxdesc_dma_addr_get(port, rx_desc); 3863 phys_addr = mvpp2_rxdesc_cookie_get(port, rx_desc); 3864 data = (void *)phys_to_virt(phys_addr); 3865 3866 pool = (rx_status & MVPP2_RXD_BM_POOL_ID_MASK) >> 3867 MVPP2_RXD_BM_POOL_ID_OFFS; 3868 bm_pool = &port->priv->bm_pools[pool]; 3869 3870 /* In case of an error, release the requested buffer pointer 3871 * to the Buffer Manager. This request process is controlled 3872 * by the hardware, and the information about the buffer is 3873 * comprised by the RX descriptor. 3874 */ 3875 if (rx_status & MVPP2_RXD_ERR_SUMMARY) 3876 goto err_drop_frame; 3877 3878 if (port->priv->percpu_pools) { 3879 pp = port->priv->page_pool[pool]; 3880 dma_dir = page_pool_get_dma_dir(pp); 3881 } else { 3882 dma_dir = DMA_FROM_DEVICE; 3883 } 3884 3885 dma_sync_single_for_cpu(dev->dev.parent, dma_addr, 3886 rx_bytes + MVPP2_MH_SIZE, 3887 dma_dir); 3888 3889 /* Prefetch header */ 3890 prefetch(data); 3891 3892 if (bm_pool->frag_size > PAGE_SIZE) 3893 frag_size = 0; 3894 else 3895 frag_size = bm_pool->frag_size; 3896 3897 if (xdp_prog) { 3898 struct xdp_rxq_info *xdp_rxq; 3899 3900 if (bm_pool->pkt_size == MVPP2_BM_SHORT_PKT_SIZE) 3901 xdp_rxq = &rxq->xdp_rxq_short; 3902 else 3903 xdp_rxq = &rxq->xdp_rxq_long; 3904 3905 xdp_init_buff(&xdp, PAGE_SIZE, xdp_rxq); 3906 xdp_prepare_buff(&xdp, data, 3907 MVPP2_MH_SIZE + MVPP2_SKB_HEADROOM, 3908 rx_bytes, false); 3909 3910 ret = mvpp2_run_xdp(port, rxq, xdp_prog, &xdp, pp, &ps); 3911 3912 if (ret) { 3913 xdp_ret |= ret; 3914 err = mvpp2_rx_refill(port, bm_pool, pp, pool); 3915 if (err) { 3916 netdev_err(port->dev, "failed to refill BM pools\n"); 3917 goto err_drop_frame; 3918 } 3919 3920 ps.rx_packets++; 3921 ps.rx_bytes += rx_bytes; 3922 continue; 3923 } 3924 } 3925 3926 skb = build_skb(data, frag_size); 3927 if (!skb) { 3928 netdev_warn(port->dev, "skb build failed\n"); 3929 goto err_drop_frame; 3930 } 3931 3932 /* If we have RX hardware timestamping enabled, grab the 3933 * timestamp from the queue and convert. 3934 */ 3935 if (mvpp22_rx_hwtstamping(port)) { 3936 timestamp = le32_to_cpu(rx_desc->pp22.timestamp); 3937 mvpp22_tai_tstamp(port->priv->tai, timestamp, 3938 skb_hwtstamps(skb)); 3939 } 3940 3941 err = mvpp2_rx_refill(port, bm_pool, pp, pool); 3942 if (err) { 3943 netdev_err(port->dev, "failed to refill BM pools\n"); 3944 dev_kfree_skb_any(skb); 3945 goto err_drop_frame; 3946 } 3947 3948 if (pp) 3949 page_pool_release_page(pp, virt_to_page(data)); 3950 else 3951 dma_unmap_single_attrs(dev->dev.parent, dma_addr, 3952 bm_pool->buf_size, DMA_FROM_DEVICE, 3953 DMA_ATTR_SKIP_CPU_SYNC); 3954 3955 ps.rx_packets++; 3956 ps.rx_bytes += rx_bytes; 3957 3958 skb_reserve(skb, MVPP2_MH_SIZE + MVPP2_SKB_HEADROOM); 3959 skb_put(skb, rx_bytes); 3960 skb->protocol = eth_type_trans(skb, dev); 3961 mvpp2_rx_csum(port, rx_status, skb); 3962 3963 napi_gro_receive(napi, skb); 3964 continue; 3965 3966 err_drop_frame: 3967 dev->stats.rx_errors++; 3968 mvpp2_rx_error(port, rx_desc); 3969 /* Return the buffer to the pool */ 3970 mvpp2_bm_pool_put(port, pool, dma_addr, phys_addr); 3971 } 3972 3973 rcu_read_unlock(); 3974 3975 if (xdp_ret & MVPP2_XDP_REDIR) 3976 xdp_do_flush_map(); 3977 3978 if (ps.rx_packets) { 3979 struct mvpp2_pcpu_stats *stats = this_cpu_ptr(port->stats); 3980 3981 u64_stats_update_begin(&stats->syncp); 3982 stats->rx_packets += ps.rx_packets; 3983 stats->rx_bytes += ps.rx_bytes; 3984 /* xdp */ 3985 stats->xdp_redirect += ps.xdp_redirect; 3986 stats->xdp_pass += ps.xdp_pass; 3987 stats->xdp_drop += ps.xdp_drop; 3988 u64_stats_update_end(&stats->syncp); 3989 } 3990 3991 /* Update Rx queue management counters */ 3992 wmb(); 3993 mvpp2_rxq_status_update(port, rxq->id, rx_done, rx_done); 3994 3995 return rx_todo; 3996 } 3997 3998 static inline void 3999 tx_desc_unmap_put(struct mvpp2_port *port, struct mvpp2_tx_queue *txq, 4000 struct mvpp2_tx_desc *desc) 4001 { 4002 unsigned int thread = mvpp2_cpu_to_thread(port->priv, smp_processor_id()); 4003 struct mvpp2_txq_pcpu *txq_pcpu = per_cpu_ptr(txq->pcpu, thread); 4004 4005 dma_addr_t buf_dma_addr = 4006 mvpp2_txdesc_dma_addr_get(port, desc); 4007 size_t buf_sz = 4008 mvpp2_txdesc_size_get(port, desc); 4009 if (!IS_TSO_HEADER(txq_pcpu, buf_dma_addr)) 4010 dma_unmap_single(port->dev->dev.parent, buf_dma_addr, 4011 buf_sz, DMA_TO_DEVICE); 4012 mvpp2_txq_desc_put(txq); 4013 } 4014 4015 static void mvpp2_txdesc_clear_ptp(struct mvpp2_port *port, 4016 struct mvpp2_tx_desc *desc) 4017 { 4018 /* We only need to clear the low bits */ 4019 if (port->priv->hw_version != MVPP21) 4020 desc->pp22.ptp_descriptor &= 4021 cpu_to_le32(~MVPP22_PTP_DESC_MASK_LOW); 4022 } 4023 4024 static bool mvpp2_tx_hw_tstamp(struct mvpp2_port *port, 4025 struct mvpp2_tx_desc *tx_desc, 4026 struct sk_buff *skb) 4027 { 4028 struct mvpp2_hwtstamp_queue *queue; 4029 unsigned int mtype, type, i; 4030 struct ptp_header *hdr; 4031 u64 ptpdesc; 4032 4033 if (port->priv->hw_version == MVPP21 || 4034 port->tx_hwtstamp_type == HWTSTAMP_TX_OFF) 4035 return false; 4036 4037 type = ptp_classify_raw(skb); 4038 if (!type) 4039 return false; 4040 4041 hdr = ptp_parse_header(skb, type); 4042 if (!hdr) 4043 return false; 4044 4045 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 4046 4047 ptpdesc = MVPP22_PTP_MACTIMESTAMPINGEN | 4048 MVPP22_PTP_ACTION_CAPTURE; 4049 queue = &port->tx_hwtstamp_queue[0]; 4050 4051 switch (type & PTP_CLASS_VMASK) { 4052 case PTP_CLASS_V1: 4053 ptpdesc |= MVPP22_PTP_PACKETFORMAT(MVPP22_PTP_PKT_FMT_PTPV1); 4054 break; 4055 4056 case PTP_CLASS_V2: 4057 ptpdesc |= MVPP22_PTP_PACKETFORMAT(MVPP22_PTP_PKT_FMT_PTPV2); 4058 mtype = hdr->tsmt & 15; 4059 /* Direct PTP Sync messages to queue 1 */ 4060 if (mtype == 0) { 4061 ptpdesc |= MVPP22_PTP_TIMESTAMPQUEUESELECT; 4062 queue = &port->tx_hwtstamp_queue[1]; 4063 } 4064 break; 4065 } 4066 4067 /* Take a reference on the skb and insert into our queue */ 4068 i = queue->next; 4069 queue->next = (i + 1) & 31; 4070 if (queue->skb[i]) 4071 dev_kfree_skb_any(queue->skb[i]); 4072 queue->skb[i] = skb_get(skb); 4073 4074 ptpdesc |= MVPP22_PTP_TIMESTAMPENTRYID(i); 4075 4076 /* 4077 * 3:0 - PTPAction 4078 * 6:4 - PTPPacketFormat 4079 * 7 - PTP_CF_WraparoundCheckEn 4080 * 9:8 - IngressTimestampSeconds[1:0] 4081 * 10 - Reserved 4082 * 11 - MACTimestampingEn 4083 * 17:12 - PTP_TimestampQueueEntryID[5:0] 4084 * 18 - PTPTimestampQueueSelect 4085 * 19 - UDPChecksumUpdateEn 4086 * 27:20 - TimestampOffset 4087 * PTP, NTPTransmit, OWAMP/TWAMP - L3 to PTP header 4088 * NTPTs, Y.1731 - L3 to timestamp entry 4089 * 35:28 - UDP Checksum Offset 4090 * 4091 * stored in tx descriptor bits 75:64 (11:0) and 191:168 (35:12) 4092 */ 4093 tx_desc->pp22.ptp_descriptor &= 4094 cpu_to_le32(~MVPP22_PTP_DESC_MASK_LOW); 4095 tx_desc->pp22.ptp_descriptor |= 4096 cpu_to_le32(ptpdesc & MVPP22_PTP_DESC_MASK_LOW); 4097 tx_desc->pp22.buf_dma_addr_ptp &= cpu_to_le64(~0xffffff0000000000ULL); 4098 tx_desc->pp22.buf_dma_addr_ptp |= cpu_to_le64((ptpdesc >> 12) << 40); 4099 4100 return true; 4101 } 4102 4103 /* Handle tx fragmentation processing */ 4104 static int mvpp2_tx_frag_process(struct mvpp2_port *port, struct sk_buff *skb, 4105 struct mvpp2_tx_queue *aggr_txq, 4106 struct mvpp2_tx_queue *txq) 4107 { 4108 unsigned int thread = mvpp2_cpu_to_thread(port->priv, smp_processor_id()); 4109 struct mvpp2_txq_pcpu *txq_pcpu = per_cpu_ptr(txq->pcpu, thread); 4110 struct mvpp2_tx_desc *tx_desc; 4111 int i; 4112 dma_addr_t buf_dma_addr; 4113 4114 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { 4115 skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 4116 void *addr = skb_frag_address(frag); 4117 4118 tx_desc = mvpp2_txq_next_desc_get(aggr_txq); 4119 mvpp2_txdesc_clear_ptp(port, tx_desc); 4120 mvpp2_txdesc_txq_set(port, tx_desc, txq->id); 4121 mvpp2_txdesc_size_set(port, tx_desc, skb_frag_size(frag)); 4122 4123 buf_dma_addr = dma_map_single(port->dev->dev.parent, addr, 4124 skb_frag_size(frag), 4125 DMA_TO_DEVICE); 4126 if (dma_mapping_error(port->dev->dev.parent, buf_dma_addr)) { 4127 mvpp2_txq_desc_put(txq); 4128 goto cleanup; 4129 } 4130 4131 mvpp2_txdesc_dma_addr_set(port, tx_desc, buf_dma_addr); 4132 4133 if (i == (skb_shinfo(skb)->nr_frags - 1)) { 4134 /* Last descriptor */ 4135 mvpp2_txdesc_cmd_set(port, tx_desc, 4136 MVPP2_TXD_L_DESC); 4137 mvpp2_txq_inc_put(port, txq_pcpu, skb, tx_desc, MVPP2_TYPE_SKB); 4138 } else { 4139 /* Descriptor in the middle: Not First, Not Last */ 4140 mvpp2_txdesc_cmd_set(port, tx_desc, 0); 4141 mvpp2_txq_inc_put(port, txq_pcpu, NULL, tx_desc, MVPP2_TYPE_SKB); 4142 } 4143 } 4144 4145 return 0; 4146 cleanup: 4147 /* Release all descriptors that were used to map fragments of 4148 * this packet, as well as the corresponding DMA mappings 4149 */ 4150 for (i = i - 1; i >= 0; i--) { 4151 tx_desc = txq->descs + i; 4152 tx_desc_unmap_put(port, txq, tx_desc); 4153 } 4154 4155 return -ENOMEM; 4156 } 4157 4158 static inline void mvpp2_tso_put_hdr(struct sk_buff *skb, 4159 struct net_device *dev, 4160 struct mvpp2_tx_queue *txq, 4161 struct mvpp2_tx_queue *aggr_txq, 4162 struct mvpp2_txq_pcpu *txq_pcpu, 4163 int hdr_sz) 4164 { 4165 struct mvpp2_port *port = netdev_priv(dev); 4166 struct mvpp2_tx_desc *tx_desc = mvpp2_txq_next_desc_get(aggr_txq); 4167 dma_addr_t addr; 4168 4169 mvpp2_txdesc_clear_ptp(port, tx_desc); 4170 mvpp2_txdesc_txq_set(port, tx_desc, txq->id); 4171 mvpp2_txdesc_size_set(port, tx_desc, hdr_sz); 4172 4173 addr = txq_pcpu->tso_headers_dma + 4174 txq_pcpu->txq_put_index * TSO_HEADER_SIZE; 4175 mvpp2_txdesc_dma_addr_set(port, tx_desc, addr); 4176 4177 mvpp2_txdesc_cmd_set(port, tx_desc, mvpp2_skb_tx_csum(port, skb) | 4178 MVPP2_TXD_F_DESC | 4179 MVPP2_TXD_PADDING_DISABLE); 4180 mvpp2_txq_inc_put(port, txq_pcpu, NULL, tx_desc, MVPP2_TYPE_SKB); 4181 } 4182 4183 static inline int mvpp2_tso_put_data(struct sk_buff *skb, 4184 struct net_device *dev, struct tso_t *tso, 4185 struct mvpp2_tx_queue *txq, 4186 struct mvpp2_tx_queue *aggr_txq, 4187 struct mvpp2_txq_pcpu *txq_pcpu, 4188 int sz, bool left, bool last) 4189 { 4190 struct mvpp2_port *port = netdev_priv(dev); 4191 struct mvpp2_tx_desc *tx_desc = mvpp2_txq_next_desc_get(aggr_txq); 4192 dma_addr_t buf_dma_addr; 4193 4194 mvpp2_txdesc_clear_ptp(port, tx_desc); 4195 mvpp2_txdesc_txq_set(port, tx_desc, txq->id); 4196 mvpp2_txdesc_size_set(port, tx_desc, sz); 4197 4198 buf_dma_addr = dma_map_single(dev->dev.parent, tso->data, sz, 4199 DMA_TO_DEVICE); 4200 if (unlikely(dma_mapping_error(dev->dev.parent, buf_dma_addr))) { 4201 mvpp2_txq_desc_put(txq); 4202 return -ENOMEM; 4203 } 4204 4205 mvpp2_txdesc_dma_addr_set(port, tx_desc, buf_dma_addr); 4206 4207 if (!left) { 4208 mvpp2_txdesc_cmd_set(port, tx_desc, MVPP2_TXD_L_DESC); 4209 if (last) { 4210 mvpp2_txq_inc_put(port, txq_pcpu, skb, tx_desc, MVPP2_TYPE_SKB); 4211 return 0; 4212 } 4213 } else { 4214 mvpp2_txdesc_cmd_set(port, tx_desc, 0); 4215 } 4216 4217 mvpp2_txq_inc_put(port, txq_pcpu, NULL, tx_desc, MVPP2_TYPE_SKB); 4218 return 0; 4219 } 4220 4221 static int mvpp2_tx_tso(struct sk_buff *skb, struct net_device *dev, 4222 struct mvpp2_tx_queue *txq, 4223 struct mvpp2_tx_queue *aggr_txq, 4224 struct mvpp2_txq_pcpu *txq_pcpu) 4225 { 4226 struct mvpp2_port *port = netdev_priv(dev); 4227 int hdr_sz, i, len, descs = 0; 4228 struct tso_t tso; 4229 4230 /* Check number of available descriptors */ 4231 if (mvpp2_aggr_desc_num_check(port, aggr_txq, tso_count_descs(skb)) || 4232 mvpp2_txq_reserved_desc_num_proc(port, txq, txq_pcpu, 4233 tso_count_descs(skb))) 4234 return 0; 4235 4236 hdr_sz = tso_start(skb, &tso); 4237 4238 len = skb->len - hdr_sz; 4239 while (len > 0) { 4240 int left = min_t(int, skb_shinfo(skb)->gso_size, len); 4241 char *hdr = txq_pcpu->tso_headers + 4242 txq_pcpu->txq_put_index * TSO_HEADER_SIZE; 4243 4244 len -= left; 4245 descs++; 4246 4247 tso_build_hdr(skb, hdr, &tso, left, len == 0); 4248 mvpp2_tso_put_hdr(skb, dev, txq, aggr_txq, txq_pcpu, hdr_sz); 4249 4250 while (left > 0) { 4251 int sz = min_t(int, tso.size, left); 4252 left -= sz; 4253 descs++; 4254 4255 if (mvpp2_tso_put_data(skb, dev, &tso, txq, aggr_txq, 4256 txq_pcpu, sz, left, len == 0)) 4257 goto release; 4258 tso_build_data(skb, &tso, sz); 4259 } 4260 } 4261 4262 return descs; 4263 4264 release: 4265 for (i = descs - 1; i >= 0; i--) { 4266 struct mvpp2_tx_desc *tx_desc = txq->descs + i; 4267 tx_desc_unmap_put(port, txq, tx_desc); 4268 } 4269 return 0; 4270 } 4271 4272 /* Main tx processing */ 4273 static netdev_tx_t mvpp2_tx(struct sk_buff *skb, struct net_device *dev) 4274 { 4275 struct mvpp2_port *port = netdev_priv(dev); 4276 struct mvpp2_tx_queue *txq, *aggr_txq; 4277 struct mvpp2_txq_pcpu *txq_pcpu; 4278 struct mvpp2_tx_desc *tx_desc; 4279 dma_addr_t buf_dma_addr; 4280 unsigned long flags = 0; 4281 unsigned int thread; 4282 int frags = 0; 4283 u16 txq_id; 4284 u32 tx_cmd; 4285 4286 thread = mvpp2_cpu_to_thread(port->priv, smp_processor_id()); 4287 4288 txq_id = skb_get_queue_mapping(skb); 4289 txq = port->txqs[txq_id]; 4290 txq_pcpu = per_cpu_ptr(txq->pcpu, thread); 4291 aggr_txq = &port->priv->aggr_txqs[thread]; 4292 4293 if (test_bit(thread, &port->priv->lock_map)) 4294 spin_lock_irqsave(&port->tx_lock[thread], flags); 4295 4296 if (skb_is_gso(skb)) { 4297 frags = mvpp2_tx_tso(skb, dev, txq, aggr_txq, txq_pcpu); 4298 goto out; 4299 } 4300 frags = skb_shinfo(skb)->nr_frags + 1; 4301 4302 /* Check number of available descriptors */ 4303 if (mvpp2_aggr_desc_num_check(port, aggr_txq, frags) || 4304 mvpp2_txq_reserved_desc_num_proc(port, txq, txq_pcpu, frags)) { 4305 frags = 0; 4306 goto out; 4307 } 4308 4309 /* Get a descriptor for the first part of the packet */ 4310 tx_desc = mvpp2_txq_next_desc_get(aggr_txq); 4311 if (!(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) || 4312 !mvpp2_tx_hw_tstamp(port, tx_desc, skb)) 4313 mvpp2_txdesc_clear_ptp(port, tx_desc); 4314 mvpp2_txdesc_txq_set(port, tx_desc, txq->id); 4315 mvpp2_txdesc_size_set(port, tx_desc, skb_headlen(skb)); 4316 4317 buf_dma_addr = dma_map_single(dev->dev.parent, skb->data, 4318 skb_headlen(skb), DMA_TO_DEVICE); 4319 if (unlikely(dma_mapping_error(dev->dev.parent, buf_dma_addr))) { 4320 mvpp2_txq_desc_put(txq); 4321 frags = 0; 4322 goto out; 4323 } 4324 4325 mvpp2_txdesc_dma_addr_set(port, tx_desc, buf_dma_addr); 4326 4327 tx_cmd = mvpp2_skb_tx_csum(port, skb); 4328 4329 if (frags == 1) { 4330 /* First and Last descriptor */ 4331 tx_cmd |= MVPP2_TXD_F_DESC | MVPP2_TXD_L_DESC; 4332 mvpp2_txdesc_cmd_set(port, tx_desc, tx_cmd); 4333 mvpp2_txq_inc_put(port, txq_pcpu, skb, tx_desc, MVPP2_TYPE_SKB); 4334 } else { 4335 /* First but not Last */ 4336 tx_cmd |= MVPP2_TXD_F_DESC | MVPP2_TXD_PADDING_DISABLE; 4337 mvpp2_txdesc_cmd_set(port, tx_desc, tx_cmd); 4338 mvpp2_txq_inc_put(port, txq_pcpu, NULL, tx_desc, MVPP2_TYPE_SKB); 4339 4340 /* Continue with other skb fragments */ 4341 if (mvpp2_tx_frag_process(port, skb, aggr_txq, txq)) { 4342 tx_desc_unmap_put(port, txq, tx_desc); 4343 frags = 0; 4344 } 4345 } 4346 4347 out: 4348 if (frags > 0) { 4349 struct mvpp2_pcpu_stats *stats = per_cpu_ptr(port->stats, thread); 4350 struct netdev_queue *nq = netdev_get_tx_queue(dev, txq_id); 4351 4352 txq_pcpu->reserved_num -= frags; 4353 txq_pcpu->count += frags; 4354 aggr_txq->count += frags; 4355 4356 /* Enable transmit */ 4357 wmb(); 4358 mvpp2_aggr_txq_pend_desc_add(port, frags); 4359 4360 if (txq_pcpu->count >= txq_pcpu->stop_threshold) 4361 netif_tx_stop_queue(nq); 4362 4363 u64_stats_update_begin(&stats->syncp); 4364 stats->tx_packets++; 4365 stats->tx_bytes += skb->len; 4366 u64_stats_update_end(&stats->syncp); 4367 } else { 4368 dev->stats.tx_dropped++; 4369 dev_kfree_skb_any(skb); 4370 } 4371 4372 /* Finalize TX processing */ 4373 if (!port->has_tx_irqs && txq_pcpu->count >= txq->done_pkts_coal) 4374 mvpp2_txq_done(port, txq, txq_pcpu); 4375 4376 /* Set the timer in case not all frags were processed */ 4377 if (!port->has_tx_irqs && txq_pcpu->count <= frags && 4378 txq_pcpu->count > 0) { 4379 struct mvpp2_port_pcpu *port_pcpu = per_cpu_ptr(port->pcpu, thread); 4380 4381 if (!port_pcpu->timer_scheduled) { 4382 port_pcpu->timer_scheduled = true; 4383 hrtimer_start(&port_pcpu->tx_done_timer, 4384 MVPP2_TXDONE_HRTIMER_PERIOD_NS, 4385 HRTIMER_MODE_REL_PINNED_SOFT); 4386 } 4387 } 4388 4389 if (test_bit(thread, &port->priv->lock_map)) 4390 spin_unlock_irqrestore(&port->tx_lock[thread], flags); 4391 4392 return NETDEV_TX_OK; 4393 } 4394 4395 static inline void mvpp2_cause_error(struct net_device *dev, int cause) 4396 { 4397 if (cause & MVPP2_CAUSE_FCS_ERR_MASK) 4398 netdev_err(dev, "FCS error\n"); 4399 if (cause & MVPP2_CAUSE_RX_FIFO_OVERRUN_MASK) 4400 netdev_err(dev, "rx fifo overrun error\n"); 4401 if (cause & MVPP2_CAUSE_TX_FIFO_UNDERRUN_MASK) 4402 netdev_err(dev, "tx fifo underrun error\n"); 4403 } 4404 4405 static int mvpp2_poll(struct napi_struct *napi, int budget) 4406 { 4407 u32 cause_rx_tx, cause_rx, cause_tx, cause_misc; 4408 int rx_done = 0; 4409 struct mvpp2_port *port = netdev_priv(napi->dev); 4410 struct mvpp2_queue_vector *qv; 4411 unsigned int thread = mvpp2_cpu_to_thread(port->priv, smp_processor_id()); 4412 4413 qv = container_of(napi, struct mvpp2_queue_vector, napi); 4414 4415 /* Rx/Tx cause register 4416 * 4417 * Bits 0-15: each bit indicates received packets on the Rx queue 4418 * (bit 0 is for Rx queue 0). 4419 * 4420 * Bits 16-23: each bit indicates transmitted packets on the Tx queue 4421 * (bit 16 is for Tx queue 0). 4422 * 4423 * Each CPU has its own Rx/Tx cause register 4424 */ 4425 cause_rx_tx = mvpp2_thread_read_relaxed(port->priv, qv->sw_thread_id, 4426 MVPP2_ISR_RX_TX_CAUSE_REG(port->id)); 4427 4428 cause_misc = cause_rx_tx & MVPP2_CAUSE_MISC_SUM_MASK; 4429 if (cause_misc) { 4430 mvpp2_cause_error(port->dev, cause_misc); 4431 4432 /* Clear the cause register */ 4433 mvpp2_write(port->priv, MVPP2_ISR_MISC_CAUSE_REG, 0); 4434 mvpp2_thread_write(port->priv, thread, 4435 MVPP2_ISR_RX_TX_CAUSE_REG(port->id), 4436 cause_rx_tx & ~MVPP2_CAUSE_MISC_SUM_MASK); 4437 } 4438 4439 if (port->has_tx_irqs) { 4440 cause_tx = cause_rx_tx & MVPP2_CAUSE_TXQ_OCCUP_DESC_ALL_MASK; 4441 if (cause_tx) { 4442 cause_tx >>= MVPP2_CAUSE_TXQ_OCCUP_DESC_ALL_OFFSET; 4443 mvpp2_tx_done(port, cause_tx, qv->sw_thread_id); 4444 } 4445 } 4446 4447 /* Process RX packets */ 4448 cause_rx = cause_rx_tx & 4449 MVPP2_CAUSE_RXQ_OCCUP_DESC_ALL_MASK(port->priv->hw_version); 4450 cause_rx <<= qv->first_rxq; 4451 cause_rx |= qv->pending_cause_rx; 4452 while (cause_rx && budget > 0) { 4453 int count; 4454 struct mvpp2_rx_queue *rxq; 4455 4456 rxq = mvpp2_get_rx_queue(port, cause_rx); 4457 if (!rxq) 4458 break; 4459 4460 count = mvpp2_rx(port, napi, budget, rxq); 4461 rx_done += count; 4462 budget -= count; 4463 if (budget > 0) { 4464 /* Clear the bit associated to this Rx queue 4465 * so that next iteration will continue from 4466 * the next Rx queue. 4467 */ 4468 cause_rx &= ~(1 << rxq->logic_rxq); 4469 } 4470 } 4471 4472 if (budget > 0) { 4473 cause_rx = 0; 4474 napi_complete_done(napi, rx_done); 4475 4476 mvpp2_qvec_interrupt_enable(qv); 4477 } 4478 qv->pending_cause_rx = cause_rx; 4479 return rx_done; 4480 } 4481 4482 static void mvpp22_mode_reconfigure(struct mvpp2_port *port) 4483 { 4484 u32 ctrl3; 4485 4486 /* Set the GMAC & XLG MAC in reset */ 4487 mvpp2_mac_reset_assert(port); 4488 4489 /* Set the MPCS and XPCS in reset */ 4490 mvpp22_pcs_reset_assert(port); 4491 4492 /* comphy reconfiguration */ 4493 mvpp22_comphy_init(port); 4494 4495 /* gop reconfiguration */ 4496 mvpp22_gop_init(port); 4497 4498 mvpp22_pcs_reset_deassert(port); 4499 4500 if (mvpp2_port_supports_xlg(port)) { 4501 ctrl3 = readl(port->base + MVPP22_XLG_CTRL3_REG); 4502 ctrl3 &= ~MVPP22_XLG_CTRL3_MACMODESELECT_MASK; 4503 4504 if (mvpp2_is_xlg(port->phy_interface)) 4505 ctrl3 |= MVPP22_XLG_CTRL3_MACMODESELECT_10G; 4506 else 4507 ctrl3 |= MVPP22_XLG_CTRL3_MACMODESELECT_GMAC; 4508 4509 writel(ctrl3, port->base + MVPP22_XLG_CTRL3_REG); 4510 } 4511 4512 if (mvpp2_port_supports_xlg(port) && mvpp2_is_xlg(port->phy_interface)) 4513 mvpp2_xlg_max_rx_size_set(port); 4514 else 4515 mvpp2_gmac_max_rx_size_set(port); 4516 } 4517 4518 /* Set hw internals when starting port */ 4519 static void mvpp2_start_dev(struct mvpp2_port *port) 4520 { 4521 int i; 4522 4523 mvpp2_txp_max_tx_size_set(port); 4524 4525 for (i = 0; i < port->nqvecs; i++) 4526 napi_enable(&port->qvecs[i].napi); 4527 4528 /* Enable interrupts on all threads */ 4529 mvpp2_interrupts_enable(port); 4530 4531 if (port->priv->hw_version != MVPP21) 4532 mvpp22_mode_reconfigure(port); 4533 4534 if (port->phylink) { 4535 phylink_start(port->phylink); 4536 } else { 4537 mvpp2_acpi_start(port); 4538 } 4539 4540 netif_tx_start_all_queues(port->dev); 4541 4542 clear_bit(0, &port->state); 4543 } 4544 4545 /* Set hw internals when stopping port */ 4546 static void mvpp2_stop_dev(struct mvpp2_port *port) 4547 { 4548 int i; 4549 4550 set_bit(0, &port->state); 4551 4552 /* Disable interrupts on all threads */ 4553 mvpp2_interrupts_disable(port); 4554 4555 for (i = 0; i < port->nqvecs; i++) 4556 napi_disable(&port->qvecs[i].napi); 4557 4558 if (port->phylink) 4559 phylink_stop(port->phylink); 4560 phy_power_off(port->comphy); 4561 } 4562 4563 static int mvpp2_check_ringparam_valid(struct net_device *dev, 4564 struct ethtool_ringparam *ring) 4565 { 4566 u16 new_rx_pending = ring->rx_pending; 4567 u16 new_tx_pending = ring->tx_pending; 4568 4569 if (ring->rx_pending == 0 || ring->tx_pending == 0) 4570 return -EINVAL; 4571 4572 if (ring->rx_pending > MVPP2_MAX_RXD_MAX) 4573 new_rx_pending = MVPP2_MAX_RXD_MAX; 4574 else if (ring->rx_pending < MSS_THRESHOLD_START) 4575 new_rx_pending = MSS_THRESHOLD_START; 4576 else if (!IS_ALIGNED(ring->rx_pending, 16)) 4577 new_rx_pending = ALIGN(ring->rx_pending, 16); 4578 4579 if (ring->tx_pending > MVPP2_MAX_TXD_MAX) 4580 new_tx_pending = MVPP2_MAX_TXD_MAX; 4581 else if (!IS_ALIGNED(ring->tx_pending, 32)) 4582 new_tx_pending = ALIGN(ring->tx_pending, 32); 4583 4584 /* The Tx ring size cannot be smaller than the minimum number of 4585 * descriptors needed for TSO. 4586 */ 4587 if (new_tx_pending < MVPP2_MAX_SKB_DESCS) 4588 new_tx_pending = ALIGN(MVPP2_MAX_SKB_DESCS, 32); 4589 4590 if (ring->rx_pending != new_rx_pending) { 4591 netdev_info(dev, "illegal Rx ring size value %d, round to %d\n", 4592 ring->rx_pending, new_rx_pending); 4593 ring->rx_pending = new_rx_pending; 4594 } 4595 4596 if (ring->tx_pending != new_tx_pending) { 4597 netdev_info(dev, "illegal Tx ring size value %d, round to %d\n", 4598 ring->tx_pending, new_tx_pending); 4599 ring->tx_pending = new_tx_pending; 4600 } 4601 4602 return 0; 4603 } 4604 4605 static void mvpp21_get_mac_address(struct mvpp2_port *port, unsigned char *addr) 4606 { 4607 u32 mac_addr_l, mac_addr_m, mac_addr_h; 4608 4609 mac_addr_l = readl(port->base + MVPP2_GMAC_CTRL_1_REG); 4610 mac_addr_m = readl(port->priv->lms_base + MVPP2_SRC_ADDR_MIDDLE); 4611 mac_addr_h = readl(port->priv->lms_base + MVPP2_SRC_ADDR_HIGH); 4612 addr[0] = (mac_addr_h >> 24) & 0xFF; 4613 addr[1] = (mac_addr_h >> 16) & 0xFF; 4614 addr[2] = (mac_addr_h >> 8) & 0xFF; 4615 addr[3] = mac_addr_h & 0xFF; 4616 addr[4] = mac_addr_m & 0xFF; 4617 addr[5] = (mac_addr_l >> MVPP2_GMAC_SA_LOW_OFFS) & 0xFF; 4618 } 4619 4620 static int mvpp2_irqs_init(struct mvpp2_port *port) 4621 { 4622 int err, i; 4623 4624 for (i = 0; i < port->nqvecs; i++) { 4625 struct mvpp2_queue_vector *qv = port->qvecs + i; 4626 4627 if (qv->type == MVPP2_QUEUE_VECTOR_PRIVATE) { 4628 qv->mask = kzalloc(cpumask_size(), GFP_KERNEL); 4629 if (!qv->mask) { 4630 err = -ENOMEM; 4631 goto err; 4632 } 4633 4634 irq_set_status_flags(qv->irq, IRQ_NO_BALANCING); 4635 } 4636 4637 err = request_irq(qv->irq, mvpp2_isr, 0, port->dev->name, qv); 4638 if (err) 4639 goto err; 4640 4641 if (qv->type == MVPP2_QUEUE_VECTOR_PRIVATE) { 4642 unsigned int cpu; 4643 4644 for_each_present_cpu(cpu) { 4645 if (mvpp2_cpu_to_thread(port->priv, cpu) == 4646 qv->sw_thread_id) 4647 cpumask_set_cpu(cpu, qv->mask); 4648 } 4649 4650 irq_set_affinity_hint(qv->irq, qv->mask); 4651 } 4652 } 4653 4654 return 0; 4655 err: 4656 for (i = 0; i < port->nqvecs; i++) { 4657 struct mvpp2_queue_vector *qv = port->qvecs + i; 4658 4659 irq_set_affinity_hint(qv->irq, NULL); 4660 kfree(qv->mask); 4661 qv->mask = NULL; 4662 free_irq(qv->irq, qv); 4663 } 4664 4665 return err; 4666 } 4667 4668 static void mvpp2_irqs_deinit(struct mvpp2_port *port) 4669 { 4670 int i; 4671 4672 for (i = 0; i < port->nqvecs; i++) { 4673 struct mvpp2_queue_vector *qv = port->qvecs + i; 4674 4675 irq_set_affinity_hint(qv->irq, NULL); 4676 kfree(qv->mask); 4677 qv->mask = NULL; 4678 irq_clear_status_flags(qv->irq, IRQ_NO_BALANCING); 4679 free_irq(qv->irq, qv); 4680 } 4681 } 4682 4683 static bool mvpp22_rss_is_supported(void) 4684 { 4685 return queue_mode == MVPP2_QDIST_MULTI_MODE; 4686 } 4687 4688 static int mvpp2_open(struct net_device *dev) 4689 { 4690 struct mvpp2_port *port = netdev_priv(dev); 4691 struct mvpp2 *priv = port->priv; 4692 unsigned char mac_bcast[ETH_ALEN] = { 4693 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }; 4694 bool valid = false; 4695 int err; 4696 4697 err = mvpp2_prs_mac_da_accept(port, mac_bcast, true); 4698 if (err) { 4699 netdev_err(dev, "mvpp2_prs_mac_da_accept BC failed\n"); 4700 return err; 4701 } 4702 err = mvpp2_prs_mac_da_accept(port, dev->dev_addr, true); 4703 if (err) { 4704 netdev_err(dev, "mvpp2_prs_mac_da_accept own addr failed\n"); 4705 return err; 4706 } 4707 err = mvpp2_prs_tag_mode_set(port->priv, port->id, MVPP2_TAG_TYPE_MH); 4708 if (err) { 4709 netdev_err(dev, "mvpp2_prs_tag_mode_set failed\n"); 4710 return err; 4711 } 4712 err = mvpp2_prs_def_flow(port); 4713 if (err) { 4714 netdev_err(dev, "mvpp2_prs_def_flow failed\n"); 4715 return err; 4716 } 4717 4718 /* Allocate the Rx/Tx queues */ 4719 err = mvpp2_setup_rxqs(port); 4720 if (err) { 4721 netdev_err(port->dev, "cannot allocate Rx queues\n"); 4722 return err; 4723 } 4724 4725 err = mvpp2_setup_txqs(port); 4726 if (err) { 4727 netdev_err(port->dev, "cannot allocate Tx queues\n"); 4728 goto err_cleanup_rxqs; 4729 } 4730 4731 err = mvpp2_irqs_init(port); 4732 if (err) { 4733 netdev_err(port->dev, "cannot init IRQs\n"); 4734 goto err_cleanup_txqs; 4735 } 4736 4737 /* Phylink isn't supported yet in ACPI mode */ 4738 if (port->of_node) { 4739 err = phylink_of_phy_connect(port->phylink, port->of_node, 0); 4740 if (err) { 4741 netdev_err(port->dev, "could not attach PHY (%d)\n", 4742 err); 4743 goto err_free_irq; 4744 } 4745 4746 valid = true; 4747 } 4748 4749 if (priv->hw_version != MVPP21 && port->port_irq) { 4750 err = request_irq(port->port_irq, mvpp2_port_isr, 0, 4751 dev->name, port); 4752 if (err) { 4753 netdev_err(port->dev, 4754 "cannot request port link/ptp IRQ %d\n", 4755 port->port_irq); 4756 goto err_free_irq; 4757 } 4758 4759 mvpp22_gop_setup_irq(port); 4760 4761 /* In default link is down */ 4762 netif_carrier_off(port->dev); 4763 4764 valid = true; 4765 } else { 4766 port->port_irq = 0; 4767 } 4768 4769 if (!valid) { 4770 netdev_err(port->dev, 4771 "invalid configuration: no dt or link IRQ"); 4772 err = -ENOENT; 4773 goto err_free_irq; 4774 } 4775 4776 /* Unmask interrupts on all CPUs */ 4777 on_each_cpu(mvpp2_interrupts_unmask, port, 1); 4778 mvpp2_shared_interrupt_mask_unmask(port, false); 4779 4780 mvpp2_start_dev(port); 4781 4782 /* Start hardware statistics gathering */ 4783 queue_delayed_work(priv->stats_queue, &port->stats_work, 4784 MVPP2_MIB_COUNTERS_STATS_DELAY); 4785 4786 return 0; 4787 4788 err_free_irq: 4789 mvpp2_irqs_deinit(port); 4790 err_cleanup_txqs: 4791 mvpp2_cleanup_txqs(port); 4792 err_cleanup_rxqs: 4793 mvpp2_cleanup_rxqs(port); 4794 return err; 4795 } 4796 4797 static int mvpp2_stop(struct net_device *dev) 4798 { 4799 struct mvpp2_port *port = netdev_priv(dev); 4800 struct mvpp2_port_pcpu *port_pcpu; 4801 unsigned int thread; 4802 4803 mvpp2_stop_dev(port); 4804 4805 /* Mask interrupts on all threads */ 4806 on_each_cpu(mvpp2_interrupts_mask, port, 1); 4807 mvpp2_shared_interrupt_mask_unmask(port, true); 4808 4809 if (port->phylink) 4810 phylink_disconnect_phy(port->phylink); 4811 if (port->port_irq) 4812 free_irq(port->port_irq, port); 4813 4814 mvpp2_irqs_deinit(port); 4815 if (!port->has_tx_irqs) { 4816 for (thread = 0; thread < port->priv->nthreads; thread++) { 4817 port_pcpu = per_cpu_ptr(port->pcpu, thread); 4818 4819 hrtimer_cancel(&port_pcpu->tx_done_timer); 4820 port_pcpu->timer_scheduled = false; 4821 } 4822 } 4823 mvpp2_cleanup_rxqs(port); 4824 mvpp2_cleanup_txqs(port); 4825 4826 cancel_delayed_work_sync(&port->stats_work); 4827 4828 mvpp2_mac_reset_assert(port); 4829 mvpp22_pcs_reset_assert(port); 4830 4831 return 0; 4832 } 4833 4834 static int mvpp2_prs_mac_da_accept_list(struct mvpp2_port *port, 4835 struct netdev_hw_addr_list *list) 4836 { 4837 struct netdev_hw_addr *ha; 4838 int ret; 4839 4840 netdev_hw_addr_list_for_each(ha, list) { 4841 ret = mvpp2_prs_mac_da_accept(port, ha->addr, true); 4842 if (ret) 4843 return ret; 4844 } 4845 4846 return 0; 4847 } 4848 4849 static void mvpp2_set_rx_promisc(struct mvpp2_port *port, bool enable) 4850 { 4851 if (!enable && (port->dev->features & NETIF_F_HW_VLAN_CTAG_FILTER)) 4852 mvpp2_prs_vid_enable_filtering(port); 4853 else 4854 mvpp2_prs_vid_disable_filtering(port); 4855 4856 mvpp2_prs_mac_promisc_set(port->priv, port->id, 4857 MVPP2_PRS_L2_UNI_CAST, enable); 4858 4859 mvpp2_prs_mac_promisc_set(port->priv, port->id, 4860 MVPP2_PRS_L2_MULTI_CAST, enable); 4861 } 4862 4863 static void mvpp2_set_rx_mode(struct net_device *dev) 4864 { 4865 struct mvpp2_port *port = netdev_priv(dev); 4866 4867 /* Clear the whole UC and MC list */ 4868 mvpp2_prs_mac_del_all(port); 4869 4870 if (dev->flags & IFF_PROMISC) { 4871 mvpp2_set_rx_promisc(port, true); 4872 return; 4873 } 4874 4875 mvpp2_set_rx_promisc(port, false); 4876 4877 if (netdev_uc_count(dev) > MVPP2_PRS_MAC_UC_FILT_MAX || 4878 mvpp2_prs_mac_da_accept_list(port, &dev->uc)) 4879 mvpp2_prs_mac_promisc_set(port->priv, port->id, 4880 MVPP2_PRS_L2_UNI_CAST, true); 4881 4882 if (dev->flags & IFF_ALLMULTI) { 4883 mvpp2_prs_mac_promisc_set(port->priv, port->id, 4884 MVPP2_PRS_L2_MULTI_CAST, true); 4885 return; 4886 } 4887 4888 if (netdev_mc_count(dev) > MVPP2_PRS_MAC_MC_FILT_MAX || 4889 mvpp2_prs_mac_da_accept_list(port, &dev->mc)) 4890 mvpp2_prs_mac_promisc_set(port->priv, port->id, 4891 MVPP2_PRS_L2_MULTI_CAST, true); 4892 } 4893 4894 static int mvpp2_set_mac_address(struct net_device *dev, void *p) 4895 { 4896 const struct sockaddr *addr = p; 4897 int err; 4898 4899 if (!is_valid_ether_addr(addr->sa_data)) 4900 return -EADDRNOTAVAIL; 4901 4902 err = mvpp2_prs_update_mac_da(dev, addr->sa_data); 4903 if (err) { 4904 /* Reconfigure parser accept the original MAC address */ 4905 mvpp2_prs_update_mac_da(dev, dev->dev_addr); 4906 netdev_err(dev, "failed to change MAC address\n"); 4907 } 4908 return err; 4909 } 4910 4911 /* Shut down all the ports, reconfigure the pools as percpu or shared, 4912 * then bring up again all ports. 4913 */ 4914 static int mvpp2_bm_switch_buffers(struct mvpp2 *priv, bool percpu) 4915 { 4916 int numbufs = MVPP2_BM_POOLS_NUM, i; 4917 struct mvpp2_port *port = NULL; 4918 bool status[MVPP2_MAX_PORTS]; 4919 4920 for (i = 0; i < priv->port_count; i++) { 4921 port = priv->port_list[i]; 4922 status[i] = netif_running(port->dev); 4923 if (status[i]) 4924 mvpp2_stop(port->dev); 4925 } 4926 4927 /* nrxqs is the same for all ports */ 4928 if (priv->percpu_pools) 4929 numbufs = port->nrxqs * 2; 4930 4931 for (i = 0; i < numbufs; i++) 4932 mvpp2_bm_pool_destroy(port->dev->dev.parent, priv, &priv->bm_pools[i]); 4933 4934 devm_kfree(port->dev->dev.parent, priv->bm_pools); 4935 priv->percpu_pools = percpu; 4936 mvpp2_bm_init(port->dev->dev.parent, priv); 4937 4938 for (i = 0; i < priv->port_count; i++) { 4939 port = priv->port_list[i]; 4940 mvpp2_swf_bm_pool_init(port); 4941 if (status[i]) 4942 mvpp2_open(port->dev); 4943 } 4944 4945 return 0; 4946 } 4947 4948 static int mvpp2_change_mtu(struct net_device *dev, int mtu) 4949 { 4950 struct mvpp2_port *port = netdev_priv(dev); 4951 bool running = netif_running(dev); 4952 struct mvpp2 *priv = port->priv; 4953 int err; 4954 4955 if (!IS_ALIGNED(MVPP2_RX_PKT_SIZE(mtu), 8)) { 4956 netdev_info(dev, "illegal MTU value %d, round to %d\n", mtu, 4957 ALIGN(MVPP2_RX_PKT_SIZE(mtu), 8)); 4958 mtu = ALIGN(MVPP2_RX_PKT_SIZE(mtu), 8); 4959 } 4960 4961 if (MVPP2_RX_PKT_SIZE(mtu) > MVPP2_BM_LONG_PKT_SIZE) { 4962 if (port->xdp_prog) { 4963 netdev_err(dev, "Jumbo frames are not supported with XDP\n"); 4964 return -EINVAL; 4965 } 4966 if (priv->percpu_pools) { 4967 netdev_warn(dev, "mtu %d too high, switching to shared buffers", mtu); 4968 mvpp2_bm_switch_buffers(priv, false); 4969 } 4970 } else { 4971 bool jumbo = false; 4972 int i; 4973 4974 for (i = 0; i < priv->port_count; i++) 4975 if (priv->port_list[i] != port && 4976 MVPP2_RX_PKT_SIZE(priv->port_list[i]->dev->mtu) > 4977 MVPP2_BM_LONG_PKT_SIZE) { 4978 jumbo = true; 4979 break; 4980 } 4981 4982 /* No port is using jumbo frames */ 4983 if (!jumbo) { 4984 dev_info(port->dev->dev.parent, 4985 "all ports have a low MTU, switching to per-cpu buffers"); 4986 mvpp2_bm_switch_buffers(priv, true); 4987 } 4988 } 4989 4990 if (running) 4991 mvpp2_stop_dev(port); 4992 4993 err = mvpp2_bm_update_mtu(dev, mtu); 4994 if (err) { 4995 netdev_err(dev, "failed to change MTU\n"); 4996 /* Reconfigure BM to the original MTU */ 4997 mvpp2_bm_update_mtu(dev, dev->mtu); 4998 } else { 4999 port->pkt_size = MVPP2_RX_PKT_SIZE(mtu); 5000 } 5001 5002 if (running) { 5003 mvpp2_start_dev(port); 5004 mvpp2_egress_enable(port); 5005 mvpp2_ingress_enable(port); 5006 } 5007 5008 return err; 5009 } 5010 5011 static int mvpp2_check_pagepool_dma(struct mvpp2_port *port) 5012 { 5013 enum dma_data_direction dma_dir = DMA_FROM_DEVICE; 5014 struct mvpp2 *priv = port->priv; 5015 int err = -1, i; 5016 5017 if (!priv->percpu_pools) 5018 return err; 5019 5020 if (!priv->page_pool[0]) 5021 return -ENOMEM; 5022 5023 for (i = 0; i < priv->port_count; i++) { 5024 port = priv->port_list[i]; 5025 if (port->xdp_prog) { 5026 dma_dir = DMA_BIDIRECTIONAL; 5027 break; 5028 } 5029 } 5030 5031 /* All pools are equal in terms of DMA direction */ 5032 if (priv->page_pool[0]->p.dma_dir != dma_dir) 5033 err = mvpp2_bm_switch_buffers(priv, true); 5034 5035 return err; 5036 } 5037 5038 static void 5039 mvpp2_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats) 5040 { 5041 struct mvpp2_port *port = netdev_priv(dev); 5042 unsigned int start; 5043 unsigned int cpu; 5044 5045 for_each_possible_cpu(cpu) { 5046 struct mvpp2_pcpu_stats *cpu_stats; 5047 u64 rx_packets; 5048 u64 rx_bytes; 5049 u64 tx_packets; 5050 u64 tx_bytes; 5051 5052 cpu_stats = per_cpu_ptr(port->stats, cpu); 5053 do { 5054 start = u64_stats_fetch_begin_irq(&cpu_stats->syncp); 5055 rx_packets = cpu_stats->rx_packets; 5056 rx_bytes = cpu_stats->rx_bytes; 5057 tx_packets = cpu_stats->tx_packets; 5058 tx_bytes = cpu_stats->tx_bytes; 5059 } while (u64_stats_fetch_retry_irq(&cpu_stats->syncp, start)); 5060 5061 stats->rx_packets += rx_packets; 5062 stats->rx_bytes += rx_bytes; 5063 stats->tx_packets += tx_packets; 5064 stats->tx_bytes += tx_bytes; 5065 } 5066 5067 stats->rx_errors = dev->stats.rx_errors; 5068 stats->rx_dropped = dev->stats.rx_dropped; 5069 stats->tx_dropped = dev->stats.tx_dropped; 5070 } 5071 5072 static int mvpp2_set_ts_config(struct mvpp2_port *port, struct ifreq *ifr) 5073 { 5074 struct hwtstamp_config config; 5075 void __iomem *ptp; 5076 u32 gcr, int_mask; 5077 5078 if (copy_from_user(&config, ifr->ifr_data, sizeof(config))) 5079 return -EFAULT; 5080 5081 if (config.flags) 5082 return -EINVAL; 5083 5084 if (config.tx_type != HWTSTAMP_TX_OFF && 5085 config.tx_type != HWTSTAMP_TX_ON) 5086 return -ERANGE; 5087 5088 ptp = port->priv->iface_base + MVPP22_PTP_BASE(port->gop_id); 5089 5090 int_mask = gcr = 0; 5091 if (config.tx_type != HWTSTAMP_TX_OFF) { 5092 gcr |= MVPP22_PTP_GCR_TSU_ENABLE | MVPP22_PTP_GCR_TX_RESET; 5093 int_mask |= MVPP22_PTP_INT_MASK_QUEUE1 | 5094 MVPP22_PTP_INT_MASK_QUEUE0; 5095 } 5096 5097 /* It seems we must also release the TX reset when enabling the TSU */ 5098 if (config.rx_filter != HWTSTAMP_FILTER_NONE) 5099 gcr |= MVPP22_PTP_GCR_TSU_ENABLE | MVPP22_PTP_GCR_RX_RESET | 5100 MVPP22_PTP_GCR_TX_RESET; 5101 5102 if (gcr & MVPP22_PTP_GCR_TSU_ENABLE) 5103 mvpp22_tai_start(port->priv->tai); 5104 5105 if (config.rx_filter != HWTSTAMP_FILTER_NONE) { 5106 config.rx_filter = HWTSTAMP_FILTER_ALL; 5107 mvpp2_modify(ptp + MVPP22_PTP_GCR, 5108 MVPP22_PTP_GCR_RX_RESET | 5109 MVPP22_PTP_GCR_TX_RESET | 5110 MVPP22_PTP_GCR_TSU_ENABLE, gcr); 5111 port->rx_hwtstamp = true; 5112 } else { 5113 port->rx_hwtstamp = false; 5114 mvpp2_modify(ptp + MVPP22_PTP_GCR, 5115 MVPP22_PTP_GCR_RX_RESET | 5116 MVPP22_PTP_GCR_TX_RESET | 5117 MVPP22_PTP_GCR_TSU_ENABLE, gcr); 5118 } 5119 5120 mvpp2_modify(ptp + MVPP22_PTP_INT_MASK, 5121 MVPP22_PTP_INT_MASK_QUEUE1 | 5122 MVPP22_PTP_INT_MASK_QUEUE0, int_mask); 5123 5124 if (!(gcr & MVPP22_PTP_GCR_TSU_ENABLE)) 5125 mvpp22_tai_stop(port->priv->tai); 5126 5127 port->tx_hwtstamp_type = config.tx_type; 5128 5129 if (copy_to_user(ifr->ifr_data, &config, sizeof(config))) 5130 return -EFAULT; 5131 5132 return 0; 5133 } 5134 5135 static int mvpp2_get_ts_config(struct mvpp2_port *port, struct ifreq *ifr) 5136 { 5137 struct hwtstamp_config config; 5138 5139 memset(&config, 0, sizeof(config)); 5140 5141 config.tx_type = port->tx_hwtstamp_type; 5142 config.rx_filter = port->rx_hwtstamp ? 5143 HWTSTAMP_FILTER_ALL : HWTSTAMP_FILTER_NONE; 5144 5145 if (copy_to_user(ifr->ifr_data, &config, sizeof(config))) 5146 return -EFAULT; 5147 5148 return 0; 5149 } 5150 5151 static int mvpp2_ethtool_get_ts_info(struct net_device *dev, 5152 struct ethtool_ts_info *info) 5153 { 5154 struct mvpp2_port *port = netdev_priv(dev); 5155 5156 if (!port->hwtstamp) 5157 return -EOPNOTSUPP; 5158 5159 info->phc_index = mvpp22_tai_ptp_clock_index(port->priv->tai); 5160 info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE | 5161 SOF_TIMESTAMPING_RX_SOFTWARE | 5162 SOF_TIMESTAMPING_SOFTWARE | 5163 SOF_TIMESTAMPING_TX_HARDWARE | 5164 SOF_TIMESTAMPING_RX_HARDWARE | 5165 SOF_TIMESTAMPING_RAW_HARDWARE; 5166 info->tx_types = BIT(HWTSTAMP_TX_OFF) | 5167 BIT(HWTSTAMP_TX_ON); 5168 info->rx_filters = BIT(HWTSTAMP_FILTER_NONE) | 5169 BIT(HWTSTAMP_FILTER_ALL); 5170 5171 return 0; 5172 } 5173 5174 static int mvpp2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) 5175 { 5176 struct mvpp2_port *port = netdev_priv(dev); 5177 5178 switch (cmd) { 5179 case SIOCSHWTSTAMP: 5180 if (port->hwtstamp) 5181 return mvpp2_set_ts_config(port, ifr); 5182 break; 5183 5184 case SIOCGHWTSTAMP: 5185 if (port->hwtstamp) 5186 return mvpp2_get_ts_config(port, ifr); 5187 break; 5188 } 5189 5190 if (!port->phylink) 5191 return -ENOTSUPP; 5192 5193 return phylink_mii_ioctl(port->phylink, ifr, cmd); 5194 } 5195 5196 static int mvpp2_vlan_rx_add_vid(struct net_device *dev, __be16 proto, u16 vid) 5197 { 5198 struct mvpp2_port *port = netdev_priv(dev); 5199 int ret; 5200 5201 ret = mvpp2_prs_vid_entry_add(port, vid); 5202 if (ret) 5203 netdev_err(dev, "rx-vlan-filter offloading cannot accept more than %d VIDs per port\n", 5204 MVPP2_PRS_VLAN_FILT_MAX - 1); 5205 return ret; 5206 } 5207 5208 static int mvpp2_vlan_rx_kill_vid(struct net_device *dev, __be16 proto, u16 vid) 5209 { 5210 struct mvpp2_port *port = netdev_priv(dev); 5211 5212 mvpp2_prs_vid_entry_remove(port, vid); 5213 return 0; 5214 } 5215 5216 static int mvpp2_set_features(struct net_device *dev, 5217 netdev_features_t features) 5218 { 5219 netdev_features_t changed = dev->features ^ features; 5220 struct mvpp2_port *port = netdev_priv(dev); 5221 5222 if (changed & NETIF_F_HW_VLAN_CTAG_FILTER) { 5223 if (features & NETIF_F_HW_VLAN_CTAG_FILTER) { 5224 mvpp2_prs_vid_enable_filtering(port); 5225 } else { 5226 /* Invalidate all registered VID filters for this 5227 * port 5228 */ 5229 mvpp2_prs_vid_remove_all(port); 5230 5231 mvpp2_prs_vid_disable_filtering(port); 5232 } 5233 } 5234 5235 if (changed & NETIF_F_RXHASH) { 5236 if (features & NETIF_F_RXHASH) 5237 mvpp22_port_rss_enable(port); 5238 else 5239 mvpp22_port_rss_disable(port); 5240 } 5241 5242 return 0; 5243 } 5244 5245 static int mvpp2_xdp_setup(struct mvpp2_port *port, struct netdev_bpf *bpf) 5246 { 5247 struct bpf_prog *prog = bpf->prog, *old_prog; 5248 bool running = netif_running(port->dev); 5249 bool reset = !prog != !port->xdp_prog; 5250 5251 if (port->dev->mtu > ETH_DATA_LEN) { 5252 NL_SET_ERR_MSG_MOD(bpf->extack, "XDP is not supported with jumbo frames enabled"); 5253 return -EOPNOTSUPP; 5254 } 5255 5256 if (!port->priv->percpu_pools) { 5257 NL_SET_ERR_MSG_MOD(bpf->extack, "Per CPU Pools required for XDP"); 5258 return -EOPNOTSUPP; 5259 } 5260 5261 if (port->ntxqs < num_possible_cpus() * 2) { 5262 NL_SET_ERR_MSG_MOD(bpf->extack, "XDP_TX needs two TX queues per CPU"); 5263 return -EOPNOTSUPP; 5264 } 5265 5266 /* device is up and bpf is added/removed, must setup the RX queues */ 5267 if (running && reset) 5268 mvpp2_stop(port->dev); 5269 5270 old_prog = xchg(&port->xdp_prog, prog); 5271 if (old_prog) 5272 bpf_prog_put(old_prog); 5273 5274 /* bpf is just replaced, RXQ and MTU are already setup */ 5275 if (!reset) 5276 return 0; 5277 5278 /* device was up, restore the link */ 5279 if (running) 5280 mvpp2_open(port->dev); 5281 5282 /* Check Page Pool DMA Direction */ 5283 mvpp2_check_pagepool_dma(port); 5284 5285 return 0; 5286 } 5287 5288 static int mvpp2_xdp(struct net_device *dev, struct netdev_bpf *xdp) 5289 { 5290 struct mvpp2_port *port = netdev_priv(dev); 5291 5292 switch (xdp->command) { 5293 case XDP_SETUP_PROG: 5294 return mvpp2_xdp_setup(port, xdp); 5295 default: 5296 return -EINVAL; 5297 } 5298 } 5299 5300 /* Ethtool methods */ 5301 5302 static int mvpp2_ethtool_nway_reset(struct net_device *dev) 5303 { 5304 struct mvpp2_port *port = netdev_priv(dev); 5305 5306 if (!port->phylink) 5307 return -ENOTSUPP; 5308 5309 return phylink_ethtool_nway_reset(port->phylink); 5310 } 5311 5312 /* Set interrupt coalescing for ethtools */ 5313 static int mvpp2_ethtool_set_coalesce(struct net_device *dev, 5314 struct ethtool_coalesce *c) 5315 { 5316 struct mvpp2_port *port = netdev_priv(dev); 5317 int queue; 5318 5319 for (queue = 0; queue < port->nrxqs; queue++) { 5320 struct mvpp2_rx_queue *rxq = port->rxqs[queue]; 5321 5322 rxq->time_coal = c->rx_coalesce_usecs; 5323 rxq->pkts_coal = c->rx_max_coalesced_frames; 5324 mvpp2_rx_pkts_coal_set(port, rxq); 5325 mvpp2_rx_time_coal_set(port, rxq); 5326 } 5327 5328 if (port->has_tx_irqs) { 5329 port->tx_time_coal = c->tx_coalesce_usecs; 5330 mvpp2_tx_time_coal_set(port); 5331 } 5332 5333 for (queue = 0; queue < port->ntxqs; queue++) { 5334 struct mvpp2_tx_queue *txq = port->txqs[queue]; 5335 5336 txq->done_pkts_coal = c->tx_max_coalesced_frames; 5337 5338 if (port->has_tx_irqs) 5339 mvpp2_tx_pkts_coal_set(port, txq); 5340 } 5341 5342 return 0; 5343 } 5344 5345 /* get coalescing for ethtools */ 5346 static int mvpp2_ethtool_get_coalesce(struct net_device *dev, 5347 struct ethtool_coalesce *c) 5348 { 5349 struct mvpp2_port *port = netdev_priv(dev); 5350 5351 c->rx_coalesce_usecs = port->rxqs[0]->time_coal; 5352 c->rx_max_coalesced_frames = port->rxqs[0]->pkts_coal; 5353 c->tx_max_coalesced_frames = port->txqs[0]->done_pkts_coal; 5354 c->tx_coalesce_usecs = port->tx_time_coal; 5355 return 0; 5356 } 5357 5358 static void mvpp2_ethtool_get_drvinfo(struct net_device *dev, 5359 struct ethtool_drvinfo *drvinfo) 5360 { 5361 strlcpy(drvinfo->driver, MVPP2_DRIVER_NAME, 5362 sizeof(drvinfo->driver)); 5363 strlcpy(drvinfo->version, MVPP2_DRIVER_VERSION, 5364 sizeof(drvinfo->version)); 5365 strlcpy(drvinfo->bus_info, dev_name(&dev->dev), 5366 sizeof(drvinfo->bus_info)); 5367 } 5368 5369 static void mvpp2_ethtool_get_ringparam(struct net_device *dev, 5370 struct ethtool_ringparam *ring) 5371 { 5372 struct mvpp2_port *port = netdev_priv(dev); 5373 5374 ring->rx_max_pending = MVPP2_MAX_RXD_MAX; 5375 ring->tx_max_pending = MVPP2_MAX_TXD_MAX; 5376 ring->rx_pending = port->rx_ring_size; 5377 ring->tx_pending = port->tx_ring_size; 5378 } 5379 5380 static int mvpp2_ethtool_set_ringparam(struct net_device *dev, 5381 struct ethtool_ringparam *ring) 5382 { 5383 struct mvpp2_port *port = netdev_priv(dev); 5384 u16 prev_rx_ring_size = port->rx_ring_size; 5385 u16 prev_tx_ring_size = port->tx_ring_size; 5386 int err; 5387 5388 err = mvpp2_check_ringparam_valid(dev, ring); 5389 if (err) 5390 return err; 5391 5392 if (!netif_running(dev)) { 5393 port->rx_ring_size = ring->rx_pending; 5394 port->tx_ring_size = ring->tx_pending; 5395 return 0; 5396 } 5397 5398 /* The interface is running, so we have to force a 5399 * reallocation of the queues 5400 */ 5401 mvpp2_stop_dev(port); 5402 mvpp2_cleanup_rxqs(port); 5403 mvpp2_cleanup_txqs(port); 5404 5405 port->rx_ring_size = ring->rx_pending; 5406 port->tx_ring_size = ring->tx_pending; 5407 5408 err = mvpp2_setup_rxqs(port); 5409 if (err) { 5410 /* Reallocate Rx queues with the original ring size */ 5411 port->rx_ring_size = prev_rx_ring_size; 5412 ring->rx_pending = prev_rx_ring_size; 5413 err = mvpp2_setup_rxqs(port); 5414 if (err) 5415 goto err_out; 5416 } 5417 err = mvpp2_setup_txqs(port); 5418 if (err) { 5419 /* Reallocate Tx queues with the original ring size */ 5420 port->tx_ring_size = prev_tx_ring_size; 5421 ring->tx_pending = prev_tx_ring_size; 5422 err = mvpp2_setup_txqs(port); 5423 if (err) 5424 goto err_clean_rxqs; 5425 } 5426 5427 mvpp2_start_dev(port); 5428 mvpp2_egress_enable(port); 5429 mvpp2_ingress_enable(port); 5430 5431 return 0; 5432 5433 err_clean_rxqs: 5434 mvpp2_cleanup_rxqs(port); 5435 err_out: 5436 netdev_err(dev, "failed to change ring parameters"); 5437 return err; 5438 } 5439 5440 static void mvpp2_ethtool_get_pause_param(struct net_device *dev, 5441 struct ethtool_pauseparam *pause) 5442 { 5443 struct mvpp2_port *port = netdev_priv(dev); 5444 5445 if (!port->phylink) 5446 return; 5447 5448 phylink_ethtool_get_pauseparam(port->phylink, pause); 5449 } 5450 5451 static int mvpp2_ethtool_set_pause_param(struct net_device *dev, 5452 struct ethtool_pauseparam *pause) 5453 { 5454 struct mvpp2_port *port = netdev_priv(dev); 5455 5456 if (!port->phylink) 5457 return -ENOTSUPP; 5458 5459 return phylink_ethtool_set_pauseparam(port->phylink, pause); 5460 } 5461 5462 static int mvpp2_ethtool_get_link_ksettings(struct net_device *dev, 5463 struct ethtool_link_ksettings *cmd) 5464 { 5465 struct mvpp2_port *port = netdev_priv(dev); 5466 5467 if (!port->phylink) 5468 return -ENOTSUPP; 5469 5470 return phylink_ethtool_ksettings_get(port->phylink, cmd); 5471 } 5472 5473 static int mvpp2_ethtool_set_link_ksettings(struct net_device *dev, 5474 const struct ethtool_link_ksettings *cmd) 5475 { 5476 struct mvpp2_port *port = netdev_priv(dev); 5477 5478 if (!port->phylink) 5479 return -ENOTSUPP; 5480 5481 return phylink_ethtool_ksettings_set(port->phylink, cmd); 5482 } 5483 5484 static int mvpp2_ethtool_get_rxnfc(struct net_device *dev, 5485 struct ethtool_rxnfc *info, u32 *rules) 5486 { 5487 struct mvpp2_port *port = netdev_priv(dev); 5488 int ret = 0, i, loc = 0; 5489 5490 if (!mvpp22_rss_is_supported()) 5491 return -EOPNOTSUPP; 5492 5493 switch (info->cmd) { 5494 case ETHTOOL_GRXFH: 5495 ret = mvpp2_ethtool_rxfh_get(port, info); 5496 break; 5497 case ETHTOOL_GRXRINGS: 5498 info->data = port->nrxqs; 5499 break; 5500 case ETHTOOL_GRXCLSRLCNT: 5501 info->rule_cnt = port->n_rfs_rules; 5502 break; 5503 case ETHTOOL_GRXCLSRULE: 5504 ret = mvpp2_ethtool_cls_rule_get(port, info); 5505 break; 5506 case ETHTOOL_GRXCLSRLALL: 5507 for (i = 0; i < MVPP2_N_RFS_ENTRIES_PER_FLOW; i++) { 5508 if (port->rfs_rules[i]) 5509 rules[loc++] = i; 5510 } 5511 break; 5512 default: 5513 return -ENOTSUPP; 5514 } 5515 5516 return ret; 5517 } 5518 5519 static int mvpp2_ethtool_set_rxnfc(struct net_device *dev, 5520 struct ethtool_rxnfc *info) 5521 { 5522 struct mvpp2_port *port = netdev_priv(dev); 5523 int ret = 0; 5524 5525 if (!mvpp22_rss_is_supported()) 5526 return -EOPNOTSUPP; 5527 5528 switch (info->cmd) { 5529 case ETHTOOL_SRXFH: 5530 ret = mvpp2_ethtool_rxfh_set(port, info); 5531 break; 5532 case ETHTOOL_SRXCLSRLINS: 5533 ret = mvpp2_ethtool_cls_rule_ins(port, info); 5534 break; 5535 case ETHTOOL_SRXCLSRLDEL: 5536 ret = mvpp2_ethtool_cls_rule_del(port, info); 5537 break; 5538 default: 5539 return -EOPNOTSUPP; 5540 } 5541 return ret; 5542 } 5543 5544 static u32 mvpp2_ethtool_get_rxfh_indir_size(struct net_device *dev) 5545 { 5546 return mvpp22_rss_is_supported() ? MVPP22_RSS_TABLE_ENTRIES : 0; 5547 } 5548 5549 static int mvpp2_ethtool_get_rxfh(struct net_device *dev, u32 *indir, u8 *key, 5550 u8 *hfunc) 5551 { 5552 struct mvpp2_port *port = netdev_priv(dev); 5553 int ret = 0; 5554 5555 if (!mvpp22_rss_is_supported()) 5556 return -EOPNOTSUPP; 5557 5558 if (indir) 5559 ret = mvpp22_port_rss_ctx_indir_get(port, 0, indir); 5560 5561 if (hfunc) 5562 *hfunc = ETH_RSS_HASH_CRC32; 5563 5564 return ret; 5565 } 5566 5567 static int mvpp2_ethtool_set_rxfh(struct net_device *dev, const u32 *indir, 5568 const u8 *key, const u8 hfunc) 5569 { 5570 struct mvpp2_port *port = netdev_priv(dev); 5571 int ret = 0; 5572 5573 if (!mvpp22_rss_is_supported()) 5574 return -EOPNOTSUPP; 5575 5576 if (hfunc != ETH_RSS_HASH_NO_CHANGE && hfunc != ETH_RSS_HASH_CRC32) 5577 return -EOPNOTSUPP; 5578 5579 if (key) 5580 return -EOPNOTSUPP; 5581 5582 if (indir) 5583 ret = mvpp22_port_rss_ctx_indir_set(port, 0, indir); 5584 5585 return ret; 5586 } 5587 5588 static int mvpp2_ethtool_get_rxfh_context(struct net_device *dev, u32 *indir, 5589 u8 *key, u8 *hfunc, u32 rss_context) 5590 { 5591 struct mvpp2_port *port = netdev_priv(dev); 5592 int ret = 0; 5593 5594 if (!mvpp22_rss_is_supported()) 5595 return -EOPNOTSUPP; 5596 if (rss_context >= MVPP22_N_RSS_TABLES) 5597 return -EINVAL; 5598 5599 if (hfunc) 5600 *hfunc = ETH_RSS_HASH_CRC32; 5601 5602 if (indir) 5603 ret = mvpp22_port_rss_ctx_indir_get(port, rss_context, indir); 5604 5605 return ret; 5606 } 5607 5608 static int mvpp2_ethtool_set_rxfh_context(struct net_device *dev, 5609 const u32 *indir, const u8 *key, 5610 const u8 hfunc, u32 *rss_context, 5611 bool delete) 5612 { 5613 struct mvpp2_port *port = netdev_priv(dev); 5614 int ret; 5615 5616 if (!mvpp22_rss_is_supported()) 5617 return -EOPNOTSUPP; 5618 5619 if (hfunc != ETH_RSS_HASH_NO_CHANGE && hfunc != ETH_RSS_HASH_CRC32) 5620 return -EOPNOTSUPP; 5621 5622 if (key) 5623 return -EOPNOTSUPP; 5624 5625 if (delete) 5626 return mvpp22_port_rss_ctx_delete(port, *rss_context); 5627 5628 if (*rss_context == ETH_RXFH_CONTEXT_ALLOC) { 5629 ret = mvpp22_port_rss_ctx_create(port, rss_context); 5630 if (ret) 5631 return ret; 5632 } 5633 5634 return mvpp22_port_rss_ctx_indir_set(port, *rss_context, indir); 5635 } 5636 /* Device ops */ 5637 5638 static const struct net_device_ops mvpp2_netdev_ops = { 5639 .ndo_open = mvpp2_open, 5640 .ndo_stop = mvpp2_stop, 5641 .ndo_start_xmit = mvpp2_tx, 5642 .ndo_set_rx_mode = mvpp2_set_rx_mode, 5643 .ndo_set_mac_address = mvpp2_set_mac_address, 5644 .ndo_change_mtu = mvpp2_change_mtu, 5645 .ndo_get_stats64 = mvpp2_get_stats64, 5646 .ndo_do_ioctl = mvpp2_ioctl, 5647 .ndo_vlan_rx_add_vid = mvpp2_vlan_rx_add_vid, 5648 .ndo_vlan_rx_kill_vid = mvpp2_vlan_rx_kill_vid, 5649 .ndo_set_features = mvpp2_set_features, 5650 .ndo_bpf = mvpp2_xdp, 5651 .ndo_xdp_xmit = mvpp2_xdp_xmit, 5652 }; 5653 5654 static const struct ethtool_ops mvpp2_eth_tool_ops = { 5655 .supported_coalesce_params = ETHTOOL_COALESCE_USECS | 5656 ETHTOOL_COALESCE_MAX_FRAMES, 5657 .nway_reset = mvpp2_ethtool_nway_reset, 5658 .get_link = ethtool_op_get_link, 5659 .get_ts_info = mvpp2_ethtool_get_ts_info, 5660 .set_coalesce = mvpp2_ethtool_set_coalesce, 5661 .get_coalesce = mvpp2_ethtool_get_coalesce, 5662 .get_drvinfo = mvpp2_ethtool_get_drvinfo, 5663 .get_ringparam = mvpp2_ethtool_get_ringparam, 5664 .set_ringparam = mvpp2_ethtool_set_ringparam, 5665 .get_strings = mvpp2_ethtool_get_strings, 5666 .get_ethtool_stats = mvpp2_ethtool_get_stats, 5667 .get_sset_count = mvpp2_ethtool_get_sset_count, 5668 .get_pauseparam = mvpp2_ethtool_get_pause_param, 5669 .set_pauseparam = mvpp2_ethtool_set_pause_param, 5670 .get_link_ksettings = mvpp2_ethtool_get_link_ksettings, 5671 .set_link_ksettings = mvpp2_ethtool_set_link_ksettings, 5672 .get_rxnfc = mvpp2_ethtool_get_rxnfc, 5673 .set_rxnfc = mvpp2_ethtool_set_rxnfc, 5674 .get_rxfh_indir_size = mvpp2_ethtool_get_rxfh_indir_size, 5675 .get_rxfh = mvpp2_ethtool_get_rxfh, 5676 .set_rxfh = mvpp2_ethtool_set_rxfh, 5677 .get_rxfh_context = mvpp2_ethtool_get_rxfh_context, 5678 .set_rxfh_context = mvpp2_ethtool_set_rxfh_context, 5679 }; 5680 5681 /* Used for PPv2.1, or PPv2.2 with the old Device Tree binding that 5682 * had a single IRQ defined per-port. 5683 */ 5684 static int mvpp2_simple_queue_vectors_init(struct mvpp2_port *port, 5685 struct device_node *port_node) 5686 { 5687 struct mvpp2_queue_vector *v = &port->qvecs[0]; 5688 5689 v->first_rxq = 0; 5690 v->nrxqs = port->nrxqs; 5691 v->type = MVPP2_QUEUE_VECTOR_SHARED; 5692 v->sw_thread_id = 0; 5693 v->sw_thread_mask = *cpumask_bits(cpu_online_mask); 5694 v->port = port; 5695 v->irq = irq_of_parse_and_map(port_node, 0); 5696 if (v->irq <= 0) 5697 return -EINVAL; 5698 netif_napi_add(port->dev, &v->napi, mvpp2_poll, 5699 NAPI_POLL_WEIGHT); 5700 5701 port->nqvecs = 1; 5702 5703 return 0; 5704 } 5705 5706 static int mvpp2_multi_queue_vectors_init(struct mvpp2_port *port, 5707 struct device_node *port_node) 5708 { 5709 struct mvpp2 *priv = port->priv; 5710 struct mvpp2_queue_vector *v; 5711 int i, ret; 5712 5713 switch (queue_mode) { 5714 case MVPP2_QDIST_SINGLE_MODE: 5715 port->nqvecs = priv->nthreads + 1; 5716 break; 5717 case MVPP2_QDIST_MULTI_MODE: 5718 port->nqvecs = priv->nthreads; 5719 break; 5720 } 5721 5722 for (i = 0; i < port->nqvecs; i++) { 5723 char irqname[16]; 5724 5725 v = port->qvecs + i; 5726 5727 v->port = port; 5728 v->type = MVPP2_QUEUE_VECTOR_PRIVATE; 5729 v->sw_thread_id = i; 5730 v->sw_thread_mask = BIT(i); 5731 5732 if (port->flags & MVPP2_F_DT_COMPAT) 5733 snprintf(irqname, sizeof(irqname), "tx-cpu%d", i); 5734 else 5735 snprintf(irqname, sizeof(irqname), "hif%d", i); 5736 5737 if (queue_mode == MVPP2_QDIST_MULTI_MODE) { 5738 v->first_rxq = i; 5739 v->nrxqs = 1; 5740 } else if (queue_mode == MVPP2_QDIST_SINGLE_MODE && 5741 i == (port->nqvecs - 1)) { 5742 v->first_rxq = 0; 5743 v->nrxqs = port->nrxqs; 5744 v->type = MVPP2_QUEUE_VECTOR_SHARED; 5745 5746 if (port->flags & MVPP2_F_DT_COMPAT) 5747 strncpy(irqname, "rx-shared", sizeof(irqname)); 5748 } 5749 5750 if (port_node) 5751 v->irq = of_irq_get_byname(port_node, irqname); 5752 else 5753 v->irq = fwnode_irq_get(port->fwnode, i); 5754 if (v->irq <= 0) { 5755 ret = -EINVAL; 5756 goto err; 5757 } 5758 5759 netif_napi_add(port->dev, &v->napi, mvpp2_poll, 5760 NAPI_POLL_WEIGHT); 5761 } 5762 5763 return 0; 5764 5765 err: 5766 for (i = 0; i < port->nqvecs; i++) 5767 irq_dispose_mapping(port->qvecs[i].irq); 5768 return ret; 5769 } 5770 5771 static int mvpp2_queue_vectors_init(struct mvpp2_port *port, 5772 struct device_node *port_node) 5773 { 5774 if (port->has_tx_irqs) 5775 return mvpp2_multi_queue_vectors_init(port, port_node); 5776 else 5777 return mvpp2_simple_queue_vectors_init(port, port_node); 5778 } 5779 5780 static void mvpp2_queue_vectors_deinit(struct mvpp2_port *port) 5781 { 5782 int i; 5783 5784 for (i = 0; i < port->nqvecs; i++) 5785 irq_dispose_mapping(port->qvecs[i].irq); 5786 } 5787 5788 /* Configure Rx queue group interrupt for this port */ 5789 static void mvpp2_rx_irqs_setup(struct mvpp2_port *port) 5790 { 5791 struct mvpp2 *priv = port->priv; 5792 u32 val; 5793 int i; 5794 5795 if (priv->hw_version == MVPP21) { 5796 mvpp2_write(priv, MVPP21_ISR_RXQ_GROUP_REG(port->id), 5797 port->nrxqs); 5798 return; 5799 } 5800 5801 /* Handle the more complicated PPv2.2 and PPv2.3 case */ 5802 for (i = 0; i < port->nqvecs; i++) { 5803 struct mvpp2_queue_vector *qv = port->qvecs + i; 5804 5805 if (!qv->nrxqs) 5806 continue; 5807 5808 val = qv->sw_thread_id; 5809 val |= port->id << MVPP22_ISR_RXQ_GROUP_INDEX_GROUP_OFFSET; 5810 mvpp2_write(priv, MVPP22_ISR_RXQ_GROUP_INDEX_REG, val); 5811 5812 val = qv->first_rxq; 5813 val |= qv->nrxqs << MVPP22_ISR_RXQ_SUB_GROUP_SIZE_OFFSET; 5814 mvpp2_write(priv, MVPP22_ISR_RXQ_SUB_GROUP_CONFIG_REG, val); 5815 } 5816 } 5817 5818 /* Initialize port HW */ 5819 static int mvpp2_port_init(struct mvpp2_port *port) 5820 { 5821 struct device *dev = port->dev->dev.parent; 5822 struct mvpp2 *priv = port->priv; 5823 struct mvpp2_txq_pcpu *txq_pcpu; 5824 unsigned int thread; 5825 int queue, err, val; 5826 5827 /* Checks for hardware constraints */ 5828 if (port->first_rxq + port->nrxqs > 5829 MVPP2_MAX_PORTS * priv->max_port_rxqs) 5830 return -EINVAL; 5831 5832 if (port->nrxqs > priv->max_port_rxqs || port->ntxqs > MVPP2_MAX_TXQ) 5833 return -EINVAL; 5834 5835 /* Disable port */ 5836 mvpp2_egress_disable(port); 5837 mvpp2_port_disable(port); 5838 5839 if (mvpp2_is_xlg(port->phy_interface)) { 5840 val = readl(port->base + MVPP22_XLG_CTRL0_REG); 5841 val &= ~MVPP22_XLG_CTRL0_FORCE_LINK_PASS; 5842 val |= MVPP22_XLG_CTRL0_FORCE_LINK_DOWN; 5843 writel(val, port->base + MVPP22_XLG_CTRL0_REG); 5844 } else { 5845 val = readl(port->base + MVPP2_GMAC_AUTONEG_CONFIG); 5846 val &= ~MVPP2_GMAC_FORCE_LINK_PASS; 5847 val |= MVPP2_GMAC_FORCE_LINK_DOWN; 5848 writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG); 5849 } 5850 5851 port->tx_time_coal = MVPP2_TXDONE_COAL_USEC; 5852 5853 port->txqs = devm_kcalloc(dev, port->ntxqs, sizeof(*port->txqs), 5854 GFP_KERNEL); 5855 if (!port->txqs) 5856 return -ENOMEM; 5857 5858 /* Associate physical Tx queues to this port and initialize. 5859 * The mapping is predefined. 5860 */ 5861 for (queue = 0; queue < port->ntxqs; queue++) { 5862 int queue_phy_id = mvpp2_txq_phys(port->id, queue); 5863 struct mvpp2_tx_queue *txq; 5864 5865 txq = devm_kzalloc(dev, sizeof(*txq), GFP_KERNEL); 5866 if (!txq) { 5867 err = -ENOMEM; 5868 goto err_free_percpu; 5869 } 5870 5871 txq->pcpu = alloc_percpu(struct mvpp2_txq_pcpu); 5872 if (!txq->pcpu) { 5873 err = -ENOMEM; 5874 goto err_free_percpu; 5875 } 5876 5877 txq->id = queue_phy_id; 5878 txq->log_id = queue; 5879 txq->done_pkts_coal = MVPP2_TXDONE_COAL_PKTS_THRESH; 5880 for (thread = 0; thread < priv->nthreads; thread++) { 5881 txq_pcpu = per_cpu_ptr(txq->pcpu, thread); 5882 txq_pcpu->thread = thread; 5883 } 5884 5885 port->txqs[queue] = txq; 5886 } 5887 5888 port->rxqs = devm_kcalloc(dev, port->nrxqs, sizeof(*port->rxqs), 5889 GFP_KERNEL); 5890 if (!port->rxqs) { 5891 err = -ENOMEM; 5892 goto err_free_percpu; 5893 } 5894 5895 /* Allocate and initialize Rx queue for this port */ 5896 for (queue = 0; queue < port->nrxqs; queue++) { 5897 struct mvpp2_rx_queue *rxq; 5898 5899 /* Map physical Rx queue to port's logical Rx queue */ 5900 rxq = devm_kzalloc(dev, sizeof(*rxq), GFP_KERNEL); 5901 if (!rxq) { 5902 err = -ENOMEM; 5903 goto err_free_percpu; 5904 } 5905 /* Map this Rx queue to a physical queue */ 5906 rxq->id = port->first_rxq + queue; 5907 rxq->port = port->id; 5908 rxq->logic_rxq = queue; 5909 5910 port->rxqs[queue] = rxq; 5911 } 5912 5913 mvpp2_rx_irqs_setup(port); 5914 5915 /* Create Rx descriptor rings */ 5916 for (queue = 0; queue < port->nrxqs; queue++) { 5917 struct mvpp2_rx_queue *rxq = port->rxqs[queue]; 5918 5919 rxq->size = port->rx_ring_size; 5920 rxq->pkts_coal = MVPP2_RX_COAL_PKTS; 5921 rxq->time_coal = MVPP2_RX_COAL_USEC; 5922 } 5923 5924 mvpp2_ingress_disable(port); 5925 5926 /* Port default configuration */ 5927 mvpp2_defaults_set(port); 5928 5929 /* Port's classifier configuration */ 5930 mvpp2_cls_oversize_rxq_set(port); 5931 mvpp2_cls_port_config(port); 5932 5933 if (mvpp22_rss_is_supported()) 5934 mvpp22_port_rss_init(port); 5935 5936 /* Provide an initial Rx packet size */ 5937 port->pkt_size = MVPP2_RX_PKT_SIZE(port->dev->mtu); 5938 5939 /* Initialize pools for swf */ 5940 err = mvpp2_swf_bm_pool_init(port); 5941 if (err) 5942 goto err_free_percpu; 5943 5944 /* Clear all port stats */ 5945 mvpp2_read_stats(port); 5946 memset(port->ethtool_stats, 0, 5947 MVPP2_N_ETHTOOL_STATS(port->ntxqs, port->nrxqs) * sizeof(u64)); 5948 5949 return 0; 5950 5951 err_free_percpu: 5952 for (queue = 0; queue < port->ntxqs; queue++) { 5953 if (!port->txqs[queue]) 5954 continue; 5955 free_percpu(port->txqs[queue]->pcpu); 5956 } 5957 return err; 5958 } 5959 5960 static bool mvpp22_port_has_legacy_tx_irqs(struct device_node *port_node, 5961 unsigned long *flags) 5962 { 5963 char *irqs[5] = { "rx-shared", "tx-cpu0", "tx-cpu1", "tx-cpu2", 5964 "tx-cpu3" }; 5965 int i; 5966 5967 for (i = 0; i < 5; i++) 5968 if (of_property_match_string(port_node, "interrupt-names", 5969 irqs[i]) < 0) 5970 return false; 5971 5972 *flags |= MVPP2_F_DT_COMPAT; 5973 return true; 5974 } 5975 5976 /* Checks if the port dt description has the required Tx interrupts: 5977 * - PPv2.1: there are no such interrupts. 5978 * - PPv2.2 and PPv2.3: 5979 * - The old DTs have: "rx-shared", "tx-cpuX" with X in [0...3] 5980 * - The new ones have: "hifX" with X in [0..8] 5981 * 5982 * All those variants are supported to keep the backward compatibility. 5983 */ 5984 static bool mvpp2_port_has_irqs(struct mvpp2 *priv, 5985 struct device_node *port_node, 5986 unsigned long *flags) 5987 { 5988 char name[5]; 5989 int i; 5990 5991 /* ACPI */ 5992 if (!port_node) 5993 return true; 5994 5995 if (priv->hw_version == MVPP21) 5996 return false; 5997 5998 if (mvpp22_port_has_legacy_tx_irqs(port_node, flags)) 5999 return true; 6000 6001 for (i = 0; i < MVPP2_MAX_THREADS; i++) { 6002 snprintf(name, 5, "hif%d", i); 6003 if (of_property_match_string(port_node, "interrupt-names", 6004 name) < 0) 6005 return false; 6006 } 6007 6008 return true; 6009 } 6010 6011 static void mvpp2_port_copy_mac_addr(struct net_device *dev, struct mvpp2 *priv, 6012 struct fwnode_handle *fwnode, 6013 char **mac_from) 6014 { 6015 struct mvpp2_port *port = netdev_priv(dev); 6016 char hw_mac_addr[ETH_ALEN] = {0}; 6017 char fw_mac_addr[ETH_ALEN]; 6018 6019 if (fwnode_get_mac_address(fwnode, fw_mac_addr, ETH_ALEN)) { 6020 *mac_from = "firmware node"; 6021 ether_addr_copy(dev->dev_addr, fw_mac_addr); 6022 return; 6023 } 6024 6025 if (priv->hw_version == MVPP21) { 6026 mvpp21_get_mac_address(port, hw_mac_addr); 6027 if (is_valid_ether_addr(hw_mac_addr)) { 6028 *mac_from = "hardware"; 6029 ether_addr_copy(dev->dev_addr, hw_mac_addr); 6030 return; 6031 } 6032 } 6033 6034 *mac_from = "random"; 6035 eth_hw_addr_random(dev); 6036 } 6037 6038 static struct mvpp2_port *mvpp2_phylink_to_port(struct phylink_config *config) 6039 { 6040 return container_of(config, struct mvpp2_port, phylink_config); 6041 } 6042 6043 static struct mvpp2_port *mvpp2_pcs_to_port(struct phylink_pcs *pcs) 6044 { 6045 return container_of(pcs, struct mvpp2_port, phylink_pcs); 6046 } 6047 6048 static void mvpp2_xlg_pcs_get_state(struct phylink_pcs *pcs, 6049 struct phylink_link_state *state) 6050 { 6051 struct mvpp2_port *port = mvpp2_pcs_to_port(pcs); 6052 u32 val; 6053 6054 state->speed = SPEED_10000; 6055 state->duplex = 1; 6056 state->an_complete = 1; 6057 6058 val = readl(port->base + MVPP22_XLG_STATUS); 6059 state->link = !!(val & MVPP22_XLG_STATUS_LINK_UP); 6060 6061 state->pause = 0; 6062 val = readl(port->base + MVPP22_XLG_CTRL0_REG); 6063 if (val & MVPP22_XLG_CTRL0_TX_FLOW_CTRL_EN) 6064 state->pause |= MLO_PAUSE_TX; 6065 if (val & MVPP22_XLG_CTRL0_RX_FLOW_CTRL_EN) 6066 state->pause |= MLO_PAUSE_RX; 6067 } 6068 6069 static int mvpp2_xlg_pcs_config(struct phylink_pcs *pcs, 6070 unsigned int mode, 6071 phy_interface_t interface, 6072 const unsigned long *advertising, 6073 bool permit_pause_to_mac) 6074 { 6075 return 0; 6076 } 6077 6078 static const struct phylink_pcs_ops mvpp2_phylink_xlg_pcs_ops = { 6079 .pcs_get_state = mvpp2_xlg_pcs_get_state, 6080 .pcs_config = mvpp2_xlg_pcs_config, 6081 }; 6082 6083 static void mvpp2_gmac_pcs_get_state(struct phylink_pcs *pcs, 6084 struct phylink_link_state *state) 6085 { 6086 struct mvpp2_port *port = mvpp2_pcs_to_port(pcs); 6087 u32 val; 6088 6089 val = readl(port->base + MVPP2_GMAC_STATUS0); 6090 6091 state->an_complete = !!(val & MVPP2_GMAC_STATUS0_AN_COMPLETE); 6092 state->link = !!(val & MVPP2_GMAC_STATUS0_LINK_UP); 6093 state->duplex = !!(val & MVPP2_GMAC_STATUS0_FULL_DUPLEX); 6094 6095 switch (port->phy_interface) { 6096 case PHY_INTERFACE_MODE_1000BASEX: 6097 state->speed = SPEED_1000; 6098 break; 6099 case PHY_INTERFACE_MODE_2500BASEX: 6100 state->speed = SPEED_2500; 6101 break; 6102 default: 6103 if (val & MVPP2_GMAC_STATUS0_GMII_SPEED) 6104 state->speed = SPEED_1000; 6105 else if (val & MVPP2_GMAC_STATUS0_MII_SPEED) 6106 state->speed = SPEED_100; 6107 else 6108 state->speed = SPEED_10; 6109 } 6110 6111 state->pause = 0; 6112 if (val & MVPP2_GMAC_STATUS0_RX_PAUSE) 6113 state->pause |= MLO_PAUSE_RX; 6114 if (val & MVPP2_GMAC_STATUS0_TX_PAUSE) 6115 state->pause |= MLO_PAUSE_TX; 6116 } 6117 6118 static int mvpp2_gmac_pcs_config(struct phylink_pcs *pcs, unsigned int mode, 6119 phy_interface_t interface, 6120 const unsigned long *advertising, 6121 bool permit_pause_to_mac) 6122 { 6123 struct mvpp2_port *port = mvpp2_pcs_to_port(pcs); 6124 u32 mask, val, an, old_an, changed; 6125 6126 mask = MVPP2_GMAC_IN_BAND_AUTONEG_BYPASS | 6127 MVPP2_GMAC_IN_BAND_AUTONEG | 6128 MVPP2_GMAC_AN_SPEED_EN | 6129 MVPP2_GMAC_FLOW_CTRL_AUTONEG | 6130 MVPP2_GMAC_AN_DUPLEX_EN; 6131 6132 if (phylink_autoneg_inband(mode)) { 6133 mask |= MVPP2_GMAC_CONFIG_MII_SPEED | 6134 MVPP2_GMAC_CONFIG_GMII_SPEED | 6135 MVPP2_GMAC_CONFIG_FULL_DUPLEX; 6136 val = MVPP2_GMAC_IN_BAND_AUTONEG; 6137 6138 if (interface == PHY_INTERFACE_MODE_SGMII) { 6139 /* SGMII mode receives the speed and duplex from PHY */ 6140 val |= MVPP2_GMAC_AN_SPEED_EN | 6141 MVPP2_GMAC_AN_DUPLEX_EN; 6142 } else { 6143 /* 802.3z mode has fixed speed and duplex */ 6144 val |= MVPP2_GMAC_CONFIG_GMII_SPEED | 6145 MVPP2_GMAC_CONFIG_FULL_DUPLEX; 6146 6147 /* The FLOW_CTRL_AUTONEG bit selects either the hardware 6148 * automatically or the bits in MVPP22_GMAC_CTRL_4_REG 6149 * manually controls the GMAC pause modes. 6150 */ 6151 if (permit_pause_to_mac) 6152 val |= MVPP2_GMAC_FLOW_CTRL_AUTONEG; 6153 6154 /* Configure advertisement bits */ 6155 mask |= MVPP2_GMAC_FC_ADV_EN | MVPP2_GMAC_FC_ADV_ASM_EN; 6156 if (phylink_test(advertising, Pause)) 6157 val |= MVPP2_GMAC_FC_ADV_EN; 6158 if (phylink_test(advertising, Asym_Pause)) 6159 val |= MVPP2_GMAC_FC_ADV_ASM_EN; 6160 } 6161 } else { 6162 val = 0; 6163 } 6164 6165 old_an = an = readl(port->base + MVPP2_GMAC_AUTONEG_CONFIG); 6166 an = (an & ~mask) | val; 6167 changed = an ^ old_an; 6168 if (changed) 6169 writel(an, port->base + MVPP2_GMAC_AUTONEG_CONFIG); 6170 6171 /* We are only interested in the advertisement bits changing */ 6172 return changed & (MVPP2_GMAC_FC_ADV_EN | MVPP2_GMAC_FC_ADV_ASM_EN); 6173 } 6174 6175 static void mvpp2_gmac_pcs_an_restart(struct phylink_pcs *pcs) 6176 { 6177 struct mvpp2_port *port = mvpp2_pcs_to_port(pcs); 6178 u32 val = readl(port->base + MVPP2_GMAC_AUTONEG_CONFIG); 6179 6180 writel(val | MVPP2_GMAC_IN_BAND_RESTART_AN, 6181 port->base + MVPP2_GMAC_AUTONEG_CONFIG); 6182 writel(val & ~MVPP2_GMAC_IN_BAND_RESTART_AN, 6183 port->base + MVPP2_GMAC_AUTONEG_CONFIG); 6184 } 6185 6186 static const struct phylink_pcs_ops mvpp2_phylink_gmac_pcs_ops = { 6187 .pcs_get_state = mvpp2_gmac_pcs_get_state, 6188 .pcs_config = mvpp2_gmac_pcs_config, 6189 .pcs_an_restart = mvpp2_gmac_pcs_an_restart, 6190 }; 6191 6192 static void mvpp2_phylink_validate(struct phylink_config *config, 6193 unsigned long *supported, 6194 struct phylink_link_state *state) 6195 { 6196 struct mvpp2_port *port = mvpp2_phylink_to_port(config); 6197 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, }; 6198 6199 /* Invalid combinations */ 6200 switch (state->interface) { 6201 case PHY_INTERFACE_MODE_10GBASER: 6202 case PHY_INTERFACE_MODE_XAUI: 6203 if (!mvpp2_port_supports_xlg(port)) 6204 goto empty_set; 6205 break; 6206 case PHY_INTERFACE_MODE_RGMII: 6207 case PHY_INTERFACE_MODE_RGMII_ID: 6208 case PHY_INTERFACE_MODE_RGMII_RXID: 6209 case PHY_INTERFACE_MODE_RGMII_TXID: 6210 if (!mvpp2_port_supports_rgmii(port)) 6211 goto empty_set; 6212 break; 6213 default: 6214 break; 6215 } 6216 6217 phylink_set(mask, Autoneg); 6218 phylink_set_port_modes(mask); 6219 6220 if (port->priv->global_tx_fc) { 6221 phylink_set(mask, Pause); 6222 phylink_set(mask, Asym_Pause); 6223 } 6224 6225 switch (state->interface) { 6226 case PHY_INTERFACE_MODE_10GBASER: 6227 case PHY_INTERFACE_MODE_XAUI: 6228 case PHY_INTERFACE_MODE_NA: 6229 if (mvpp2_port_supports_xlg(port)) { 6230 phylink_set(mask, 10000baseT_Full); 6231 phylink_set(mask, 10000baseCR_Full); 6232 phylink_set(mask, 10000baseSR_Full); 6233 phylink_set(mask, 10000baseLR_Full); 6234 phylink_set(mask, 10000baseLRM_Full); 6235 phylink_set(mask, 10000baseER_Full); 6236 phylink_set(mask, 10000baseKR_Full); 6237 } 6238 if (state->interface != PHY_INTERFACE_MODE_NA) 6239 break; 6240 fallthrough; 6241 case PHY_INTERFACE_MODE_RGMII: 6242 case PHY_INTERFACE_MODE_RGMII_ID: 6243 case PHY_INTERFACE_MODE_RGMII_RXID: 6244 case PHY_INTERFACE_MODE_RGMII_TXID: 6245 case PHY_INTERFACE_MODE_SGMII: 6246 phylink_set(mask, 10baseT_Half); 6247 phylink_set(mask, 10baseT_Full); 6248 phylink_set(mask, 100baseT_Half); 6249 phylink_set(mask, 100baseT_Full); 6250 phylink_set(mask, 1000baseT_Full); 6251 phylink_set(mask, 1000baseX_Full); 6252 if (state->interface != PHY_INTERFACE_MODE_NA) 6253 break; 6254 fallthrough; 6255 case PHY_INTERFACE_MODE_1000BASEX: 6256 case PHY_INTERFACE_MODE_2500BASEX: 6257 if (port->comphy || 6258 state->interface != PHY_INTERFACE_MODE_2500BASEX) { 6259 phylink_set(mask, 1000baseT_Full); 6260 phylink_set(mask, 1000baseX_Full); 6261 } 6262 if (port->comphy || 6263 state->interface == PHY_INTERFACE_MODE_2500BASEX) { 6264 phylink_set(mask, 2500baseT_Full); 6265 phylink_set(mask, 2500baseX_Full); 6266 } 6267 break; 6268 default: 6269 goto empty_set; 6270 } 6271 6272 bitmap_and(supported, supported, mask, __ETHTOOL_LINK_MODE_MASK_NBITS); 6273 bitmap_and(state->advertising, state->advertising, mask, 6274 __ETHTOOL_LINK_MODE_MASK_NBITS); 6275 6276 phylink_helper_basex_speed(state); 6277 return; 6278 6279 empty_set: 6280 bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS); 6281 } 6282 6283 static void mvpp2_xlg_config(struct mvpp2_port *port, unsigned int mode, 6284 const struct phylink_link_state *state) 6285 { 6286 u32 val; 6287 6288 mvpp2_modify(port->base + MVPP22_XLG_CTRL0_REG, 6289 MVPP22_XLG_CTRL0_MAC_RESET_DIS, 6290 MVPP22_XLG_CTRL0_MAC_RESET_DIS); 6291 mvpp2_modify(port->base + MVPP22_XLG_CTRL4_REG, 6292 MVPP22_XLG_CTRL4_MACMODSELECT_GMAC | 6293 MVPP22_XLG_CTRL4_EN_IDLE_CHECK | 6294 MVPP22_XLG_CTRL4_FWD_FC | MVPP22_XLG_CTRL4_FWD_PFC, 6295 MVPP22_XLG_CTRL4_FWD_FC | MVPP22_XLG_CTRL4_FWD_PFC); 6296 6297 /* Wait for reset to deassert */ 6298 do { 6299 val = readl(port->base + MVPP22_XLG_CTRL0_REG); 6300 } while (!(val & MVPP22_XLG_CTRL0_MAC_RESET_DIS)); 6301 } 6302 6303 static void mvpp2_gmac_config(struct mvpp2_port *port, unsigned int mode, 6304 const struct phylink_link_state *state) 6305 { 6306 u32 old_ctrl0, ctrl0; 6307 u32 old_ctrl2, ctrl2; 6308 u32 old_ctrl4, ctrl4; 6309 6310 old_ctrl0 = ctrl0 = readl(port->base + MVPP2_GMAC_CTRL_0_REG); 6311 old_ctrl2 = ctrl2 = readl(port->base + MVPP2_GMAC_CTRL_2_REG); 6312 old_ctrl4 = ctrl4 = readl(port->base + MVPP22_GMAC_CTRL_4_REG); 6313 6314 ctrl0 &= ~MVPP2_GMAC_PORT_TYPE_MASK; 6315 ctrl2 &= ~(MVPP2_GMAC_INBAND_AN_MASK | MVPP2_GMAC_PCS_ENABLE_MASK | MVPP2_GMAC_FLOW_CTRL_MASK); 6316 6317 /* Configure port type */ 6318 if (phy_interface_mode_is_8023z(state->interface)) { 6319 ctrl2 |= MVPP2_GMAC_PCS_ENABLE_MASK; 6320 ctrl4 &= ~MVPP22_CTRL4_EXT_PIN_GMII_SEL; 6321 ctrl4 |= MVPP22_CTRL4_SYNC_BYPASS_DIS | 6322 MVPP22_CTRL4_DP_CLK_SEL | 6323 MVPP22_CTRL4_QSGMII_BYPASS_ACTIVE; 6324 } else if (state->interface == PHY_INTERFACE_MODE_SGMII) { 6325 ctrl2 |= MVPP2_GMAC_PCS_ENABLE_MASK | MVPP2_GMAC_INBAND_AN_MASK; 6326 ctrl4 &= ~MVPP22_CTRL4_EXT_PIN_GMII_SEL; 6327 ctrl4 |= MVPP22_CTRL4_SYNC_BYPASS_DIS | 6328 MVPP22_CTRL4_DP_CLK_SEL | 6329 MVPP22_CTRL4_QSGMII_BYPASS_ACTIVE; 6330 } else if (phy_interface_mode_is_rgmii(state->interface)) { 6331 ctrl4 &= ~MVPP22_CTRL4_DP_CLK_SEL; 6332 ctrl4 |= MVPP22_CTRL4_EXT_PIN_GMII_SEL | 6333 MVPP22_CTRL4_SYNC_BYPASS_DIS | 6334 MVPP22_CTRL4_QSGMII_BYPASS_ACTIVE; 6335 } 6336 6337 /* Configure negotiation style */ 6338 if (!phylink_autoneg_inband(mode)) { 6339 /* Phy or fixed speed - no in-band AN, nothing to do, leave the 6340 * configured speed, duplex and flow control as-is. 6341 */ 6342 } else if (state->interface == PHY_INTERFACE_MODE_SGMII) { 6343 /* SGMII in-band mode receives the speed and duplex from 6344 * the PHY. Flow control information is not received. */ 6345 } else if (phy_interface_mode_is_8023z(state->interface)) { 6346 /* 1000BaseX and 2500BaseX ports cannot negotiate speed nor can 6347 * they negotiate duplex: they are always operating with a fixed 6348 * speed of 1000/2500Mbps in full duplex, so force 1000/2500 6349 * speed and full duplex here. 6350 */ 6351 ctrl0 |= MVPP2_GMAC_PORT_TYPE_MASK; 6352 } 6353 6354 if (old_ctrl0 != ctrl0) 6355 writel(ctrl0, port->base + MVPP2_GMAC_CTRL_0_REG); 6356 if (old_ctrl2 != ctrl2) 6357 writel(ctrl2, port->base + MVPP2_GMAC_CTRL_2_REG); 6358 if (old_ctrl4 != ctrl4) 6359 writel(ctrl4, port->base + MVPP22_GMAC_CTRL_4_REG); 6360 } 6361 6362 static int mvpp2__mac_prepare(struct phylink_config *config, unsigned int mode, 6363 phy_interface_t interface) 6364 { 6365 struct mvpp2_port *port = mvpp2_phylink_to_port(config); 6366 6367 /* Check for invalid configuration */ 6368 if (mvpp2_is_xlg(interface) && port->gop_id != 0) { 6369 netdev_err(port->dev, "Invalid mode on %s\n", port->dev->name); 6370 return -EINVAL; 6371 } 6372 6373 if (port->phy_interface != interface || 6374 phylink_autoneg_inband(mode)) { 6375 /* Force the link down when changing the interface or if in 6376 * in-band mode to ensure we do not change the configuration 6377 * while the hardware is indicating link is up. We force both 6378 * XLG and GMAC down to ensure that they're both in a known 6379 * state. 6380 */ 6381 mvpp2_modify(port->base + MVPP2_GMAC_AUTONEG_CONFIG, 6382 MVPP2_GMAC_FORCE_LINK_PASS | 6383 MVPP2_GMAC_FORCE_LINK_DOWN, 6384 MVPP2_GMAC_FORCE_LINK_DOWN); 6385 6386 if (mvpp2_port_supports_xlg(port)) 6387 mvpp2_modify(port->base + MVPP22_XLG_CTRL0_REG, 6388 MVPP22_XLG_CTRL0_FORCE_LINK_PASS | 6389 MVPP22_XLG_CTRL0_FORCE_LINK_DOWN, 6390 MVPP22_XLG_CTRL0_FORCE_LINK_DOWN); 6391 } 6392 6393 /* Make sure the port is disabled when reconfiguring the mode */ 6394 mvpp2_port_disable(port); 6395 6396 if (port->phy_interface != interface) { 6397 /* Place GMAC into reset */ 6398 mvpp2_modify(port->base + MVPP2_GMAC_CTRL_2_REG, 6399 MVPP2_GMAC_PORT_RESET_MASK, 6400 MVPP2_GMAC_PORT_RESET_MASK); 6401 6402 if (port->priv->hw_version != MVPP21) { 6403 mvpp22_gop_mask_irq(port); 6404 6405 phy_power_off(port->comphy); 6406 } 6407 } 6408 6409 /* Select the appropriate PCS operations depending on the 6410 * configured interface mode. We will only switch to a mode 6411 * that the validate() checks have already passed. 6412 */ 6413 if (mvpp2_is_xlg(interface)) 6414 port->phylink_pcs.ops = &mvpp2_phylink_xlg_pcs_ops; 6415 else 6416 port->phylink_pcs.ops = &mvpp2_phylink_gmac_pcs_ops; 6417 6418 return 0; 6419 } 6420 6421 static int mvpp2_mac_prepare(struct phylink_config *config, unsigned int mode, 6422 phy_interface_t interface) 6423 { 6424 struct mvpp2_port *port = mvpp2_phylink_to_port(config); 6425 int ret; 6426 6427 ret = mvpp2__mac_prepare(config, mode, interface); 6428 if (ret == 0) 6429 phylink_set_pcs(port->phylink, &port->phylink_pcs); 6430 6431 return ret; 6432 } 6433 6434 static void mvpp2_mac_config(struct phylink_config *config, unsigned int mode, 6435 const struct phylink_link_state *state) 6436 { 6437 struct mvpp2_port *port = mvpp2_phylink_to_port(config); 6438 6439 /* mac (re)configuration */ 6440 if (mvpp2_is_xlg(state->interface)) 6441 mvpp2_xlg_config(port, mode, state); 6442 else if (phy_interface_mode_is_rgmii(state->interface) || 6443 phy_interface_mode_is_8023z(state->interface) || 6444 state->interface == PHY_INTERFACE_MODE_SGMII) 6445 mvpp2_gmac_config(port, mode, state); 6446 6447 if (port->priv->hw_version == MVPP21 && port->flags & MVPP2_F_LOOPBACK) 6448 mvpp2_port_loopback_set(port, state); 6449 } 6450 6451 static int mvpp2_mac_finish(struct phylink_config *config, unsigned int mode, 6452 phy_interface_t interface) 6453 { 6454 struct mvpp2_port *port = mvpp2_phylink_to_port(config); 6455 6456 if (port->priv->hw_version != MVPP21 && 6457 port->phy_interface != interface) { 6458 port->phy_interface = interface; 6459 6460 /* Reconfigure the serdes lanes */ 6461 mvpp22_mode_reconfigure(port); 6462 6463 /* Unmask interrupts */ 6464 mvpp22_gop_unmask_irq(port); 6465 } 6466 6467 if (!mvpp2_is_xlg(interface)) { 6468 /* Release GMAC reset and wait */ 6469 mvpp2_modify(port->base + MVPP2_GMAC_CTRL_2_REG, 6470 MVPP2_GMAC_PORT_RESET_MASK, 0); 6471 6472 while (readl(port->base + MVPP2_GMAC_CTRL_2_REG) & 6473 MVPP2_GMAC_PORT_RESET_MASK) 6474 continue; 6475 } 6476 6477 mvpp2_port_enable(port); 6478 6479 /* Allow the link to come up if in in-band mode, otherwise the 6480 * link is forced via mac_link_down()/mac_link_up() 6481 */ 6482 if (phylink_autoneg_inband(mode)) { 6483 if (mvpp2_is_xlg(interface)) 6484 mvpp2_modify(port->base + MVPP22_XLG_CTRL0_REG, 6485 MVPP22_XLG_CTRL0_FORCE_LINK_PASS | 6486 MVPP22_XLG_CTRL0_FORCE_LINK_DOWN, 0); 6487 else 6488 mvpp2_modify(port->base + MVPP2_GMAC_AUTONEG_CONFIG, 6489 MVPP2_GMAC_FORCE_LINK_PASS | 6490 MVPP2_GMAC_FORCE_LINK_DOWN, 0); 6491 } 6492 6493 return 0; 6494 } 6495 6496 static void mvpp2_mac_link_up(struct phylink_config *config, 6497 struct phy_device *phy, 6498 unsigned int mode, phy_interface_t interface, 6499 int speed, int duplex, 6500 bool tx_pause, bool rx_pause) 6501 { 6502 struct mvpp2_port *port = mvpp2_phylink_to_port(config); 6503 u32 val; 6504 int i; 6505 6506 if (mvpp2_is_xlg(interface)) { 6507 if (!phylink_autoneg_inband(mode)) { 6508 val = MVPP22_XLG_CTRL0_FORCE_LINK_PASS; 6509 if (tx_pause) 6510 val |= MVPP22_XLG_CTRL0_TX_FLOW_CTRL_EN; 6511 if (rx_pause) 6512 val |= MVPP22_XLG_CTRL0_RX_FLOW_CTRL_EN; 6513 6514 mvpp2_modify(port->base + MVPP22_XLG_CTRL0_REG, 6515 MVPP22_XLG_CTRL0_FORCE_LINK_DOWN | 6516 MVPP22_XLG_CTRL0_FORCE_LINK_PASS | 6517 MVPP22_XLG_CTRL0_TX_FLOW_CTRL_EN | 6518 MVPP22_XLG_CTRL0_RX_FLOW_CTRL_EN, val); 6519 } 6520 } else { 6521 if (!phylink_autoneg_inband(mode)) { 6522 val = MVPP2_GMAC_FORCE_LINK_PASS; 6523 6524 if (speed == SPEED_1000 || speed == SPEED_2500) 6525 val |= MVPP2_GMAC_CONFIG_GMII_SPEED; 6526 else if (speed == SPEED_100) 6527 val |= MVPP2_GMAC_CONFIG_MII_SPEED; 6528 6529 if (duplex == DUPLEX_FULL) 6530 val |= MVPP2_GMAC_CONFIG_FULL_DUPLEX; 6531 6532 mvpp2_modify(port->base + MVPP2_GMAC_AUTONEG_CONFIG, 6533 MVPP2_GMAC_FORCE_LINK_DOWN | 6534 MVPP2_GMAC_FORCE_LINK_PASS | 6535 MVPP2_GMAC_CONFIG_MII_SPEED | 6536 MVPP2_GMAC_CONFIG_GMII_SPEED | 6537 MVPP2_GMAC_CONFIG_FULL_DUPLEX, val); 6538 } 6539 6540 /* We can always update the flow control enable bits; 6541 * these will only be effective if flow control AN 6542 * (MVPP2_GMAC_FLOW_CTRL_AUTONEG) is disabled. 6543 */ 6544 val = 0; 6545 if (tx_pause) 6546 val |= MVPP22_CTRL4_TX_FC_EN; 6547 if (rx_pause) 6548 val |= MVPP22_CTRL4_RX_FC_EN; 6549 6550 mvpp2_modify(port->base + MVPP22_GMAC_CTRL_4_REG, 6551 MVPP22_CTRL4_RX_FC_EN | MVPP22_CTRL4_TX_FC_EN, 6552 val); 6553 } 6554 6555 if (port->priv->global_tx_fc) { 6556 port->tx_fc = tx_pause; 6557 if (tx_pause) 6558 mvpp2_rxq_enable_fc(port); 6559 else 6560 mvpp2_rxq_disable_fc(port); 6561 if (port->priv->percpu_pools) { 6562 for (i = 0; i < port->nrxqs; i++) 6563 mvpp2_bm_pool_update_fc(port, &port->priv->bm_pools[i], tx_pause); 6564 } else { 6565 mvpp2_bm_pool_update_fc(port, port->pool_long, tx_pause); 6566 mvpp2_bm_pool_update_fc(port, port->pool_short, tx_pause); 6567 } 6568 if (port->priv->hw_version == MVPP23) 6569 mvpp23_rx_fifo_fc_en(port->priv, port->id, tx_pause); 6570 } 6571 6572 mvpp2_port_enable(port); 6573 6574 mvpp2_egress_enable(port); 6575 mvpp2_ingress_enable(port); 6576 netif_tx_wake_all_queues(port->dev); 6577 } 6578 6579 static void mvpp2_mac_link_down(struct phylink_config *config, 6580 unsigned int mode, phy_interface_t interface) 6581 { 6582 struct mvpp2_port *port = mvpp2_phylink_to_port(config); 6583 u32 val; 6584 6585 if (!phylink_autoneg_inband(mode)) { 6586 if (mvpp2_is_xlg(interface)) { 6587 val = readl(port->base + MVPP22_XLG_CTRL0_REG); 6588 val &= ~MVPP22_XLG_CTRL0_FORCE_LINK_PASS; 6589 val |= MVPP22_XLG_CTRL0_FORCE_LINK_DOWN; 6590 writel(val, port->base + MVPP22_XLG_CTRL0_REG); 6591 } else { 6592 val = readl(port->base + MVPP2_GMAC_AUTONEG_CONFIG); 6593 val &= ~MVPP2_GMAC_FORCE_LINK_PASS; 6594 val |= MVPP2_GMAC_FORCE_LINK_DOWN; 6595 writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG); 6596 } 6597 } 6598 6599 netif_tx_stop_all_queues(port->dev); 6600 mvpp2_egress_disable(port); 6601 mvpp2_ingress_disable(port); 6602 6603 mvpp2_port_disable(port); 6604 } 6605 6606 static const struct phylink_mac_ops mvpp2_phylink_ops = { 6607 .validate = mvpp2_phylink_validate, 6608 .mac_prepare = mvpp2_mac_prepare, 6609 .mac_config = mvpp2_mac_config, 6610 .mac_finish = mvpp2_mac_finish, 6611 .mac_link_up = mvpp2_mac_link_up, 6612 .mac_link_down = mvpp2_mac_link_down, 6613 }; 6614 6615 /* Work-around for ACPI */ 6616 static void mvpp2_acpi_start(struct mvpp2_port *port) 6617 { 6618 /* Phylink isn't used as of now for ACPI, so the MAC has to be 6619 * configured manually when the interface is started. This will 6620 * be removed as soon as the phylink ACPI support lands in. 6621 */ 6622 struct phylink_link_state state = { 6623 .interface = port->phy_interface, 6624 }; 6625 mvpp2__mac_prepare(&port->phylink_config, MLO_AN_INBAND, 6626 port->phy_interface); 6627 mvpp2_mac_config(&port->phylink_config, MLO_AN_INBAND, &state); 6628 port->phylink_pcs.ops->pcs_config(&port->phylink_pcs, MLO_AN_INBAND, 6629 port->phy_interface, 6630 state.advertising, false); 6631 mvpp2_mac_finish(&port->phylink_config, MLO_AN_INBAND, 6632 port->phy_interface); 6633 mvpp2_mac_link_up(&port->phylink_config, NULL, 6634 MLO_AN_INBAND, port->phy_interface, 6635 SPEED_UNKNOWN, DUPLEX_UNKNOWN, false, false); 6636 } 6637 6638 /* Ports initialization */ 6639 static int mvpp2_port_probe(struct platform_device *pdev, 6640 struct fwnode_handle *port_fwnode, 6641 struct mvpp2 *priv) 6642 { 6643 struct phy *comphy = NULL; 6644 struct mvpp2_port *port; 6645 struct mvpp2_port_pcpu *port_pcpu; 6646 struct device_node *port_node = to_of_node(port_fwnode); 6647 netdev_features_t features; 6648 struct net_device *dev; 6649 struct phylink *phylink; 6650 char *mac_from = ""; 6651 unsigned int ntxqs, nrxqs, thread; 6652 unsigned long flags = 0; 6653 bool has_tx_irqs; 6654 u32 id; 6655 int phy_mode; 6656 int err, i; 6657 6658 has_tx_irqs = mvpp2_port_has_irqs(priv, port_node, &flags); 6659 if (!has_tx_irqs && queue_mode == MVPP2_QDIST_MULTI_MODE) { 6660 dev_err(&pdev->dev, 6661 "not enough IRQs to support multi queue mode\n"); 6662 return -EINVAL; 6663 } 6664 6665 ntxqs = MVPP2_MAX_TXQ; 6666 nrxqs = mvpp2_get_nrxqs(priv); 6667 6668 dev = alloc_etherdev_mqs(sizeof(*port), ntxqs, nrxqs); 6669 if (!dev) 6670 return -ENOMEM; 6671 6672 phy_mode = fwnode_get_phy_mode(port_fwnode); 6673 if (phy_mode < 0) { 6674 dev_err(&pdev->dev, "incorrect phy mode\n"); 6675 err = phy_mode; 6676 goto err_free_netdev; 6677 } 6678 6679 /* 6680 * Rewrite 10GBASE-KR to 10GBASE-R for compatibility with existing DT. 6681 * Existing usage of 10GBASE-KR is not correct; no backplane 6682 * negotiation is done, and this driver does not actually support 6683 * 10GBASE-KR. 6684 */ 6685 if (phy_mode == PHY_INTERFACE_MODE_10GKR) 6686 phy_mode = PHY_INTERFACE_MODE_10GBASER; 6687 6688 if (port_node) { 6689 comphy = devm_of_phy_get(&pdev->dev, port_node, NULL); 6690 if (IS_ERR(comphy)) { 6691 if (PTR_ERR(comphy) == -EPROBE_DEFER) { 6692 err = -EPROBE_DEFER; 6693 goto err_free_netdev; 6694 } 6695 comphy = NULL; 6696 } 6697 } 6698 6699 if (fwnode_property_read_u32(port_fwnode, "port-id", &id)) { 6700 err = -EINVAL; 6701 dev_err(&pdev->dev, "missing port-id value\n"); 6702 goto err_free_netdev; 6703 } 6704 6705 dev->tx_queue_len = MVPP2_MAX_TXD_MAX; 6706 dev->watchdog_timeo = 5 * HZ; 6707 dev->netdev_ops = &mvpp2_netdev_ops; 6708 dev->ethtool_ops = &mvpp2_eth_tool_ops; 6709 6710 port = netdev_priv(dev); 6711 port->dev = dev; 6712 port->fwnode = port_fwnode; 6713 port->has_phy = !!of_find_property(port_node, "phy", NULL); 6714 port->ntxqs = ntxqs; 6715 port->nrxqs = nrxqs; 6716 port->priv = priv; 6717 port->has_tx_irqs = has_tx_irqs; 6718 port->flags = flags; 6719 6720 err = mvpp2_queue_vectors_init(port, port_node); 6721 if (err) 6722 goto err_free_netdev; 6723 6724 if (port_node) 6725 port->port_irq = of_irq_get_byname(port_node, "link"); 6726 else 6727 port->port_irq = fwnode_irq_get(port_fwnode, port->nqvecs + 1); 6728 if (port->port_irq == -EPROBE_DEFER) { 6729 err = -EPROBE_DEFER; 6730 goto err_deinit_qvecs; 6731 } 6732 if (port->port_irq <= 0) 6733 /* the link irq is optional */ 6734 port->port_irq = 0; 6735 6736 if (fwnode_property_read_bool(port_fwnode, "marvell,loopback")) 6737 port->flags |= MVPP2_F_LOOPBACK; 6738 6739 port->id = id; 6740 if (priv->hw_version == MVPP21) 6741 port->first_rxq = port->id * port->nrxqs; 6742 else 6743 port->first_rxq = port->id * priv->max_port_rxqs; 6744 6745 port->of_node = port_node; 6746 port->phy_interface = phy_mode; 6747 port->comphy = comphy; 6748 6749 if (priv->hw_version == MVPP21) { 6750 port->base = devm_platform_ioremap_resource(pdev, 2 + id); 6751 if (IS_ERR(port->base)) { 6752 err = PTR_ERR(port->base); 6753 goto err_free_irq; 6754 } 6755 6756 port->stats_base = port->priv->lms_base + 6757 MVPP21_MIB_COUNTERS_OFFSET + 6758 port->gop_id * MVPP21_MIB_COUNTERS_PORT_SZ; 6759 } else { 6760 if (fwnode_property_read_u32(port_fwnode, "gop-port-id", 6761 &port->gop_id)) { 6762 err = -EINVAL; 6763 dev_err(&pdev->dev, "missing gop-port-id value\n"); 6764 goto err_deinit_qvecs; 6765 } 6766 6767 port->base = priv->iface_base + MVPP22_GMAC_BASE(port->gop_id); 6768 port->stats_base = port->priv->iface_base + 6769 MVPP22_MIB_COUNTERS_OFFSET + 6770 port->gop_id * MVPP22_MIB_COUNTERS_PORT_SZ; 6771 6772 /* We may want a property to describe whether we should use 6773 * MAC hardware timestamping. 6774 */ 6775 if (priv->tai) 6776 port->hwtstamp = true; 6777 } 6778 6779 /* Alloc per-cpu and ethtool stats */ 6780 port->stats = netdev_alloc_pcpu_stats(struct mvpp2_pcpu_stats); 6781 if (!port->stats) { 6782 err = -ENOMEM; 6783 goto err_free_irq; 6784 } 6785 6786 port->ethtool_stats = devm_kcalloc(&pdev->dev, 6787 MVPP2_N_ETHTOOL_STATS(ntxqs, nrxqs), 6788 sizeof(u64), GFP_KERNEL); 6789 if (!port->ethtool_stats) { 6790 err = -ENOMEM; 6791 goto err_free_stats; 6792 } 6793 6794 mutex_init(&port->gather_stats_lock); 6795 INIT_DELAYED_WORK(&port->stats_work, mvpp2_gather_hw_statistics); 6796 6797 mvpp2_port_copy_mac_addr(dev, priv, port_fwnode, &mac_from); 6798 6799 port->tx_ring_size = MVPP2_MAX_TXD_DFLT; 6800 port->rx_ring_size = MVPP2_MAX_RXD_DFLT; 6801 SET_NETDEV_DEV(dev, &pdev->dev); 6802 6803 err = mvpp2_port_init(port); 6804 if (err < 0) { 6805 dev_err(&pdev->dev, "failed to init port %d\n", id); 6806 goto err_free_stats; 6807 } 6808 6809 mvpp2_port_periodic_xon_disable(port); 6810 6811 mvpp2_mac_reset_assert(port); 6812 mvpp22_pcs_reset_assert(port); 6813 6814 port->pcpu = alloc_percpu(struct mvpp2_port_pcpu); 6815 if (!port->pcpu) { 6816 err = -ENOMEM; 6817 goto err_free_txq_pcpu; 6818 } 6819 6820 if (!port->has_tx_irqs) { 6821 for (thread = 0; thread < priv->nthreads; thread++) { 6822 port_pcpu = per_cpu_ptr(port->pcpu, thread); 6823 6824 hrtimer_init(&port_pcpu->tx_done_timer, CLOCK_MONOTONIC, 6825 HRTIMER_MODE_REL_PINNED_SOFT); 6826 port_pcpu->tx_done_timer.function = mvpp2_hr_timer_cb; 6827 port_pcpu->timer_scheduled = false; 6828 port_pcpu->dev = dev; 6829 } 6830 } 6831 6832 features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | 6833 NETIF_F_TSO; 6834 dev->features = features | NETIF_F_RXCSUM; 6835 dev->hw_features |= features | NETIF_F_RXCSUM | NETIF_F_GRO | 6836 NETIF_F_HW_VLAN_CTAG_FILTER; 6837 6838 if (mvpp22_rss_is_supported()) { 6839 dev->hw_features |= NETIF_F_RXHASH; 6840 dev->features |= NETIF_F_NTUPLE; 6841 } 6842 6843 if (!port->priv->percpu_pools) 6844 mvpp2_set_hw_csum(port, port->pool_long->id); 6845 6846 dev->vlan_features |= features; 6847 dev->gso_max_segs = MVPP2_MAX_TSO_SEGS; 6848 dev->priv_flags |= IFF_UNICAST_FLT; 6849 6850 /* MTU range: 68 - 9704 */ 6851 dev->min_mtu = ETH_MIN_MTU; 6852 /* 9704 == 9728 - 20 and rounding to 8 */ 6853 dev->max_mtu = MVPP2_BM_JUMBO_PKT_SIZE; 6854 dev->dev.of_node = port_node; 6855 6856 /* Phylink isn't used w/ ACPI as of now */ 6857 if (port_node) { 6858 port->phylink_config.dev = &dev->dev; 6859 port->phylink_config.type = PHYLINK_NETDEV; 6860 6861 phylink = phylink_create(&port->phylink_config, port_fwnode, 6862 phy_mode, &mvpp2_phylink_ops); 6863 if (IS_ERR(phylink)) { 6864 err = PTR_ERR(phylink); 6865 goto err_free_port_pcpu; 6866 } 6867 port->phylink = phylink; 6868 } else { 6869 port->phylink = NULL; 6870 } 6871 6872 /* Cycle the comphy to power it down, saving 270mW per port - 6873 * don't worry about an error powering it up. When the comphy 6874 * driver does this, we can remove this code. 6875 */ 6876 if (port->comphy) { 6877 err = mvpp22_comphy_init(port); 6878 if (err == 0) 6879 phy_power_off(port->comphy); 6880 } 6881 6882 err = register_netdev(dev); 6883 if (err < 0) { 6884 dev_err(&pdev->dev, "failed to register netdev\n"); 6885 goto err_phylink; 6886 } 6887 netdev_info(dev, "Using %s mac address %pM\n", mac_from, dev->dev_addr); 6888 6889 priv->port_list[priv->port_count++] = port; 6890 6891 return 0; 6892 6893 err_phylink: 6894 if (port->phylink) 6895 phylink_destroy(port->phylink); 6896 err_free_port_pcpu: 6897 free_percpu(port->pcpu); 6898 err_free_txq_pcpu: 6899 for (i = 0; i < port->ntxqs; i++) 6900 free_percpu(port->txqs[i]->pcpu); 6901 err_free_stats: 6902 free_percpu(port->stats); 6903 err_free_irq: 6904 if (port->port_irq) 6905 irq_dispose_mapping(port->port_irq); 6906 err_deinit_qvecs: 6907 mvpp2_queue_vectors_deinit(port); 6908 err_free_netdev: 6909 free_netdev(dev); 6910 return err; 6911 } 6912 6913 /* Ports removal routine */ 6914 static void mvpp2_port_remove(struct mvpp2_port *port) 6915 { 6916 int i; 6917 6918 unregister_netdev(port->dev); 6919 if (port->phylink) 6920 phylink_destroy(port->phylink); 6921 free_percpu(port->pcpu); 6922 free_percpu(port->stats); 6923 for (i = 0; i < port->ntxqs; i++) 6924 free_percpu(port->txqs[i]->pcpu); 6925 mvpp2_queue_vectors_deinit(port); 6926 if (port->port_irq) 6927 irq_dispose_mapping(port->port_irq); 6928 free_netdev(port->dev); 6929 } 6930 6931 /* Initialize decoding windows */ 6932 static void mvpp2_conf_mbus_windows(const struct mbus_dram_target_info *dram, 6933 struct mvpp2 *priv) 6934 { 6935 u32 win_enable; 6936 int i; 6937 6938 for (i = 0; i < 6; i++) { 6939 mvpp2_write(priv, MVPP2_WIN_BASE(i), 0); 6940 mvpp2_write(priv, MVPP2_WIN_SIZE(i), 0); 6941 6942 if (i < 4) 6943 mvpp2_write(priv, MVPP2_WIN_REMAP(i), 0); 6944 } 6945 6946 win_enable = 0; 6947 6948 for (i = 0; i < dram->num_cs; i++) { 6949 const struct mbus_dram_window *cs = dram->cs + i; 6950 6951 mvpp2_write(priv, MVPP2_WIN_BASE(i), 6952 (cs->base & 0xffff0000) | (cs->mbus_attr << 8) | 6953 dram->mbus_dram_target_id); 6954 6955 mvpp2_write(priv, MVPP2_WIN_SIZE(i), 6956 (cs->size - 1) & 0xffff0000); 6957 6958 win_enable |= (1 << i); 6959 } 6960 6961 mvpp2_write(priv, MVPP2_BASE_ADDR_ENABLE, win_enable); 6962 } 6963 6964 /* Initialize Rx FIFO's */ 6965 static void mvpp2_rx_fifo_init(struct mvpp2 *priv) 6966 { 6967 int port; 6968 6969 for (port = 0; port < MVPP2_MAX_PORTS; port++) { 6970 mvpp2_write(priv, MVPP2_RX_DATA_FIFO_SIZE_REG(port), 6971 MVPP2_RX_FIFO_PORT_DATA_SIZE_4KB); 6972 mvpp2_write(priv, MVPP2_RX_ATTR_FIFO_SIZE_REG(port), 6973 MVPP2_RX_FIFO_PORT_ATTR_SIZE_4KB); 6974 } 6975 6976 mvpp2_write(priv, MVPP2_RX_MIN_PKT_SIZE_REG, 6977 MVPP2_RX_FIFO_PORT_MIN_PKT); 6978 mvpp2_write(priv, MVPP2_RX_FIFO_INIT_REG, 0x1); 6979 } 6980 6981 static void mvpp22_rx_fifo_set_hw(struct mvpp2 *priv, int port, int data_size) 6982 { 6983 int attr_size = MVPP2_RX_FIFO_PORT_ATTR_SIZE(data_size); 6984 6985 mvpp2_write(priv, MVPP2_RX_DATA_FIFO_SIZE_REG(port), data_size); 6986 mvpp2_write(priv, MVPP2_RX_ATTR_FIFO_SIZE_REG(port), attr_size); 6987 } 6988 6989 /* Initialize TX FIFO's: the total FIFO size is 48kB on PPv2.2 and PPv2.3. 6990 * 4kB fixed space must be assigned for the loopback port. 6991 * Redistribute remaining avialable 44kB space among all active ports. 6992 * Guarantee minimum 32kB for 10G port and 8kB for port 1, capable of 2.5G 6993 * SGMII link. 6994 */ 6995 static void mvpp22_rx_fifo_init(struct mvpp2 *priv) 6996 { 6997 int remaining_ports_count; 6998 unsigned long port_map; 6999 int size_remainder; 7000 int port, size; 7001 7002 /* The loopback requires fixed 4kB of the FIFO space assignment. */ 7003 mvpp22_rx_fifo_set_hw(priv, MVPP2_LOOPBACK_PORT_INDEX, 7004 MVPP2_RX_FIFO_PORT_DATA_SIZE_4KB); 7005 port_map = priv->port_map & ~BIT(MVPP2_LOOPBACK_PORT_INDEX); 7006 7007 /* Set RX FIFO size to 0 for inactive ports. */ 7008 for_each_clear_bit(port, &port_map, MVPP2_LOOPBACK_PORT_INDEX) 7009 mvpp22_rx_fifo_set_hw(priv, port, 0); 7010 7011 /* Assign remaining RX FIFO space among all active ports. */ 7012 size_remainder = MVPP2_RX_FIFO_PORT_DATA_SIZE_44KB; 7013 remaining_ports_count = hweight_long(port_map); 7014 7015 for_each_set_bit(port, &port_map, MVPP2_LOOPBACK_PORT_INDEX) { 7016 if (remaining_ports_count == 1) 7017 size = size_remainder; 7018 else if (port == 0) 7019 size = max(size_remainder / remaining_ports_count, 7020 MVPP2_RX_FIFO_PORT_DATA_SIZE_32KB); 7021 else if (port == 1) 7022 size = max(size_remainder / remaining_ports_count, 7023 MVPP2_RX_FIFO_PORT_DATA_SIZE_8KB); 7024 else 7025 size = size_remainder / remaining_ports_count; 7026 7027 size_remainder -= size; 7028 remaining_ports_count--; 7029 7030 mvpp22_rx_fifo_set_hw(priv, port, size); 7031 } 7032 7033 mvpp2_write(priv, MVPP2_RX_MIN_PKT_SIZE_REG, 7034 MVPP2_RX_FIFO_PORT_MIN_PKT); 7035 mvpp2_write(priv, MVPP2_RX_FIFO_INIT_REG, 0x1); 7036 } 7037 7038 /* Configure Rx FIFO Flow control thresholds */ 7039 static void mvpp23_rx_fifo_fc_set_tresh(struct mvpp2 *priv) 7040 { 7041 int port, val; 7042 7043 /* Port 0: maximum speed -10Gb/s port 7044 * required by spec RX FIFO threshold 9KB 7045 * Port 1: maximum speed -5Gb/s port 7046 * required by spec RX FIFO threshold 4KB 7047 * Port 2: maximum speed -1Gb/s port 7048 * required by spec RX FIFO threshold 2KB 7049 */ 7050 7051 /* Without loopback port */ 7052 for (port = 0; port < (MVPP2_MAX_PORTS - 1); port++) { 7053 if (port == 0) { 7054 val = (MVPP23_PORT0_FIFO_TRSH / MVPP2_RX_FC_TRSH_UNIT) 7055 << MVPP2_RX_FC_TRSH_OFFS; 7056 val &= MVPP2_RX_FC_TRSH_MASK; 7057 mvpp2_write(priv, MVPP2_RX_FC_REG(port), val); 7058 } else if (port == 1) { 7059 val = (MVPP23_PORT1_FIFO_TRSH / MVPP2_RX_FC_TRSH_UNIT) 7060 << MVPP2_RX_FC_TRSH_OFFS; 7061 val &= MVPP2_RX_FC_TRSH_MASK; 7062 mvpp2_write(priv, MVPP2_RX_FC_REG(port), val); 7063 } else { 7064 val = (MVPP23_PORT2_FIFO_TRSH / MVPP2_RX_FC_TRSH_UNIT) 7065 << MVPP2_RX_FC_TRSH_OFFS; 7066 val &= MVPP2_RX_FC_TRSH_MASK; 7067 mvpp2_write(priv, MVPP2_RX_FC_REG(port), val); 7068 } 7069 } 7070 } 7071 7072 /* Configure Rx FIFO Flow control thresholds */ 7073 void mvpp23_rx_fifo_fc_en(struct mvpp2 *priv, int port, bool en) 7074 { 7075 int val; 7076 7077 val = mvpp2_read(priv, MVPP2_RX_FC_REG(port)); 7078 7079 if (en) 7080 val |= MVPP2_RX_FC_EN; 7081 else 7082 val &= ~MVPP2_RX_FC_EN; 7083 7084 mvpp2_write(priv, MVPP2_RX_FC_REG(port), val); 7085 } 7086 7087 static void mvpp22_tx_fifo_set_hw(struct mvpp2 *priv, int port, int size) 7088 { 7089 int threshold = MVPP2_TX_FIFO_THRESHOLD(size); 7090 7091 mvpp2_write(priv, MVPP22_TX_FIFO_SIZE_REG(port), size); 7092 mvpp2_write(priv, MVPP22_TX_FIFO_THRESH_REG(port), threshold); 7093 } 7094 7095 /* Initialize TX FIFO's: the total FIFO size is 19kB on PPv2.2 and PPv2.3. 7096 * 3kB fixed space must be assigned for the loopback port. 7097 * Redistribute remaining avialable 16kB space among all active ports. 7098 * The 10G interface should use 10kB (which is maximum possible size 7099 * per single port). 7100 */ 7101 static void mvpp22_tx_fifo_init(struct mvpp2 *priv) 7102 { 7103 int remaining_ports_count; 7104 unsigned long port_map; 7105 int size_remainder; 7106 int port, size; 7107 7108 /* The loopback requires fixed 3kB of the FIFO space assignment. */ 7109 mvpp22_tx_fifo_set_hw(priv, MVPP2_LOOPBACK_PORT_INDEX, 7110 MVPP22_TX_FIFO_DATA_SIZE_3KB); 7111 port_map = priv->port_map & ~BIT(MVPP2_LOOPBACK_PORT_INDEX); 7112 7113 /* Set TX FIFO size to 0 for inactive ports. */ 7114 for_each_clear_bit(port, &port_map, MVPP2_LOOPBACK_PORT_INDEX) 7115 mvpp22_tx_fifo_set_hw(priv, port, 0); 7116 7117 /* Assign remaining TX FIFO space among all active ports. */ 7118 size_remainder = MVPP22_TX_FIFO_DATA_SIZE_16KB; 7119 remaining_ports_count = hweight_long(port_map); 7120 7121 for_each_set_bit(port, &port_map, MVPP2_LOOPBACK_PORT_INDEX) { 7122 if (remaining_ports_count == 1) 7123 size = min(size_remainder, 7124 MVPP22_TX_FIFO_DATA_SIZE_10KB); 7125 else if (port == 0) 7126 size = MVPP22_TX_FIFO_DATA_SIZE_10KB; 7127 else 7128 size = size_remainder / remaining_ports_count; 7129 7130 size_remainder -= size; 7131 remaining_ports_count--; 7132 7133 mvpp22_tx_fifo_set_hw(priv, port, size); 7134 } 7135 } 7136 7137 static void mvpp2_axi_init(struct mvpp2 *priv) 7138 { 7139 u32 val, rdval, wrval; 7140 7141 mvpp2_write(priv, MVPP22_BM_ADDR_HIGH_RLS_REG, 0x0); 7142 7143 /* AXI Bridge Configuration */ 7144 7145 rdval = MVPP22_AXI_CODE_CACHE_RD_CACHE 7146 << MVPP22_AXI_ATTR_CACHE_OFFS; 7147 rdval |= MVPP22_AXI_CODE_DOMAIN_OUTER_DOM 7148 << MVPP22_AXI_ATTR_DOMAIN_OFFS; 7149 7150 wrval = MVPP22_AXI_CODE_CACHE_WR_CACHE 7151 << MVPP22_AXI_ATTR_CACHE_OFFS; 7152 wrval |= MVPP22_AXI_CODE_DOMAIN_OUTER_DOM 7153 << MVPP22_AXI_ATTR_DOMAIN_OFFS; 7154 7155 /* BM */ 7156 mvpp2_write(priv, MVPP22_AXI_BM_WR_ATTR_REG, wrval); 7157 mvpp2_write(priv, MVPP22_AXI_BM_RD_ATTR_REG, rdval); 7158 7159 /* Descriptors */ 7160 mvpp2_write(priv, MVPP22_AXI_AGGRQ_DESCR_RD_ATTR_REG, rdval); 7161 mvpp2_write(priv, MVPP22_AXI_TXQ_DESCR_WR_ATTR_REG, wrval); 7162 mvpp2_write(priv, MVPP22_AXI_TXQ_DESCR_RD_ATTR_REG, rdval); 7163 mvpp2_write(priv, MVPP22_AXI_RXQ_DESCR_WR_ATTR_REG, wrval); 7164 7165 /* Buffer Data */ 7166 mvpp2_write(priv, MVPP22_AXI_TX_DATA_RD_ATTR_REG, rdval); 7167 mvpp2_write(priv, MVPP22_AXI_RX_DATA_WR_ATTR_REG, wrval); 7168 7169 val = MVPP22_AXI_CODE_CACHE_NON_CACHE 7170 << MVPP22_AXI_CODE_CACHE_OFFS; 7171 val |= MVPP22_AXI_CODE_DOMAIN_SYSTEM 7172 << MVPP22_AXI_CODE_DOMAIN_OFFS; 7173 mvpp2_write(priv, MVPP22_AXI_RD_NORMAL_CODE_REG, val); 7174 mvpp2_write(priv, MVPP22_AXI_WR_NORMAL_CODE_REG, val); 7175 7176 val = MVPP22_AXI_CODE_CACHE_RD_CACHE 7177 << MVPP22_AXI_CODE_CACHE_OFFS; 7178 val |= MVPP22_AXI_CODE_DOMAIN_OUTER_DOM 7179 << MVPP22_AXI_CODE_DOMAIN_OFFS; 7180 7181 mvpp2_write(priv, MVPP22_AXI_RD_SNOOP_CODE_REG, val); 7182 7183 val = MVPP22_AXI_CODE_CACHE_WR_CACHE 7184 << MVPP22_AXI_CODE_CACHE_OFFS; 7185 val |= MVPP22_AXI_CODE_DOMAIN_OUTER_DOM 7186 << MVPP22_AXI_CODE_DOMAIN_OFFS; 7187 7188 mvpp2_write(priv, MVPP22_AXI_WR_SNOOP_CODE_REG, val); 7189 } 7190 7191 /* Initialize network controller common part HW */ 7192 static int mvpp2_init(struct platform_device *pdev, struct mvpp2 *priv) 7193 { 7194 const struct mbus_dram_target_info *dram_target_info; 7195 int err, i; 7196 u32 val; 7197 7198 /* MBUS windows configuration */ 7199 dram_target_info = mv_mbus_dram_info(); 7200 if (dram_target_info) 7201 mvpp2_conf_mbus_windows(dram_target_info, priv); 7202 7203 if (priv->hw_version != MVPP21) 7204 mvpp2_axi_init(priv); 7205 7206 /* Disable HW PHY polling */ 7207 if (priv->hw_version == MVPP21) { 7208 val = readl(priv->lms_base + MVPP2_PHY_AN_CFG0_REG); 7209 val |= MVPP2_PHY_AN_STOP_SMI0_MASK; 7210 writel(val, priv->lms_base + MVPP2_PHY_AN_CFG0_REG); 7211 } else { 7212 val = readl(priv->iface_base + MVPP22_SMI_MISC_CFG_REG); 7213 val &= ~MVPP22_SMI_POLLING_EN; 7214 writel(val, priv->iface_base + MVPP22_SMI_MISC_CFG_REG); 7215 } 7216 7217 /* Allocate and initialize aggregated TXQs */ 7218 priv->aggr_txqs = devm_kcalloc(&pdev->dev, MVPP2_MAX_THREADS, 7219 sizeof(*priv->aggr_txqs), 7220 GFP_KERNEL); 7221 if (!priv->aggr_txqs) 7222 return -ENOMEM; 7223 7224 for (i = 0; i < MVPP2_MAX_THREADS; i++) { 7225 priv->aggr_txqs[i].id = i; 7226 priv->aggr_txqs[i].size = MVPP2_AGGR_TXQ_SIZE; 7227 err = mvpp2_aggr_txq_init(pdev, &priv->aggr_txqs[i], i, priv); 7228 if (err < 0) 7229 return err; 7230 } 7231 7232 /* Fifo Init */ 7233 if (priv->hw_version == MVPP21) { 7234 mvpp2_rx_fifo_init(priv); 7235 } else { 7236 mvpp22_rx_fifo_init(priv); 7237 mvpp22_tx_fifo_init(priv); 7238 if (priv->hw_version == MVPP23) 7239 mvpp23_rx_fifo_fc_set_tresh(priv); 7240 } 7241 7242 if (priv->hw_version == MVPP21) 7243 writel(MVPP2_EXT_GLOBAL_CTRL_DEFAULT, 7244 priv->lms_base + MVPP2_MNG_EXTENDED_GLOBAL_CTRL_REG); 7245 7246 /* Allow cache snoop when transmiting packets */ 7247 mvpp2_write(priv, MVPP2_TX_SNOOP_REG, 0x1); 7248 7249 /* Buffer Manager initialization */ 7250 err = mvpp2_bm_init(&pdev->dev, priv); 7251 if (err < 0) 7252 return err; 7253 7254 /* Parser default initialization */ 7255 err = mvpp2_prs_default_init(pdev, priv); 7256 if (err < 0) 7257 return err; 7258 7259 /* Classifier default initialization */ 7260 mvpp2_cls_init(priv); 7261 7262 return 0; 7263 } 7264 7265 static int mvpp2_get_sram(struct platform_device *pdev, 7266 struct mvpp2 *priv) 7267 { 7268 struct resource *res; 7269 7270 res = platform_get_resource(pdev, IORESOURCE_MEM, 2); 7271 if (!res) { 7272 if (has_acpi_companion(&pdev->dev)) 7273 dev_warn(&pdev->dev, "ACPI is too old, Flow control not supported\n"); 7274 else 7275 dev_warn(&pdev->dev, "DT is too old, Flow control not supported\n"); 7276 return 0; 7277 } 7278 7279 priv->cm3_base = devm_ioremap_resource(&pdev->dev, res); 7280 if (IS_ERR(priv->cm3_base)) 7281 return PTR_ERR(priv->cm3_base); 7282 7283 return 0; 7284 } 7285 7286 static int mvpp2_probe(struct platform_device *pdev) 7287 { 7288 const struct acpi_device_id *acpi_id; 7289 struct fwnode_handle *fwnode = pdev->dev.fwnode; 7290 struct fwnode_handle *port_fwnode; 7291 struct mvpp2 *priv; 7292 struct resource *res; 7293 void __iomem *base; 7294 int i, shared; 7295 int err; 7296 7297 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); 7298 if (!priv) 7299 return -ENOMEM; 7300 7301 if (has_acpi_companion(&pdev->dev)) { 7302 acpi_id = acpi_match_device(pdev->dev.driver->acpi_match_table, 7303 &pdev->dev); 7304 if (!acpi_id) 7305 return -EINVAL; 7306 priv->hw_version = (unsigned long)acpi_id->driver_data; 7307 } else { 7308 priv->hw_version = 7309 (unsigned long)of_device_get_match_data(&pdev->dev); 7310 } 7311 7312 /* multi queue mode isn't supported on PPV2.1, fallback to single 7313 * mode 7314 */ 7315 if (priv->hw_version == MVPP21) 7316 queue_mode = MVPP2_QDIST_SINGLE_MODE; 7317 7318 base = devm_platform_ioremap_resource(pdev, 0); 7319 if (IS_ERR(base)) 7320 return PTR_ERR(base); 7321 7322 if (priv->hw_version == MVPP21) { 7323 priv->lms_base = devm_platform_ioremap_resource(pdev, 1); 7324 if (IS_ERR(priv->lms_base)) 7325 return PTR_ERR(priv->lms_base); 7326 } else { 7327 res = platform_get_resource(pdev, IORESOURCE_MEM, 1); 7328 if (has_acpi_companion(&pdev->dev)) { 7329 /* In case the MDIO memory region is declared in 7330 * the ACPI, it can already appear as 'in-use' 7331 * in the OS. Because it is overlapped by second 7332 * region of the network controller, make 7333 * sure it is released, before requesting it again. 7334 * The care is taken by mvpp2 driver to avoid 7335 * concurrent access to this memory region. 7336 */ 7337 release_resource(res); 7338 } 7339 priv->iface_base = devm_ioremap_resource(&pdev->dev, res); 7340 if (IS_ERR(priv->iface_base)) 7341 return PTR_ERR(priv->iface_base); 7342 7343 /* Map CM3 SRAM */ 7344 err = mvpp2_get_sram(pdev, priv); 7345 if (err) 7346 dev_warn(&pdev->dev, "Fail to alloc CM3 SRAM\n"); 7347 7348 /* Enable global Flow Control only if handler to SRAM not NULL */ 7349 if (priv->cm3_base) 7350 priv->global_tx_fc = true; 7351 } 7352 7353 if (priv->hw_version != MVPP21 && dev_of_node(&pdev->dev)) { 7354 priv->sysctrl_base = 7355 syscon_regmap_lookup_by_phandle(pdev->dev.of_node, 7356 "marvell,system-controller"); 7357 if (IS_ERR(priv->sysctrl_base)) 7358 /* The system controller regmap is optional for dt 7359 * compatibility reasons. When not provided, the 7360 * configuration of the GoP relies on the 7361 * firmware/bootloader. 7362 */ 7363 priv->sysctrl_base = NULL; 7364 } 7365 7366 if (priv->hw_version != MVPP21 && 7367 mvpp2_get_nrxqs(priv) * 2 <= MVPP2_BM_MAX_POOLS) 7368 priv->percpu_pools = 1; 7369 7370 mvpp2_setup_bm_pool(); 7371 7372 7373 priv->nthreads = min_t(unsigned int, num_present_cpus(), 7374 MVPP2_MAX_THREADS); 7375 7376 shared = num_present_cpus() - priv->nthreads; 7377 if (shared > 0) 7378 bitmap_fill(&priv->lock_map, 7379 min_t(int, shared, MVPP2_MAX_THREADS)); 7380 7381 for (i = 0; i < MVPP2_MAX_THREADS; i++) { 7382 u32 addr_space_sz; 7383 7384 addr_space_sz = (priv->hw_version == MVPP21 ? 7385 MVPP21_ADDR_SPACE_SZ : MVPP22_ADDR_SPACE_SZ); 7386 priv->swth_base[i] = base + i * addr_space_sz; 7387 } 7388 7389 if (priv->hw_version == MVPP21) 7390 priv->max_port_rxqs = 8; 7391 else 7392 priv->max_port_rxqs = 32; 7393 7394 if (dev_of_node(&pdev->dev)) { 7395 priv->pp_clk = devm_clk_get(&pdev->dev, "pp_clk"); 7396 if (IS_ERR(priv->pp_clk)) 7397 return PTR_ERR(priv->pp_clk); 7398 err = clk_prepare_enable(priv->pp_clk); 7399 if (err < 0) 7400 return err; 7401 7402 priv->gop_clk = devm_clk_get(&pdev->dev, "gop_clk"); 7403 if (IS_ERR(priv->gop_clk)) { 7404 err = PTR_ERR(priv->gop_clk); 7405 goto err_pp_clk; 7406 } 7407 err = clk_prepare_enable(priv->gop_clk); 7408 if (err < 0) 7409 goto err_pp_clk; 7410 7411 if (priv->hw_version != MVPP21) { 7412 priv->mg_clk = devm_clk_get(&pdev->dev, "mg_clk"); 7413 if (IS_ERR(priv->mg_clk)) { 7414 err = PTR_ERR(priv->mg_clk); 7415 goto err_gop_clk; 7416 } 7417 7418 err = clk_prepare_enable(priv->mg_clk); 7419 if (err < 0) 7420 goto err_gop_clk; 7421 7422 priv->mg_core_clk = devm_clk_get(&pdev->dev, "mg_core_clk"); 7423 if (IS_ERR(priv->mg_core_clk)) { 7424 priv->mg_core_clk = NULL; 7425 } else { 7426 err = clk_prepare_enable(priv->mg_core_clk); 7427 if (err < 0) 7428 goto err_mg_clk; 7429 } 7430 } 7431 7432 priv->axi_clk = devm_clk_get(&pdev->dev, "axi_clk"); 7433 if (IS_ERR(priv->axi_clk)) { 7434 err = PTR_ERR(priv->axi_clk); 7435 if (err == -EPROBE_DEFER) 7436 goto err_mg_core_clk; 7437 priv->axi_clk = NULL; 7438 } else { 7439 err = clk_prepare_enable(priv->axi_clk); 7440 if (err < 0) 7441 goto err_mg_core_clk; 7442 } 7443 7444 /* Get system's tclk rate */ 7445 priv->tclk = clk_get_rate(priv->pp_clk); 7446 } else if (device_property_read_u32(&pdev->dev, "clock-frequency", 7447 &priv->tclk)) { 7448 dev_err(&pdev->dev, "missing clock-frequency value\n"); 7449 return -EINVAL; 7450 } 7451 7452 if (priv->hw_version != MVPP21) { 7453 err = dma_set_mask(&pdev->dev, MVPP2_DESC_DMA_MASK); 7454 if (err) 7455 goto err_axi_clk; 7456 /* Sadly, the BM pools all share the same register to 7457 * store the high 32 bits of their address. So they 7458 * must all have the same high 32 bits, which forces 7459 * us to restrict coherent memory to DMA_BIT_MASK(32). 7460 */ 7461 err = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32)); 7462 if (err) 7463 goto err_axi_clk; 7464 } 7465 7466 /* Map DTS-active ports. Should be done before FIFO mvpp2_init */ 7467 fwnode_for_each_available_child_node(fwnode, port_fwnode) { 7468 if (!fwnode_property_read_u32(port_fwnode, "port-id", &i)) 7469 priv->port_map |= BIT(i); 7470 } 7471 7472 if (priv->hw_version != MVPP21) { 7473 if (mvpp2_read(priv, MVPP2_VER_ID_REG) == MVPP2_VER_PP23) 7474 priv->hw_version = MVPP23; 7475 } 7476 7477 /* Init mss lock */ 7478 spin_lock_init(&priv->mss_spinlock); 7479 7480 /* Initialize network controller */ 7481 err = mvpp2_init(pdev, priv); 7482 if (err < 0) { 7483 dev_err(&pdev->dev, "failed to initialize controller\n"); 7484 goto err_axi_clk; 7485 } 7486 7487 err = mvpp22_tai_probe(&pdev->dev, priv); 7488 if (err < 0) 7489 goto err_axi_clk; 7490 7491 /* Initialize ports */ 7492 fwnode_for_each_available_child_node(fwnode, port_fwnode) { 7493 err = mvpp2_port_probe(pdev, port_fwnode, priv); 7494 if (err < 0) 7495 goto err_port_probe; 7496 } 7497 7498 if (priv->port_count == 0) { 7499 dev_err(&pdev->dev, "no ports enabled\n"); 7500 err = -ENODEV; 7501 goto err_axi_clk; 7502 } 7503 7504 /* Statistics must be gathered regularly because some of them (like 7505 * packets counters) are 32-bit registers and could overflow quite 7506 * quickly. For instance, a 10Gb link used at full bandwidth with the 7507 * smallest packets (64B) will overflow a 32-bit counter in less than 7508 * 30 seconds. Then, use a workqueue to fill 64-bit counters. 7509 */ 7510 snprintf(priv->queue_name, sizeof(priv->queue_name), 7511 "stats-wq-%s%s", netdev_name(priv->port_list[0]->dev), 7512 priv->port_count > 1 ? "+" : ""); 7513 priv->stats_queue = create_singlethread_workqueue(priv->queue_name); 7514 if (!priv->stats_queue) { 7515 err = -ENOMEM; 7516 goto err_port_probe; 7517 } 7518 7519 if (priv->global_tx_fc && priv->hw_version != MVPP21) { 7520 err = mvpp2_enable_global_fc(priv); 7521 if (err) 7522 dev_warn(&pdev->dev, "Minimum of CM3 firmware 18.09 and chip revision B0 required for flow control\n"); 7523 } 7524 7525 mvpp2_dbgfs_init(priv, pdev->name); 7526 7527 platform_set_drvdata(pdev, priv); 7528 return 0; 7529 7530 err_port_probe: 7531 i = 0; 7532 fwnode_for_each_available_child_node(fwnode, port_fwnode) { 7533 if (priv->port_list[i]) 7534 mvpp2_port_remove(priv->port_list[i]); 7535 i++; 7536 } 7537 err_axi_clk: 7538 clk_disable_unprepare(priv->axi_clk); 7539 7540 err_mg_core_clk: 7541 if (priv->hw_version != MVPP21) 7542 clk_disable_unprepare(priv->mg_core_clk); 7543 err_mg_clk: 7544 if (priv->hw_version != MVPP21) 7545 clk_disable_unprepare(priv->mg_clk); 7546 err_gop_clk: 7547 clk_disable_unprepare(priv->gop_clk); 7548 err_pp_clk: 7549 clk_disable_unprepare(priv->pp_clk); 7550 return err; 7551 } 7552 7553 static int mvpp2_remove(struct platform_device *pdev) 7554 { 7555 struct mvpp2 *priv = platform_get_drvdata(pdev); 7556 struct fwnode_handle *fwnode = pdev->dev.fwnode; 7557 int i = 0, poolnum = MVPP2_BM_POOLS_NUM; 7558 struct fwnode_handle *port_fwnode; 7559 7560 mvpp2_dbgfs_cleanup(priv); 7561 7562 fwnode_for_each_available_child_node(fwnode, port_fwnode) { 7563 if (priv->port_list[i]) { 7564 mutex_destroy(&priv->port_list[i]->gather_stats_lock); 7565 mvpp2_port_remove(priv->port_list[i]); 7566 } 7567 i++; 7568 } 7569 7570 destroy_workqueue(priv->stats_queue); 7571 7572 if (priv->percpu_pools) 7573 poolnum = mvpp2_get_nrxqs(priv) * 2; 7574 7575 for (i = 0; i < poolnum; i++) { 7576 struct mvpp2_bm_pool *bm_pool = &priv->bm_pools[i]; 7577 7578 mvpp2_bm_pool_destroy(&pdev->dev, priv, bm_pool); 7579 } 7580 7581 for (i = 0; i < MVPP2_MAX_THREADS; i++) { 7582 struct mvpp2_tx_queue *aggr_txq = &priv->aggr_txqs[i]; 7583 7584 dma_free_coherent(&pdev->dev, 7585 MVPP2_AGGR_TXQ_SIZE * MVPP2_DESC_ALIGNED_SIZE, 7586 aggr_txq->descs, 7587 aggr_txq->descs_dma); 7588 } 7589 7590 if (is_acpi_node(port_fwnode)) 7591 return 0; 7592 7593 clk_disable_unprepare(priv->axi_clk); 7594 clk_disable_unprepare(priv->mg_core_clk); 7595 clk_disable_unprepare(priv->mg_clk); 7596 clk_disable_unprepare(priv->pp_clk); 7597 clk_disable_unprepare(priv->gop_clk); 7598 7599 return 0; 7600 } 7601 7602 static const struct of_device_id mvpp2_match[] = { 7603 { 7604 .compatible = "marvell,armada-375-pp2", 7605 .data = (void *)MVPP21, 7606 }, 7607 { 7608 .compatible = "marvell,armada-7k-pp22", 7609 .data = (void *)MVPP22, 7610 }, 7611 { } 7612 }; 7613 MODULE_DEVICE_TABLE(of, mvpp2_match); 7614 7615 #ifdef CONFIG_ACPI 7616 static const struct acpi_device_id mvpp2_acpi_match[] = { 7617 { "MRVL0110", MVPP22 }, 7618 { }, 7619 }; 7620 MODULE_DEVICE_TABLE(acpi, mvpp2_acpi_match); 7621 #endif 7622 7623 static struct platform_driver mvpp2_driver = { 7624 .probe = mvpp2_probe, 7625 .remove = mvpp2_remove, 7626 .driver = { 7627 .name = MVPP2_DRIVER_NAME, 7628 .of_match_table = mvpp2_match, 7629 .acpi_match_table = ACPI_PTR(mvpp2_acpi_match), 7630 }, 7631 }; 7632 7633 module_platform_driver(mvpp2_driver); 7634 7635 MODULE_DESCRIPTION("Marvell PPv2 Ethernet Driver - www.marvell.com"); 7636 MODULE_AUTHOR("Marcin Wojtas <mw@semihalf.com>"); 7637 MODULE_LICENSE("GPL v2"); 7638